ISL95813EV1Z_技术文档

Single Phase Core Controller for VR12.6

ISL95813

Features

The ISL95813 single-phase controller provides a fully compliant

VR12.6 power supply solution for Intel™ microprocessors. It

provides a tightly regulated output voltage that is programmed

through a high speed serial bus interface with the CPU. This

interface also allows the CPU to acquire real-time information from

the voltage regulator (VR), which includes load current and VR

temperature.

• Full VR12.6 specification compliance

• Wide input voltage range: 4.6V to 25V

• R3™ control architecture delivers excellent transient response

and power state mode transitions

• Current monitor (IMON) with temperature compensation

• VRHOT# indicator for CPU protection

Based on Intersil's Robust Ripple Regulator (R3™) technology, the

PWM modulator provides faster transient response and settling

time when compared against traditional modulation schemes. Its

variable frequency topology also allows for natural period stretching

discontinuous conduction mode (DCM) for increased efficiency and

power savings in light load situations.

• Digitally selectable switching frequency:

- 425kHz, 550kHz, 700kHz with ECO and PRO options

• Enhanced light-load efficiency discontinuous conduction mode

operation

• Ultra-small 20 lead 3mmx4mm QFN package

• Enable and power-good monitor

The ISL95813 has several other key features that include: DCR

current sensing with single NTC thermal compensation; discrete

resistor current sensing; differential remote voltage feedback; and

Applications

• Notebook Computers

user-programmable boot voltage, I

slew rate, and switching frequency.

, T

, voltage transition

MAX MAX

• Tablets, Ultrabooks™, and AIO

Related Literature

• AN1846 Designer’s Guide to the ISL95813 Evaluation Board

205kΩ

VIN

20

19

18

17

{4.6V TO 25V}

113kΩ

VR_ON

LG

1

2

3

4

5

6

16

15

14

13

12

11

BSC052N03LS

2200pF

LOUT

PGOOD

PHASE

VR12.6

CPU

0.15µH

COUT

14x22µF

VTT

499

IMON

UG

ISL95813

20 Ld 3x4 QFN

0.22µF

Ω

CERAMIC

BOOT

VRHOT#

BSC011N03LS

VCC

470kΩ (NTC)

27.4kΩ

3.83kΩ

NTC

E-PAD

(GND)

PGRM2

COMP

5.9kΩ

6800pF

124kΩ

1µF

7

8

9

10

3.65k

Ω

2.61kΩ

0.056µF

11kΩ

10kΩ (NTC)

Ω

549

82pF

1.82kΩ

FIGURE 1. TYPICAL 40Amax, 12.6, APPLICATION DIAGRAM

May 15, 2013

FN8449.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

R3 Technologies and Intersil (and design) are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL95813

Ordering Information

PART NUMBER

(Notes 1, 2)

PART

MARKING

TEMP. RANGE

PACKAGE

(Pb-Free)

PKG.

DWG. #

(°C)

ISL95813HRZ

ISL95813IRZ

ISL95813EV1Z

NOTES:

813H

813I

-10 to +100

-40 to +100

20 LD 3x4 QFN

L20.3x4

Evaluation Board

1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95813. For more information on MSL, please see tech brief TB363.

Pin Configuration

ISL95813

(20 LD 3X4 QFN)

TOP VIEW

20 19 18 17

VR_ON

PGOOD

IMON

LG

1

2

3

4

5

6

16

15

14

13

12

11

PHASE

UG

GND

VRHOT#

NTC

BOOT

VCC

PRGM2

COMP

7

8

9

10

Pin Descriptions

NAME

FUNCTION

1

VR_ON

Digital Input

Enable input for controller. Connect to ground to disable the part. Connect to VCC to initiate

soft-start and regulation.

2

3

PGOOD

IMON

Digital Output

Power-Good open-drain output indicating when VR is in regulation with no faults detected. Pull up

externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.

Analog Output:

[Small-signal]

VR output current monitor. IMON pin sources a current proportional to the regulator output current.

A resistor connected from this pin to ground will set a voltage that is proportional to the load

current. This voltage is sampled with an internal ADC to produce a digital IMON signal that can be

read through the serial communications bus.

4

5

6

VRHOT#

NTC

Digital Output

Open drain thermal overload output indicator. Can be considered part of communication bus with

CPU.

Analog Input:

[Small-Signal]

Thermistor input to VR_HOT# circuit. Used to monitor VR temperature.

COMP

Analog Output:

[Small-signal]

Output of the gm error-amplifier for loop control. Connect to ground through the compensation

network.

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2

ISL95813

Pin Descriptions(Continued)

NAME

FUNCTION

Output voltage feedback sensing input for regulation. Connect via resistor to VCC

7

FB

Analog Input:

[Small-signal]

on CPU.

SENSE

8

RTN

ISUMN

ISUMP

PRGM2

VCC

Analog Input:

[Small-signal]

Ground return for differential remote output voltage sensing.Connect via resistor to VCC

CPU.

on

SENSE

9

Analog Input:

[Small-signal]

VR Loadline, Droop, and DCR sensing input.

10

11

12

13

14

15

16

17

Analog Input:

[Small-signal]

Analog Input:

[Small-signal]

ADC input to program switching frequency and boot voltage using a resistor to ground. See

“PROGRAM 2 Pin” on page 13 for all programming options.

Analog Input:

[Small-signal]

5V IC bias supply input. Bypass to ground with a high-quality 0.1µF ceramic capacitor.

BOOT

UG

Analog Input:

[Power]

Floating high-side gate drive voltage supply. Connect to PHASE with a 0.1µF to 0.22µF high-quality

ceramic capacitor.

Analog Output:

[Power]

Upper MOSFET gate drive. Connect with a wide trace to the gate of the upper switching MOSFET.

PHASE

LG

Analog I/O:

[Power]

Switching node and upper MOSFET gate drive return path. Connect with a wide trace to the source

of the upper switching MOSFET, the drain of the lower switching MOSFET, and the output inductor.

Analog Output:

[Power]

Lower MOSFET gate drive. Connect with a wide trace to the gate of the lower switching MOSFET.

PRGM1

Analog Input:

[Small-signal]

ADC input to program I and FSEL bit using a resistor to ground. See “PROGRAM 1 Pin” on

CCMAX

page 13 for all programming options.

Data input/output for CPU serial interface.

Alert signal for CPU serial interface.

Clock input for CPU serial interface.

18

19

SDA

ALERT#

SCLK

Digital I/O

Digital Output

Digital Input

20

e-pad

GND

Analog Input:

[Power]

Ground reference for IC as well as gate drive power ground return path. Connect to system ground

plane with multiple vias.

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ISL95813

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . . PHASE-0.3V (DC) to BOOT

. . . . . . . . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT

LGATE Voltage

Thermal Resistance (Typical)

20 Ld QFN Package (Notes 4, 5) . . . . . . . .

θ

_JA(°C/W)

44

θ

_JC(°C/W)

6

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

. . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)

Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V

Recommended Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6V to 25V

Ambient Temperature

HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C

Junction Temperature

HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C

IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: VDD = 5V, T = -10°C to +100°C or -40°C to +100°C, f = 700kHz, unless otherwise

A

SW

noted. Boldface limits apply over the operating temperature range for High Temp Commercial at -10°C to +100°C or Industrial Temp at -40°C to +100°C.

MIN

MAX

PARAMETER

INPUT POWER SUPPLY

+5V Supply Current

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

3.5

90

(Note 6)

UNITS

I

VR_ON = 1V

VR_ON = 0V

PS4 State

5

1

mA

µA

VDD

150

POWER-ON-RESET THRESHOLDS

VDD Power-On-Reset Threshold

VDDPOR

V

rising

4.35

4.15

4.5

V

r

DD

falling

4.00

f

SYSTEM AND REFERENCES

System Accuracy

HRZ

%Error (V

VID = 1.50V to 2.30V

VID = 1.00V to 1.49V

VID = 0.50V to 0.99V

VID = 1.50V to 2.30V

VID = 1.00V to 1.49V

VID = 0.50V to 0.99V

HRTZ (Set by R_PROG2)

IRTZ (Set by R_PROG2)

VID = [11111111]

-0.5

-8

+0.5

+8

%

mV

%

OUT)

-10

+10

+1

IRZ

%Error (V

-1

)

OUT

-15

+15

+20

1.717

1.725

mV

V

-20

Internal V

1.683

1.675

1.7

2.3

0.5

BOOT

V

Maximum Output Voltage

Minimum Output Voltage

V

OUT(MAX)

V

VID = [00000001]

V

OUT(MIN)

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4

ISL95813

Electrical Specifications Operating Conditions: VDD = 5V, T = -10°C to +100°C or -40°C to +100°C, f = 700kHz, unless otherwise

A

SW

noted. Boldface limits apply over the operating temperature range for High Temp Commercial at -10°C to +100°C or Industrial Temp at -40°C to +100°C.

(Continued)

MIN

MAX

PARAMETER

CHANNEL FREQUENCY

425kHz Configuration

550kHz Configuration

700kHz Configuration

1000kHz Configuration

AMPLIFIERS

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNITS

f

395

510

650

915

425

550

700

985

455

590

kHz

SW_425k

SW_550k

SW_700k

Set by R_PROG1

f

750

f

Set by R_PROG1 (PRO PS2/PS3 only)

1055

SW_1000k

Current-Sense Amplifier Input Offset

I

= 0A, HRZ

= 0A, IRZ

-0.2

-0.3

+0.2

+0.3

mV

dB

FB

Error Amp DC Gain (Note 7)

A

90

18

v0

GBW

Error Amp Gain-Bandwidth Product

(Note 7)

C = 20pF

MHz

L

POWER-GOOD AND PROTECTION MONITORS

PGOOD Low Voltage

V

I

= 4mA

0.15

0.4

1

V

OL

PGOOD

PGOOD = 3.3V

= 1.7V

PGOOD Leakage Current

I

µA

ms

Ω

OH

PGOOD Delay

tpgd

V

1.2

7

BOOT

ALERT# Low Voltage (Note 6)

VR_HOT# Low Voltage (Note 6)

ALERT# Leakage Current

12

1

7

Ω

µA

VR_HOT# Leakage Current

GATE DRIVER

1

UGATE Pull-Up Resistance (Note 7)

UGATE Source Current (Note 7)

UGATE Sink Resistance (Note 7)

UGATE Sink Current (Note 7)

LGATE Pull-Up Resistance (Note 7)

LGATE Source Current (Note 7)

LGATE Sink Resistance (Note 7)

LGATE Sink Current (Note 7)

R

200mA Source Current

UGATE - PHASE = 2.5V

1.0

2.0

1.0

2.0

1.0

2.0

0.5

4.0

17

1.5

0.9

Ω

A

UGPU

I

UGSRC

R

250mA Sink Current

Ω

A

UGPD

I

UGATE - PHASE = 2.5V

UGSNK

R

250mA Source Current

LGATE - GND= 2.5V

Ω

A

LGPU

I

LGSRC

R

250mA Sink Current

Ω

A

LGPD

I

LGATE - GND = 2.5V

LGSNK

UGATE to LGATE Deadtime

LGATE to UGATE Deadtime

BOOTSTRAP DIODE

ON-Resistance

t

UGATE falling to LGATE rising, no load

LGATE falling to UGATE rising, no load

ns

UGFLGR

LGFUGR

t

29

R

22

Ω

F

Reverse Leakage

I

V

= 25V

R

0.2

µA

R

PROTECTION

Overvoltage Threshold

Overcurrent Threshold

LOGIC THRESHOLDS

VR_ON Input Low

OV

ISUMN rising above setpoint for >1µs

240

56

300

60

360

64

mV

µA

H

V

0.3

V

IL

VR_ON Input High

V

HRZ

IRZ

0.7

IH

V

0.75

THERMAL MONITOR

NTC Source Current

VR_HOT# Trip Voltage

VR_HOT# Reset Voltage

NTC = 1.3V

Falling

58

60

62

µA

V

0.881

0.924

0.893

0.936

0.905

0.948

Rising

V

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5

ISL95813

Electrical Specifications Operating Conditions: VDD = 5V, T = -10°C to +100°C or -40°C to +100°C, f = 700kHz, unless otherwise

A

SW

noted. Boldface limits apply over the operating temperature range for High Temp Commercial at -10°C to +100°C or Industrial Temp at -40°C to +100°C.

(Continued)

MIN

MAX

PARAMETER

Therm_Alert Trip Voltage

Therm_Alert Reset Voltage

CURRENT MONITOR

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNITS

Falling

Rising

0.92

0.932

0.974

0.944

0.986

V

0.962

IMON Output Current

I

ISUMN pin current = 40µA

ISUMN pin current = 20µA

ISUMN pin current = 4µA

Rising

9.7

10

5

10.3

5.2

µA

V

IMON

4.8

0.875

1.185

1.122

1

1.125

1.215

1.152

I

Alert Trip Voltage

V

1.2

1.14

CCMAX

IMONMAX

Alert Reset Voltage

Falling

V

CCMAX

INPUTS

VR_ON Leakage Current

I

VR_ON = 0V

-1

0

3

1

5

1

µA

VR_ON

VR_ON = 1V

SCLK, SDA Leakage

VR_ON = 0V, SCLK & SDA = 0V & 1V

VR_ON = 1V, SCLK & SDA = 1V

VR_ON = 1V, SCLK & SDA = 0V, SCLK

VR_ON = 1V, SCLK & SDA = 0V, SDA

-1

-5

-42

-21

SLEW RATE (For VID Change)

Fast Slew Rate

Set by R_PROG2

12

3

mV/µs

Slow Slew Rate

NOTES:

Default setting Fast Slew divided by 4

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

7. Limits established by characterization and are not production tested.

FN8449.0

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6

ISL95813

Gate Driver Timing Diagram

PWM

t

LGFUGR

t

FU

t

RU

1V

UGATE

LGATE

1V

t

RL

t

FL

t

UGFLGR

Typical Performance Waveforms (V = 19V, 700kHz, PRO)

IN

VID = 1.8V

FIGURE 2. PS0, 1-35A LOAD RELEASE

FIGURE 3. PS0, 1-35A HIGH REP LOAD TRANSIENT

VID = 1.8V

FIGURE 4. PS0, 1-35A LOAD INSERTION

FIGURE 5. PS3 TO PS0, 1-35A TRANSIENT

53mV/µs

10A LOAD

53mV/µs

10A LOAD

FIGURE 6. PS0, SET VID FAST FROM 1.6V TO 1.8V

FIGURE 7. PS0, SET VID FAST FROM 1.8V TO 1.6V

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ISL95813

Typical Performance Waveforms (V = 19V, 700kHz, PRO)

IN

13.5mV/µs

10A LOAD

13.5mV/µs

10A LOAD

FIGURE 8. PS0, SET VID FAST FROM 1.6V TO 1.8V

FIGURE 9. PS0, SET VID FAST FROM 1.8V TO 1.6V

FIGURE 10. PS4 EXIT TO 1.6V, IO = 1A, SLEWRATE = 53mV/µs

TEMP

MONITOR

NTC

T_MONITOR

PROG

VR_HOT#

PRGM1

PRGM2

IMAX

VBOOT

DROOP

VIN

IDROOP

DAC

VR_ON

SDA

A/D

VCC

D/A

DIGITAL

INTERFACE

ALERT#

SCLK

MODE

BOOT

DRIVER

UGATE

PHASE

COMP

+

LGATE

+

R3

RTN

FB

+

_

Σ

MODULATOR

E/A

IDROOP

ISUMP

ISUMN

+

_

CURRENT

SENSE

IMON

GND

OC FAULT

PGOOD

OV FAULT

FIGURE 11. BLOCK DIAGRAM

FN8449.0

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8

ISL95813

turns off LGATE when the phase node voltage reaches zero to

prevent the inductor current from reversing direction.

Theory of Operation

3™

R

Modulator

3™

If the load current reaches the critical conduction point the

inductor current will reach and stay at zero before the next phase

node pulse and the regulator is in discontinuous conduction

mode (DCM). Should the load current rise above the critical

conduction point, the inductor current will not cross 0A in a

switching cycle, and the regulator is in CCM although the

controller is in DE mode.Equation 1 below gives the formula for

The R Modulator is Intersil’s proprietary synthetic current-

mode hysteretic controller and is a blend of fixed frequency PWM

and variable frequency hysteretic control technology. This

modulator topology offers high noise immunity and a rapid

transient response to dynamic load scenarios. Under static

conditions the desired switching frequency is maintained within

the entire specified range of input voltages, output voltages, and

load currents. During load transients the controller will increase

or decrease the PWM pulses and switching frequency to

maintain output voltage regulation. Figure 12 illustrates this

effect during a load insertion. As the window voltage starts to

climb from a load step the time between PWM pulses decreases

critical conduction, where I

is the load current for critical

critical

conduction and ΔI is the ripple on the inductor current.

L

ΔI

L

(EQ. 1)

-------

I

=

critical

2

Figure 14 shows the operation principle in diode emulation mode

at light load. The load gets incrementally lighter in the three cases

from top to bottom. The PWM on-time is determined by the VW

window size, therefore is the same, making the peak inductor

current the same in the three cases. The controller clamps the

synthetic current DE mode to make it mimic the inductor current. It

takes the synthesized current longer to hit the lower window

voltage, naturally stretching the switching period. The inductor

current triangles move further apart from each other such that the

inductor current average value is equal to the load current. By

reducing the switching frequency in DE mode switching losses are

decreased and light load efficiency is improved.

as f

increases to keep the output within regulation.

SW

WINDOW VOLTAGE V

W

SYNTHETIC CURRENT SIGNAL

(WRT V

)

COMP

ERROR AMPLIFIER

CCM/DCM BOUNDARY

VW

VOLTAGE V

COMP

SYNTHETIC

CURRENT

PWM

I_L

LIGHT DCM

VW

FIGURE 12. MODULATOR WAVEFORMS DURING LOAD TRANSIENT

SYNTHETIC

CURRENT

Diode Emulation and Period Stretching

I_L

DEEP DCM

VW

V O U T

P H A S E

SYNTHETIC

CURRENT

U G A TE

LG A TE

I_L

FIGURE 14. PERIOD STRETCHING

IL

ECO and PRO Mode DCM

The ISL95813 has the ability to set both ECO and PRO mode DCM

FIGURE 13. DIODE EMULATION

options for 700kHz switching applications. In ECO mode the time

The ISL95813 can operate in diode emulation (DE) mode to

improve light load efficiency. In DE mode, the low-side MOSFET

conducts only when the current is flowing from source to drain and

does not allow reverse current, emulating a diode like a standard

buck regulator. As Figure 13 shows, when LGATE is on, the low-side

MOSFET conducts, creating negative voltage on the phase node

due to the voltage drop across the ON-resistance. The controller

monitors the current through monitoring the phase node voltage. It

1

from Upper Gate On to Lower Gate Off is set to /

or

700kHz

1.43µs. When PRO mode is selected the UG On to LG Off time is

1

reduced to /

or 1.0µs. For applications where efficiency is

1MHz

important ECO mode should be implemented as the longer

switching times reduce the amount of switching loss in the FETs.

PRO mode is ideal for applications that require lower DCM ripple

as the shorter gate times reduce the amount of output ripple.

Because of the reduced ripple in PRO mode the amount of output

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9

ISL95813

TABLE 1. VID TABLE (Continued)

VID

capacitance can be reduced, saving both board space and BOM

costs.

V

(V)

O

See “PROGRAM 1 RESISTOR VALUES” on page 13 for the

ECO/PRO programming resistor options.

7

0

6

0

5

0

1

4

0

1

0

1

3

1

0

1

0

1

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hex

VR12.6

0.62000

0.63000

0.64000

0.65000

0.66000

0.67000

0.68000

0.69000

0.70000

0.71000

0.72000

0.73000

0.74000

0.75000

0.76000

0.77000

0.78000

0.79000

0.80000

0.81000

0.82000

0.83000

0.84000

0.85000

0.86000

0.87000

0.88000

0.89000

0.90000

0.91000

0.92000

0.93000

0.94000

0.95000

0.96000

0.97000

0.98000

0.99000

1.00000

0

1

2

3

D

E

F

Start-up Timing

With the controller's V voltage above the POR threshold, the

DD

start-up sequence begins when VR_ON exceeds the logic high

threshold. Figure 15 shows the typical start-up timing. The

controller uses digital soft-start to ramp-up DAC to the voltage

programmed by the SetVID command. PGOOD is asserted high

and ALERT# is asserted low at the end of the ramp up. Similar

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

results occur if VR_ON is tied to V , with the soft-start sequence

DD

starting 1.1ms after V crosses the POR threshold.

DD

VDD

SLEW RATE

DVID-SLOW

VR_ON

VID

COMMAND

VOLTAGE

V_BOOT

1.1ms

DAC

PGOOD

ALERT#

…...

FIGURE 15. SOFT-START WAVEFORMS

Voltage Regulation and Load Line

Implementation

After the start-up sequence, the controller regulates the output

voltage to the value set by the VID information in Table 1. The

controller will control the no-load output voltage to an accuracy of

±0.5% over the VID voltage range. A differential amplifier allows

voltage sensing for precise voltage regulation at the

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

microprocessor die. Current silicon maximum VID is set as 2.3V,

and any VID command above 2.3V will be rejected.

TABLE 1. VID TABLE

VID

V (V)

O

7

0

6

0

5

0

4

0

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Hex

VR12.6

0.00000

0.50000

0.51000

0.52000

0.53000

0.54000

0.55000

0.56000

0.57000

0.58000

0.59000

0.60000

0.61000

0

1

2

3

4

5

6

7

8

9

A

B

C

0

1

2

3

FN8449.0

May 15, 2013

10

ISL95813

TABLE 1. VID TABLE (Continued)

VID

TABLE 1. VID TABLE (Continued)

VID

V

(V)

V (V)

O

7

0

6

0

1

5

1

0

4

1

0

1

3

0

1

0

1

0

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Hex

VR12.6

1.01000

1.02000

1.03000

1.04000

1.05000

1.06000

1.07000

1.08000

1.09000

1.10000

1.11000

1.12000

1.13000

1.14000

1.15000

1.16000

1.17000

1.18000

1.19000

1.20000

1.21000

1.22000

1.23000

1.24000

1.25000

1.26000

1.27000

1.28000

1.29000

1.30000

1.31000

1.32000

1.33000

1.34000

1.35000

1.36000

1.37000

1.38000

1.39000

7

0

1

6

1

0

5

0

1

0

4

1

0

1

0

3

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hex

VR12.6

1.40000

1.41000

1.42000

1.43000

1.44000

1.45000

1.46000

1.47000

1.48000

1.49000

1.50000

1.51000

1.52000

1.53000

1.54000

1.55000

1.56000

1.57000

1.58000

1.59000

1.60000

1.61000

1.62000

1.63000

1.64000

1.65000

1.66000

1.67000

1.68000

1.69000

1.70000

1.71000

1.72000

1.73000

1.74000

1.75000

1.76000

1.77000

1.78000

3

4

5

4

5

6

7

8

9

A

B

C

D

E

F

5

6

7

8

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

0

1

FN8449.0

May 15, 2013

11

ISL95813

TABLE 1. VID TABLE (Continued)

VID

TABLE 1. VID TABLE (Continued)

VID

V

(V)

V (V)

O

7

1

6

0

5

0

1

4

0

1

0

3

0

1

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Hex

VR12.6

1.79000

1.80000

1.81000

1.82000

1.83000

1.84000

1.85000

1.86000

1.87000

1.88000

1.89000

1.90000

1.91000

1.92000

1.93000

1.94000

1.95000

1.96000

1.97000

1.98000

1.99000

2.00000

2.01000

2.02000

2.03000

2.04000

2.05000

2.06000

2.07000

2.08000

2.09000

2.10000

2.11000

2.12000

2.13000

2.14000

2.15000

2.16000

2.17000

7

1

6

0

5

1

4

0

1

3

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hex

VR12.6

2.18000

2.19000

2.20000

2.21000

2.22000

2.23000

2.24000

2.25000

2.26000

2.27000

2.28000

2.29000

2.30000

8

9

A

2

3

4

5

6

7

8

9

A

B

C

D

E

F

A

B

9

A

B

C

D

E

F

0

1

2

3

4

5

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Rdroop

Vdroop

VCC_SENSE

VR LOCAL

CATCH

RESISTOR

FB

VO

Idroop

COMP

E/A

VIDs

VID

DAC

X 1

Σ

VDAC

RTN

GND

VSS_SENSE

INTERNAL

TO IC

CATCH

RESISTOR

FIGURE 16. DIFFERENTIAL SENSING AND LOAD LINE

IMPLEMENTATION

As the load current increases from zero, the output voltage will

droop from the VID table value by an amount proportional to the

load current to achieve the load line. The controller can sense the

inductor current through the intrinsic DC Resistance (DCR) of the

inductors as shown in the Typical Applications Diagram or through a

current sense resistor in series with the inductor (Figure 24). In both

methods, the capacitor C voltage represents the inductor total

current. A droop amplifier converts C voltage into an internal

current source with the gain set by resistor R . The current source is

used for load line implementation, current monitor and overcurrent

protection.

n

0

1

2

3

4

5

6

7

8

n

i

V

Cn

(EQ. 2)

----------

I

=

droop

R

i

When using inductor DCR current sensing, a single NTC element

is used to compensate the positive temperature coefficient of the

copper winding thus sustaining the load line accuracy with

reduced cost.

FN8449.0

May 15, 2013

12

ISL95813

I

flows through resistor R

droop

and creates a voltage drop as

PROGRAM 1 Pin

droop

shown in Equation 3.

PRGM1 programs I

register and switching frequency. For

CCMAX

V

= R

× I

droop droop

(EQ. 3)

proper operation, it is recommended the 1% resistor value called

out in the table be used in the final application.

droop

V

is the droop voltage required to implement load line.

droop

TABLE 2. PROGRAM 1 RESISTOR VALUES

Changing R

or scaling I

can both change the load line

also sets the overcurrent protection level, it is

droop

slope. Since I

droop

R_PROG1

(±3%, kΩ)

I

f

SW

(kHz)

CCMAX

(A)

recommended to first scale I

then select an appropriate R

load line slope.

based on OCP requirement,

value to obtain the desired

droop

1.0

5.76

9.31

13.3

17.4

21

17

21

28

33

35

40

17

21

28

33

35

40

17

21

28

33

35

40

17

21

28

33

35

40

Differential Voltage Sensing

Figure 16 also shows the differential voltage sensing scheme.

VCC

from the processor die. A unity gain differential amplifier senses

the VSS voltage and add it to the DAC output. The error

amplifier regulates the inverting and the non-inverting input

voltages to be equal as shown in Equation 4:

425

and VSS are the remote voltage sensing signals

SENSE

24.9

28.7

33

(EQ. 4)

(EQ. 5)

VCC

+ V

= V

+ VSS

DAC SENSE

SENSE

droop

Rewriting Equation 4 and substitution of Equation 3 gives

550

42.2

49.9

57.6

64.9

73.2

80.6

90.9

102

113

124

137

154

169

187

205

VCC

– VSS

= V

– R

× I

droop droop

SENSE

DAC

Equation 5 is the exact equation required for load line

implementation.

The VCC

SENSE

and VSS signals come from the processor die.

SENSE

The feedback will be open circuit in the absence of the processor. As

Figure 16 shows, it is recommended to add a “catch” resistor to feed

the VR local output voltage back to the compensator, and add

another “catch” resistor to connect the VR local output ground to the

RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage

feedback if the system is powered up without a processor installed.

700 ECO

CCM Switching Frequency

The PROG2 pin configures the CCM switching frequency. When

the ISL95813 is in continuous conduction mode (CCM), the

switching frequency is not absolutely constant due to the nature

700 PRO

3

of the R ™ modulator. Section “R3™ Modulator” on page 9

explains that the effective switching frequency will increase

during load insertion and will decrease during load release to

achieve fast response. On the other hand, the switching

frequency is relatively constant at steady state. Variation is

expected when the power stage condition, such as input voltage,

output voltage, load, etc. changes. The variation is usually less

than 15% and doesn’t have any significant effect on output

voltage ripple magnitude.

PROGRAM 2 Pin

PRGM2 pin programs the both boot up voltage V

VID Slew Rate. For proper operation, it is recommended the 1%

resistor value called out in the table be used in the final

application.

, and the

BOOT

TABLE 3. PROGRAM 2 RESISTOR VALUES

VID Slew

R_PROG2 (±3%, kΩ)

V

(V)

BOOT

0

(mV/µs)

12

1.0

5.76

9.31

13.3

1.65

1.7

1.75

FN8449.0

May 15, 2013

13

ISL95813

TABLE 3. PROGRAM 2 RESISTOR VALUES (Continued)

SetVID_fast command prompts the controller to enter CCM and

to actively drive the output voltage to the new VID value at a

minimum 12mV/µs slew rate or the fast slew rate set by

R_PROG2.

VID Slew

(mV/µs)

R_PROG2 (±3%, kΩ)

V

(V)

BOOT

17.4

21

1.75

1.7

1.65

0

SetVID_slow command prompts the controller to enter CCM and

to actively drive the output voltage to the new VID value at a

minimum 3mV/µs slew rate.

24

40

45

53

80

24.9

28.7

33

SetVID_decay command prompts the controller to enter DE

mode. The output voltage, V

, will decay down to the new VID

0

core

value at a slew rate determined by the load as shown in

Equation 6.

42.2

49.9

57.6

64.9

73.2

80.6

90.9

102

113

124

137

154

169

187

205

1.65

1.7

1.75

1.7

1.65

0

dV

I

out

core

------------------

------------

=

(EQ. 6)

dt

C

out

Overvoltage protection is blanked during VID down transition in

DE mode until the output voltage is within 60mV of the VID value.

If the voltage decay rate is too fast, the controller will limit the

voltage slew rate at SetVID_slow slew rate.

ALERT# will be asserted low at the end of SetVID_fast and

SetVID_slow VID transitions.

0

1.65

1.7

1.75

1.7

1.65

0

S e tV ID _ d e c a y

S e tV ID _ fa s t/s lo w

V o

V ID

t_ a le rt

t3

t1

t2

A L E R T #

Power State Modes

FIGURE 17. SETVID DECAY PRE-EMPTIVE BEHAVIOR

Table 4 shows the power state operation mode.

Figure 17 shows SetVID Decay Pre-Emptive behavior. The

controller receives a SetVID_decay command at t1. The VR

enters DE mode and the output voltage Vo decays down slowly.

At t2, before Vo reaches the intended VID target of the

SetVID_decay command, the controller receives a SetVID_fast (or

SetVID_slow) command to go to a voltage higher than the actual

Vo. The controller will react immediately and slew Vo to the new

target voltage at the slew rate specified by the SetVID command.

At t3, Vo reaches the new target voltage and the controller

asserts the ALERT# signal.

TABLE 4. POWER STATE OPERATION MODE

POWER STATE

CONFIGURATION

1-phase CCM

PS0

PS1

PS2

PS3

PS4

1-phase CCM

1-phase DE

Very low power state

3™

The R modulator intrinsically has voltage feed-forward. The

output voltage is insensitive to a fast slew rate input voltage

change.

For PS0 and PS1, the ISL95813 operates in CCM while in PS2

and PS3 the device enters DCM.

In PS4, ISL95813 enters a very low power state and shuts down

all the drivers and internal circuits. In this mode the controller

only accepts SetVID-fast and SetVID-slow commands, all other

SVID commands will be rejected. ISL95813 quiescent power is

about 0.5mW in PS4.

Current Monitor

The controller provides the current monitor function. IMON pin

reports the inductor current.

The IMON pin outputs a high-speed analog current source that is

1/4 of the droop current flowing out of the FB pin. Thus

becoming Equation 7:

Dynamic Operation

I

= 0.25 × I

(EQ. 7)

The ISL95813 responds to VID changes by slewing to the new

voltage at a slew rate indicated in the SetVID command. There

are three SetVID slew rates, namely SetVID_fast, SetVID_slow

and SetVID_decay.

IMON

droop

As the Typical Applications Diagram shows in Figure 1, a resistor

is connected to the IMON pin to convert the IMON pin

R

imon

FN8449.0

May 15, 2013

14

ISL95813

current to voltage. A capacitor should be paralleled with R

imon

to

All the above fault conditions can be reset by toggling VR_ON low.

When VR_ON is brought back to its high operating levels a

soft-start will occur.

filter the voltage information. This voltage is sampled with an

internal ADC to produce a digital IMON signal that can be read

through the serial communications bus.

Table 5 summarizes the fault protections.

The IMON pin voltage range is 0V to 1.2V. The controller monitors

the IMON pin voltage and considers that ISL95813 has reached

TABLE 5. FAULT PROTECTION SUMMARY

FAULT DURATION

I

when IMON pin voltage is 1.2V.

CCMAX

BEFORE

FAULT

RESET

FAULT TYPE

Overcurrent

PROTECTION

PROTECTION ACTION

PWM tri-state,

Adaptive Body Diode Conduction Time

Reduction

In DCM, the controller turns off the low-side MOSFET when the

inductor current approaches zero. During on-time of the low-side

MOSFET, the phase node sits at a negative voltage equal to the

120µs

VR_ON

PGOOD latched low toggle or

VDD toggle

Overvoltage

+300mV

Immediately

PGOOD latched low.

Actively pulls the

output voltage to

below VID value, then

tri-state.

MOSFET r

voltage drop. A phase comparator inside the

DSON

controller monitors the phase voltage during the on-time of the

low-side MOSFET and compares it against a threshold to

determine the zero-crossing point of the inductor current. Should

the inductor current not reach zero when the lower FET turns off,

it will then flow through the low-side MOSFET body diode,

decreasing the voltage on the phase node until the inductor

current completely decays to zero. When the inductor current

finally reaches 0A phase is considered to be in tri-state mode and

Supported Data And Configuration Registers

The controller supports the following data and configuration

registers.

TABLE 6. SUPPORTED DATA AND CONFIGURATION

REGISTERS

its voltage floats to the set V

value.

OUT

REGISTER

NAME

DEFAULT

VALUE

INDEX

DESCRIPTION

If the inductor current has crossed zero and reversed the

direction when the low-side MOSFET turns off, current will then

flow through the high-side MOSFET body diode, causing a voltage

spike on phase which will decay to the set V

tri-states.

00h Vendor ID

Uniquely identifies the VR vendor.

Assigned by Intel.

12h

voltage as phase

OUT

01h Product ID

Uniquely identifies the VR product.

Intersil assigns this number.

0Ch

The controller continues monitoring the phase voltage after turning

off the low-side MOSFET and adjusts the phase comparator

threshold voltage accordingly in iterative steps such that the low-

side MOSFET body diode conducts for approximately 30ns to

minimize the body diode-related loss.

02h Product

Revision

Uniquely identifies the revision of the VR 04h

control IC. Intersil assigns this data.

05h Protocol ID Identifies what revision of SVID protocol 03h

the controller supports.

06h Capability

Identifies the SVID VR capabilities and 81h

which of the optional telemetry registers

are supported.

Protection

The ISL95813 provides the designer with overcurrent, overvoltage,

and over-temperature protection.

10h Status_1

Data register read after ALERT# signal. 00h

Indicating if a VR rail has settled, has

reached VR_HOT# condition or has

The controller determines overcurrent protection (OCP) by

comparing the average value of the droop current I

with an

droop

reached I

.

CCMAX

internal current source threshold as Table 5 shows. It declares OCP

when I is above the threshold for 120µs.

11h Status_2

Data register showing Status_2

communication.

00h

droop

For over temperature and overcurrent faults, the controller takes

the same actions: de-assertion of PGOOD and turn-off of all the

high-side and low-side power MOSFETs. Any residual inductor

current will decay through the MOSFET body diodes or load.

12h Temperature Data register showing temperature

Zone

zones that have been entered.

1Ch Status_2_

LastRead

This register contains a copy of the

Status_2 data that was last read with

the GetReg (Status_2) command.

The controller will declare an overvoltage fault and de-assert PGOOD

if the output voltage exceeds the VID set value by +300mV. The

controller will immediately declare an OV fault, toggle PGOOD to

ground. The low-side power MOSFET remains on until the output

voltage is pulled down below the VID set value before being shut

off, and placing phase into tri-state. If the output voltage rises

above the VID set value +300mV again, the protection process is

repeated. This behavior provides the maximum amount of

protection against shorted high-side power MOSFETs while

preventing output ringing below ground.

21h

I

Data register containing the I

CCMAX

platform supports, set at start-up by

the Set by

R_PROG1

CCMAX

resistors R_PROG1. The platform design

engineer programs this value during the

design process. Binary format in amps,

i.e., 100A = 64h

24h SR-fast

Slew Rate Normal. The fastest slew rate Set by

the platform VR can sustain. Binary

format in mV/µs. i.e., 0Ch = 12mV/µs.

R_PROG2

FN8449.0

May 15, 2013

15

ISL95813

Key Component Selection

TABLE 6. SUPPORTED DATA AND CONFIGURATION

REGISTERS (Continued)

Inductor DCR Current-Sensing Network

REGISTER

NAME

DEFAULT

VALUE

INDEX

DESCRIPTION

25h SR-slow

Default is 4x slower than normal. Binary Set by

Phase

format in mV/us. i.e., 03h = 3mV/µs.

Can be configured by register 2Ah.

R_PROG2

and

Register

2Ah

Rsum

26h

V

If programmed by the platform, the VR Set by

supports V voltage during start-up R_PROG2

BOOT

ISUMP

BOOT

ramp. The VR will ramp to V

and

BOOT

until it receives a new

hold at V

BOOT

L

Rntcs

Rntc

SetVID command to move to a different

voltage.

Cn

Vcn

Rp

2Ah Slow slew

01h = 1/2 of fast slew rate

02h

rate selector 02h = 1/4 of fast slew rate

DCR

Io

04h = 1/8 of fast slew rate

08h = 1/16 of fast slew rate

Ri

ISUMN

2Bh PS4 exit

latency

Report 48µs

76h

38h

C2h

2Ch PS3 exit

latency

FIGURE 18. DCR CURRENT-SENSING NETWORK

Figure 18 shows the inductor DCR current-sensing network for a

single phase solution. This loop monitors the voltage drop across

the DCR creating by current flowing in the inductor and feeds that

2Dh Enable to

VR_Ready

latency

information to the ISL95813 for I

and load line purposes.

MON

30h

V

max

This register is programmed by the

master and sets the maximum VID the

VR will support. If a higher VID code is

received, the VR will respond with “not

supported” acknowledge.

B5h

OUT

The summed inductor current information is presented to the

capacitor C . Equations 8 thru 12 describe the frequency-domain

n

relationship between inductor total current I (s) and C

o

n

voltageV (s):

Cn

31h VID Setting Data register containing currently

programmed VID voltage. VID data

format.

00h

R

⎛

⎞

ntcnet

+ R

sum

-----------------------------------------

× DCR × I (s) × A (s)

⎟

o cs

V

R

(s) =

⎜

⎝

(EQ. 8)

(EQ. 9)

Cn

R

⎠

ntcnet

32h Power State Register containing the current

programmed power state.

(R

+ R ) × R

ntc p

ntcs

----------------------------------------------------

=

ntcnet

R

+ R

ntc p

ntcs

33h Voltage

Offset

Sets offset in VID steps added to the VID 00h

setting for voltage margining. Bit 7 is a

sign bit, 0 = positive margin,

1 = negative margin. Remaining 7 bits

are # VID steps for the margin.

00h = no margin,

s

------

1 +

ω

L

----------------------

(EQ. 10)

A

(s) =

cs

L

s

------------

1 +

ω

sns

DCR

-------------

=

ω

01h = +1 VID step

02h = +2 VID steps...

(EQ. 11)

(EQ. 12)

L

1

-------------------------------------------------------

=

34h Multi VR

Config

Data register that configures multiple

VRs behavior on the same SVID bus.

00h

sns

R

× R

sum

+ R

sum

ntcnet

-----------------------------------------

× C

n

R

ntcnet

35h SetRegADR Serial data bus communication address 00h

In the DCR network, transfer function A (s) has unity gain at DC. As

c

winding temperature increases, the DCR of the inductor increases

which causes a higher reading of the DC current flowing through the

inductor. To compensate for this effect, the resistance of the NTC

R

decreases as its temperature increases. Choosing the

ntc

remaining components of the DCR network correctly ensures that

the capacitor voltage V accurately represents the total DC current

cn

through the inductor over the entire operating temperature range.

It is recommended when designing the DCR network to maintain

V

as the highest feasible fraction of the voltage that is dropped

cn

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May 15, 2013

16

ISL95813

across the inductor’s DCR in order to ensure the droop circuitry on

chip has a high signal level to operate with.

i

While final component values should be fine tuned for a given

application, a good starting point for the DCR temperature

compensation network is as follows: Rsum = 3.65kΩ, Rp = 11kΩ,

Rntcs = 2.61kΩ, and Rntc = 10kΩ (ERT-J1VR103J). To check the

operation of the compensation network apply the full load DC

current and record the output voltage both immediately and once

the circuit has reached its thermal equilibrium. A well designed

NTC network can limit the amount of drift on the output voltage

to within 2 mV.

o

V

o

FIGURE 20. LOAD TRANSIENT RESPONSE WHEN C IS TOO SMALL

n

In order to achieve proper transient response it is also crucial that

V

(s) represents real-time I (s) of the controller. This is done by

Cn

o

matching the pole and zero present in A (s) to one another which

cs

sets the transfer function to unity gain for all frequencies. To ensure

i

o

unity gain force ω equal to ω

and solve for C as seen in

L

sns

n

Equation 13.

L

--------------------------------------------------------------

C

=

(EQ. 13)

n

R

× R

sum

ntcnet

-----------------------------------------

× DCR

R

+ R

sum

V

ntcnet

o

For example, with R

= 3.65kΩ, R = 11kΩ, R

= 2.61kΩ,

sum

p

ntcs

R

= 10kΩ, DCR = 1mΩ, and L = 0.2µH, Equation 13 gives

FIGURE 21. LOAD TRANSIENT RESPONSE WHEN C IS TOO LARGE

n

ntc

C = 0.088µF.

n

With proper compensator design, Figure 19 shows the expected

load transient response waveforms. When the load current i has a

i

o

i

L

square change, the output voltage V also has a square response.

o

If C value is too large or too small, V (s) will not accurately

Cn

n

represent real-time i (s) and the transient response of the controller

o

will degrade. When C is too small, V will sag excessively as seen in

n

o

V

o

Figure 20 and potentially trigger a system failure. Figure 21 shows

the transient response when C is sized too large. In this case V will

RING

BACK

n

o

reach its expected droop voltage much too slowly with respect to the

load insertion. Should a load release occur during this time there will

be excessive overshoot on V which may potentially hurt CPU

o

FIGURE 22. OUTPUT VOLTAGE RING BACK PROBLEM

reliability.

Figure 22 gives an example of ring back on the output voltage

during load transient response. Ring back occurs when the load

i

o

current i has a fast step change, but the inductor current i

o

L

cannot accurately track it. Instead, i responds in a first order

L

fashion due to the nature of current loop. Instead of the output

accurately responding to the load insertion the parasitic ESR and

ESL properties of the output capacitors cause an abrupt dip in

V

o

the voltage. However, the controller regulates V according to the

o

droop current i

, which is a real-time representation of i ;

L

droop

therefore it pulls V back to the level dictated by i , introducing

o

L

the ring back into the response. This phenomenon can be

mitigated through the use of very low ESR and ESL ceramic

capacitors for the output filter.

FIGURE 19. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

Figure 23 shows two circuits for ring back reduction that can be

used in conjunction with low parasitic output filter components if

need be. Normally C , the capacitor used to match the inductor

n

time constant, is implemented through the parallel combination

of two or more capacitors shown in Figure 23 as C and C

.

n.1 n.2

The first option to reduce ring back is to add resistor R in series

n

to C . At steady state operation C + C provide the desired

n.1 n.1 n.2

C capacitance calculated from Equation 11. At the beginning of

n

i change however, the effective capacitance of the matching

o

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May 15, 2013

17

ISL95813

network is less because R increases the impedance of the C

Resistor Current-Sensing Network

n

n.1

branch. As Figure 20 explains, V tends to dip when C is too

o

n

small which will reduce the amount of ring back seen during load

transients. This effect is more pronounced when C is larger

Phase

n.1

than C as well as when the value of R is increased. However,

n.2

when designing the final circuit, care should be taken not to

make R larger than necessary or make C much larger than

n

L

n

n.1

C

or else excessive ripple will be seen on V . It is

n.2

cn

recommended to keep C greater than 2200pF and R in the

DCR

n.2

n

range of only few ohms. The final values of C , C and R

should be determined through tuning the load transient response

waveforms on an actual board to be used in the end application.

n.1 n.2

n

ISUMP

Rsum

Cn

Vcn

Ri

The second method for ring back reduction is to add the series

Rsen

combination of R and C in parallel with R . These components

ip ip

i

should be sized to provide a lower impedance path than R alone at

i

the beginning of an i transient. During steady state operation R

o

ip

ISUMN

and C do not have any effect on the controller’s operation. Through

ip

Io

proper selection of R and C values, i

can more closely

resemble i rather than i , and ring back on the output voltage will

ip ip droop

o

L

not be seen. The recommended value for R is 100Ω. while the

recommended range for C is 100pF to 2000pF though final values

ip

should be tuned to the final end product board. It should be noted

ip

FIGURE 24. RESISTOR CURRENT-SENSING NETWORK

Above is an example of using a resistor sense method of sensing

load current instead of SCR sensing. In this method, the inductor

that the R -C branch may distort the i

signal by introducing

ip ip droop

current creates a voltage across R

averaged by the RC filter composed of R

sum

which is then filters and

and C . The results

sen

sharp spikes to the normally triangular waveform which may

adversely affect the average value detection and therefore may

affect OCP accuracy. Discretion is recommended when

implementing this second ring back reduction method in order to

maintain a robust system.

n

voltage, V , is then fed into the current sense amplifier on chip

cn

through the ISUMP and ISUMN pins. No NTC network is needed in

this scenario because the value of the current sensing resistor, R

,

sen

will not vary appreciably over temperature. The design equations for

this method of current sensing are given in Equations 14 through

16.

ISUMP

(EQ. 14)

V

A

(s) = R

(s) =

× I (s) × A

(s)

Rsen

Cn

sen

o

Rntcs

Cn.1

1

---------------------------

(EQ. 15)

(EQ. 16)

Rsen

s

-----------------

1 +

Vcn

Cn.2

Rp

ω

Rsen

Rn

Rntc

1

----------------------------

ω

=

Rsen

R

× C

n

sum

ISUMN

Ri

OPTIONAL

Recommended values for R

respectively. As with the DCR method, final values should be

tuned in on the actual application board.

and C are 1kΩ and 5600pF

n

sum

Cip

Rip

OPTIONAL

Overcurrent Protection

Refer to Equation 2 on page 12 and Figures 18, 22 and 25;

FIGURE 23. OPTIONAL CIRCUITS FOR RING BACK REDUCTION

resistor R sets the droop current I

. Table 5 shows the

i

droop

internal OCP threshold. It is recommended to design I

droop

without using the R

resistor.

comp

For example, assume the OCP threshold is 60µA for 1-phase

solution. We will design I to be 48µA at full load.

droop

From Equation 8 in inductor DCR sensing applications assuming

DC conditions gives the relationship of V (s) to I (s) in

cn

o

Equation 17.

R

ntcnet

+ R

sum

-----------------------------------------

V

=

× DCR × I

Cn

o

(EQ. 17)

R

ntcnet

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May 15, 2013

18

ISL95813

Substituting of Equation 17 into Equation 2 yields Equation 18

I

into Equation 3 and solve for the DC load line, shown in

droop

which can then be solved for R .

Equation 25:

i

R

1

R

ntcnet

V

R

ntcnet

+ R

ntcnet sum

----- -----------------------------------------

i

I

=

×

× DCR × I

(EQ. 18)

(EQ. 19)

droop

o

R

+ R

ntcnet sum

------------------

------------------- -----------------------------------------

× × DCR

LL =

=

(EQ. 25)

I

R

o

i

R

× DCR × I

o

For resistor sensing, substitute Equation 22 into Equation 3 to

get the load line slope expression:

ntcnet

----------------------------------------------------------------------

R =

i

(R

+ R

) × I

sum droop

ntcnet

V

R

× R

sen droop

droop

(EQ. 26)

------------------

---------------------------------------

LL =

=

I

R

i

o

Expanding the R

term using Equation 9 and applying of the

ntcnet

OCP condition in Equation 19 gives the final expression for R in

Equation 20.

To find the value of R

Equation 25 and solve for R

Equation 26 and solve for R

, substitute Equation 19 into

, or substitute Equation 23 into

i

droop

. Both methods give the same

(R

+ R ) × R

ntc p

droop

ntcs

----------------------------------------------------

× DCR × I

result, which is shown in Equation 27:

omax

R

+ R

ntc p

ntcs

-----------------------------------------------------------------------------------------------------------------

R =

(EQ. 20)

i

I

o

(R

+ R ) × R

⎛

⎜

⎝

⎞

ntcs

ntc p

----------------

R

=

× LL

(EQ. 27)

----------------------------------------------------

droop

+ R

× I

droopmax

⎟

I

sum

droop

R

+ R

ntc p

⎠

ntcs

One can use the full load condition to calculate R

droop

. For

where I

is the full load current, I is the

droopmax

omax

example, given I

= 33A, I

= 48µA and LL = 2.0mΩ,

omax

Equation 27 gives R

droopmax

corresponding droop current. For example, given R

= 3.65kΩ,

sum

= 1.37kΩ.

droop

R = 11kΩ, R

ntcs

= 2.61kΩ, R = 10kΩ, DCR = 0.9mΩ,

p

ntc

It is recommended to start with the R

value calculated by

I

= 33A and I

= 48µA, Equation 20 gives

droop

omax

R = 381Ω.

droopmax

Equation 27 and fine tune it on the actual board to get accurate

load line slope. One should record the output voltage readings at

no load and at full load for load line slope calculation. Reading

the output voltage at lighter load instead of full load will increase

the measurement error.

i

When resistor sensing methods are used, assuming DC

conditions in Equation 14 gives the following relationship

between V and I .

cn

o

(EQ. 21)

V

= R

× I

sen o

Cn

Compensator

Figure 19 shows the desired load transient response waveforms

while Figure 25 shows the equivalent circuit of a voltage regulator

(VR) with the droop function. A VR is equivalent to a voltage source

Substituting Equation 21 into Equation 2 gives Equation 22:

1

-----

I

=

× R

× I

sen o

(EQ. 22)

droop

R

i

(VID) and output impedance Z (s). If Z (s) is equal to the load

out out

line slope LL, i.e. constant output impedance, in the entire frequency

Therefore

range, V will have square response when I has a square change.

o

R

× I

o

sen

(EQ. 23)

------------------------

R =

i

Z_out(s) = LL

i

o

I

droop

Assuming the OCP conditions put in place previously in

Equation 23 gives Equation 24:

VR

V

VID

LOAD

o

R

× I

omax

sen

-----------------------------------

R =

(EQ. 24)

i

I

droopmax

FIGURE 25. VOLTAGE REGULATOR EQUIVALENT CIRCUIT

where I

is the full load current, I

is the

omax

droopmax

corresponding droop current. For example, given R

= 1mΩ,

sen

= 48µA, Equation 24 gives

A voltage regulator with an active droop function is a dual-loop

system consisting of a voltage loop and a current based droop

loop, of which neither is sufficient to describe the entire system

alone.

I

= 33A and I

droopmax

omax

R = 687Ω.

i

As before, with the DCR and R

sense

components, the final value

of Ri should be tuned to fit the final application.

Figure 26 conceptually shows T1(s) measurement set-up and

Figure 27 conceptually shows T2(s) measurement set-up. The VR

senses the inductor current, multiplies it by a gain of the load line

slope, then adds it on top of the sensed output voltage and feeds it

to the compensator. T(1) is measured after the summing node,

and T2(s) is measured in the voltage loop before the summing

node.

Load Line Slope

For this section please refer to Figure 16 on page 12.

In order to calculate the load line in DCR sense applications start

by substituting Equation 8 into Equation 2 to give a more detailed

expression for I

. Next, substitute the new expression for

droop

T1(s) is the total loop gain of the voltage loop and the droop loop.

It always has a higher crossover frequency than T2(s) and has

more meaning of system stability. T2(s) is the voltage loop gain

FN8449.0

May 15, 2013

19

ISL95813

with closed droop loop. It has more meaning of output voltage

response. Only T2(s) can be actually measured in a laboratory

setting on the ISL95813 regulator.

Next, substitute Equation 29 into Equation 28 giving the final

expression for V

.

Rimon

0.25I × LL

o

-----------------------------

V

=

× R

(EQ. 30)

Rimon

imon

R

droop

Typically, one should design the compensator to get stable T1(s)

and T2(s) with sufficient phase margin, and output impedance

equal or smaller than the load line slope.

Assuming I = I

omax

for choosing the value of R

and rewriting Equation 30 gives Equation 31

o

.

imon

V_O

L

V

× R

droop

Rimon

----------------------------------------------

R

=

(EQ. 31)

= 1.2V

imon

0.25I × LL

Q1

o

I_O

Q2

V_IN

GATE

C_OUT

For example, given LL = 2.0mΩ, R

= 1.37kΩ, V

Rimon

droop

= 33A, Equation 31 gives R

DRIVER

at I

= 100kΩ. The results

omax

imon

from Equation 29 should be treated as a starting point for the

design and the resistor value should be finalized on an actual

application board.

LOAD LINE SLOPE

Ω

20

COMP

A capacitor C

imon

should be but in parallel with R to filter the

imon

EA

MOD.

IMON pin voltage. It is recommended to have a time constant long

enough to remove any switching frequency ripples from the IMON

signal.

VID

ISOLATION

TRANSFORMER

CHANNEL B

CHANNEL A

LOOP GAIN =

Slew Rate Compensation Circuit For VID

Transition

CHANNEL A

NETWORK

ANALYZER

CHANNEL B

EXCITATION OUTPUT

FIGURE 26. LOOP GAIN T1(s) MEASUREMENT SET-UP

Rdroop

Vcore

Cvid

V_O

Rvid

L

OPTIONAL

Q1

FB

Ivid

Idroop_vid

I_O

V

IN

GATE Q2

DRIVER

C_OUT

COMP

E/A

VIDs

VID

DAC

LOAD LINE SLOPE

COMP

Σ _VDAC

Ω

20

RTN

VSS

VSS_SENSE

MOD.

EA

X 1

VID

ISOLATION

TRANSFORMER

INTERNAL TO IC

CHANNEL B

CHANNEL A

LOOP GAIN =

VID

Vfb

Ivid

CHANNEL A

CHANNEL B

NETWORK

ANALYZER

EXCITATION OUTPUT

FIGURE 27. LOOP GAIN T2(s) MEASUREMENT SET-UP

Current Monitor

Refer to Equation 7 on page 14 for the IMON pin current

expression.

Vcore

Looking at the “TYPICAL 40Amax, 12.6, APPLICATION DIAGRAM”

on page 1, the current flowing from the IMON pin goes through

R

creating a voltage V . The expression for voltage is

imon

expressed in Equation 28:

Rimon

Idroop_vid

(EQ. 28)

V

= 0.25 × I

× R

Rimon

droop imon

FIGURE 28. SLEW RATE COMPENSATION CIRCUIT FOR VID

TRANSITION

To expand this expression, first solve Equation 27 for I

Equation 29:

giving

droop

During a large VID transition, the DAC steps through the VIDs at a

controlled slew rate while maintaining an output voltage, V

rate of 10mV/µs.

I

o

-------------------

droop

I

=

× LL

slew

(EQ. 29)

droop

core,

R

FN8449.0

May 15, 2013

20

ISL95813

Figure 28 shows the waveforms of VID transition. During VID

transition, the output capacitor is being charged and discharged,

causing C x dV /dt current on the inductor. The controller

VR Temperature

3% Hysteresis

Temp Zone

Bit 7 =1

1111 1111

0111 1111

0011 1111

0001 1111

7

out core

senses the inductor current increase during the up transition (as

the I waveform shows) and will droop the output voltage

1

10

Bit 6 =1

Bit 5 =1

droop_vid

accordingly, making V

occurs during the down transition. To get the correct V

V

slew rate slow. Similar behavior

slew

core

12

rate during VID transition, one can add the R to C branch,

vid vid

Temp Zone

Register

whose current I cancels I

.

vid

droop_vid

2

8

0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111

It’s recommended to choose the R and C values from the

vid vid

reference design as a starting point. Then tweak the actual

values on the board to get the best performance.

Status 1

Register

3

= “001”

= “011”

= “001”

13

14

15

5

GerReg

Status1

GerReg

Status1

SVID

During normal transient response, the FB pin voltage is held

constant, therefore is virtual ground in small signal sense. The

ALERT#

6

4

16

R

to C network is between the virtual ground and the real

vid

ground, and hence has no effect on transient response.

VR_HOT#

9

11

VR_HOT#/ALERT# Behavior

FIGURE 29. VR_HOT#/ALERT# BEHAVIOR

The ISL95813 sources 60µA of current out of the NTC pin at

1kHz with a 50% duty cycle. The current source flows through the

respective NTC resistor network on the pin and creates a voltage

that is monitored by the controller through an A/D converter

Figure 29 shows how the NTC and the NTCG network should be

designed to get correct VR_HOT#/ALERT# behavior when the

system temperature rises and falls which is manifested as the NTC

pin voltage rising and falling. The series of events are:

(ADC) to generate the T

value. Table 7 shows the

ZONE

programming table for T

1. The temperature rises so the NTC pin voltage drops. T

value changes accordingly.

ZONE

. The user needs to scale the NTC

ZONE

resistor network such that it generates the NTC pin voltage that

corresponds to the left-most column. Do not use any capacitor to

filter the voltage.

2. The temperature crosses the threshold where T

Bit 6 changes from 0 to 1.

register

ZONE

3. The controller changes Status_1 register bit 1 from 0 to 1.

4. The controller asserts ALERT#.

TABLE 7. T

VALUES

ZONE

VNTC

(V)

TMAX

(%)

5. The CPU reads Status_1 register value to know that the alert

T

ZONE

assertion is due to T

register bit 6 flipping.

ZONE

0.84

0.88

0.92

0.96

1.00

1.04

1.08

1.12

1.16

1.2

>100

100

97

FFh

6. The controller clears ALERT#.

FFh

7Fh

3Fh

1Fh

0Fh

07h

7. The temperature continues rising.

8. The temperature crosses the threshold where T

Bit 7 changes from 0 to 1.

register

ZONE

94

91

9. The controllers asserts VR_HOT# signal. The CPU throttles

back and the system temperature starts dropping eventually.

88

10. The temperature crosses the threshold where T

register

85

ZONE

Bit 6 changes from 1 to 0. This threshold is 1 ADC step lower

than the one when VR_HOT# gets asserted, to provide 3%

hysteresis.

82

03h

01h

00h

79

76

11. The controllers de-asserts VR_HOT# signal.

>1.2

<76

12. The temperature crosses the threshold where T

register

ZONE

bit 5 changes from 1 to 0. This threshold is 1 ADC step lower

than the one when ALERT# gets asserted during the

temperature rise to provide 3% hysteresis.

13. The controller changes Status_1 register Bit 1 from 1 to 0.

14. The controller asserts ALERT#.

15. The CPU reads Status_1 register value to know that the alert

assertion is due to T

register Bit 5 flipping.

ZONE

16. The controller clears ALERT#.

FN8449.0

May 15, 2013

21

ISL95813

Layout Guidelines

ISL95813

SYMBOL

LAYOUT GUIDELINES

BOTTOM PAD

GND

Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to

connect to ground planes in PCB internal layers.

18, 19, 20

SCLK,

SDA,

Follow Intel recommendation.

ALERT#

1

2

3

4

5

VR_ON

PGOOD

IMON

No special consideration.

VR_HOT#

NTC

The NTC thermistor needs to be placed close to the thermal source that is monitored to determine CPU Vcore thermal

throttling. Recommend placing it at the hottest spot of the CPU Vcore VR.

6

7

COMP

FB

Place the compensator components in general proximity of the controller.

10

9

ISUMN

ISUMP

Place the current sensing circuit in general proximity of the controller.

Place capacitor Cn very close to the controller.

Place the NTC thermistor next to the inductor so it senses the inductor temperature correctly.

The power stage requires a pair of VSUMP and VSUMN signals to the controller. These two signal traces should run in

a parallel fashion with decent width (>20mil).

IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces

on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is

allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings

show the two preferred ways of routing current sensing traces.

INDUCTOR

Vias

CURRENT-SENSING TRACES

13

14

15

BOOT1

UG

Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

Run these two traces in parallel fashion with a decent width (>30mil). Avoid any sensitive analog signal trace from

crossing over or getting close. Recommend routing PHASE trace to high-side MOSFET source pins instead of general

copper.

PHASE

16

12

17

11

8

LG

Use a decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

A capacitor decouples it to GND. Place it in close proximity of the controller.

Connect a resistor to GND. Place it in close proximity of the controller.

VCC

PROG1

PROG2

RTN

Connect a resistor to GND. Place it in close proximity of the controller.

Place the RTN filter in close proximity of the controller for good decoupling.

FN8449.0

May 15, 2013

22

ISL95813

Package Outline Drawing

L20.3x4

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 3/10

0.10 M

C

A

B

3.00

A

M

0.05

0.50

16X

20X 0.25 ^+0.05

6

B

4

-0.07

PIN 1 INDEX AREA

(C 0.40)

17

20

A

16

1

6

PIN 1

INDEX AREA

4.00

+0.10

2.65

-0.15

11

6

0.15 (4X)

A

10

7

VIEW "A-A"

1.65 ^+0.10

-0.15

TOP VIEW

20x 0.40±0.10

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0.9± 0.10

SEATING PLANE

0.08

C

SIDE VIEW

(16 x 0.50)

(2.65)

(3.80)

(20 x 0.25)

5

0.2 REF

C

(20 x 0.60)

0.00 MIN.

0.05 MAX.

(1.65)

(2.80)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN8449.0

May 15, 2013

23

ISL95813

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that

you have the latest revision.

DATE

REVISION

FN8449.0

CHANGE

May 15, 2013

Initial Release

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal

computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting

www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at

http://www.intersil.com/en/support/qualandreliability.html#reliability

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8449.0

May 15, 2013

24


型号：	ISL95813EV1Z
厂家：	Intersil
描述：	Single Phase Core Controller for VR12.6
文件：	总24页 (文件大小：655K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL95813EV1Z [INTERSIL]

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