ISLA212P50_1105_技术文档

12-Bit, 500MSPS ADC

ISLA212P50

Features

• Automatic Fine Interleave Correction Calibration

• Single Supply 1.8V Operation

• Clock Duty Cycle Stabilizer

The ISLA212P50 is a 12-bit, 500MSPS analog-to-digital converter

designed with Intersil’s proprietary FemtoCharge™ technology on

a standard CMOS process. The ISLA212P50 is part of a

pin-compatible portfolio of 12 to 16-bit A/Ds with maximum

sample rates ranging from 130MSPS to 500MSPS.

• 75fs Clock Jitter

• 700MHz Bandwidth

The device utilizes two time-interleaved 250MSPS unit ADCs to

achieve the ultimate sample rate of 500MSPS. A single 500MHz

conversion clock is presented to the converter, and all interleave

clocking is managed internally. The proprietary Intersil Interleave

Engine (I2E) performs automatic correction of offset, gain, and

sample time mismatches between the unit ADCs to optimize

performance.

• Programmable Built-in Test Patterns

• Multi-ADC Support

- SPI Programmable Fine Gain and Offset Control

- Support for Multiple ADC Synchronization

- Optimized Output Timing

A serial peripheral interface (SPI) port allows for extensive

configurability of the A/D. The SPI also controls the interleave

correction circuitry, allowing the system to issue offline and

continuous calibration commands as well as configure many

dynamic parameters.

• Nap and Sleep Modes

- 200µs Sleep Wake-up Time

• Data Output Clock

• DDR LVDS-Compatible or LVCMOS Outputs

• User-accessible Digital Temperature Monitor

Digital output data is presented in selectable LVDS or CMOS

formats. The ISLA212P50 is available in a 72 Ld QFN package

with an exposed paddle. Operating from a 1.8V supply,

performance is specified over the full industrial temperature

range (-40°C to +85°C).

Applications

• Radar Array Processing

• Software Defined Radios

• Broadband Communications

• High-Performance Data Acquisition

• Communications Test Equipment

Key Specifications

• SNR @ 500MSPS

= 70.3dBFS f = 30MHz

IN

= 68.7dBFS f = 363MHz

IN

• SFDR @ 500MSPS

= 84dBc f = 30MHz

IN

= 76dBc f = 363MHz

IN

• Total Power Consumption = 823mW @ 500MSPS

Pin-Compatible Family

SPEED

(MSPS)

MODEL

RESOLUTION

CLKP

CLKN

CLKOUTP

CLOCK

MANAGEMENT

ISLA216P25

ISLA216P20

ISLA216P13

ISLA214P50

ISLA214P25

ISLA214P20

ISLA214P13

ISLA212P50

ISLA212P25

ISLA212P20

ISLA212P13

16

14

12

250

200

130

500

250

200

130

500

250

200

130

CLKOUTN

12-BIT

250 MSPS

ADC

D[11:0]P

D[11:0]N

SHA

VREF

ORP

ORN

VINP

VINN

Gain, Offset

and Skew

Adjustments

DIGITAL

ERROR

CORRECTION

I2E

12-BIT

250 MSPS

ADC

SHA

VREF

+

–

VCM

SPI

CONTROL

May 25, 2011

FN7843.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISLA212P50

Pin Configuration - LVDS MODE

ISLA212P50

(72 LD QFN)

TOP VIEW

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

DNC

1

2

54 D1P

D1N

D2P

D2N

D3P

D3N

53

52

51

50

49

3

NAPSLP

VCM

4

5

AVSS

AVDD

AVSS

VINN

6

7

48 CLKOUTP

CLKOUTN

46 RLVDS

8

47

VINN

9

10

11

45

44

VINP

OVSS

D4P

VINP

AVSS 12

43 D4N

13

14

42

41

AVDD

AVSS

D5P

D5N

D6P

D6N

CLKDIV

IPTAT

DNC

15

16

17

40

39

Thermal Pad Not Drawn to Scale,

Consult Mechanical Drawing

for Physical Dimensions

38 D7P

37 D7N

Connect Thermal Pad to AVSS

RESETN 18

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Pin Descriptions - 72 Ld QFN, LVDS Mode

PIN NUMBER

LVDS PIN NAME

LVDS PIN FUNCTION

1, 2, 17, 57, 58, 59, 60

DNC

Do Not Connect

1.8V Analog Supply

Analog Ground

6, 13, 19, 20, 21, 70, 71, 72

AVDD

5, 7, 12, 14

AVSS

27, 32, 62

OVDD

1.8V Output Supply

Output Ground

26, 45, 61, 65

OVSS

3

4

NAPSLP

VCM

Tri-Level Power Control (Nap, Sleep modes)

Common Mode Output

8, 9

VINN

Analog Input Negative

FN7843.1

May 25, 2011

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ISLA212P50

Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)

PIN NUMBER

10, 11

15

LVDS PIN NAME

LVDS PIN FUNCTION

VINP

Analog Input Positive

CLKDIV

Tri-Level Clock Divider Control

16

IPTAT

Temperature Monitor (Output current proportional to absolute temperature)

Power On Reset (Active Low)

18

RESETN

22, 23

24, 25

28, 29

30, 31

33, 34

35, 36

37, 38

39, 40

41, 42

43, 44

46

CLKP, CLKN

CLKDIVRSTP, CLKDIVRSTN

D11N, D11P

D10N, D10P

D9N, D9P

D8N, D8P

D7N, D7P

D6N, D6P

D5N, D5P

D4N, D4P

RLVDS

Clock Input True, Complement

Synchronous Clock Divider Reset True, Complement

LVDS Bit 11 (MSB) Output Complement, True

LVDS Bit 10 Output Complement, True

LVDS Bit 9 Output Complement, True

LVDS Bit 8 Output Complement, True

LVDS Bit 7 Output Complement, True

LVDS Bit 6 Output Complement, True

LVDS Bit 5 Output Complement, True

LVDS Bit 4 Output Complement, True

LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)

LVDS Clock Output Complement, True

LVDS Bit 3 Output Complement, True

LVDS Bit 2 Output Complement, True

LVDS Bit 1 Output Complement, True

LVDS Bit 0 (LSB) Output Complement, True

LVDS Over Range Complement, True

SPI Serial Data Output

47, 48

49, 50

51, 52

53, 54

55, 56

63, 64

66

CLKOUTN, CLKOUTP

D3N, D3P

D2N, D2P

D1N, D1P

D0N, D0P

ORN, ORP

SDO

67

CSB

SPI Chip Select (active low)

68

SCLK

SPI Clock

69

SDIO

SPI Serial Data Input/Output

Exposed Paddle

AVSS

Analog Ground

FN7843.1

May 25, 2011

3

ISLA212P50

Pin Configuration - CMOS MODE

ISLA212P50

(72 LD QFN)

TOP VIEW

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

DNC

1

2

54 D1

DNC

53

52

51

50

49

3

NAPSLP

VCM

D2

4

DNC

D3

5

AVSS

AVDD

AVSS

VINN

6

DNC

7

48 CLKOUT

DNC

46 RLVDS

8

47

VINN

9

10

11

45

44

VINP

OVSS

D4

VINP

AVSS 12

43 DNC

13

14

42

41

AVDD

AVSS

D5

DNC

D6

CLKDIV

IPTAT

DNC

15

16

17

40

39

DNC

Thermal Pad Not Drawn to Scale,

Consult Mechanical Drawing

Connect Thermal Pad to AVSS

38 D7

for Physical Dimensions

RESETN 18

37 DNC

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Pin Descriptions - 72 Ld QFN, CMOS Mode

PIN NUMBER

CMOS PIN NAME

CMOS PIN FUNCTION

1, 2, 17, 28, 30, 33, 35, 37, 39, 41,

43, 47, 49, 51, 53, 55, 57, 58, 59,

60, 63

DNC

Do Not Connect

6, 13, 19, 20, 21, 70, 71, 72

AVDD

AVSS

1.8V Analog Supply

Analog Ground

5, 7, 12, 14

27, 32, 62

OVDD

OVSS

1.8V Output Supply

Output Ground

26, 45, 61, 65

3

4

NAPSLP

VCM

Tri-Level Power Control (Nap, Sleep modes)

Common Mode Output

FN7843.1

May 25, 2011

4

ISLA212P50

Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)

PIN NUMBER

CMOS PIN NAME

CMOS PIN FUNCTION

8, 9

VINN

Analog Input Negative

Analog Input Positive

10, 11

VINP

15

CLKDIV

Tri-Level Clock Divider Control

16

IPTAT

Temperature Monitor (Output current proportional to absolute temperature)

Power On Reset (Active Low)

Clock Input True, Complement

Synchronous Clock Divider Reset True, Complement

CMOS Bit 11 (MSB) Output

CMOS Bit 10 Output

18

RESETN

22, 23

CLKP, CLKN

24, 25

CLKDIVRSTP, CLKDIVRSTN

29

D11

D10

D9

31

34

CMOS Bit 9 Output

36

D8

CMOS Bit 8 Output

38

D7

CMOS Bit 7 Output

40

D6

CMOS Bit 6 Output

42

D5

CMOS Bit 5 Output

44

D4

CMOS Bit 4 Output

46

RLVDS

CLKOUT

D3

LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)

CMOS Clock Output

48

50

CMOS Bit 3 Output

52

D2

CMOS Bit 2 Output

54

D1

CMOS Bit 1 Output

56

D0

CMOS Bit 0 (LSB) Output

CMOS Over Range

64

OR

66

SDO

CSB

SCLK

SDIO

AVSS

SPI Serial Data Output

67

SPI Chip Select (active low)

SPI Clock

68

69

SPI Serial Data Input/Output

Analog Ground

Exposed Paddle

FN7843.1

May 25, 2011

5

ISLA212P50

Ordering Information

PART NUMBER

(Notes 1, 2)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISLA212P50IRZ

ISLA214P50IR72EV1Z

NOTES:

ISLA212P50 IRZ

-40 to +85

72 Ld QFN

L72.10x10E

14-bit 500MSPS ADC Evaluation Board (This 14-bit ADC evaluation board can be configured for 12-bit testing.)

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materialsand NiPdAu plate--e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA212P50. For more information on MSL please see Tech Brief TB363.

FN7843.1

May 25, 2011

6

ISLA212P50

Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table of Contents

Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

FS/4 Filter (Notch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Nyquist Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Configurability and Communication . . . . . . . . . . . . . . .22

Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . 22

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . 25

SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . .25

SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Device Configuration/Control . . . . . . . . . . . . . . . . . . . .25

Address 0x60-0x64: I2E initialization . . . . . . . . . . . . .28

Global Device Configuration/Control . . . . . . . . . . . . . .28

SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Split Ground and Power Planes . . . . . . . . . . . . . . . . . .35

Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . .35

Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . 38

Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . 2

Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . 4

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I2E Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . 14

Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 17

User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Temperature Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I2E Requirements and Restrictions . . . . . . . . . . . . . . . . . 21

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

FN7843.1

May 25, 2011

7

ISLA212P50

Absolute Maximum Ratings

Thermal Information

AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V

OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V

AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V

Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V

Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V

Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V

Latchup (Tested per JESD-78C; Class 2, Level A . . . . . . . . . . . . . . . 100mA

Thermal Resistance (Typical)

72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

(°C/W)

23

θ

(°C/W)

0.9

JA

JC

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f

operating temperature range, -40°C to +85°C.

= 500MSPS. Boldface limits apply over the

A

IN

SAMPLE

ISLA212P50

MIN

MAX

PARAMETER

DC SPECIFICATIONS (Note 6)

Analog Input

SYMBOL

CONDITIONS

(Note 5)

TYP

(Note 5)

UNITS

Full-Scale Analog Input Range

Input Resistance

V

Differential

Full Temp

1.95

-5.0

2.0

300

9

2.15

5.0

V

P-P

FS

R

Ω

IN

Input Capacitance

C

pF

ppm/°C

mV

Full Scale Range Temp. Drift

Input Offset Voltage

A

160

-1.3

0.94

2.6

VTC

V

OS

CM

Common-Mode Output Voltage

V

Common-Mode Input Current

(per pin)

I

µA/MSPS

Clock Inputs

Inputs Common Mode Voltage

CLKP, CLKN Input Swing

Power Requirements

0.9

1.8

V

1.8V Analog Supply Voltage

1.8V Digital Supply Voltage

1.8V Analog Supply Current

1.8V Digital Supply Current (Note 6)

AVDD

OVDD

1.7

1.8

372

85

1.9

391

95

V

I

mA

AVDD

I

3mA LVDS, (I2E powered down,

Fs/4 Filter powered down)

OVDD

Power Supply Rejection Ratio

PSRR

30MHz, 45mVP-P signal on AVDD

60

dB

FN7843.1

May 25, 2011

8

ISLA212P50

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f

operating temperature range, -40°C to +85°C. (Continued)

= 500MSPS. Boldface limits apply over the

A

IN

SAMPLE

ISLA212P50

MIN

MAX

PARAMETER

Total Power Dissipation

Normal Mode

SYMBOL

CONDITIONS

(Note 5)

TYP

(Note 5)

UNITS

P

2mA LVDS, (I2E powered down,

Fs/4 Filter powered down)

809

823

mW

D

3mA LVDS, (I2E powered down,

Fs/4 Filter powered down)

875

3mA LVDS, (I2E on, Fs/4 Filter off)

3mA LVDS, (I2E on, Fs/4 Filter on)

858

892

89

mW

µs

943

104

19

Nap Mode

P

D

Sleep Mode

CSB at logic high

7

D

Nap/Sleep Mode Wakeup Time

AC SPECIFICATIONS

Differential Nonlinearity

Sample Clock Running

200

DNL

INL

f

= 105MHz

-0.7

-1.8

±0.16

±0.7

0.7

LSB

IN

No Missing Codes

Integral Nonlinearity

fin = 105MHz

1.8

80

LSB

MSPS

dBFS

Bits

Minimum Conversion Rate (Note 7)

Maximum Conversion Rate

Signal-to-Noise Ratio (Note 8)

f MIN

S

f

MAX

500

S

SNR

f

= 30MHz

70.3

IN

= 105MHz

= 190MHz

= 363MHz

= 461MHz

= 605MHz

= 30MHz

68.0

69.8

68.7

68.1

66.9

Signal-to-Noise and Distortion

(Note 8)

SINAD

69.6

= 105MHz

= 190MHz

= 363MHz

= 461MHz

= 605MHz

= 30MHz

67.5

69.6

68.8

68.1

66.1

62.4

Effective Number of Bits (Note 8)

ENOB

11.27

11.14

11.02

10.69

10.07

= 105MHz

= 190MHz

= 363MHz

= 461MHz

= 605MHz

10.92

Bits

FN7843.1

May 25, 2011

9

ISLA212P50

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f

operating temperature range, -40°C to +85°C. (Continued)

= 500MSPS. Boldface limits apply over the

A

IN

SAMPLE

ISLA212P50

MIN

MAX

PARAMETER

SYMBOL

SFDR

CONDITIONS

(Note 5)

TYP

84

82

78

76

66

61

88

89

88

83

84

77

88

96

(Note 5)

UNITS

dBc

dBFS

Spurious-Free Dynamic Range

(Note 8)

f

= 30MHz

IN

= 105MHz

= 190MHz

= 363MHz

= 461MHz

= 605MHz

= 30MHz

72

Spurious-Free Dynamic Range

Excluding H2,H3 (Note 8)

SFDRX23

= 105MHz

= 190MHz

= 363MHz

= 461MHz

= 605MHz

= 70MHz

Intermodulation Distortion

IMD

= 170MHz

-12

10

Word Error Rate

Full Power Bandwidth

NOTES:

WER

FPBW

700

MHz

5. Compliance to datasheet limits is assured by one of the following methods: production test, characterization and/or design.

6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I

digital output.

specifications apply for 10pF load on each

OVDD

7. The DLL Range setting must be changed for low-speed operation.

8. Minimum specification guaranteed when calibrated at +85°C.

Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

(Note 5)

TYP

(Note 5)

UNITS

INPUTS (Note 9)

Input Current High (RESETN)

Input Current Low (RESETN)

Input Current High (SDIO)

I

V

= 1.8V

= 0V

0

1

-12

4

10

-8

µA

V

IH

IN

I

-25

IL

= 1.8V

= 0V

12

IH

Input Current Low (SDIO)

I

-600

40

-415

58

5

-300

75

IL

Input Current High (CSB)

= 1.8V

= 0V

IH

Input Current Low (CSB)

I

10

IL

Input Current High (CLKDIV)

Input Current Low (CLKDIV)

16

-34

25

-25

34

IH

I

-16

IL

Input Voltage High (SDIO, RESETN)

Input Voltage Low (SDIO, RESETN)

Input Capacitance

V

1.17

IH

V

.63

V

IL

C

4

pF

DI

LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)

Input Common Mode Range

Input Differential Swing (peak to peak, single-ended)

V

825

250

1575

450

mV

ICM

V

ID

FN7843.1

May 25, 2011

10

ISLA212P50

Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

CLKDIVRSTP Input Pull-down Resistance

CLKDIVRSTN Input Pull-up Resistance

LVDS OUTPUTS

SYMBOL

CONDITIONS

(Note 5)

TYP

100

(Note 5)

1200

0.3

UNITS

kΩ

R

Ipd

Ipu

kΩ

Differential Output Voltage (Note 10)

Output Offset Voltage

Output Rise Time

V

3mA Mode

612

1150

240

mV

T

P-P

mV

V

1120

OS

t

ps

R

Output Fall Time

t

240

F

CMOS OUTPUTS

Voltage Output High

V

I

= -500µA

= 1mA

OVDD - 0.3 OVDD - 0.1

V

OH

Voltage Output Low

V

0.1

1.8

1.4

OL

Output Rise Time

t

ns

R

Output Fall Time

t

F

NOTES:

9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending

on desired function.

10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.

I2E Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

(Note 5)

TYP

-65

-70

(Note 5)

UNITS

dBFS

ms

Offset Mismatch-induced Spurious Power

No I2E Calibration performed

Active Run state enabled

I2E Settling Times

I2Epost_t Calibration settling time for

Active Run state

1000

100

Minimum Duration of Valid Analog Input

Largest Interleave Spur

t

Allow one I2E iteration of Offset,

Gain and Phase correction

µs

TE

f

= 10MHz to 240MHz, Active

-99

-80

dBc

IN

Run State enabled, in Track Mode

f

= 10MHz to 240MHz, Active

-75

IN

Run State enabled and previously

settled, in Hold Mode

f

= 260MHz to 490MHz, Active

-99

-75

dBc

IN

Run State enabled, in Track Mode

f

= 260MHz to 490MHz, Active

IN

Run State enabled and previously

settled, in Hold Mode

Total Interleave Spurious Power

Active Run State enabled, in

-85

-75

dBc

Track Mode, f is a broadband

IN

st

signal in the 1 Nyquist zone

Active Run State enabled, in

Track Mode, f is a broadband

IN

nd

signal in the 2 Nyquist zone

Sample Time Mismatch Between Unit ADCs

Gain Mismatch Between Unit ADCs

Offset Mismatch Between Unit ADCs

Active Run State enabled, in

Track Mode

25

0.01

1

fs

%FS

mV

FN7843.1

May 25, 2011

11

ISLA212P50

Timing Diagrams

INP

INN

t_A

CLKN

CLKP

LATENCY = L CYCLES

t_CPD

CLKOUTN

CLKOUTP

t_DC

t_PD

D[11:0]N

D[11:0]P

DATA N-L

DATA N-L+1

DATA N

FIGURE 1A. LVDS

INP

INN

t_A

CLK

LATENCY = L CYCLES

t_CPD

CLKOUT

D[11:0]

t_DC

t_PD

DATA N-L

DATA N-L+1

DATA N

FIGURE 1B. CMOS

FIGURE 1. TIMING DIAGRAMS

FN7843.1

May 25, 2011

12

ISLA212P50

Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

MIN

MAX

PARAMETER

CONDITION

SYMBOL

(Note 5)

TYP

(Note 5)

UNITS

ADC OUTPUT

Aperture Delay

t

114

75

ps

fs

A

RMS Aperture Jitter

j

A

Input Clock to Output Clock Propagation

Delay

AVDD, OVDD = 1.7V to 1.9V,

t

1.65

2.4

3

ns

CPD

T

= -40°C to +85°C

A

AVDD, OVDD = 1.8V, T = +25°C

A

1.9

2.3

2.75

450

ns

ps

CPD

Relative Input Clock to Output Clock

Propagation Delay (Note 13)

AVDD, OVDD = 1.7V to 1.9V,

dt

-450

CPD

T

= -40°C to +85°C

A

Input Clock to Data Propagation Delay

t

1.65

-0.1

2.4

3.5

0.5

ns

PD

Output Clock to Data Propagation Delay,

LVDS Mode

Rising/Falling Edge

0.16

DC

Output Clock to Data Propagation Delay,

CMOS Mode

t

-0.1

0.4

0.2

0.65

ns

DC

Synchronous Clock Divider Reset Setup

Time (with respect to the positive edge of

CLKP)

t

0.06

RSTS

Synchronous Clock Divider Reset Hold Time

(with respect to the positive edge of CLKP)

t

0.02

52

0.35

ns

µs

RSTH

Synchronous Clock Divider Reset Recovery DLL recovery time after

Time

t

RSTRT

L

Synchronous Reset

Latency (Pipeline Delay)

Overvoltage Recovery

SPI INTERFACE (Notes 11, 12)

SCLK Period

20

2

cycles

t

OVR

t

Write Operation

Read Operation

Read or Write

Write

32

56

10

32

12

cycles

CLK

t

CLK

CSB↓ to SCLK↑ Setup Time

CSB↑ after SCLK↑ Hold Time

CSB↑ after SCLK↓ Hold Time

Data Valid to SCLK↑ Setup Time

Data Valid after SCLK↑ Hold Time

Data Valid after SCLK↓ Time

NOTES:

t

S

t

H

Read

t

HR

Write

t

DS

DH

Read or Write

Read

t

8

t

10

DVR

11. SPI Interface timing is directly proportional to the ADC sample period (t ). Values above reflect multiples of a 2ns sample period, and must be scaled

S

proportionally for lower sample rates. ADC sample clock must be running for SPI communication.

12. The SPI may operate asynchronously with respect to the ADC sample clock.

13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is

specified over the full operating temperature and voltage range.

FN7843.1

May 25, 2011

13

ISLA212P50

Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless

otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f

= 500MSPS.

A

IN

SAMPLE

-55

95

90

85

80

75

70

65

60

55

-60

-65

-70

-75

-80

-85

-90

-95

SFDR (EXCLUDING H2,H3)

SFDR

HD2

SNR

HD3

0

100

200

300

400

500

600

0

100

200

300

400

500

600

INPUT FREQUENCY (MHz)

FIGURE 2. SNR AND SFDR vs f

FIGURE 3. HD2 AND HD3 vs f

IN

100

90

80

70

60

-30

SFDR (dBFS)

-40

-50

HD2 (dBc)

-60

HD3 (dBc)

SNR (dBFS)

-70

-80

50 SFDR (dBc)

HD2 (dBFS)

-90

40

30

20

10

SNR (dBc)

-100

-110

-120

HD3 (dBFS)

-50

-60

-40

-30

-20

-10

0

-60

-50

-40

-30

-20

-10

0

INPUT AMPLITUDE (dBFS)

FIGURE 4. SNR AND SFDR vs A

FIGURE 5. HD2 AND HD3 vs A

IN

90

85

80

75

70

-75

-80

-85

-90

-95

SFDR

HD3

HD2

-100

SNR

-105

250

300

350

400

450

500

300

350

SAMPLE RATE (MSPS)

FIGURE 7. HD2 AND HD3 vs f

400

450

500

SAMPLE RATE (MSPS)

FIGURE 6. SNR AND SFDR vs f

SAMPLE

FN7843.1

May 25, 2011

14

ISLA212P50

Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless

otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f

= 500MSPS. (Continued)

A

IN

SAMPLE

1.00

900

850

800

750

700

650

0.75

0.50

0.25

0

-0.25

-0.50

-0.75

-1.00

0

500 1000 1500 2000 2500 3000 3500 4000

CODE

250

300

350

400

450

500

SAMPLE RATE (MSPS)

FIGURE 8. POWER vs f

IN 3mA LVDS MODE

FIGURE 9. DIFFERENTIAL NONLINEARITY

SAMPLE

1.0

90

85

80

75

70

65

60

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

0

500 1000 1500 2000 2500 3000 3500 4000

CODE

0.75

0.80

0.85

0.90

0.95

(V)

1.00

1.05

1.10

1.15

V

CM

FIGURE 10. INTEGRAL NONLINEARITY

FIGURE 11. SNR AND SFDR vs V

CM

200,000

180,000

160,000

140,000

120,000

100,000

80,000

60,000

40,000

20,000

0

A

= -1.0 dBFS

IN

182,936

SNR = 70.4 dBFS

SFDR = 81.1 dBc

SINAD = 69.8 dBFS

-20

-40

-60

-80

-100

-120

10,849

6,212

0

3

0

50

100

150

200

250

2042 2043 2044 2045 2046 2047 2048 2049

CODE

FREQUENCY (MHz)

FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz

FIGURE 12. NOISE HISTOGRAM

FN7843.1

May 25, 2011

15

ISLA212P50

Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless

otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f

= 500MSPS. (Continued)

A

IN

SAMPLE

0

A = -1.0 dBFS

IN

A

= -1.0 dBFS

IN

SNR = 69.1 dBFS

SFDR = 75.4 dBc

SINAD = 68.1 dBFS

SNR = 69.9 dBFS

SFDR = 78.4 dBc

SINAD = 69.0 dBFS

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

FREQUENCY (MHz)

FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz

FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz

0

IMD2

IMD3

IMD2

IMD3

-20

-40

-20

-40

2ND HARMONICS

3RD HARMONICS

2ND HARMONICS

3RD HARMONICS

-60

-80

-60

-80

IMD3 = -96 dBFS

IMD3 = -88 dBFS

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

FREQUENCY (MHz)

FIGURE 16. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz

-7dBFS)

FIGURE 17. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz

-7dBFS)

100

FIS IS APPROX. 97dB

BELOW FULL SCALE

FIS (INTERLEAVING SPUR)

95

AT CAL FREQUENCY

FIS IS APPROX. 96dB

BELOW FULL SCALE

AT CAL FREQUENCY

90

85

80

75

70

65

85

FIS (INTERLEAVING SPUR)

80

SFDR

75

SFDR

70

SNR

65

SNR

60

250

300

350

400

450

500

30 50 70 90 110 130 150 170 190 210 230 250

FREQUENCY (MHz)

FIGURE 19. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E

PREVIOUSLY CALIBRATED AT 363MHZ

FIGURE 18. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E

PREVIOUSLY CALIBRATED AT 105MHZ

FN7843.1

May 25, 2011

16

ISLA212P50

Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless

otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f

= 500MSPS. (Continued)

A

IN

SAMPLE

100

85

80

75

70

65

60

SFDR IS DETERMINED BY FIS

(INTERLEAVING SPUR)

95

90

85

80

75

70

65

SFDR (= FIS)

FIS

SFDR

SNR

1.75

SUPPLY VOLTAGE (AVDD)

1.70

1.80

1.85

1.90

-40

-20

0

20

40

60

80

TEMPERATURE (°C)

FIGURE 20. TEMPERATURE SWEEP WITH I2E FROZEN, I2E

PREVIOUSLY CALIBRATED AT +25°C, F = 105MHZ

FIGURE 21. ANALOG SUPPLY VOLTAGE SWEEP WITH I2E FROZEN,

I2E PREVIOUSLY CALIBRATED AT 1.8V, F = 105MHZ

IN

analog and digital supply voltages are above a threshold. The

following conditions must be adhered to for the power-on

calibration to execute successfully:

Theory of Operation

Functional Description

The ISLA212P50 is based upon a 12-bit, 250MSPS A/D converter

core that utilizes a pipelined successive approximation

• A frequency-stable conversion clock must be applied to the

CLKP/CLKN pins

architecture (see Figure 22). The input voltage is captured by a

Sample-Hold Amplifier (SHA) and converted to a unit of charge.

Proprietary charge-domain techniques are used to successively

compare the input to a series of reference charges. Decisions

made during the successive approximation operations determine

the digital code for each input value. Digital error correction is also

applied, resulting in a total latency of 20 clock cycles. This is

evident to the user as a latency between the start of a conversion

and the data being available on the digital outputs.

• DNC pins must not be connected

• SDO has an internal pull-up and should not be driven externally

• RESETN is pulled low by the ADC internally during POR.

External driving of RESETN is optional.

• SPI communications must not be attempted

A user-initiated reset can subsequently be invoked in the event

that the above conditions cannot be met at power-up.

The device contains two core A/D converters with carefully matched

transfer characteristics. The cores are clocked on alternate clock

edges, resulting in a doubling of the sample rate.

After the power supply has stabilized the internal POR releases

RESETN and an internal pull-up pulls it high, which starts the

calibration sequence. If a subsequent user-initiated reset is

desired, the RESETN pin should be connected to an open-drain

driver with an off-state/high impedance state leakage of less

than 0.5mA to assure exit from the reset state so calibration can

start.

Time–interleaved A/D systems can exhibit non–ideal artifacts in the

frequency domain if the individual core A/D characteristics are not

well matched. Gain, offset and timing skew mismatches are of

primary concern.

The calibration sequence is initiated on the rising edge of

RESETN, as shown in Figure 23. Calibration status can be

determined by reading the cal_status bit (LSB) at 0xB6. This bit is

‘0’ during calibration and goes to a logic ‘1’ when calibration is

complete. The data outputs output 0xCCCC during calibration;

this can also be used to determine calibration status.

The Intersil Interleave Engine (I2E) performs automatic interleave

calibration for the offset, gain, and sample time skew mismatch

between the core A/Ds. The I2E circuitry also adjusts in real-time for

temperature and voltage variations.

Residual gain and sample time skew mismatch result in

fundamental image spurs at f

± f . Offset mismatches

NYQUIST IN

While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is

set low. Normal operation of the output clock resumes at the

next input clock edge (CLKP/CLKN) after RESETN is de-asserted.

At 250MSPS the nominal calibration time is 200ms, while the

maximum calibration time is 550ms.

create spurs at DC and multiples of f

.

NYQUIST

Power-On Calibration

As mentioned previously, the cores perform a self-calibration at

start-up. An internal power-on-reset (POR) circuit detects the

supply voltage ramps and initiates the calibration when the

FN7843.1

May 25, 2011

17

ISLA212P50

CLOCK

GENERATION

INP

INN

2.5-BIT

FLASH

6- STAGE

1.5-BIT/ STAGE

3- STAGE

1-BIT/ STAGE

3-BIT

FLASH

2.5-BIT

FLASH

SHA

+

1.25V

–

DIGITAL

ERROR

CORRECTION

LVDS/ LVCMOS

OUTPUTS

FIGURE 22. A/D CORE BLOCK DIAGRAM

changes may necessitate recalibration, depending on system

performance requirements. Best performance will be achieved

by recalibrating the A/D under the environmental conditions at

which it will operate.

CLKN

CLKP

CALIBRATION

TIME

RESETN

A supply voltage variation of less than 100mV will generally

result in an SNR change of less than 0.5dBFS and SFDR change

of less than 3dBc.

CALIBRATION

BEGINS

CAL_STATUS

BIT

CALIBRATION

COMPLETE

In situations where the sample rate is not constant, best results

will be obtained if the device is calibrated at the highest sample

rate. Reducing the sample rate by less than 80MSPS will typically

result in an SNR change of less than 0.5dBFS and an SFDR

change of less than 3dBc.

CLKOUTP

FIGURE 23. CALIBRATION TIMING

Figures 24 through 26 show the effect of temperature on SNR

and SFDR performance with power on calibration performed at

-40°C, +25°C, and +85°C. Each plot shows the variation of

SNR/SFDR across temperature after a single power on

calibration at -40°C, +25°C and +85°C. Best performance is

typically achieved by a user-initiated power on calibration at the

operating conditions, as stated earlier. Applications working

across the full temperature range can use the on-chip calibration

feature to maximize performance when large temperature

variations are expected.

User Initiated Reset

Recalibration of the A/D can be initiated at any time by driving

the RESETN pin low for a minimum of one clock cycle. An

open-drain driver with a drive strength in its high impedance

state of less than 0.5mA is recommended, as RESETN has an

internal high impedance pull-up to OVDD. As is the case during

power-on reset, RESETN and DNC pins must be in the proper

state for the calibration to successfully execute.

The performance of the ISLA212P50 changes with variations in

temperature, supply voltage or sample rate. The extent of these

FN7843.1

May 25, 2011

18

ISLA212P50

Temperature Calibration

90

85

80

75

SFDR (dBc)

85

80

75

SNR (dBFS)

70

-40

-35

-30

-25

-20

5

10

15

20

25

30

35

40

45

TEMPERATURE (°C)

FIGURE 25. TYPICAL SNR, SFDR PERFORMANCE vs

FIGURE 24. TYPICAL SNR, SFDR PERFORMANCE vs

TEMPERATURE,DEVICE CALIBRATED AT -40°C,

TEMPERATURE, DEVICE CALIBRATED AT +25°C,

500MSPS OPERATION, f = 105MHz

IN

Best performance is obtained when the analog inputs are driven

differentially. The common-mode output voltage, VCM, should be

used to properly bias the inputs as shown in Figures 28

through 30. An RF transformer will give the best noise and

distortion performance for wideband and/or high intermediate

frequency (IF) inputs. Two different transformer input schemes

are shown in Figures 28 and 29.

83

78

73

68

SFDR (dBc)

ADT1-1WT

SNR (dBFS)

1000pF

A/D

VCM

65

70

75

80

85

TEMPERATURE (°C)

0.1µF

FIGURE 26. TYPICAL SNR, SFDR PERFORMANCE vs

TEMPERATURE, DEVICE CALIBRATED AT +85°C,

500MSPS OPERATION, f = 105MHz

IN

FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE

APPLICATIONS

Analog Input

TX-2-5-1

ADTL1-12

A single fully differential input (VINP/VINN) connects to the

sample and hold amplifier (SHA) of each unit A/D. The ideal

full-scale input voltage is 2.0V, centered at the VCM voltage of

0.94V as shown in Figure 27.

1000pF

A/D

VCM

1000pF

1.8

1.4

1.0

0.6

0.2

VINN

VINP

FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR

HIGH IF APPLICATIONS

VCM

0.94V

1.0V

This dual transformer scheme is used to improve common-mode

rejection, which keeps the common-mode level of the input

matched to VCM. The value of the shunt resistor should be

determined based on the desired load impedance. The

differential input resistance of the ISLA212P50 is 300Ω.

FIGURE 27. ANALOG INPUT RANGE

The SHA design uses a switched capacitor input stage (see

Figure 43 on page 34), which creates current spikes when the

sampling capacitance is reconnected to the input voltage. This

causes a disturbance at the input which must settle before the

FN7843.1

May 25, 2011

19

ISLA212P50

next sampling point. Lower source impedance will result in faster

TABLE 1. CLKDIV PIN SETTINGS

settling and improved performance. Therefore a 1:1 transformer

and low shunt resistance are recommended for optimal

performance.

CLKDIV PIN

DIVIDE RATIO

AVSS

Float

AVDD

2

1

Not Allowed

Jitter

A/D

In a sampled data system, clock jitter directly impacts the

achievable SNR performance. The theoretical relationship

between clock jitter (t ) and SNR is shown in Equation 1 and is

J

illustrated in Figure 32.

1

⎛

⎝

⎞

⎠

-------------------

SNR = 20 log

(EQ. 1)

10

2πf

t

IN J

FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT

A differential amplifier, as shown in the simplified block diagram

in Figure 30, can be used in applications that require

100

95

90

85

80

75

70

65

60

55

tj = 0.1ps

DC-coupling. In this configuration, the amplifier will typically

dominate the achievable SNR and distortion performance.

Intersil’s new ISL552xx differential amplifier family can also be

used in certain AC applications with minimal performance

degradation. Contact the factory for more information.

14 BITS

tj = 1ps

12 BITS

tj = 10ps

10 BITS

Clock Input

The clock input circuit is a differential pair (see Figure 44).

tj = 100ps

Driving these inputs with a high level (up to 1.8V

on each

P-P

50

input) sine or square wave will provide the lowest jitter

performance. A transformer with 4:1 impedance ratio will

provide increased drive levels. The clock input is functional with

AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the

lowest possible aperture jitter, it is recommended to have high

slew rate at the zero crossing of the differential clock input

signal.

1M

10M

100M

1G

INPUT FREQUENCY (Hz)

FIGURE 32. SNR vs CLOCK JITTER

This relationship shows the SNR that would be achieved if clock

jitter were the only non-ideal factor. In reality, achievable SNR is

limited by internal factors such as linearity, aperture jitter and

thermal noise. Internal aperture jitter is the uncertainty in the

sampling instant shown in Figure1A. The internal aperture jitter

combines with the input clock jitter in a root-sum-square fashion,

since they are not statistically correlated, and this determines

the total jitter in the system. The total jitter, combined with other

noise sources, then determines the achievable SNR.

The recommended drive circuit is shown in Figure 31. A duty

range of 40% to 60% is acceptable. The clock can be driven

single-ended, but this will reduce the edge rate and may impact

SNR performance. The clock inputs are internally self-biased to

AVDD/2 to facilitate AC coupling.

1000pF

TC4-19G2+

Voltage Reference

CLKP

200

A temperature compensated internal voltage reference provides

the reference charges used in the successive approximation

operations. The full-scale range of each A/D is proportional to the

reference voltage. The nominal value of the voltage reference is

1.25V.

0.01µF

CLKN

1000pF

Digital Outputs

1000pF

Output data is available as a parallel bus in LVDS-compatible

(default) or CMOS modes. In either case, the data is presented in

double data rate (DDR) format. Figure 1 shows the timing

relationships for LVDS and CMOS modes, respectively.

FIGURE 31. RECOMMENDED CLOCK DRIVE

A selectable 2x frequency divider is provided in series with the

clock input. The divider can be used in the 2x mode with a

sample clock equal to twice the desired sample rate. This allows

the use of the Phase Slip feature, which enables synchronization

of multiple ADCs. The Phase Slip feature can be used as an

alternative to using the CLKDIVRST pins to synchronize ADCs in a

multiple ADC system.

Additionally, the drive current for LVDS mode can be set to a

nominal 3mA(default) or a power-saving 2mA. The lower current

setting can be used in designs where the receiver is in close

physical proximity to the A/D. The applicability of this setting is

dependent upon the PCB layout, therefore the user should

FN7843.1

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20

ISLA212P50

experiment to determine if performance degradation is

observed.

BINARY

11

10

9

1

0

• • • •

The output mode can be controlled through the SPI port, by

writing to address 0x73, see “Serial Peripheral Interface” on

page 25.

• • • •

An external resistor creates the bias for the LVDS drivers. A 10kΩ,

1% resistor must be connected from the RLVDS pin to OVSS.

Power Dissipation

GRAY CODE

11

10

9

1

0

The power dissipated by the ISLA212P50 is primarily dependent

on the sample rate and the output modes: LVDS vs CMOS and

DDR vs SDR. There is a static bias in the analog supply, while the

remaining power dissipation is linearly related to the sample

rate. The output supply dissipation changes to a lesser degree in

LVDS mode, but is more strongly related to the clock frequency in

CMOS mode.

FIGURE 33. BINARY TO GRAY CODE CONVERSION

Converting back to offset binary from Gray code must be done

recursively, using the result of each bit for the next lower bit as

shown in Figure 34.

GRAY CODE

11

10

9

1

0

• • • •

Nap/Sleep

Portions of the device may be shut down to save power during

times when operation of the A/D is not required. Two power saving

modes are available: Nap, and Sleep. Nap mode reduces power

dissipation to less than 104mW while Sleep mode reduces power

dissipation to less than 19mW.

• • • •

All digital outputs (Data, CLKOUT and OR) are placed in a high

impedance state during Nap or Sleep. The input clock should

remain running and at a fixed frequency during Nap or Sleep, and

CSB should be high. Recovery time from Nap mode will increase

if the clock is stopped, since the internal DLL can take up to 52µs

to regain lock at 500MSPS.

By default after the device is powered on, the operational state is

controlled by the NAPSLP pin as shown in Table 2.

BINARY

11

10

9

1

0

TABLE 2. NAPSLP PIN SETTINGS

NAPSLP PIN

AVSS

MODE

Normal

Sleep

Nap

Mapping of the input voltage to the various data formats is

shown in Table 3.

Float

TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING

AVDD

INPUT

TWO’S

VOLTAGE

OFFSET BINARY

COMPLEMENT

GRAY CODE

The power-down mode can also be controlled through the SPI

port, which overrides the NAPSLP pin setting. Details on this are

contained in “Serial Peripheral Interface” on page 25.

–Full Scale 0000 0000 0000 1000 0000 0000 0000 0000 0000

–Full Scale 0000 0000 0001 1000 0000 0001 0000 0000 0001

+ 1LSB

Data Format

Mid–Scale 1000 0000 0000 0000 0000 0000 1100 0000 0000

Output data can be presented in three formats: two’s

complement (default), Gray code and offset binary. The data

format can also be controlled through the SPI port, by writing to

address 0x73. Details on this are contained in “Serial Peripheral

Interface” on page 25.

+Full Scale 1111 1111 1110 0111 1111 1110 1000 0000 0001

– 1LSB

+Full Scale 1111 1111 1111 0111 1111 1111 1000 0000 0000

Offset binary coding maps the most negative input voltage to

code 0x000 (all zeros) and the most positive input to 0xFFF (all

ones). Two’s complement coding simply complements the MSB

of the offset binary representation.

I2E Requirements and

Restrictions

Overview

When calculating Gray code the MSB is unchanged. The

remaining bits are computed as the XOR of the current bit

position and the next most significant bit. Figure 33 shows this

operation.

I2E is a blind and background capable algorithm, designed to

transparently eliminate interleaving artifacts. This circuitry

eliminates interleave artifacts due to offset, gain, and sample time

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ISLA212P50

mismatches between unit A/Ds, and across supply voltage and

temperature variations in real-time.

in interleave artifacts induced by supply voltage and

temperature changes. The I2E circuitry will remain in Hold

Mode until such time as the analog input signal meets the

requirements for Track Mode.

Differences in the offset, gain, and sample times of time-interleaved

A/Ds create artifacts in the digital outputs. Each of these artifacts

creates a unique signature that may be detectable in the captured

samples. The I2E algorithm optimizes performance by detecting

error signatures and adjusting each unit A/D using minimal

additional power.

Power Meter

The power meter calculates the average power of the analog

input, and determines if it’s within range to allow operation in

Track Mode. Both AC RMS and total RMS power are calculated,

and there are separate SPI programmable thresholds and

hysteresis values for each.

I2E calibration is off by default at power-up. The I2E algorithm can

be put in Active Run state via SPI. When the I2E algorithm is in

Active Run state, it detects and corrects for offset, gain, and sample

time mismatches in real time (see Track Mode description under

“Active Run State” on page 22). However, certain analog input

characteristics can obscure the estimation of these mismatches.

The I2E algorithm is capable of detecting these obscuring analog

input characteristics, and as long as they are present I2E will stop

updating the correction in real time. Effectively, this freezes the

current correction circuitry to the last known-good state (see Hold

Mode description under “Active Run State” on page 22). Once the

analog input signal stops obscuring the interleaved artifacts, the I2E

algorithm will automatically start correcting for mismatch in real

time again.

FS/4 Filter (Notch)

A digital filter removes the signal energy in a 100kHz band

around f /4 before the I2E circuitry uses these samples for

S

estimating offset, gain, and sample time mismatches (data

samples produced by the A/D are unaffected by this filtering).

This allows the I2E algorithm to continue in Active Run state

while in the presence of a large amount of input energy near the

f /4 frequency. This filter can be powered down if it’s known that

S

the signal characteristics won’t violate the restrictions. Powering

down the FS/4 filter will reduce power consumption by

approximately 30mW.

Active Run State

Nyquist Zones

During the Active Run state the I2E algorithm actively suppresses

artifacts due to interleaving based on statistics in the digitized

data. I2E has two modes of operation in this state (described in

the following), dynamically chosen in real-time by the algorithm

based on the statistics of the analog input signal.

The I2E circuitry allows the use of any one Nyquist zone without

configuration, but requires the use of only one Nyquist zone.

Inputs that switch dynamically between Nyquist zones will cause

poor performance for the I2E circuitry. For example, I2E will

function properly for a particular application that has f =

S

st

500MSPS and uses the 1 Nyquist zone (0MHz to 250MHz). I2E

1. Track Mode refers to the default state of the algorithm, when

all artifacts due to interleaving are actively being eliminated.

To be in Track Mode the analog input signal to the device must

adhere to the following requirements:

will also function properly for an application that uses

nd

f = 500MSPS and the 2 Nyquist zone (250MHz to 500MHz).

S

I2E will not function properly for an application that uses

f = 500MSPS, and input frequency bands from 150MHz to

S

• Possess total power greater than -20dBFS, integrated from

1MHz to Nyquist but excluding signal energy in a 100kHz band

210MHz and 250MHz to 290MHz simultaneously. There is no

need to configure the I2E algorithm to use a particular Nyquist

zone, but no dynamic switching between Nyquist zones is

permitted while I2E is running.

centered at f /4

S

The criteria above assumes 500MSPS operation; the frequency

bands should be scaled proportionally for lower sample rates. Note

that the effect of excluding energy in the 100kHz band around of

Configurability and Communication

I2E can respond to status queries, be turned on and turned off,

and generally configured via SPI programmable registers.

Configuring of I2E is generally unnecessary unless the

application cannot meet the requirements of Track Mode on or

after power up. Parameters that can be adjusted and read back

include FS/4 filter threshold and status, Power Meter threshold

and status, and initial values for the offset, gain, and sample

time values to use when I2E starts.

f /4 exists in every Nyquist zone. This band generalizes to the form

S

(N*f /4 - 50kHz) to (N*f /4 + 50kHz), where N is any odd integer.

S

An input signal that violates these criteria briefly (approximately

10µs), before and after which it meets this criteria, will not impact

system performance.

The algorithm must be in Track Mode for approximately one second

(defined as I2Epost_t on “I2E Specifications” on page 11) after

power-up before the specifications apply. Once this requirement has

been met, the specifications of the device will continue to be met

while I2E remains in Track Mode, even in the presence of

temperature and supply voltage changes.

Clock Divider Synchronous Reset

An output clock (CLKOUTP, CLKOUTN) is provided to facilitate

latching of the sampled data. This clock is at half the frequency

of the sample clock, and the absolute phase of the output clocks

for multiple A/Ds is indeterminate. This feature allows the phase

of multiple A/Ds to be synchronized (refer to Figure 35), which

greatly simplifies data capture in systems employing multiple

A/Ds.

2. Hold Mode refers to the state of the I2E algorithm when the

analog input signal does not meet the requirements specified

above. If the algorithm detects that the signal no longer

meets the criteria, it automatically enters Hold Mode. In Hold

Mode, the I2E circuitry freezes the adjustment values based

on the most recent set of valid input conditions. However, in

Hold Mode, the I2E circuitry will not correct for new changes

The reset signal must be well-timed with respect to the sample

clock (see “Switching Specifications” Table on page 13).

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ISLA212P50

Sample Clock

Input

s1

L+t_d

Analog Input

(Note 14)

s2

t_RSTH

(Note 15)

CLKDIVRSTP

t_RSTS

t_RSTRT

ADC1 Output Data

s0

s1

s2

s3

ADC1 CLKOUTP

ADC2 Output Data

s1

ADC2 CLKOUTP

(Note 16)

(phase 1)

ADC2 CLKOUTP

(Note 16)

(phase 2)

NOTES:

14. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay, t

d

15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge. CLKDIVRSTN is

not shown, but must be driven, and is the complement of CLKDIVRSTP.

16. Either Output Clock Phase (phase 1 or phase 2) equally likely prior to synchronization.

FIGURE 35. SYNCHRONOUS RESET OPERATION

CSB

SCLK

SDIO

R/W

W1

W0

A12

A11

A10

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

FIGURE 36. MSB-FIRST ADDRESSING

CSB

SCLK

SDIO

A0

A1

A2

A11

A12

W0

W1

R/W

D0

D1

D2

D3

D4

D5

D6

D7

FIGURE 37. LSB-FIRST ADDRESSING

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ISLA212P50

t_DSW

t_CLK

t_HI

t_H

t_DHW

CSB

t_S

t_LO

SCLK

SDIO

W1 W0 A12 A11 A10 A9

A8

A7

D0

R/W

D5

D4

D3

D2

D1

SPI WRITE

FIGURE 38. SPI WRITE

t_DSW

t_CLK

t_HR

t_HI

t_DVR

t_S

CSB

t_DHW

t_LO

SCLK

WRITING A READ COMMAND

A9 A2 A1

READING DATA

)

( 3 WIRE MODE

D2 D1 D0

SDIO

SDO

A0

D7 D6

D3

W1 W 0

A12 A11

A10

R/W

( 4 WIRE MODE)

D3 D2 D1

D7

D0

FIGURE 39. SPI READ

CSB STALLING

CSB

SCLK

SDIO

INSTRUCTION/ADDRESS

DATA WORD 1

DATA WORD 2

FIGURE 40. 2-BYTE TRANSFER

LAST LEGAL

CSB STALLING

CSB

SCLK

SDIO

INSTRUCTION/ADDRESS

DATA WORD 1

DATA WORD N

FIGURE 41. N-BYTE TRANSFER

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ISLA212P50

of the CSB pin is allowed at any byte boundary

Serial Peripheral Interface

(instruction/address or data) if the number of bytes being

transferred is three or less. For transfers of four bytes or more,

CSB is allowed to stall in the middle of the instruction/address

bytes or before the first data byte. If CSB transitions to a high

state after that point the state machine will reset and terminate

the data transfer.

A serial peripheral interface (SPI) bus is used to facilitate

configuration of the device and to optimize performance. The SPI

bus consists of chip select (CSB), serial clock (SCLK) serial data

output (SDO), and serial data input/output (SDIO). The maximum

SCLK rate is equal to the A/D sample rate (f

) divided by 32

SAMPLE

for both write operations and read operations. At

= 500MHz, maximum SCLK is 15.63MHz for writing and

TABLE 4. BYTE TRANSFER SELECTION

f

SAMPLE

[W1:W0]

00

BYTES TRANSFERRED

read operations. There is no minimum SCLK rate.

1

The following sections describe various registers that are used to

configure the SPI or adjust performance or functional parameters.

Many registers in the available address space (0x00 to 0xFF) are

not defined in this document. Additionally, within a defined

register there may be certain bits or bit combinations that are

reserved. Undefined registers and undefined values within defined

registers are reserved and should not be selected. Setting any

reserved register or value may produce indeterminate results.

01

2

3

10

11

4 or more

Figures 40 and 41 on page 24 illustrate the timing relationships

for 2-byte and N-byte transfers, respectively. The operation for a

3-byte transfer can be inferred from these diagrams.

SPI Physical Interface

SPI Configuration

The serial clock pin (SCLK) provides synchronization for the data

transfer. By default, all data is presented on the serial data

input/output (SDIO) pin in three-wire mode. The state of the SDIO

pin is set automatically in the communication protocol

(described in the following). A dedicated serial data output pin

(SDO) can be activated by setting 0x00[7] high to allow operation

in four-wire mode.

ADDRESS 0X00: CHIP_PORT_CONFIG

Bit ordering and SPI reset are controlled by this register. Bit order

can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB

first) to accommodate various micro controllers.

Bit 7 SDO Active

Bit 6 LSB First

Setting this bit high configures the SPI to interpret serial data

as arriving in LSB to MSB order.

The SPI port operates in a half duplex master/slave

configuration, with the ISLA212P50 functioning as a slave.

Multiple slave devices can interface to a single master in

three-wire mode only, since the SDO output of an unaddressed

device is asserted in four wire mode.

Bit 5 Soft Reset

Setting this bit high resets all SPI registers to default values.

Bit 4 Reserved

The chip-select bar (CSB) pin determines when a slave device is

being addressed. Multiple slave devices can be written to

concurrently, but only one slave device can be read from at a

given time (again, only in three-wire mode). If multiple slave

devices are selected for reading at the same time, the results will

be indeterminate.

This bit should always be set high.

Bits 3:0 These bits should always mirror bits 4:7 to avoid

ambiguity in bit ordering.

ADDRESS 0X02: BURST_END

If a series of sequential registers are to be set, burst mode can

improve throughput by eliminating redundant addressing.

Setting the burst_end address determines the end of the

transfer; during a write operation, the user must be cautious to

transmit the correct number of bytes based on the starting and

ending addresses.

The communication protocol begins with an instruction/address

phase. The first rising SCLK edge following a high to low

transition on CSB determines the beginning of the two-byte

instruction/address command; SCLK must be static low before

the CSB transition. Data can be presented in MSB-first order or

LSB-first order. The default is MSB-first, but this can be changed

by setting 0x00[6] high. Figures 36 and 37 show the appropriate

bit ordering for the MSB-first and LSB-first modes, respectively. In

MSB-first mode, the address is incremented for multi-byte

transfers, while in LSB-first mode it is decremented.

Bits 7:0 Burst End Address

This register value determines the ending address of the burst

data.

Device Information

In the default mode, the MSB is R/W, which determines if the

data is to be read (active high) or written. The next two bits, W1

and W0, determine the number of data bytes to be read or

written (see Table 4). The lower 13 bits contain the first address

for the data transfer. This relationship is illustrated in Figure 38,

and timing values are given in “Switching Specifications on

page 13.

ADDRESS 0X08: CHIP_ID

ADDRESS 0X09: CHIP_VERSION

The generic die identifier and a revision number, respectively, can

be read from these two registers.

Device Configuration/Control

A common SPI map, which can accommodate single-channel or

multi-channel devices, is used for all Intersil A/D products.

After the instruction/address bytes have been read, the

appropriate number of data bytes are written to or read from the

A/D (based on the R/W bit status). The data transfer will

continue as long as CSB remains low and SCLK is active. Stalling

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ISLA212P50

ADDRESS 0X20: OFFSET_COARSE_ADC0

ADDRESS 0X21: OFFSET_FINE_ADC0

ADDRESS 0X25: MODES

Two distinct reduced power modes can be selected. By default,

the tri-level NAPSLP pin can select normal operation, nap or

sleep modes (refer to“Nap/Sleep” on page 21). This functionality

can be overridden and controlled through the SPI. This is an

indexed function when controlled from the SPI, but a global

function when driven from the pin. This register is not changed by

a Soft Reset.

The input offset of the A/D core can be adjusted in fine and

coarse steps. Both adjustments are made via an 8-bit word as

detailed in Table 5. The data format is twos complement.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the

register value then write the incremented or decremented value

back to the same register.

TABLE 8. POWER-DOWN CONTROL

0x25[2:0]

VALUE

000

001

POWER DOWN MODE

TABLE 5. OFFSET ADJUSTMENTS

Pin Control

0x20[7:0]

COARSE OFFSET

0x21[7:0]

FINE OFFSET

PARAMETER

Steps

Normal Operation

Nap Mode

255

010

–Full Scale (0x00)

Mid–Scale (0x80)

+Full Scale (0xFF)

Nominal Step Size

-133LSB (-47mV)

0.0LSB (0.0mV)

+133LSB (+47mV)

1.04LSB (0.37mV)

-5LSB (-1.75mV)

0.0LSB

100

Sleep Mode

ADDRESS 0X26: OFFSET_COARSE_ADC1

ADDRESS 0X27: OFFSET_FINE_ADC1

+5LSB (+1.75mV)

0.04LSB (0.014mV)

The input offset of A/D core#1 can be adjusted in fine and

coarse steps in the same way that offset for core#0 can be

adjusted. Both adjustments are made via an 8-bit word as

detailed in Table 5. The data format is two’s complement.

ADDRESS 0X22: GAIN_COARSE__ADC0

ADDRESS 0X23: GAIN_MEDIUM_ADC0

ADDRESS 0X24: GAIN_FINE_ADC0

Gain of the A/D core can be adjusted in coarse, medium and fine

steps. Coarse gain is a 4-bit adjustment while medium and fine

are 8-bit. Multiple Coarse Gain Bits can be set for a total

adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%)

It is recommended to use one of the coarse gain settings (-4.2%,

-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the

registers at 23h and 24h.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the register

value then write the incremented or decremented value back to the

same register.

ADDRESS 0X28: GAIN_COARSE__ADC1

ADDRESS 0X29: GAIN_MEDIUM_ADC1

ADDRESS 0X2A: GAIN_FINE_ADC1

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the

register value then write the incremented or decremented value

back to the same register.

Gain of A/D core #1 can be adjusted in coarse, medium and fine

steps in the same way that core #0 can be adjusted. Coarse gain is

a 4-bit adjustment while medium and fine are 8-bit. Multiple

Coarse Gain Bits can be set for a total adjustment range of ±4.2.

TABLE 6. COARSE GAIN ADJUSTMENT

0x22[3:0] core 0

0x26[3:0] core 1

NOMINAL COARSE GAIN ADJUST

(%)

ADDRESS 0X30: I2E STATUS

Bit3

Bit2

Bit1

Bit0

+2.8

+1.4

-2.8

The I2E general status register.

Bits 0 and 1 indicate if the I2E circuitry is in Active Run or Hold state.

The state of the I2E circuitry is dependent on the analog input signal

itself. If the input signal obscures the interleave mismatched

artifacts such that I2E cannot estimate the mismatch, the algorithm

will dynamically enter the Hold state. For example, a DC mid-scale

input to the A/D does not contain sufficient information to estimate

the gain and sample time skew mismatches, and thus the I2E

algorithm will enter the Hold state. In the Hold state, the analog

adjustments for interleave correction will be frozen and mismatch

estimate calculations will cease until such time as the analog input

achieves sufficient quality to allow the I2E algorithm to make

mismatch estimates again.

-1.4

TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS

0x23[7:0]

0x24[7:0]

PARAMETER

Steps

MEDIUM GAIN

FINE GAIN

256

-2%

256

–Full Scale (0x00)

Mid–Scale (0x80)

+Full Scale (0xFF)

Nominal Step Size

-0.20%

0.00%

+2%

+0.2%

Bit 0: 0 = I2E has not detected a low power condition. 1 = I2E has

detected a low power condition, and the analog adjustments for

interleave correction are frozen.

0.016%

0.0016%

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ISLA212P50

Bit 1: 0 = I2E has not detected a low AC power condition. 1 = I2E has

Under such circumstances, I2E enters Hold state. In the Hold

state, the analog adjustments will be frozen and mismatch

estimate calculations will cease until such time as the analog

input achieves sufficient quality to allow the I2E algorithm to

make mismatch estimates again.

detected a low AC power condition, and I2E will continue to correct

with best known information but will not update its interleave

correction adjustments until the input signal achieves sufficient AC

RMS power.

Bit 2: When first started, the I2E algorithm can take a significant

amount of time to settle (~1s), dependent on the characteristics of

the analog input signal. 0 = I2E is still settling, 1 = I2E has

completed settling.

These registers allow the programming of the thresholds of the

meters used to determine the quality of the input signal. This can be

used by the application to optimize I2E’s behavior based on

knowledge of the input signal. For example, if a specific application

had an input signal that was typically 30dB down from full scale,

and was primarily concerned about analog performance of the A/D

at this input power, lowering the RMS power threshold would allow

I2E to continue tracking with this input power level, thus allowing it

to track over voltage and temperature changes.

ADDRESS 0X31: I2E CONTROL

The I2E general control register. This register can be written while

I2E is running to control various parameters.

Bit 0: 0 = turn I2E off, 1= turn I2E on

0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold

Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings in the current

state. Subsequently writing a 0 to this bit will allow I2E to continue

from the state it was left in.

This 16-bit quantity is the RMS power threshold at which I2E will

enter Hold state. The RMS power of the analog input is calculated

continuously by I2E on incoming data.

Bit 2-4: Disable any of the interleave adjustments of offset, gain, or

sample time skew

Only the upper 12 bits of the ADC sample outputs are used in the

averaging process for comparison to the power threshold registers.

A 12-bit number squared produces a 24-bit result (for A/D

Bit 5: 0 = bypass notch (fs/4) filter, 1 = use notch filter on incoming

data before estimating interleave mismatch terms

resolutions under 12-bits, the A/D samples are MSB-aligned to

12-bit data). A dynamic number of these 24-bit results are averaged

to compare with this threshold approximately every 1µs to decide

whether or not to freeze I2E. The 24-bit threshold is constructed with

bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned

to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. As

an example, if the application wanted to set this threshold to trigger

near the RMS analog input of a -20dBFS sinusoidal input, the

calculation to determine this register’s value would be:

ADDRESS 0X32: I2E STATIC CONTROL

The I2E general static control register. This register must be written

prior to turning I2E on for the settings to take effect.

Bit 1-4: Reserved, always set to 0

Bit 5: 0 = normal operation, 1 = skip coarse adjustment of the

offset, gain, and sample time skew analog controls when I2E is first

turned on. This bit would typically be used if optimal analog

adjustment values for offset, gain, and sample time skew have been

preloaded in order to have the I2E algorithm converge more quickly.

–20

20

⎛

⎝

⎞

⎠

---------

12

2

-------

RMS

=

× 10

× 2 ≅ (290)codes

codes

The system gain of the pair of interleaved core A/Ds can be set by

programming the medium and fine gain of the reference A/D before

turning I2E on. In this case, I2E will adjust the non-reference A/D’s

gain to match the reference A/D’s gain.

(EQ. 2)

= 0x1488

2

hex(((290)) ) = 0x14884

TruncateMSBandLSBhexdigit

(EQ. 3)

Bit 7: Reserved, always set to 0

Therefore, programming 0x1488 into these two registers will cause

I2E to freeze when the signal being digitized has less RMS power

than a -20dBFS sinusoid.

ADDRESS 0X4A: I2E POWER DOWN

This register provides the capability to completely power down the

I2E algorithm and the Notch (fs/4) filter. This would typically be done

to conserve power.

The default value of this register is 0x1000, causing I2E to freeze

when the input amplitude is less than -21.2 dBFS.

The freezing of I2E by the RMS power meter threshold affects the

gain and sample time skew interleave mismatch estimates, but not

the offset mismatch estimate.

BIT 0: Power down the I2E Algorithm

BIT 1: Power down the Notch (fs/4) Filter

0x52 RMS Power Hysteresis

ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS

In order to prevent I2E from constantly oscillating between the

Hold and Track state, there is hysteresis in the comparison

described above. After I2E enters a frozen state, the RMS input

power must achieve ³ threshold value + hysteresis to again enter

the Track state. The hysteresis quantity is a 24-bit value,

constructed with bits 23 through 12 (MSBs) being assigned to 0,

bits 11 through 4 assigned to this register’s value, and bits 3

through 0 (LSBs) assigned to 0.

This group of registers provides programming access to configure

I2E’s dynamic freeze control. As with any interleave mismatch

correction algorithm making estimates of the interleave

mismatch errors using the digitized application input signal,

there are certain characteristics of the input signal that can

obscure the mismatch estimates. For example, a DC input to the

A/D contains no information about the sample time skew

mismatch between the core A/Ds, and thus should not be used

by the I2E algorithm to update its sample time skew estimate.

FN7843.1

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ISLA212P50

0X53(LSBS), 0X54(MSBS) AC RMS POWER

THRESHOLD

TABLE 9. DIFFERENTIAL SKEW ADJUSTMENT

0x70[7:0]

PARAMETER

DIFFERENTIAL SKEW

Similar to RMS power threshold, there must be sufficient AC RMS

power (or dV/dt) of the input signal to measure sample time skew

mismatch for an arbitrary input. This is clear from observing the

effect when a high voltage (and therefore large RMS value) DC input

is applied to the A/D input. Without sufficient dV/dt in the input

signal, no information about the sample time skew between the

core A/Ds can be determined from the digitized samples. The AC

RMS Power Meter is implemented as a high-passed (via DSP) RMS

power meter.

Steps

256

-6.5ps

0.0ps

+6.5ps

51fs

–Full Scale (0x00)

Mid–Scale (0x80)

+Full Scale (0xFF)

Nominal Step Size

ADDRESS 0X71: PHASE_SLIP

The required algorithm is documented as follows.

The output data clock is generated by dividing down the A/D input

sample clock. Some systems with multiple A/Ds can more easily latch

the data from each A/D by controlling the phase of the output data

clock. This control is accomplished through the use of the phase_slip

SPI feature, which allows the rising edge of the output data clock to be

advanced by one input clock period, as shown in the Figure 42.

Execution of a phase_slip command is accomplished by first writing a

'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address

0x71.

1. Write the MSBs of the 16-bit quantity to SPI Address 0x54

2. Write the LSBs of the 16-bit quantity to SPI Address 0x53

Only the upper 12 bits of the ADC sample outputs are used in the

averaging process for comparison to the power threshold registers.

A 12-bit number squared produces a 24-bit result (for A/D

resolutions under 12-bits, the A/D samples are MSB-aligned to

12-bit data). A dynamic number of these 24-bit results are averaged

to compare with this threshold approximately every 1µs to decide

whether or not to freeze I2E. The 24-bit threshold is constructed with

bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned

to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. The

calculation methodology to set this register is identical to the

description in the RMS power threshold description.

ADC Input

Clock (500MHz)

2ns

4ns

Output Data

Clock (250MHz)

No clock_slip

2n

s

The freezing of I2E when the AC RMS power meter threshold is not

met affects the sample time skew interleave mismatch estimate,

but not the offset or gain mismatch estimates.

Output Data

Clock (250MHz)

1 clock_slip

Output Data

Clock (250MHz)

2 clock_slip

0x55 AC RMS Power Hysteresis

In order to prevent I2E from constantly oscillating between the

Hold and Track state, there is hysteresis in the comparison

described above. After I2E enters a frozen state, the AC RMS

input power must achieve threshold value + hysteresis to again

enter the Track state. The hysteresis quantity is a 24-bit value,

constructed with bits 23 through 12 (MSBs) being assigned to 0,

bits 11 through 4 assigned to this register’s value, and bits 3

through 0 (LSBs) assigned to 0.

FIGURE 42. PHASE SLIP

ADDRESS 0X72: CLOCK_DIVIDE

The ISLA212P50 has a selectable clock divider that can be set to

divide by two or one (no division). By default, the tri-level CLKDIV

pin selects the divisor This functionality can be overridden and

controlled through the SPI, as shown in Table 10. This register is

not changed by a Soft Reset.

Address 0x60-0x64: I2E initialization

These registers provide access to the initialization values for each of

offset, gain, and sample time skew that I2E programs into the target

core A/D before adjusting to minimize interleave mismatch. They

can be used by the system to, for example, reduce the convergence

time of the I2E algorithm by programming in the optimal values

before turning I2E on. In this case, I2E only needs to adjust for

temperature and voltage-induced changes since the optimal values

were recorded.

TABLE 10. CLOCK DIVIDER SELECTION

0x72[2:0]

VALUE

000

CLOCK DIVIDER

Pin Control

001

Divide by 1

010

Divide by 2

Global Device Configuration/Control

other

Not Allowed

ADDRESS 0X70: SKEW_DIFF

ADDRESS 0X73: OUTPUT_MODE_A

The value in the skew_diff register adjusts the timing skew

between the two A/D cores. The nominal range and resolution of

this adjustment are given in Table 9. The default value of this

register after power-up is 80h.

The output_mode_A register controls the physical output format

of the data, as well as the logical coding. The ISLA212P50 can

present output data in two physical formats: LVDS (default) or

LVCMOS. Additionally, the drive strength in LVDS mode can be set

high (default, 3mA or low (2mA).

FN7843.1

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ISLA212P50

Data can be coded in three possible formats: two’s complement

(default), Gray code or offset binary. See Table 12.

ADDRESS 0XC0: TEST_IO

Bits 7:4 Output Test Mode

This register is not changed by a Soft Reset.

TABLE 11. OUTPUT MODE CONTROL

These bits set the test mode according to table below. Other

values are reserved.User test patterns loaded at 0xC1 through

0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a

pattern depth value to [2:0] at 0xC0. See the memory map.

0x73[7:5]

VALUE

000

OUTPUT MODE

LVDS 3mA (Default)

LVDS 2mA

Bits 2:0 User Test Mode

The three LSBs in this register determine the test pattern in

combination with registers 0xC1 through 0xD0. Refer to the SPI

Memory Map on page 31.

001

100

LVCMOS

TABLE 14. OUTPUT TEST MODES

0xC0[7:4]

TABLE 12. OUTPUT FORMAT CONTROL

0x73[2:0]

VALUE

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

OUTPUT TEST MODE

WORD 1

WORD 2

VALUE

OUTPUT FORMAT

Two’s Complement (Default)

Gray Code

Off

000

Midscale

0x8000

0xFFFF

0x0000

N/A

010

Positive Full-Scale

Negative Full-Scale

Checkerboard (DDR)

Reserved

100

Offset Binary

ADDRESS 0X74: OUTPUT_MODE_B

Bit 6 DLL Range

N/A

Reserved

This bit sets the DLL operating range to fast (default) or slow.

All on/off (DDR)

User Pattern

Reserved

Internal clock signals are generated by a delay-locked loop (DLL),

which has a finite operating range. Table 13 shows the allowable

sample rate ranges for the slow and fast settings. Note that Bit 4

at 0x74 is reserved and must not change value. A user writing to

Bit 6 should first read 0x74 to determine proper value to write

back to Bit 4 when writing to 0x74.

user_patt1

N/A

user_patt2

N/A

Ramp

N/A

ADDRESS 0XC1: USER_PATT1_LSB

ADDRESS 0XC2: USER_PATT1_MSB

TABLE 13. DLL RANGES

DLL RANGE

Slow

MIN

80

MAX

200

500

UNIT

MSPS

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 1.

ADDRESS 0XC3: USER_PATT2_LSB

ADDRESS 0XC4: USER_PATT2_MSB

Fast

160

ADDRESS 0XB6: CALIBRATION STATUS

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 2

The LSB at address 0xB6 can be read to determine calibration

status. The bit is ‘0’ during calibration and goes to a logic ‘1’ when

calibration is complete.This register is unique in that it can be read

after POR at calibration, unlike the other registers on chip, which

can’t be read until calibration is complete.

ADDRESS 0XC5: USER_PATT3_LSB

ADDRESS 0XC6: USER_PATT3_MSB

These registers define the lower and upper eight bits, respectively, of

the user-defined pattern 3

DEVICE TEST

The ISLA212P50 can produce preset or user defined patterns on

the digital outputs to facilitate in-situ testing. A user can pick

from preset built-in patterns by writing to the output test mode

field [7:4] at C0h or user defined patterns by writing to the user

test mode field [2:0] at C0h. The user defined patterns should be

loaded at address space C1 through D0, see the “SPI Memory

Map” on page 31 for more detail. The predefined patterns are

shown in Table 14. The test mode is enabled asynchronously to

the sample clock, therefore several sample clock cycles may

elapse before the data is present on the output bus.

ADDRESS 0XC7: USER_PATT4_LSB

ADDRESS 0XC8: USER_PATT4_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 4.

ADDRESS 0XC9: USER_PATT5_LSB

ADDRESS 0XCA: USER_PATT5_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 5.

FN7843.1

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ISLA212P50

Bit [5] Temperature counter power down bit. Set to ‘1’ to power

down temperature counter.

ADDRESS 0XCB: USER_PATT6_LSB

ADDRESS 0XCC: USER_PATT6_MSB

Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 6

Bit [3:1] Three bit frequency divider field. Sets temperature counter

update rate. Update rate is proportional to ADC sample clock rate

and divide ratio. A ‘101’ updates the temp counter every ~ 66µs (for

250Msps). Faster updates rates result in lower precision.

ADDRESS 0XCD: USER_PATT7_LSB

ADDRESS 0XCE: USER_PATT7_MSB

Bit [0] Select sampler bit. Set to ‘0’.

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 7.

This set of registers provides digital access to an PTAT or

IPTAT-based temperature sensor, allowing the system to estimate

the temperature of the die, allowing easy access to information that

can be used to decide when to recalibrate the A/D as needed.

ADDRESS 0XCF: USER_PATT8_LSB

ADDRESS 0XD0: USER_PATT8_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 8

The nominal transfer function of the temperature counter is Codes

(in decimal) = 0.56*T(°C) + 618. This corresponds to approximately

a 65 LSB increase from -40°C to +85°C. The accuracy of the sensor

is approximately ±20% for both slope and starting code offset.

Digital Temperature Sensor

ADDRESS 0X4B: TEMP_COUNTER_HIGH

A typical temperature measurement can occur as follows:

Bits [2:0] of this register hold the 3 MSBs of the 11-bit temperature

code.

1. Write ‘0xCA’ to address 0x4D - enable temp counter, divide =

‘101’

Bit [7] of this register indicates a valid temperature_counter read

was performed. A logic ‘1’ indicates a valid read.

2. Wait >= 132uS (at 250Msps) - longer wait time ensures the

sensor completes one valid cycle.

ADDRESS 0X4C: TEMP_COUNTER_LOW

3. Write ‘0x20’ to address 0x4D - power-down, disable temp

counter - recommended between measurements. This

ensures that the output does not change between MSB and

LSB reads.

Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit

temperature code.

ADDRESS 0X4D: TEMP_COUNTER_CONTROL

4. Read address 0x4B (MSBs)

5. Read address 0x4C (LSBs)

6. Record temp code value

Bit [7] Measurement mode select bit, set to ‘1’ for recommended

PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and not

recommended.

7. Write ‘0x20’ to address 0x4D - power-down, disable temp

counter

Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.

Contact the factory for more information if needed.

FN7843.1

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30

ISLA212P50

SPI Memory Map

Addr.

Bit 7

(MSB)

Def. Value

(Hex)

Parameter Name

port_config

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

00

SDO

Active

LSB First

Soft

Reset

Mirror

(bit5)

Mirror

(bit6)

Mirror

(bit7)

00h

01

02

Reserved

burst_end

Reserved

Burst end address [7:0]

Reserved

00h

03-07

08

09

chip_id

chip_version

Chip ID #

Chip Version #

Reserved

Read only

0A-0F

10-1F

20

Reserved

offset_coarse_adc0

offset_fine_adc0

gain_coarse_adc0

gain_medium_adc0

gain_fine_adc0

modes_adc0

Coarse Offset

Fine Offset

cal. value

21

22

Reserved

Coarse Gain

23

Medium Gain

Fine Gain

24

25

Reserved

Power Down Mode ADC0 [2:0]

000 = Pin Control

001 = Normal Operation

010 = Nap

00h

NOT reset by

Soft Reset

100 = Sleep

Other codes = Reserved

26

27

28

29

2A

2B

offset_coarse_adc1

offset_fine_adc1

gain_coarse_adc1

gain_medium_adc1

gain_fine_adc1

Coarse Offset

Fine Offset

cal. value

Reserved

Coarse Gain

Medium Gain

Fine Gain

modes_adc1

Reserved

Power Down Mode ADC1 [2:0]

000 = Pin Control

001 = Normal Operation

010 = Nap

00h

NOT reset by

Soft Reset

100 = Sleep

Other codes = Reserved

2C-2F

30

Reserved

I2E_status

I2E

Settled

Low AC

RMS

Power

Low

RMS

Power

Read only

20h

31

32

I2E_control

Enable

Notch

(fs/4) Filter

Disable

Offset

Disable

Gain

Disable

Skew

Freeze

Run

I2E_static_control

Reserved

must be

set to 0

Skip

coarse

adj.

Reserved, must be set to 0

Should be

set to 1

01h

33-49

4A

Reserved

I2E_power_down

Notch

(fs/4)

Filter

I2E

Power

Down

03h

Power

Down

4B

4C

temp_counter_high

temp_counter_low

Temp Counter [10:8]

Read only

00h

Temp Counter [7:0]

Reset

4D

temp_counter_control

Reserved

Enable

PD

Divider [2:0] Select

4E-4F

50

Reserved

I2E_rms_power_threshold_lsb

RMS Power Threshold, LSBs [7:0]

00h

FN7843.1

May 25, 2011

31

ISLA212P50

SPI Memory Map (Continued)

Addr.

(Hex)

Bit 7

Def. Value

(Hex)

Parameter Name

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

51

I2E_rms_power_threshold_ms

b

RMS Power Threshold, MSBs [15:8]

10h

52

53

I2E_rms_hysteresis

RMS Power Hysteresis

FFh

I2E_ac_rms_power_threshold

_lsb

AC Power Threshold, LSBs, [7:0]

50h

54

I2E_ac_rms_power_threshold

_msb

AC Power Threshold, MSBs, [15:8]

00h

10h

55

56-5F

60

I2E_ac_rms_hysteresis

Reserved

AC RMS Power Hysteresis

Reserved

coarse_offset_init

fine_offset_init

medium_gain_init

fine_gain_init

Coarse Offset Initialization value

Fine Offset Initialization value

Medium Gain Initialization value

Fine Gain Initialization value

80h

61

62

63

64

sample_time_skew_init

Reserved

Sample Time Skew Initialization value

Reserved

65-6F

70

skew_diff

Differential Skew

Reserved

80h

00h

71

phase_slip

Next Clock

Edge

72

73

74

clock_divide

output_mode_A

output_mode_B

Clock Divide [2:0]

000 = Pin Control

001 = divide by 1

00h

NOT reset by

Soft Reset

010 = divide by 2

Other codes = Reserved

Output Mode [7:5]

000 =LVDS 3mA (Default)

001 = LVDS 2mA

100 = LVCMOS

Other codes = Reserved

Output Format [2:0]

000 = Two’s Complement (Default) NOT reset by

00h

010 = Gray Code

100 = Offset Binary

Other codes = Reserved

Soft Reset

DLL Range

0 = Fast

1 = Slow

Reserved

00h

NOT reset by

Soft Reset

(Default = ‘0’)

75-BF

A4

Reserved

dll_ctrl_upper_adc0

dll_ctrl_lower_adc0

dll_status_upper_adc0

dll_status_lower_adc0

dll_ctrl_upper_adc1

dll_ctrl_lower_adc1

dll_status_upper_adc1

dll_status_lower_adc1

Reserved

Consult Factory

Reserved

cal. value

Read only

cal. value

Read only

A5

A6

A7

A8

A9

AA

AB

AC-B5

B6

Cal_Status

Reserved

Calibration Read only

Done

B7-BF

Reserved

FN7843.1

May 25, 2011

32

ISLA212P50

SPI Memory Map (Continued)

Addr.

(Hex)

Bit 7

Def. Value

(Hex)

Parameter Name

test_io

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

C0

Output Test Mode (DDR) [7:4]

User Test Mode(DDR) [2:0]

00h

0 = Off (Note 14)

1 = Midscale Short

2 = +FS Short

3 = -FS Short

4 = Checker Board output - 0xAAAA, 0x5555

0 = cycle pattern 1 through 2

1 = cycle pattern 1 through 4

2 = cycle pattern 1 through 6

3 = cycle pattern 1 through 8

4-7 =NA

DDR

5 = Reserved

6 = Reserved

7 = 0xFFFF,0x0000 all on pattern, DDR Word

Toggle

8 = User Pattern (1 to 8 deep, DDR, MSB

justified)

9 = Reserved

10 = Ramp

11-15 = Reserved

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

user_patt1_lsb

user_patt1_msb

user_patt2_lsb

user_patt2_msb

user_patt3_lsb

user_patt3_msb

user_patt4_lsb

user_patt4_msb

user_patt5_lsb

user_patt5_msb

user_patt6_lsb

user_patt6_msb

user_patt7_lsb

user_patt7_msb

user_patt8_lsb

user_patt8_msb

Reserved

B7

B15

B7

B6

B14

B6

B5

B13

B5

B4

B12

B4

B3

B11

B3

B2

B10

B2

B1

B9

B1

B9

B1

B9

B1

B9

B1

B9

B1

B9

B1

B9

B1

B9

B0

B8

B0

B8

B0

B8

B0

B8

B0

B8

B0

B8

B0

B8

B0

B8

00h

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

CD

CE

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

CF

D0

D1-FD

FE

B15

B14

B13

B12

B11

B10

Reserved

VRAM_latch_enable

LE

00h

Active high

FF

Reserved

NOTE:

14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of

calibration. This behavior can be used as an option to monitoring Over range to determine calibration state.

FN7843.1

May 25, 2011

33

ISLA212P50

Equivalent Circuits

AVDD

TO

CLOCK-

AVDD

PHASE

GENERATION

CLKP

AVDD

CSAMP

9pF

TO

11kOΩ

INP

INN

CHARGE

PIPELINE

18kOΩ

E2

E3

E1

300 Ω

AVDD

CSAMP

9pF

18kOΩ

AVDD

TO

CHARGE

PIPELINE

E2

CLKN

E3

FIGURE 43. ANALOG INPUTS

FIGURE 44. CLOCK INPUTS

AVDD

(20k PULL-UP

ON RESETN

ONLY)

OVDD

AVDD

Ω

75kO

OVDD

AVDD

TO

SENSE

LOGIC

OVDD

Ω

75kO

20k

Ω

280O

INPUT

TO

LOGIC

280

Ω

75kO

Ω

75kO

FIGURE 45. TRI-LEVEL DIGITAL INPUTS

FIGURE 46. DIGITAL INPUTS

OVDD

2mA OR

3mA

OVDD

DATA

OVDD

D[11:0]P

D[11:0]N

OVDD

DATA

D[11:0]

DATA

2mA OR

3mA

FIGURE 48. CMOS OUTPUTS

FIGURE 47. LVDS OUTPUTS

FN7843.1

May 25, 2011

34

ISLA212P50

Equivalent Circuits(Continued)

AVDD

VCM

+

0.94V

–

FIGURE 49. VCM_OUT OUTPUT

LVDS Outputs

A/D Evaluation Platform

Output traces and connections must be designed for 50Ω (100Ω

differential) characteristic impedance. Keep traces direct and

minimize bends where possible. Avoid crossing ground and

power-plane breaks with signal traces.

Intersil offers an A/D Evaluation platform which can be used to

evaluate any of Intersil’s high speed A/D products. The platform

consists of a FPGA based data capture motherboard and a family

of A/D daughtercards. This USB based platform allows a user to

quickly evaluate the A/D’s performance at a user’s specific

application frequency requirements. More information is

available at

LVCMOS Outputs

Output traces and connections must be designed for 50Ω

http://www.intersil.com/converters/adc_eval_platform/

characteristic impedance.

Unused Inputs

Layout Considerations

Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will

not be operated do not require connection to ensure optimal A/D

performance. These inputs can be left floating if they are not

used. Tri-level inputs (NAPSLP) accept a floating input as a valid

state, and therefore should be biased according to the desired

functionality.

Split Ground and Power Planes

Data converters operating at high sampling frequencies require

extra care in PC board layout. Many complex board designs

benefit from isolating the analog and digital sections. Analog

supply and ground planes should be laid out under signal and

clock inputs. Locate the digital planes under outputs and logic

pins. Grounds should be joined under the chip.

Definitions

Analog Input Bandwidth is the analog input frequency at which

the spectral output power at the fundamental frequency (as

determined by FFT analysis) is reduced by 3dB from its full-scale

low-frequency value. This is also referred to as Full Power

Bandwidth.

Clock Input Considerations

Use matched transmission lines to the transformer inputs for the

analog input and clock signals. Locate transformers and

terminations as close to the chip as possible.

Aperture Delay or Sampling Delay is the time required after the

rise of the clock input for the sampling switch to open, at which

time the signal is held for conversion.

Exposed Paddle

The exposed paddle must be electrically connected to analog

ground (AVSS) and should be connected to a large copper plane

using numerous vias for optimal thermal performance.

Aperture Jitter is the RMS variation in aperture delay for a set of

samples.

Bypass and Filtering

Clock Duty Cycle is the ratio of the time the clock wave is at logic

high to the total time of one clock period.

Bulk capacitors should have low equivalent series resistance.

Tantalum is a good choice. For best performance, keep ceramic

bypass capacitors very close to device pins. Longer traces will

increase inductance, resulting in diminished dynamic

performance and accuracy. Make sure that connections to

ground are direct and low impedance. Avoid forming ground

loops.

Differential Non-Linearity (DNL) is the deviation of any code width

from an ideal 1 LSB step.

Effective Number of Bits (ENOB) is an alternate method of

specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it

is calculated as: ENOB = (SINAD - 1.76)/6.02

Gain Error is the ratio of the difference between the voltages that

cause the lowest and highest code transitions to the full-scale

voltage less 2 LSB. It is typically expressed in percent.

I2E The Intersil Interleave Engine. This highly configurable

circuitry performs estimates of offset, gain, and sample time

FN7843.1

May 25, 2011

35

ISLA212P50

skew mismatches between the core converters, and updates

analog adjustments for each to minimize interleave spurs.

Power Supply Rejection Ratio (PSRR) is the ratio of the observed

magnitude of a spur in the A/D FFT, caused by an AC signal

superimposed on the power supply voltage.

Integral Non-Linearity (INL) is the maximum deviation of the

A/D’s transfer function from a best fit line determined by a least

squares curve fit of that transfer function, measured in units of

LSBs.

Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS

signal amplitude to the RMS sum of all other spectral

components below one half the clock frequency, including

harmonics but excluding DC.

Least Significant Bit (LSB) is the bit that has the smallest value or

weight in a digital word. Its value in terms of input voltage is

Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS

signal amplitude to the RMS sum of all other spectral

components below one-half the sampling frequency, excluding

harmonics and DC.

N

V

/(2 -1) where N is the resolution in bits.

FS

Missing Codes are output codes that are skipped and will never

appear at the A/D output. These codes cannot be reached with

any input value.

SNR and SINAD are either given in units of dB when the power of

the fundamental is used as the reference, or dBFS (dB to full

scale) when the converter’s full-scale input power is used as the

reference.

Most Significant Bit (MSB) is the bit that has the largest value or

weight.

Pipeline Delay is the number of clock cycles between the

initiation of a conversion and the appearance at the output pins

of the data.

Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS

signal amplitude to the RMS value of the largest spurious

spectral component. The largest spurious spectral component

may or may not be a harmonic.

FN7843.1

May 25, 2011

36

ISLA212P50

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN7843.1

CHANGE

5/25/11

Initial Release to Web

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISLA212P50

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7843.1

May 25, 2011

37

ISLA212P50

Package Outline Drawing

L72.10x10E

72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 11/09

10.00

A

Z

X

6

EXPOSED

PAD AREA

9.75

B

PIN #1

72

INDEX AREA

1

6

PIN 1

INDEX AREA

9.75

10.00

0.100 M C A B

(4X)

0.15

4.150 REF.

7.150 REF.

TOP VIEW

9.75 ±0.10

0.100 M C A B

BOTTOM VIEW

11°

Y

ALL AROUND

C0.400X45° (4X)

10.00 ±0.10

SIDE VIEW

(0.350)

R0.200

(7.15)

(4.15 REF)

1

0.500 ±0.100

R0.115 TYP.

72

(4X 9.70)

(4X 8.50)

(3.00 )

DETAIL "X"

DETAIL "Z"

(6.00)

R0.200 MAX.

ALL AROUND

( 72X 0 .23)

0.100 C

( 72X 0 .70)

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

SEATING

PLANE

0.080C

0.190~0.245

0.23 ±0.050

2. Dimensioning and tolerancing conform to ANSI Y14.5m-1994.

0.50

C

0.025 ±0.020

3.

Unless otherwise specified, tolerance : Decimal ± 0.10

Angular ±2.50°

0.100M C A B

0.050M C

4. Dimension applies to the metallized terminal and is measured

between 0.015mm and 0.30mm from the terminal tip.

DETAIL "Y"

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

Package outline compliant to JESD-M0220.

7.

FN7843.1

May 25, 2011

38


型号：	ISLA212P50_1105
厂家：	Intersil
描述：	12-Bit, 500MSPS ADC Programmable Built-in Test Patterns 12位，500Msps ADC可编程内置测试模式测试
文件：	总38页 (文件大小：1204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISLA212P50_1105 [INTERSIL]

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