KAD5510P-21Q48 [INTERSIL]
Low Power 10-Bit, 250/210/170/125MSPS ADC; 低功耗， 10位，二百一十分之二百五十零/ 170 / 125MSPS ADC
| 型号： | KAD5510P-21Q48 |
| 厂家： | 
Intersil |
| 描述： | Low Power 10-Bit, 250/210/170/125MSPS ADC |
| 文件： | 总31页 (文件大小：1155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power 10-Bit, 250/210/170/125MSPS ADC
KAD5510P
Features
The KAD5510P is a family of low power, high performance 10-bit
analog-to-digital converters. Designed with Intersil’s proprietary
FemtoCharge™ technology on a standard CMOS process, the
family supports sampling rates of up to 250MSPS. The
KAD5510P is part of a pin-compatible portfolio of 10, 12 and
14-bit A/Ds with sample rates ranging from 125MSPS to
500MSPS.
• 1.5GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Programmable Gain, Offset and Skew Control
• Over-Range Indicator
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Clock Phase Selection
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters such
as gain and offset.
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
Digital output data is presented in selectable LVDS or CMOS formats.
The KAD5510P is available in a 48-contact QFN package with an
exposed paddle. Operating from a 1.8V supply, performance is
specified over the full industrial temperature range (-40°C to +85°C).
Key Specifications
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• SNR = 60.7dBFS for f = 105MHz (-1dBFS)
IN
• SFDR = 86.1dBc for f = 105MHz (-1dBFS)
IN
• Total Power Consumption
- 234/189mW @ 250/125MSPS (DDR Mode)
• High-Performance Data Acquisition
• Communications Test Equipment
• WiMAX and Microwave Receivers
Related Literature
• See FN6811, KAD5510P-50, “10-Bit, 500MSPS A/D
Converter”
0
Ain = -1.0dBFS
SNR = 60.7dBFS
CLKP
CLKOUTP
CLKOUTN
CLOCK
-20
-40
SFDR = 85.9dBc
GENERATION
CLKN
SINAD = 60.7dBFS
(DDR)
D[4:0]P
D[4:0]N
-60
VINP
VINN
10-BIT
250 MSPS
ADC
DIGITAL
ERROR
CORRECTION
SHA
-80
ORP
ORN
-100
-120
VCM
LVDS/CMOS
DRIVERS
+
–
OUTFMT
1.25V
SPI
CONTROL
OUTMODE
0M
20M
40M
60M
80M
100M
120M
FREQUENCY (Hz)
SINGLE-TONE SPECTRUM @ 105MHz (250MSPS)
January 3, 2011
FN7693.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
KAD5510P
Pin-Compatible Family
PACKAGE
SPEED
(MSPS)
MODEL
KAD5514P-25/21/17/12
KAD5512P-50
RESOLUTION
Q48EP
X
Q72EP
14
12
12
12
10
10
250/210/170/125
500
X
X
X
X
X
KAD5512P-25/21/17/12
KAD5512HP-25/21/17/12
KAD5510P-50
250/210/170/125
250/210/170/125
500
X
X
KAD5510P-25/21/17/12
250/210/170/125
X
Pin Configuration
KAD5510P
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
AVDD
DNC
DNC
DNC
AVSS
VINN
D3P
D3N
D2P
D2N
3
4
5
32 CLKOUTP
6
31
30
29
CLKOUTN
RLVDS
PAD
7
VINP
AVSS
AVDD
8
OVSS
9
28 D1P
D1N
VCM
10
27
26 D0P
D0N
DNC 11
CONNECT THERMAL PAD TO AVSS
AVSS
12
25
13 14 15 16 17 18 19 20 21 22 23 24
FIGURE 1. PIN CONFIGURATION
FN7693.1
January 3, 2011
2
KAD5510P
Pin Descriptions - 48 Ld QFN
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 9, 13, 17, 47
AVDD
DNC
1.8V Analog Supply
Do Not Connect
2, 3, 4, 11, 21, 22,
23, 24
5, 8, 12, 48
6, 7
AVSS
VINN, VINP
VCM
Analog Ground
Analog Input Negative, Positive
Common Mode Output
10
14, 15
16
CLKP, CLKN
NAPSLP
RESETN
OVSS
Clock Input True, Complement
Tri-Level Power Control (Nap, Sleep modes)
Power On Reset (Active Low, see page 16)
Output Ground
18
19, 29, 42
20, 37
25
OVDD
1.8V Output Supply
D0N
[NC]
LVDS DDR Logical Bits 1, 0 Output Complement
[NC in LVCMOS]
26
27
28
D0P
[D0]
LVDS DDR Logical Bits 1, 0 Output True
[CMOS DDR Logical Bits 1, 0 in LVCMOS]
D1N
[NC]
LVDS DDR Logical Bits 3, 2 Output Complement
[NC in LVCMOS]
D1P
[D1]
LVDS DDR Logical Bits 3, 2 Output True
[CMOS DDR Logical Bits 3, 2 in LVCMOS]
30
31
RLVDS
LVDS Bias Resistor (Connect to OVSS with a 10kΩ, 1% resistor)
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
32
33
34
35
36
38
39
40
41
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
D2N
[NC]
LVDS DDR Logical Bits 5, 4 Output Complement
[NC in LVCMOS]
D2P
[D2]
LVDS DDR Logical Bits 5, 4 Output True
[CMOS DDR Logical Bits 5, 4 in LVCMOS]
D3N
[NC]
LVDS DDR Logical Bits 7, 6 Output Complement
[NC in LVCMOS]
D3P
[D3]
LVDS DDR Logical Bits 7, 6 Output True
[CMOS DDR Logical Bits 7, 6 in LVCMOS]
D4N
[NC]
LVDS DDR Logical Bits 9, 8 Output Complement
[NC in LVCMOS]
D4P
[D4]
LVDS DDR Logical Bits 9, 8 Output True
[CMOS DDR Logical Bits 9, 8 in LVCMOS]
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
43
44
45
46
SDO
CSB
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
SPI Chip Select (active low)
SCLK
SDIO
AVSS
SPI Clock
SPI Serial Data Input/Output
PAD
Analog Ground (Connect to a low thermal impedance analog ground plane with
multiple vias)
(Exposed Paddle)
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).
FN7693.1
January 3, 2011
3
KAD5510P
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
KAD5510P-25Q48
KAD5510P-21Q48
KAD5510P-17Q48
KAD5510P-12Q48
NOTES:
KAD5510P-25 Q48EP-I
KAD5510P-21 Q48EP-I
KAD5510P-17 Q48EP-I
KAD5510P-12 Q48EP-I
250
210
170
125
-40 to +85
-40 to +85
-40 to +85
-40 to +85
48 Ld QFN
48 Ld QFN
48 Ld QFN
48 Ld QFN
L48.7x7E
L48.7x7E
L48.7x7E
L48.7x7E
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for KAD5510P. For more information on MSL please see techbrief TB363.
FN7693.1
January 3, 2011
4
KAD5510P
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
User-Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VCM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Over Range Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Indexed Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
48 Pin Package Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PCB Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bypass and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FN7693.1
January 3, 2011
5
KAD5510P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Resistance (Typical)
48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
JA (°C/W)
25
θ
JC (°C/W)
0.5
Recommended Operating Conditions
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V
OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f
Boldface limits apply over the operating temperature range, -40°C to +85°C.
= Maximum Conversion Rate (per speed grade).
A
IN
SAMPLE
KAD5510P-25
KAD5510P-21
KAD5510P-17
KAD5510P-12
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
V
Differential
1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54
V
P-P
FS
Input Resistance
Input Capacitance
R
C
Differential
Differential
Full Temp
1000
1.8
1000
1.8
1000
1.8
1000
1.8
Ω
pF
IN
IN
Full Scale Range
Temp. Drift
A
90
90
90
90
ppm/°C
VTC
Input Offset Voltage
Gain Error
V
-10
±2
10
-10
±2
10
-10
±2
10
-10
±2
10
mV
%
OS
E
±0.6
±0.6
±0.6
±0.6
G
Common-Mode
Output Voltage
V
435 535 635 435 535 635 435 535 635 435 535 635
mV
CM
Common-Mode
Input Current (per
pin)
I
2.5
2.5
2.5
2.5
µA/
MSPS
CM
Clock Inputs
Input Common
Mode Voltage
0.9
1.8
0.9
0.9
1.8
0.9
1.8
V
V
CLKP,CLKN Input
Swing
1.8
Power Requirements
1.8V Analog Supply
Voltage
AVDD
OVDD
1.7
1.7
1.8
1.8
1.9 1.7
1.9 1.7
1.8
1.8
1.9 1.7
1.9 1.7
1.8
1.8
1.9 1.7
1.9 1.7
1.8
1.8
1.9
1.9
V
V
1.8V Digital Supply
Voltage
FN7693.1
January 3, 2011
6
KAD5510P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f = Maximum Conversion Rate (per speed grade).
SAMPLE
A
IN
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
KAD5510P-25 KAD5510P-21
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
KAD5510P-17
KAD5510P-12
PARAMETER
SYMBOL
CONDITIONS
1.8V Analog Supply
Current
I
90
96
83
89
77
82
69
74
mA
AVDD
I
1.8V Digital Supply
Current (DDR)
(Note 5)
3mA LVDS
39
45
38
45
36
40
35
40
mA
OVDD
Power Supply
Rejection Ratio
PSRR
30MHz, 200mV
signal on AVDD
-36
-36
-36
-36
dB
P-P
Total Power Dissipation
Normal Mode
(DDR)
P
3mA LVDS
234 254
219 242
204 220
189 205
mW
D
Nap Mode
P
P
84
2
95
6
80
2
91
6
78
2
88
6
74
2
84
6
mW
mW
µs
D
D
Sleep Mode
CSB at logic high
Nap Mode Wakeup
Time (Note 6)
Sample Clock
Running
1
1
1
1
Sleep Mode
Wakeup Time
(Note 6)
Sample Clock
Running
1
1
1
1
ms
AC SPECIFICATIONS
Differential
Nonlinearity
DNL
INL
-0.5 ±0.12 0.5 -0.5 ±0.17 0.5 -0.5 ±0.17 0.5 -0.5 ±0.17 0.5
-0.75 ±0.2 0.75 -0.75 ±0.3 0.75 -0.75 ±0.3 0.75 -0.75 ±0.3 0.75
LSB
LSB
Integral
Nonlinearity
Minimum
f
MIN
40
40
40
40
MSPS
S
Conversion Rate
(Note 7)
Maximum
f
MAX
250
210
170
125
MSPS
S
Conversion Rate
Signal-to-Noise
Ratio
SNR
f
f
f
f
f
f
f
f
f
f
f
f
= 10MHz
60.8
60.8
61.0
61.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 10MHz
59.5 60.7
60.6
60.0 60.9
60.8
60.2 61.0
60.9
60.2 61.0
60.9
60.5
60.6
60.7
60.7
59.9
60.0
60.1
60.0
59.1
59.2
59.3
59.2
Signal-to-Noiseand
Distortion
SINAD
60.7
60.8
60.9
61.0
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
59.3 60.7
60.5
59.9 60.9
60.8
60.0 60.9
60.8
60.0 61.0
60.9
60.4
60.5
60.6
60.4
56.5
57.3
56.9
56.6
49.8
46.9
47.7
49.1
FN7693.1
January 3, 2011
7
KAD5510P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f = Maximum Conversion Rate (per speed grade).
SAMPLE
A
IN
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
KAD5510P-25 KAD5510P-21
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
KAD5510P-17
KAD5510P-12
PARAMETER
SYMBOL
CONDITIONS
= 10MHz
Effective Number of
Bits
ENOB
f
f
f
f
f
f
f
f
f
f
f
f
f
f
9.8
9.8
9.8
9.7
9.1
8.0
83.0
9.8
9.8
9.8
9.8
9.2
7.5
82.0
9.8
9.8
9.8
9.8
9.2
7.6
78.0
9.8
9.8
9.8
9.7
9.1
7.9
79.0
Bits
Bits
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 10MHz
9.5
9.6
9.6
9.6
Bits
Bits
Bits
Bits
Spurious-Free
Dynamic Range
SFDR
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 70MHz
73.0 86.1
78.0
73.0 86.6
80.1
73.0 84.6
81.0
73.0 85.8
81.2
76.2
77.1
77.9
72.1
60.8
61.9
61.0
61.1
50.2
47.2
47.9
49.4
Intermodulation
Distortion
IMD
-86.1
-96.9
-92.1
-87.1
-94.5
-91.6
-95.1
-85.7
= 170MHz
-12
10
-12
10
-12
10
-12
10
Word Error Rate
WER
Full Power
Bandwidth
FPBW
1.5
1.5
1.5
1.5
GHz
NOTES:
5. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
specifications apply for 10pF load on each digital
OVDD
output.
6. See “Nap/Sleep” on page 18 for more details.
7. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 21 for more detail.
FN7693.1
January 3, 2011
8
KAD5510P
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS
Input Current High (SDIO, RESETN, CSB, SCLK)
Input Current Low (SDIO, RESETN, CSB, SCLK)
Input Voltage High (SDIO, RESETN, CSB, SCLK)
Input Voltage Low (SDIO, RESETN, CSB, SCLK)
Input Current High (NAPSLP) (Note 9)
Input Current Low (NAPSLP)
Input Capacitance
I
V
V
= 1.8V
= 0V
0
1
10
-5
µA
µA
V
IH
IN
IN
I
-25
1.17
-12
IL
V
IH
V
0.63
40
V
IL
I
15
25
25
3
µA
µA
pF
IH
I
-40
-15
IL
C
DI
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
V
3mA Mode
3mA Mode
620
965
500
500
mV
T
P-P
V
950
980
mV
OS
Output Rise Time
t
ps
ps
R
Output Fall Time
t
F
CMOS OUTPUTS
Voltage Output High
V
I
I
= -500µA
= 1mA
OVDD - 0.3
OVDD - 0.1
0.1
V
V
OH
OH
OL
Voltage Output Low
V
0.3
OL
Output Rise Time
t
1.8
ns
ns
R
Output Fall Time
t
1.4
F
FN7693.1
January 3, 2011
9
KAD5510P
Timing Diagrams
SAMPLE N
INP
INN
t
A
CLKN
CLKP
t
CPD
LATENCY = L CYCLES
CLKOUTN
CLKOUTP
t
DC
t
D[8/6/4/2/0]P
D[8/6/4/2/0]N
PD
ODD BITS
ODD BITS EVEN BITS
ODD BITS
EVEN BITS
EVEN BITS
N-L + 2
EVEN BITS
N-L + 1
N-L
N-L + 1
N
N-L + 2
N-L
FIGURE 1. DDR LVDS TIMING DIAGRAM (See “Digital Outputs” on page 18)
SAMPLE N
INP
INN
t
A
CLKN
CLKP
t
CPD
LATENCY = L CYCLES
CLKOUT
t
DC
t
PD
ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS
EVEN BITS
D[8/6/4/2/0]
N-L N-L N-L + 1 N-L + 1 N-L + 2 N-L + 2
N
FIGURE 1. DDR CMOS TIMING DIAGRAM (See “Digital Outputs” on page 18)
FN7693.1
January 3, 2011
10
KAD5510P
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
CONDITION
SYMBOL
(Note 8)
TYP
(Note 8)
UNITS
ADC OUTPUT
Aperture Delay
t
375
60
ps
fs
A
RMS Aperture Jitter
j
A
Output Clock to Data Propagation Delay,
LVDS Mode (Note 10)
DDR Rising Edge
t
t
t
t
t
t
-260
-160
-260
-220
-310
-310
-50
10
120
230
230
200
110
200
ps
DC
DC
DC
DC
DC
DDR Falling Edge
SDR Falling Edge
DDR Rising Edge
DDR Falling Edge
SDR Falling Edge
ps
-40
-10
-90
-50
7.5
1
ps
Output Clock to Data Propagation Delay,
CMOS Mode (Note 10)
ps
ps
ps
DC
L
Latency (Pipeline Delay)
Overvoltage Recovery
SPI INTERFACE (Notes 11, 12)
SCLK Period
cycles
cycles
t
OVR
t
Write Operation
16
cycles
CLK
(Note 11)
Read Operation
Read or Write
Read or Write
Read or Write
Write
t
66
25
1
cycles
%
CLK
SCLK Duty Cycle (t /t
HI CLK
or t /t
LO CLK)
50
75
CSB↓ to SCLK↑ Setup Time
t
cycles
cycles
cycles
cycles
cycles
cycles
µs
S
CSB↑ after SCLK↑ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
Data Invalid after SCLK↑ Time
t
3
H
t
1
DSW
Write
t
3
DHW
Read
t
16.5
DVR
Read
t
3
DHR
Sleep Mode CSB↓ to SCLK↑ Setup Time
Read or Write in Sleep Mode
t
150
S
(Note 13)
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact factory for more info if needed.
11. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps).
12. The SPI may operate asynchronously with respect to the ADC sample clock but the ADC sample clock must be active to access SPI registers.
13. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time
(4ns min).
FN7693.1
January 3, 2011
11
KAD5510P
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions
unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f = Maximum Conversion Rate
SAMPLE
A
IN
IN
(per speed grade).
90
85
80
75
70
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
SFDR @ 125MSPS
SFDR @ 250MSPS
HD2 @ 125MSPS
HD2 @ 250MSPS
HD3 @ 125MSPS
SNR @ 125MSPS
65
60
55
50
HD3 @ 250MSPS
SNR @ 250MSPS
0M 200M
400M
600M
800M
1G
0M
200M
400M
600M
800M
1G
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
FIGURE 3. HD2 AND HD3 vs f
FIGURE 2. SNR AND SFDR vs f
IN
IN
100
90
80
70
60
50
40
30
20
10
0
-10
-20
SFDRFS (dBFS)
SNRFS (dBFS)
-30
-40
HD3 (dBc)
HD2 (dBc)
-50
-60
-70
HD2 (dBFS)
SFDR (dBc)
-80
SNR (dBc)
-90
-100
-110
HD3 (dBFS)
-40
INPUT AMPLITUDE (dBFS)
-60
-50
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
FIGURE 4. SNR AND SFDR vs A
FIGURE 5. HD2 AND HD3 vs A
IN
IN
90
85
80
75
70
65
60
55
-60
-70
SFDR
HD3
-80
-90
HD2
-100
-110
-120
SNR
40
70
100
130
160
190
220
250
40
70
100
130
160
190
220
250
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 6. SNR AND SFDR vs f
FIGURE 7. HD2 AND HD3 vs f
SAMPLE
SAMPLE
FN7693.1
January 3, 2011
12
KAD5510P
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions
unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f = Maximum Conversion Rate
SAMPLE
A
IN
IN
(per speed grade). (Continued)
450
400
350
300
250
200
150
100
50
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
0
40
70
100
130
160
190
220
250
0
128
256
384
512
640
768
896
1024
CODE
SAMPLE RATE (MSPS)
FIGURE 8. POWER vs f
IN 3mA LVDS MODE
FIGURE 9. DIFFERENTIAL NONLINEARITY
SAMPLE
90
85
80
75
70
65
60
55
50
0.25
0.20
0.15
SFDR
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
SNR
300
400
500
600
700
800
0
128
256
384
512
640
768
896
1024
INPUT COMMON MODE (mV)
CODE
FIGURE 11. SNR AND SFDR vs VCM
FIGURE 10. INTEGRAL NONLINEARITY
70000
40000
10000
80000
50000
20000
90000
60000
30000
0
0
-20
Ain = -1.0dBFS
SNR = 60.7dBFS
SFDR = 82.5dBc
SINAD = 60.7dBFS
-40
-60
-80
-100
-120
2050 2051 2052 2053 2054 2055 2056 2057 2058
CODE
0M
20M
40M
60M
80M
100M
120M
FREQUENCY (Hz)
FIGURE 12. NOISE HISTOGRAM
FIGURE 13. SINGLE-TONE SPECTRUM @ 10MHz
FN7693.1
January 3, 2011
13
KAD5510P
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions
unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz, f
(per speed grade). (Continued)
= Maximum Conversion Rate
A
IN
IN
SAMPLE
0
0
Ain = -1.0dBFS
SNR = 60.7dBFS
Ain = -1.0dBFS
SNR = 60.6dBFS
-20
-20 SFDR = 78.5dBc
SINAD = 60.5dBFS
SFDR = 85.9dBc
SINAD = 60.7dBFS
-40
-40
-60
-80
-60
-80
-100
-120
-100
-120
0M
20M
40M
60M
80M
100M
120M
0M
20M
40M
60M
80M
100M
120M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
0
-20
0
Ain = -1.0dBFS
Ain = -1.0dBFS
SNR = 60.2dBFS
SFDR = 68.9dBc
SINAD = 59.4dBFS
SNR = 58.9dBFS
SFDR = 49.8dBc
SINAD = 49.5dBFS
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0M
20M
40M
60M
80M
100M
120M
0M
20M
40M
60M
80M
100M
120M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. SINGLE-TONE SPECTRUM @ 995MHz
FIGURE 16. SINGLE-TONE SPECTRUM @ 495MHz
0
0
-20
IMD = -86.1dBFS
IMD = -96.9dBFS
-20
-40
-60
-40
-60
-80
-80
-100
-120
-100
-120
0M
20M
40M
60M
80M
100M
120M
0M
20M
40M
60M
80M
100M
120M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 18. TWO-TONE SPECTRUM @ 70MHz
FIGURE 19. TWO-TONE SPECTRUM @ 170MHz
FN7693.1
January 3, 2011
14
KAD5510P
A user-initiated reset can subsequently be invoked in the event
that the previously mentioned conditions cannot be met at
power-up.
Theory of Operation
Functional Description
The KAD5510P is based upon a 10-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture (Figure
20). The input voltage is captured by a Sample-Hold Amplifier (SHA) and
converted to a unit of charge. Proprietary charge-domain techniques
are used to successively compare the input to a series of reference
charges. Decisions made during the successive approximation
operations determine the digital code for each input value. The
converter pipeline requires six samples to produce a result. Digital error
correction is also applied, resulting in a total latency of seven and one
half clock cycles. This is evident to the user as a time lag between the
start of a conversion and the data being available on the digital outputs.
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If the
SDO pin is pulled low externally during power-up, calibration will
not be executed properly.
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high starting the calibration
sequence. When the RESETN pin is driven by external logic, it
should be connected to an open-drain output with open-state
leakage of less than 0.5mA to assure exit from the reset state. A
driver that can be switched from logic low to high impedance can
also be used to drive RESETN provided the high impedance state
leakage is less than 0.5mA and the logic voltages are the same.
Power-On Calibration
The calibration sequence is initiated on the rising edge of RESETN, as
shown in Figure 21. The over-range output (OR) is set high once RESETN
is pulled low, and remains in that state until calibration is complete. The
OR output returns to normal operation at that time, so it is important
that the analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range condition, the OR
pin will stay high, and it will not be possible to detect the end of the
calibration cycle.
The ADC performs a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is deasserted.
At 250MSPS the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
• DNC pins must not be pulled up or down
• SDO must be high
• RESETN will be pulled low by the ADC during POR then
released
• SPI communications must not be attempted
CLOCK
GENERATION
INP
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
SHA
INN
+
1.25V
–
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 20. ADC CORE BLOCK DIAGRAM
FN7693.1
January 3, 2011
15
KAD5510P
CLKN
CLKP
3
CALIBRATION
TIME
CAL DONE AT
+85°C
2
1
RESETN
ORP
0
CALIBRATION
BEGINS
-1
-2
-3
-4
CAL DONE AT
+25°C
CAL DONE AT
-40°C
CALIBRATION
COMPLETE
CLKOUTP
-40
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 22. SNR PERFORMANCE vs TEMPERATURE
FIGURE 21. CALIBRATION TIMING
15
10
5
User-Initiated Reset
CAL DONE AT
-40°C
Recalibration of the ADC can be initiated at any time by driving the
RESETN pin low for a minimum of one clock cycle. An open-drain driver
with less than 0.5mA open-state leakage is recommended so the
internal high impedance pull-up to OVDD can assure exit from the reset
state. As is the case during power-on reset, the SDO, RESETN and DNC
pins must be in the proper state for the calibration to successfully
execute.
0
-5
CAL DONE AT
+25°C
CAL DONE AT
-10
-15
+85°C
The performance of the KAD5510P changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the ADC under the environmental conditions at
which it will operate.
-40
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 23. SFDR PERFORMANCE vs TEMPERATURE
Analog Input
The ADC core contains a fully differential input (VINP/VINN) to
the sample and hold amplifier (SHA). The ideal full-scale input
voltage is 1.45V, centered at the VCM voltage of 0.535V as
shown in Figure 24.
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.5dBFS and SFDR change
of less than 3dBc.
In situations where the sample rate is not constant, best results will be
obtained if the device is calibrated at the highest sample rate. Reducing
the sample rate by less than 75MSPS will typically result in an SNR
change of less than 0.5dBFS and an SFDR change of less than 3dBc.
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 25 through
27. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 25 and 26.
Figures 22 and 23 show the effect of temperature on SNR and
SFDR performance with calibration performed at -40°C, +25°C,
and +85°C. Each plot shows the variation of SNR/SFDR across
temperature after a single calibration at -40°C, +25°C and
+85°C. Best performance is typically achieved by a user-initiated
calibration at the operating conditions, as stated earlier.
1.8
However, it can be seen that performance drift with temperature
is not a very strong function of the temperature at which the
calibration is performed. Full rated performance will be achieved
after power-up calibration regardless of the operating conditions.
1.4
INN
INP
1.0
0.6
0.2
0.725V
VCM
0.535V
FIGURE 24. ANALOG INPUT RANGE
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January 3, 2011
16
KAD5510P
This dual transformer scheme is used to improve common-mode
250MSPS) may be used to calculate the expected voltage drop
across any series resistance.
rejection, which keeps the common-mode level of the input matched to
VCM. The value of the shunt resistor should be determined based on the
desired load impedance. The differential input resistance of the
KAD5510P is 1000Ω.
VCM Output
The VCM output is buffered with a series output impedance of
20Ω. It can easily drive a typical ADC driver’s 10kΩ common
mode control pin. If an external buffer is not used the voltage
drop across the internal 20Ω impedance must be considered
when calculating the expected DC bias voltage at the analog
input pins.
ADT1-1WT
ADT1-1WT
1000pF
KAD5512P
VCM
Clock Input
0.1µF
The clock input circuit is a differential pair (see Figure 41).
Driving these inputs with a high level (up to 1.8V
on each
P-P
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
FIGURE 25. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
The recommended drive circuit is shown in Figure 28. A duty
cycle range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
ADTL1-12 ADTL1-12
0.1µF
1000pF
KAD5512P
VCM
1000pF
200pF
TC4-1W
CLKP
1000pF
200pF
FIGURE 26. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
Ω
200
The SHA design uses a switched capacitor input stage
(see Figure 40 on page 27), which creates current spikes when
the sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle before
the next sampling point. Lower source impedance will result in
faster settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
CLKN
200pF
FIGURE 28. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. This allows
the use of the Phase Slip feature, which enables synchronization
of multiple ADCs.
Ω
348
Ω
69.8
The clock divider can be controlled through the SPI port. Details on this
are contained in “Serial Peripheral Interface” on page 21.
Ω
25
100Ω
Ω
KAD5512P
VCM
A delay-locked loop (DLL) generates internal clock signals for
various stages within the charge pipeline. If the frequency of the
input clock changes, the DLL may take up to 52µs to regain lock
at 250MSPS. The lock time is inversely proportional to the
sample rate.
217
CM
Ω
100
0.22µF
Ω
25
Ω
49.9
Ω
69.8
0.1µF
Ω
348
Jitter
FIGURE 27. DIFFERENTIAL AMPLIFIER INPUT
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
A differential amplifier, as shown in Figure 27, can be used in
applications that require DC-coupling. In this configuration, the
amplifier will typically dominate the achievable SNR and
distortion performance.
between clock jitter (t ) and SNR is shown in Equation 1 and is
J
illustrated in Figure 29.
1
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
10
2πf
t
IN J
The current spikes from the SHA will try to force the analog input
pins toward ground. In cases where the input pins are biased with
more than 50 ohms in series from VCM care must be taken to
make sure the input common mode range is not violated. The
provided ICM value (250µA/MHz * 250MHz = 625µA at
FN7693.1
January 3, 2011
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KAD5510P
Over Range Indicator
100
95
90
85
80
75
70
65
60
55
50
The over range (OR) bit is asserted when the output code reaches
positive full-scale (e.g. 0xFFF in offset binary mode). The output
code does not wrap around during an over-range condition. The OR
bit is updated at the sample rate.
tj = 0.1ps
14 BITS
12 BITS
tj = 1ps
Power Dissipation
tj = 10ps
The power dissipated by the KAD5510P is primarily dependent
on the sample rate and the output modes: LVDS vs. CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation is approximately constant in
LVDS mode, but linearly related to the clock frequency in CMOS
mode. Figures 33 and 34 illustrate these relationships.
10 BITS
tj = 100ps
1
10
100
1000
INPUT FREQUENCY (MHz)
FIGURE 29. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 1. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to less than 95mW and recovers to normal operation in
approximately 1µs. Sleep mode reduces power dissipation to less
than 6mW but requires approximately 1ms to recover from a sleep
command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during sleep,
requiring a user to wait 150µs max after CSB is asserted
(brought low) prior to writing ‘001x’ to SPI Register 25. The
device would be fully powered up, in normal mode 1ms after this
command is written.
Voltage Reference
A temperature compensated voltage reference provides the reference
charges used in the successive approximation operations. The full-scale
range of each A/D is proportional to the reference voltage. The voltage
reference is internally bypassed and is not accessible to the user.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible or
CMOS double data rate (DDR) modes. When CLKOUT is low the
MSB and all odd logical bits are output, while on the high phase
the LSB and all even logical bits are presented. Figures 1 and 1
show the timing relationships for LVDS/CMOS DDR modes.
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
The KAD5510P is only offered in the 48-QFN package with five
LVDS data output pin pairs. It only supports outputs in DDR
mode.
In an application where CSB was kept low in sleep mode, the
150µs CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation increases
by ~ 15mW in this case. The 1ms wake-up time after the write of a
‘001x’ to register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional SPI
activity on the ADC.
LVDS output drive current can be set to a nominal 3mA or a
power-saving 2mA. The lower current setting can be used in
designs where the receiver is in close physical proximity to the
ADC. The applicability of this setting is dependent upon the PCB
layout, therefore the user should experiment to determine if
performance degradation is observed.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
The output mode and LVDS drive current are selected via SPI
registers. Details are contained in “Serial Peripheral Interface” on
page 21.
Care should be taken when using the DDR CMOS outputs at clock
rates greater than 200MHz. Series termination resistors close to
the ADC should drive short traces with minimum parasitic
loading to assure adequate signal integrity.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 1.
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
FN7693.1
January 3, 2011
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KAD5510P
TABLE 1. NAPSLP PIN SETTINGS
NAPSLP PIN
BINARY
9
8
7
1
0
• • • •
MODE
Normal
Sleep
Nap
AVSS
Float
AVDD
• • • •
• • • •
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 21. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin.
GRAY CODE
9
8
7
1
0
FIGURE 30. BINARY TO GRAY CODE CONVERSION
Data Format
Output data can be presented in three formats: two’s complement,
Gray code and offset binary. The data format can be controlled
through the SPI port. Details on this are contained in “Serial
Peripheral Interface” on page 21.
GRAY CODE
9
8
7
1
0
• • • •
Offset binary coding maps the most negative input voltage to code
0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s
complement coding simply complements the MSB of the offset binary
representation.
• • • •
• • • •
• • • •
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 30 shows this
operation.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 31.
Mapping of the input voltage to the various data formats is
shown in Table 2.
BINARY
9
8
7
1
0
FIGURE 31. GRAY CODE TO BINARY CONVERSION
TABLE 2. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT VOLTAGE
–Full Scale
OFFSET BINARY
000 00 000 00
000 00 000 01
100 00 000 00
111 11 111 10
111 11 111 11
TWO’S COMPLEMENT
100 00 000 00
100 00 000 01
000 00 000 00
011 11 111 10
011 11 111 11
GRAY CODE
000 00 000 00
000 00 000 01
110 00 000 00
100 00 000 01
100 00 000 00
–Full Scale + 1LSB
Mid–Scale
+Full Scale – 1LSB
+Full Scale
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January 3, 2011
19
KAD5510P
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1D
0
FIGURE 32. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 33. LSB-FIRST ADDRESSING
t
DSW
t
t
t
CLK
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 34. SPI WRITE
t
DSW
t
t
t
CLK
HI
H
t
DHW
t
t
CSB
t
S
DVR
DHR
t
LO
SCLK
WRITING A READ COMMAND
R/W W1 W0 A12 A11 A10 A9 A2 A1 A0
READING DATA
(3 WIRE MODE)
SDIO
SDO
D3
D7 D6
D7
D2
D1 D0
(4 WIRE MODE)
D3 D2 D1 D0
SPI READ
FIGURE 35. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 36. 2-BYTE TRANSFER
FN7693.1
January 3, 2011
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KAD5510P
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 37. N-BYTE TRANSFER
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 32 and 33 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the ADC sample rate (f
for write operations and f
SAMPLE
) divided by 16
divided by 66 for reads. At
SAMPLE
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 3). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 34,
and timing values are given in “Switching
f
= 250MHz, maximum SCLK is 15.63MHz for writing and
SAMPLE
3.79MHz for read operations. There is no minimum SCLK rate but
the ADC clock (CLKP/CLKN) must be active to access the SPI
registers.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
Specifications Boldface limits apply over the operating
temperature range, -40°C to +85°C.” on page 11.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described below). A dedicated serial data output pin (SDO) can
be activated by setting 0x00[7] high to allow operation in four-
wire mode.
TABLE 3. BYTE TRANSFER SELECTION
[W1:W0]
00
BYTES TRANSFERRED
1
SDO should always be connected to OVDD with a 4.7kΩ resistor
even if not used. If the 4.7kΩ resistor is not present the ADC will
not exit the reset state.
01
2
3
10
11
4 or more
The SPI port operates in a half duplex master/slave
configuration, with the KAD5510P functioning as a slave.
Multiple slave devices can interface to a single master in three-
wire mode only, since the SDO output of an unaddressed device
is asserted in four-wire mode.
Figures 36 and 37 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order can be
selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to
accommodate various microcontrollers.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high to low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
Bit 7 SDO Active
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January 3, 2011
21
KAD5510P
Bit 6 LSB First
ADDRESS 0X20: OFFSET_COARSE AND
Setting this bit high configures the SPI to interpret
serial data as arriving in LSB to MSB order.
ADDRESS 0X21: OFFSET_FINE
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 4.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default
values.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
TABLE 4. OFFSET ADJUSTMENTS
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
ADDRESS 0X02: BURST_END
PARAMETER
Steps
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. In
3-wire SPI mode the burst is ended by pulling the CSB pin high. If
the device is operated in
2-wire mode the CSB pin is not available. In that case, setting the
burst_end address determines the end of the transfer. During a
write operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
255
255
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
+5LSB (+1.75mV)
0.04LSB (0.014mV)
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Bits 7:0 Burst End Address
This register value determines the ending address of
the burst data.
Device Information
Gain of the ADC core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2% (‘0011’ =~ -4.2% and
‘1100’ =~ +4.2%). It is recommended to use one of the coarse
gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-
tune the gain using the registers at 23h and 24h.
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Indexed Device Configuration/Control
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X10: DEVICE_INDEX_A
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil ADC products.
Certain configuration commands (identified as Indexed in the SPI
map) can be executed on a per-converter basis. This register
determines which converter is being addressed for an Indexed
command. It is important to note that only a single converter can
be addressed at a time.
TABLE 5. COARSE GAIN ADJUSTMENT
NOMINAL COARSE GAIN ADJUST
0x22[3:0]
Bit3
(%)
+2.8
+1.4
-2.8
-1.4
This register defaults to 00h, indicating that no ADC is
addressed. Therefore Bit 0 must be set high in order to execute
any Indexed commands. Error code ‘AD’ is returned if any
indexed register is read from without properly setting
device_index_A.
Bit2
Bit1
Bit0
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January 3, 2011
22
KAD5510P
71h followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles).
TABLE 6. MEDIUM AND FINE GAIN ADJUSTMENTS
0x23[7:0]
0x24[7:0]
FINE GAIN
PARAMETER
MEDIUM GAIN
CLK = CLKP – CLKN
Steps
256
256
-0.20%
0.00%
CLK
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-2%
1.00ns
0.00%
+2%
+0.2%
CLK÷4
0.016%
0.0016%
4.00ns
ADDRESS 0X25: MODES
CLK÷4
SLIP ONCE
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation or sleep
modes (refer to “Nap/Sleep” on page 18). This functionality can
be overridden and controlled through the SPI. This is an indexed
function when controlled from the SPI, but a global function
when driven from the pin. This register is not changed by a Soft
Reset.
CLK÷4
SLIP TWICE
FIGURE 38. PHASE SLIP: CLK÷4 MODE, f
= 1000MHz
CLOCK
TABLE 7. POWER-DOWN CONTROL
ADDRESS 0X72: CLOCK_DIVIDE
0x25[2:0]
The KAD5510P has a selectable clock divider that can be set to
divide by four, two or one (no division, refer to “Clock Input” on
page 17). This functionality can be controlled through the SPI, as
shown in Table 8. This register is not changed by a Soft Reset.
VALUE
000
POWER-DOWN MODE
Pin Control
001
Normal Operation
Nap Mode
TABLE 8. CLOCK DIVIDER SELECTION
0x72[2:0]
010
100
Sleep Mode
VALUE
CLOCK DIVIDER
Pin Control
Divide by 1
Divide by 2
Divide by 4
000
Nap mode must be entered by executing the following sequence:
001
010
SEQUENCE
REGISTER
0x10
VALUE
0x01
0x02
0x02
0x02
100
1
2
3
4
0x25
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The KAD5510P can
present output data in two physical formats: LVDS or LVCMOS.
Additionally, the drive strength in LVDS mode can be set high
(3mA) or low (2mA). This functionality can be controlled through
the SPI, as shown in Table 9.
0x10
0x25
Return to Normal operation as follows:
SEQUENCE
REGISTER
0x10
VALUE
0x01
0x01
0x02
0x01
TABLE 9. OUTPUT MODE CONTROL
1
2
3
4
VALUE
000
0x93[7:5]
Pin Control
LVDS 2mA
LVDS 3mA
LVCMOS
0x25
0x10
001
0x25
010
100
Global Device Configuration/Control
Data can be coded in three possible formats: two’s complement, Gray
code or offset binary. This functionality can be controlled through the
SPI, as shown in Table 10.
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases. This is
particularly important when multiple ADCs are used in a time-
interleaved system. The phase slip feature allows the rising edge
of the divided clock to be advanced by one input clock cycle when
in CLK/4 mode, as shown in Figure 38. Execution of a phase_slip
command is accomplished by first writing a ‘0’ to bit 0 at address
This register is not changed by a Soft Reset.
FN7693.1
January 3, 2011
23
KAD5510P
ADDRESS 0XC0: TEST_IO
TABLE 10. OUTPUT FORMAT CONTROL
0x93[2:0]
Bits 7:6 User Test Mode
VALUE
OUTPUT FORMAT
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
000
Pin Control
001
Two’s Complement
Gray Code
The four LSBs in this register (Output Test Mode) determine the
test pattern in combination with registers 0xC2 through 0xC5.
Refer to Table 12.
010
100
Offset Binary
TABLE 12. OUTPUT TEST MODES
ADDRESS 0X74: OUTPUT_MODE_B
0xC0[3:0]
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
OUTPUT TEST MODE
Off
WORD 1
WORD 2
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Midscale
0x8000
0xFFFF
0x0000
0xAAAA
N/A
N/A
N/A
This bit sets the DLL operating range to fast (default)
or slow.
Positive Full-Scale
Negative Full-Scale
Checkerboard
Reserved
N/A
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 11 shows the allowable
sample rate ranges for the slow and fast settings.
0x5555
N/A
TABLE 11. DLL RANGES
Reserved
N/A
N/A
DLL RANGE
Slow
MIN
40
MAX
100
UNIT
MSPS
MSPS
One/Zero
0xFFFF
user_patt1
0x0000
user_patt2
User Pattern
Fast
80
f MAX
S
ADDRESS 0XC2: USER_PATT1_LSB AND
ADDRESS 0XC3: USER_PATT1_MSB
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency range
of the DLL clock generator. The method of setting these options
is different from the other registers.
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
READ
OUTPUT_MODE_B
0x74
ADDRESS 0XC4: USER_PATT2_LSB AND
ADDRESS 0XC5: USER_PATT2_MSB
READ
CONFIG_STATUS
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
WRITE TO
0x74
0x75
DESIRED
VALUE
48 Pin Package Notes
FIGURE 39. SETTING OUTPUT_MODE_B REGISTER
The KAD5510 is only available in a 48-pin package. While fully
compatible with other family members in the 48-pin package
there are some key differences from the 72-pin package. The 48
pin package option supports LVDS DDR only. A reduced set of pin
selectable functions are available in the 48 pin package due to
the reduced pinout; (OUTMODE, OUTFMT, and CLKDIV pins are
not available). Table 13 shows the default state for these
functions for the 48-pin package. Note that these functions are
available through the SPI, allowing a user to set these modes as
they desire, offering the same flexibility as the 72-pin family
members.
The procedure for setting output_mode_B is shown in Figure 39.
Read the contents of output_mode_B and config_status and XOR
them. Then XOR this result with the desired value for
output_mode_B and write that XOR result to the register.
Bit 4 DDR Enable
This bit sets the output mode to DDR or SDR.
This bit is set high by default enabling DDR outputs. Do not set
this bit low or invalid output data will result.
TABLE 13. 48 PIN SPI - ADDRESSABLE FUNCTIONS
Device Test
FUNCTION
CLKDIV
DESCRIPTION
Clock Divider
DEFAULT STATE
Divide by 1
The KAD5510 can produce preset or user defined patterns on the
digital outputs to facilitate in-site testing. A static word can be
placed on the output bus, or two different words can alternate. In
the alternate mode, the values defined as Word 1 and Word 2 (as
shown in Table 12) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the sample
clock, therefore several sample clock cycles may elapse before
the data is present on the output bus.
OUTMODE
OUTFMT
Output Driver Mode
Data Coding
LVDS, 3mA (DDR)
Two’s Complement
FN7693.1
January 3, 2011
24
KAD5510P
SPI Memory Map
TABLE 14. SPI MEMORY MAP
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
00
port_config
SDO
Active
LSB First
Soft
Reset
Mirror Mirror
(bit5) (bit6)
Mirror
(bit7)
00h
G
01
02
reserved
burst_end
reserved
Reserved
Burst end address [7:0]
Reserved
00h
G
03-07
08
chip_id
Chip ID #
Read only
Read only
00h
G
G
I
09
chip_version
device_index_A
reserved
Chip Version #
Reserved
10
ADC00
11-1F
20
Reserved
offset_coarse
offset_fine
gain_coarse
gain_medium
gain_fine
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
I
I
I
I
I
I
21
22
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
modes
Reserved
Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT
affected by
Soft Reset
100 = Sleep
other codes = reserved
26-5F
60-6F
70
reserved
reserved
reserved
phase_slip
Reserved
Reserved
Reserved
71
Reserved
Next
Clock
Edge
00h
G
G
72
73
74
clock_divide
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
00h
NOT
affected by
Soft Reset
output_mode_A
output_mode_B
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
other codes = reserved
00h
NOT
affected by
Soft Reset
G
other codes = reserved
DLL Range
0 = fast
1 = slow
DDR
Enable
(Note 14)
00h
NOT
affected by
Soft Reset
G
G
75
config_status
reserved
XOR
Result
XOR
Result
Read Only
76-BF
Reserved
FN7693.1
January 3, 2011
25
KAD5510P
TABLE 14. SPI MEMORY MAP (Continued)
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
C0
test_io
User Test Mode [1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
Output Test Mode [3:0]
00h
G
0 = Off
7 = One/Zero Word
Toggle
1 = Midscale Short
2 = +FS Short
3 = -FS Short
8 = User Input
9-15 = Reserved
4 = Checker Board
5 = Reserved
6 = Reserved
C1
C2
Reserved
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
Reserved
Reserved
00h
00h
00h
00h
00h
G
G
G
G
G
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B0
B8
B0
B8
C3
C4
C5
B15
B14
B13
B12
B11
B10
C6-FF
Reserved
NOTE:
14. At power-up, the DDR Enable bit is set to a logic ‘1’ internally for the 48 pin package by an internal pull-up. Do not set this bit low or invalid output data will
result.
FN7693.1
January 3, 2011
26
KAD5510P
Equivalent Circuits
AVDD
TO
CLOCK-
AVDD
PHASE
GENERATION
CLKP
AVDD
AVDD
CSAMP
1.6pF
TO
CHARGE
PIPELINE
11k
11k
INP
INN
18k
Φ
Φ
3
2
Φ
F 1
Ω
1000O
CSAMP
1.6pF
18k
AVDD
AVDD
TO
CHARGE
PIPELINE
CLKN
FΦ2
FΦ3
Φ1
FIGURE 40. ANALOG INPUTS
FIGURE 41. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
OVDD
AVDD
Ω
75kO
OVDD
OVDD
INPUT
AVDD
20k
Ω
TO
SENSE
LOGIC
75kOΩ
280OΩ
TO
INPUT
LOGIC
280
Ω
Ω
75kO
75kOΩ
FIGURE 42. TRI-LEVEL DIGITAL INPUTS
FIGURE 43. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
D[11:0]P
OVDD
OVDD
OVDD
D[11:0]N
DATA
DATA
DATA
D[11:0]
2mA OR
3mA
FIGURE 45. CMOS OUTPUTS
FIGURE 44. LVDS OUTPUTS
FN7693.1
January 3, 2011
27
KAD5510P
Equivalent Circuits (Continued)
AVDD
VCM
+
0.535V
–
FIGURE 46. VCM_OUT OUTPUT
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be used to
evaluate any of the KADxxxxx ADC family. The platform consists
of a FPGA based data capture motherboard and a family of ADC
daughtercards. This USB based platform allows a user to quickly
evaluate the ADC’s performance at a user’s specific application
frequency requirements. More information is available at:
LVDS Outputs
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
http://www.intersil.com/converters/adc_eval_platform/
LVCMOS Outputs
Layout Considerations
Output traces and connections must be designed for 50Ω
characteristic impedance. Care should be taken when using the
DDR CMOS outputs at clock rates greater than 200MHz. Series
termination resistors close to the ADC should drive short traces
with minimum parasitic loading to assure adequate signal
integrity
PCB Layout Example
For an example application circuit and PCB layout, please refer to
the evaluation board documentation provided in the web product
folder at:
http://www.intersil.com/products/partsearch.asp?txtprodnr=ka
d5510p
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO) which will not
be operated do not require connection to ensure optimal ADC
performance. These inputs can be left floating if they are not
used. The SDO output must be connected to OVDD with a 4.7kΩ
resistor or the ADC will not exit the reset state. Tri-level inputs
(NAPSLP) accept a floating input as a valid state, and therefore
should be biased according to the desired functionality.
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
General PowerPAD Design
Considerations
Figure 47 is a generic illustration of how to use vias to remove
heat from a QFN package with an exposed thermal pad. A
specific example can be found in the evaluation board PCB
layout previously referenced.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and terminations
as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
FIGURE 47. PCB VIA PATTERN
FN7693.1
January 3, 2011
28
KAD5510P
Filling the exposed thermal pad area with vias provides optimum heat
Integral Non-Linearity (INL) is the maximum deviation of the
ADC’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
transfer to the PCB’s internal plane(s). Vias should be evenly distributed
from edge-to-edge on the exposed pad to maintain a constant
temperature across the entire pad. Setting the center-to-center spacing
of the vias at three times the via pad radius will provide good heat
transfer for high power devices. The vias below the KAD5510P may be
spaced further apart as shown on the evaluation board since it is a low-
power device. The via diameter should be small but not too small to
allow solder wicking during reflow. PCB fabrication and assembly
companies can provide specific guidelines based on the layer stack and
assembly process.
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
N
V
/(2 -1) where N is the resolution in bits.
FS
Missing Codes are output codes that are skipped and will never
appear at the ADC output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Connect all vias under the KAD5510P to AVSS. It is important to
maximize the heat transfer by avoiding the use of “thermal relief”
patterns when connecting the vias to the internal AVSS plane(s).
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Definitions
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the ADC FFT, caused by an AC signal
superimposed on the power supply voltage.
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of specifying
Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as:
ENOB = (SINAD - 1.76)/6.02
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less 2 LSB. It is typically expressed in percent.
FN7693.1
January 3, 2011
29
KAD5510P
Revision History
DATE
REVISION
CHANGE
1/3/11
FN7693.1 Initial release to web.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: KAD5510P
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN7693.1
January 3, 2011
30
KAD5510P
Package Outline Drawing
L48.7x7E
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 2/09
PIN 1
INDEX AREA
4X 5.50
A
7.00
PIN 1
6
INDEX AREA
B
37
48
6
1
36
44X 0.50
Exp. DAP
5.60 Sq.
7.00
12
25
(4X)
0.15
24
13
48X 0.25
0.10 M C A B
4
48X 0.40
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
C
C
0.10
0.08 C
SEATING PLANE
SIDE VIEW
44X 0.50
6.80 Sq
5
0. 2 REF
C
48X 0.25
48X 0.60
5.60 Sq
0. 00 MIN.
0. 05 MAX.
DETAIL "X"
NOTES:
1.
TYPICAL RECOMMENDED LAND PATTERN
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
Connect Exp. DAP (PAD) to AVSS with multiple vias to a low
thermal impedance plane
FN7693.1
January 3, 2011
31
相关型号：
KAD5512HP-12Q48
12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs; QFN48, QFN72; Temp Range: -40° to 85°C
RENESAS
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