MWS5101DL3X [INTERSIL]
256-Word x 4-Bit LSI Static RAM; 256字×4位LSI静态RAM
| 型号： | MWS5101DL3X |
| 厂家： | 
Intersil |
| 描述： | 256-Word x 4-Bit LSI Static RAM |
| 文件： | 总7页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
March 1997
Features
Description
• Industry Standard Pinout
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
at V
= 5V and Cycle Time = 1µs
DD
• Two Chip Select Inputs Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
• Separate Data Inputs and Outputs
• TTL Compatible (MWS5101A)
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
Pinout
MWS5101, MWS5101A
(PDIP, SBDIP)
TOP VIEW
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
22
21
20
19
18
17
16
15
14
13
12
V
DD
1
2
A3
A2
A1
A0
A5
A6
A7
A4
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
in chip form (H suffix).
R/W
CSI
O.D.
CS2
DO4
DI4
3
4
5
6
7
8
V
SS
DO3
9
DI1
DI3
10
11
DO1
DI2
DO2
Ordering Information
MWS5101
MWS5101A
PACKAGE
TEMP. RANGE
250ns
350ns
250ns
350ns
PKG. NO.
E22.4
o
o
PDIP
0 C to +70 C
MWS5101EL2
MWS5101ELS
MWS5101AEL2 MWS5101AEL3
Burn-In
MWS5101AEL3X E22.4
MWS5101ADL3 D22.4A
D22.4A
o
o
SBDIP
Burn-In
0 C to +70 C
-
MWS5101DL3X
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1106.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-56
MWS5101, MWS5101A
OPERATIONAL MODES
INPUTS
CHIP SELECT 1
CHIP SELECT 2
OUTPUT
DISABLE (OD)
READ/WRITE
(R/W)
MODE
(CS )
1
(CS )
2
OUTPUT
Read
0
0
0
1
X
X
1
1
1
X
0
X
0
0
1
X
X
1
1
0
Read
Write
Data In
Write
0
High Impedance
High Impedance
High Impedance
High Impedance
Standby
Standby
X
X
X
Output Disable
NOTE: Logic 1 = High, Logic 0 = Low, X = Don’t Care.
Functional Block Diagram
†
4
3
(32)
ROW
(5)
INPUT
BUFFERS
AND
ALL ROWS
DESELECT
FUNCTION
A0
A1
A2
A3
A4
†
†
†
†
† † †
22
2
V
DD
DECODERS
1
21
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(4)
†
†
†
†
††
9
10
12
DI1
DI2
DI3
DI4
D01
BUFFER
DRIVERS
††
11
BITS
(1-4)
D02
(4)
GATES
††
13
15
14
16
D03
††
D04
BIT (1)
(8)
BIT (2)
(8)
BIT (3)
(8)
BIT (4)
(8)
(3)
INPUT
BUFFERS
AND
ALL COLUMNS
DESELECT
FUNCTION
†
†
†
5
6
COLUMN
DECODERS
COLUMN
DECODERS
COLUMN
DECODERS
COLUMN
DECODERS
A5
A6
A7
7
†
20
CONTROL
B
R/W
† † †
8
†
19
CONTROL
A
CONTROL
C
V
SS
CSI
CS2
OD
†
17
†
18
V
V
V
DD
DD
DD
V
V
V
SS
SS
SS
INPUT PROTECTION
NETWORK
OUTPUT
PROTECTION
CIRCUIT
OVER VOLTAGE
PROTECTION
CIRCUIT
†
††
† ††
6-57
MWS5101, MWS5101A
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal). . . . . . . . -0.5V to +7V
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
75
80
N/A
21
SS
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DD
Operating Temperature Range (T )
A
o
o
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
Maximum Storage Temperature Range (T
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
o
o
o
) . . .-65 C to +150 C
STG
o
o
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Maximum Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ±0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
LIMITS
PARAMETER
MIN
MAX
UNITS
DC Operating Voltage Range
Input Voltage Range
4
6.5
V
V
V
V
DD
SS
o
o
Static Electrical Specifications At T = 0 C to +70 C, V = 5V ±5%
A
DD
CONDITIONS
LIMITS
MWS5101
MWS5101A
V
V
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
SYMBOL
(V)
(V)
0, 5
0, 10
0, 5
0, 5
0, 5
0, 5
-
MIN
TYP
MAX
MIN
TYP
MAX
50
200
-
UNITS
Quiescent Device
Current
L2 Types
L3 Types
I
-
-
25
100
4
50
200
-
-
25
100
4
µA
µA
mA
mA
V
DD
-
-
-
Output Low (Sink) Current
Output High (Source) Current
Output Voltage Low-Level
Output Voltage High-Level
Input Low Voltage
I
0.4
2
2
OL
I
4.6
-1
-2
0
-
-1
-2
0
-
OH
V
-
-
0.1
-
-
0.1
-
OL
V
-
4.9
5
4.9
5
V
OH
V
-
-
-
1.5
-
-
-
0.65
-
V
IL
IH
IN
Input High Voltage
V
-
-
3.5
-
2.2
-
V
Input Leakage Current
Operating Current (Note 2)
I
-
0, 5
0, 5
0, 5
0, 5
-
-
-
-
-
-
-
-
±5
8
-
-
-
-
-
-
-
±5
8
µA
mA
µA
µA
pF
pF
I
-
0, 5
0, 5
-
4
4
DD1
OUT
Three-State Output
Leakage Current
L2 Types
L3 Types
I
-
±5
±5
7.5
15
-
±5
±5
7.5
15
-
-
Input Capacitance
Output Capacitance
NOTES:
C
5
5
IN
C
-
-
10
10
OUT
o
1. Typical values are for T = +25 C and nominal V
A
.
DD
2. Outputs open circuited; Cycle time = 1µs.
6-58
MWS5101, MWS5101A
o
o
Dynamic Electrical Specifications at T = 0 C to +70 C, V = 5V ±5%
A
DD
LIMITS (NOTE 1)
L2 TYPES
L3 TYPES
(NOTE 2)
MIN
(NOTE 3)
TYP
(NOTE 2)
MIN
(NOTE 3)
TYP
PARAMETER
READ CYCLE TIMES (FIGURE 1)
Read Cycle
SYMBOL
MAX
MAX
UNITS
t
250
-
-
-
250
250
250
110
-
350
-
-
-
350
350
350
150
-
ns
ns
ns
ns
ns
ns
ns
ns
RC
Access from Address
Output Valid from Chip Select 1
Output Valid from Chip Select 2
Output Valid from Output Disable
Output Hold from Chip Select 1
Output Hold from Chip Select 2
Output Hold from Output Disable
WRITE CYCLE TIMES (FIGURE 2)
Write Cycle
t
150
200
AA
t
t
t
-
150
-
200
DOA1
DOA2
DOA3
DOH1
DOH2
DOH3
-
150
-
200
-
-
-
-
-
-
-
-
-
-
t
t
t
20
20
20
20
20
20
-
-
-
-
t
t
300
110
40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
150
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Address Setup
t
AS
Write Recovery
WR
Write Width
t
150
150
40
200
200
50
WRW
Input Data Setup Time
Data in Hold
t
DS
t
DH
Chip Select 1 Setup
t
t
110
110
0
150
150
0
CS1S
CS2S
CS1H
CS2H
Chip Select 2 Setup
Chip Select 1 Hold
t
t
Chip Select 2 Hold
0
0
Output Disable Setup
NOTES:
t
110
150
ODS
1. MWS5101: t , t = 20ns, V = 0.7V , V = 0.3V ; C = 100pF and MWS5101A: t , t = 20ns, V = 2.2V, V = 0.65V; C = 50pF
R
F
IH
DD IL
DD
L
R
F
IH
IL
L
and 1 TTL Load.
2. Time required by a limit device to allow for the indicated function.
o
3. Typical values are for T = 25 C and nominal V
A
DD.
6-59
MWS5101, MWS5101A
t
RC
A0 - A7
t
DOA1
CHIP SELECT 1
t
DOH1
t
t
DOH2
CHIP SELECT 2
OUTPUT DISABLE
READ/WRITE
DOA2
t
t
DOH3
DOA3
t
AA
DATA OUT
VALID
DATA OUT
HIGH
IMPEDANCE
HIGH
IMPEDANCE
FIGURE 1. READ CYCLE TIMING WAVEFORMS
t
WC
t
WR
A0-A7
t
t
CS1S
CS1H
CHIP SELECT 1
CHIP SELECT 2
t
CS2H
t
CS2S
(NOTE)
OUTPUT DISABLE
DI1-DI4
t
t
t
DH
ODS
DS
DATA IN STABLE
t
WRW
READ/WRITE
t
AS
DON’T CARE
NOTE: t
ODS
is required for common I/O operation only; for separate I/O operations, output disable is “don’t care”.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-60
MWS5101, MWS5101A
o
o
Data Retention Specifications at T = 0 C to +70 C; See Figure 3
A
TEST
CONDITIONS
LIMITS
ALL TYPES
V
V
(NOTE 1)
DR
DD
PARAMETER
Minimum Data Retention Voltage
Data Retention Quiescent Current
SYMBOL
(V)
(V)
MIN
TYP
MAX
UNITS
V
V
-
-
-
-
1.5
2
5
-
2
10
50
-
DR
L2 Types
L3 Types
I
2
2
-
-
µA
µA
ns
DD
-
-
Chip Deselect to Data Retention Time
Recovery to Normal Operation Time
t
5
5
5
600
600
1
CDR
t
-
-
-
ns
RC
V
to V
Rise and Fall Time
t , t
2
-
-
µs
DD
DR
R
F
NOTE:
o
1. Typical Values are for T = 25 C and nominal V
A
.
DD
V
DD
READ
ADDRESS
DECODER
DATA RETENTION
MODE
V
DD
0.95 V
0.95 V
DD
DD
V
DR
V
SS
t
t
t
t
RC
CDR
F
R
WRITE
ADDRESS
DECODER
C
S2
V
V
IH
IH
V
IL
V
IL
V
DD
FIGURE 3. LOW V
DD
DATA RETENTION TIMING WAVEFORMS
FIGURE 4. MEMORY CELL CONFIGURATION
6-61
MWS5101, MWS5101A
CONTROL A
CS1
CS2
19
17
A
CHIP-SELECT
CONTROL
CONTROL B
CONTROL C
B
R/W
20
CHIP-SELECT AND
R/W CONTROL
C
OUTPUT
DISABLE
CONTROL
OUTPUT
DISABLE
18
FIGURE 5. LOGIC DIAGRAM OF CONTROLS FOR MWS5101, MWS5101A
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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6-62
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