X4283V8Z-2.7A [INTERSIL]
CPU Supervisor with 128K EEPROM; CPU监控器， 128K EEPROM
| 型号： | X4283V8Z-2.7A |
| 厂家： | 
Intersil |
| 描述： | CPU Supervisor with 128K EEPROM |
| 文件： | 总22页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X4283, X4285
®
128K, 16K x 8 Bit
Data Sheet
May 23, 2006
FN8121.1
DESCRIPTION
CPU Supervisor with 128K EEPROM
The X4283, X4285 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
FEATURES
• Selectable watchdog timer
• Low V detection and reset assertion
CC
—Four standard reset threshold voltages
—Adjust low V reset threshold voltage using
CC
special programming sequence
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
—Reset signal valid to V = 1V
CC
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting
the system when V falls below the set minimum V
™
Block Lock protection
CC
CC
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld TSSOP
trip point. RESET/RESET is asserted until V returns
CC
to proper operating level and stabilizes. Four industry
standard Vtrip thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET (X4283)
RESET (X4285)
Data
Register
SDA
Status
Register
EEPROM Array
Command
Reset &
Watchdog
Timebase
SCL
Decode &
Control
Logic
S0
S1
VCC Threshold
Reset logic
Power-on and
Low Voltage
+
-
VCC
Reset
Kb=Kilobyte
Generation
VTRIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X4283, X4285
The memory portion of the device is a CMOS Serial
PIN CONFIGURATION
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software
protocol allowing operation on an 2-wire bus.
8-Pin JEDEC SOIC
VCC
1
8
7
6
5
S0
S1
2
3
4
WP
SCL
SDA
RST/RST
VSS
8-Pin TSSOP
SCL
SDA
1
2
3
4
8
7
6
5
WP
VCC
VSS
RST/RST
S0
S1
PIN DESCRIPTION
Pin
Pin
(SOIC) (TSSOP)
Name
S0
Function
1
2
3
3
4
5
Device Select Input
Device Select Input
S1
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain ac-
tive until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up
and remains active for 250ms after the power supply stabilizes.
4
5
6
7
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
6
7
8
1
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
8
2
VCC
Supply Voltage
FN8121.1
May 23, 2006
2
X4283, X4285
Ordering Information
PART NUMBER
PART NUMBER
RESET
RESET
PART
PART
V
CC RANGE VTRIP RANGE
TEMP
PKG.
(ACTIVE LOW)
MARKING (ACTIVE HIGH) MARKING
(V)
(V)
RANGE (°C)
PACKAGE
8 Ld SOIC
DWG #
X4283S8-2.7
X4283 F
X4285S8-2.7
X4285 F
X4285 ZF
X4285 G
X4285 ZG
4285 F
2.7 to 5.5
2.55 to 2.7
0 to 70
0 to 70
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
(150 mil)
X4283S8Z-2.7 (Note) X4283 ZF X4285S8Z-2.7
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4283S8I-2.7
X4283 G
X4285S8I-2.7
-40 to +85
-40 to +85
0 to 70
8 Ld SOIC
(150 mil)
X4283S8IZ-2.7
(Note)
X4283 ZG X4285S8IZ-2.7
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4283V8-2.7
4283 F
X4285V8-2.7
8 Ld TSSOP
(4.4mm)
X4283V8Z-2.7 (Note) 4283 FZ
X4285V8Z-2.7
(Note)
4285 FZ
4285 G
0 to 70
8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283V8I-2.7
4283 G
X4285V8I-2.7
-40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8IZ-2.7
(Note)
4283 GZ
X4285V8IZ-2.7
(Note)
4285 GZ
X4285 AN
X4285 ZAN
X4285 AP
-40 to +85 8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
X4283S8-2.7A*
X4283 AN X4285S8-2.7A
2.85 to 3.0
0 to 70
0 to 70
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X4283S8Z-2.7A
(Note)
X4283 ZAN X4285S8Z-2.7A
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4283S8I-2.7A*
X4283 AP X4285S8I-2.7A
-40 to +85
-40 to +85
0 to 70
8 Ld SOIC
(150 mil)
X4283S8IZ-2.7A*
(Note)
X4283 ZAP X4285S8IZ-2.7A X4285 ZAP
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4283V8-2.7A
4283 AN
X4285V8-2.7A
4285 AN
4285 ANZ
4285 AP
8 Ld TSSOP
(4.4mm)
X4283V8Z-2.7A
(Note)
4283 ANZ X4285V8Z-2.7A
(Note)
0 to 70
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
X4283V8I-2.7A
4283 AP
X4285V8I-2.7A
-40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8IZ-2.7A
(Note)
4283 APZ X4285V8IZ-2.7A 4285 APZ
(Note)
-40 to +85 8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
X4283S8
X4283
X4285S8
X4285
4.5 to 5.5
4.5 to 4.75
0 to 70
0 to 70
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X4283S8Z (Note)
X4283S8I
X4283 Z
X4283 I
X4283 ZI
4283
X4285S8Z (Note) X4285 Z
8 Ld SOIC
(150 mil) (Pb-free)
X4285S8I
X4285 I
-40 to +85
-40 to +85
0 to 70
8 Ld SOIC
(150 mil)
X4283S8IZ (Note)
X4283V8
X4285S8IZ (Note) X4285 ZI
8 Ld SOIC
(150 mil) (Pb-free)
X4285V8
4285
8 Ld TSSOP
(4.4mm)
X4283V8Z (Note)
X4283V8I
4283 Z
4283 I
X4285V8Z (Note) 4285 Z
0 to 70
8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4285V8I
4285 I
-40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
FN8121.1
May 23, 2006
3
X4283, X4285
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
PART NUMBER
RESET
MARKING (ACTIVE HIGH) MARKING
PART
PART
V
CC RANGE VTRIP RANGE
TEMP
RANGE (°C)
PKG.
DWG #
(V)
(V)
PACKAGE
X4283V8IZ (Note)
4283 IZ X4285V8IZ (Note) 4285 IZ
4.5 to 5.5
4.5 to 4.75
-40 to +85 8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283S8-4.5A
X4283 AL X4285S8-4.5A
X4285 AL
X4285 ZAL
X4285 AM
0 to 70
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X4283S8Z-4.5A
(Note)
X4283 ZAL X4285S8Z-4.5A
(Note)
0 to 70
8 Ld SOIC
(150 mil) (Pb-free)
X4283S8I-4.5A
X4283 AM X4285S8I-4.5A
-40 to +85
-40 to +85
0 to 70
8 Ld SOIC
(150 mil)
X4283S8IZ-4.5A
(Note)
X4283 ZAM X4285S8IZ-4.5A X4285 ZAM
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4283V8-4.5A
4283 AL
4283 ALZ
4283 AM
X4285V8-4.5A
4285 AL
4285 ALZ
4285 AM
8 Ld TSSOP
(4.4mm)
X4283V8Z-4.5A
(Note)
X4285V8Z-4.5A
(Note)
0 to 70
8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283V8I-4.5A
X4285V8I-4.5A
-40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8IZ-4.5A
(Note)
4283 AMZ X4285V8IZ-4.5A 4285 AMZ
(Note)
-40 to +85 8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8121.1
May 23, 2006
4
X4283, X4285
PRINCIPLES OF OPERATION
Power-on Reset
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Application of power to the X4283, X4285 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
EEPROM INADVERTENT WRITE PROTECTION
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-
up.
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any
in-progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
When V
exceeds the device V
threshold value
CC
TRIP
for
200ms
(nominal)
the
circuit
releases
RESET/RESET allowing the system to begin opera-
tion.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
LOW VOLTAGE MONITORING
During operation, the X4283, X4285 monitors the V
CC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V . The RESET/RESET
V
THRESHOLD RESET PROCEDURE
CC
TRIP
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
The X4283, X4285 is shipped with a standard V
CC
threshold (V
) voltage. This value will not change
TRIP
over normal operating and storage conditions. How-
ever, in applications where the standard V is not
It also remains active until V
returns and exceeds
CC
TRIP
V
for 200ms.
TRIP
exactly right, or if higher precision is needed in the
value, the X4283, X4285 threshold may be
V
TRIP
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
Figure 1. Set V
Level Sequence (V = desired V values WEL bit set)
TRIP
TRIP
CC
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
00h
01h
00h
FN8121.1
May 23, 2006
5
X4283, X4285
Setting the V
Voltage
Resetting the V
Voltage
TRIP
TRIP
This procedure is used to set the V
to a higher or
This procedure is used to set the V
to a “native”
TRIP
TRIP
lower voltage value. It is necessary to reset the trip
point before setting the new value.
voltage level. For example, if the current V
is 4.4V
must
TRIP
TRIP
and the new V
must be 4.0V, then the V
TRIP
be reset. When V
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
is reset, the new V
is some-
TRIP
TRIP
To set the new V
bit in the control register, then apply the desired V
threshold voltage to the V pin and the programming
voltage, start by setting the WEL
TRIP
TRIP
CC
voltage, V , to the WP pin and 2 byte address and 1
To reset the new V
voltage start by setting the
TRIP
P
byte of “00” data. The stop bit following a valid write
WEL bit in the control register, apply V and the pro-
CC
operation initiates the V
programming sequence.
gramming voltage, V , to the WP pin and 2 byte
TRIP
P
Bring WP LOW to complete the operation.
address and 1 byte of “00” data. The stop bit of a valid
write operation initiates the V
programming
TRIP
sequence. Bring WP LOW to complete the operation.
Figure 2. Reset V
Level Sequence (V > 3V. WP = 12-15V, WEL bit set)
CC
TRIP
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
00h
03h
00h
Figure 3. Sample V
Reset Circuit
TRIP
VP
SOIC
Adjust
4.7K
µC
1
2
3
4
8
7
6
5
RESET
Run
X4283
VTRIP
Adj.
SCL
SDA
FN8121.1
May 23, 2006
6
X4283, X4285
Figure 4. V
Programming Sequence
TRIP
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied + Error
New VCC Applied =
Old VCC Applied - Error
Execute
Set VTRIP
Sequence
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error ≤ –Emax
Error ≥ Emax
Measured VTRIP
Desired VTRIP
-
–Emax < Error < Emax
DONE
Emax = Maximum Allowed VTRIP Error
Control Register
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4283, X4285
will not acknowledge any data bytes written after the
first byte is entered.
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
FN8121.1
May 23, 2006
7
X4283, X4285
The state of the Control Register can be read at any
WD1, WD0: Watchdog Timer Bits
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4283, X4285 resets itself after the first byte is
read. The master should supply a stop condition to be
consistent with the bus protocol, but a stop is not
required to end this operation.
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
600 milliseconds
7
6
5
4
3
2
1
0
200 milliseconds
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
disabled (factory setting)
RWEL: Register Write Enable Latch (Volatile)
Write Protect Enable
The RWEL bit must be set to “1” prior to a write to the
Control Register.
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this pro-
tection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming
the BP2 bit is set to 0).
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes as well as
to the block protected sections in the memory array
cannot be written. Only the sections of the memory
array that are not block protected can be written. Note
that since the WPEN bit is write protected, it cannot be
changed back to a LOW state; so write protection is
enabled as long as the WP pin is held HIGH.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
Protected Addresses
(Size)
Array Lock
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (factory setting)
3000h - 3FFFh (4K bytes)
Upper 1/4 (Q4)
2000h - 3FFFh (8K bytes) Upper 1/2 (Q3,Q4)
0000h - 3FFFh (16K bytes)
000h - 03Fh (64 bytes)
000h - 07Fh (128 bytes)
000h - 0FFh (256 bytes)
000h - 1FFh (512 bytes)
Full Array (All)
First Page (P1)
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
FN8121.1
May 23, 2006
8
X4283, X4285
Table 1. Write Protect Enable Bit and WP Pin Function
Memory Array not
Block Protected
Memory Array
Block Protect
Bits
WP
WPEN
Block Protected
WPEN Bit
Writes OK
Protection
Software
LOW
HIGH
HIGH
X
0
1
Writes OK
Writes OK
Writes OK
Writes Blocked
Writes Blocked
Writes Blocked
Writes OK
Writes OK
Writes OK
Software
Writes Blocked
Writes Blocked
Hardware
Writing to the Control Register
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a start
and ended with a stop).
SERIAL INTERFACE
Serial Interface Conventions
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be repre-
sented as 0xys t 01r in binary, where xy are the WD
bits, and rst are the BP bits. (Operation preceded by a
start and ended with a stop). Since this is a nonvola-
tile write cycle it will take up to 10ms to complete. The
RWEL bit is reset by this cycle and the sequence
must be repeated to change the nonvolatile bits
again. If bit 2 is set to ‘1’ in this third step (0xys t11r)
then the RWEL bit is set, but the WD1, WD0, BP2,
BP1 and BP0 bits remain unchanged. Writing a sec-
ond byte to the control register is not allowed. Doing
so aborts the write operation and returns a NACK.
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto
the bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera-
tions. Therefore, the devices in this family operate as
slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
FN8121.1
May 23, 2006
9
X4283, X4285
Serial Start Condition
Serial Stop Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
START
Acknowledge
FN8121.1
May 23, 2006
10
X4283, X4285
Serial Write Operations
BYTE WRITE
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a
stop condition, at which time the device begins the inter-
nal write cycle to the nonvolatile memory. During this
internal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 8.
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
Figure 8. Byte Write Sequence
S
S
t
a
r
Signals from
the Master
Slave
Address
Word Address
Byte 1
Word Address
t
Byte 0
Data
o
p
t
SDA Bus
1 0 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
A write to a protected block of memory will suppress
the acknowledge bit.
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writing
at location 60, and loads 12 bytes, then the first 4
bytes are written to locations 60 through 63, and the
last 8 bytes are written to locations 0 through 7. After-
wards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64 bytes of data, then new data over-writes
the previous data, one byte at a time.
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
Figure 9. Page Write Operation
(1 < n < 64)
S
t
a
r
t
S
t
o
p
Signals from
the Master
Data
(1)
Data
(n)
Word Address
Byte 1
Word Address
Byte 0
Slave
Address
SDA Bus
1 0 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FN8121.1
May 23, 2006
11
X4283, X4285
Figure 10. Writing 12 bytes to a 64-byte page starting at location 60.
8 Bytes
4 Bytes
Address Pointer
Ends Here
Addr = 8
Address
Address
= 7
Address
n-1
60
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Figure 11. Acknowledge Polling Sequence
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
returned?
Acknowledge Polling
YES
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal nonvolatile cycle. Acknowl-
edge polling can be initiated immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
device is still busy with the nonvolatile cycle then no
ACK will be returned. If the device has completed the
write operation, an ACK will be returned and the host
can then proceed with the read or write operation.
Refer to the flow chart in Figure 11.
NO
Nonvolatile Cycle
Complete. Continue
Command Sequence?
Issue STOP
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
FN8121.1
May 23, 2006
12
X4283, X4285
Serial Read Operations
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 12 for the
address, acknowledge, and data transfer sequence.
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Figure 12. Current Address Read Sequence
S
S
t
o
p
Slave
Address
t
a
r
Signals from
the Master
t
SDA Bus
0
1
0
1
1
A
C
Signals from
the Slave
Data
K
Random Read
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
Figure 13. Random Address Read Sequence
S
S
Signals from
the Master
t
a
r
S
t
o
p
t
a
r
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Slave
Address
t
t
SDA Bus
1 0 1 0
0
1
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
FN8121.1
May 23, 2006
13
X4283, X4285
There is a similar operation, called “Set Current
indicating it requires additional data. The device con-
tinues to output data for each acknowledge received.
The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
Sequential Read
0000 and the device continues to output data for each
H
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge,
acknowledge received. Refer to Figure 14 for the
acknowledge and data transfer sequence.
Figure 14. Sequential Read Sequence
S
t
o
p
Signals from
Slave
the Master
SDA Bus
A
C
K
A
C
K
A
C
K
Address
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
X4283, X4285 Addressing
SLAVE ADDRESS BYTE
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
– a device type identifier that is ‘1010’ to access the
array
– one bits of ‘0’.
– next two bits are the device address select bits S1
and S0.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
FN8121.1
May 23, 2006
14
X4283, X4285
Figure 15. X4283, X4285 Addressing
Device Identifier
Device Select
1
0
1
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
A13
(X7)
A12
(X6)
A11
(X5)
A10
(X4)
A9
(X3)
A8
(X2)
0
0
Word Address Byte 0–128K
Low Order Word Address
A7
(X1)
A6
(X0)
A5
(Y5)
A4
(Y4)
A3
(Y3)
A2
(Y2)
A1
(Y1)
A0
(Y0)
Word Address Byte 0 for all Options
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte for all Options
Operational Notes
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress
communication is terminated.
The device powers-up in the following state:
– The device is in the low power standby state.
– Block Lock bits can protect sections of the memory
array from write operations.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
SYMBOL TABLE
– SDA pin is the input mode.
– RESET/RESET Signal is active for t
.
PURST
WAVEFORM
INPUTS
OUTPUTS
Data Protection
Must be
steady
Will be
steady
The following circuitry has been included to prevent
inadvertent writes:
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
N/A
Center Line
is High
Impedance
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
FN8121.1
May 23, 2006
15
X4283, X4285
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to+150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Option
-2.7 and -2.7A
Blank and -4.5A
Supply Voltage Limits
2.7V to 5.5V
4.5V to 5.5V
-40°C
+85°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
V
= 2.7 to 5.5V
CC
Symbol
Parameter
Min
Max
1.0
3.0
1
Unit
mA
mA
µA
Test Conditions
(1)
ICC1
Active Supply Current Read
Active Supply Current Write
Standby Current DC (WDT off)
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz, SDA = Commands
(1)
ICC2
(2)
ISB1
VSDA = VSCL = VSB
Others = GND or VSB
(2)
ISB2
Standby Current DC (WDT on)
20
µA
VSDA = VSCL = VSB
Others = GND or VSB
ILI
Input Leakage Current
Output Leakage Current
10
10
µA
µA
VIN = GND to VCC
ILO
VSDA = GND to VCC
Device is in Standby(2)
(3)
VIL
Input LOW Voltage
Input nonvolatile
-0.5
VCC x 0.3
VCC +0.5
V
V
(3)
VIH
VCC x 0.7
VHYS
Schmitt Trigger Input Hysteresis
Fixed input level
0.2
V
V
VCC related level .05 x VCC
VOL
Output LOW Voltage
0.4
V
IOL = 3.0mA (2.7-5.5V)
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
FN8121.1
May 23, 2006
16
X4283, X4285
CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5V)
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Conditions
VOUT = 0V
(4)
COUT
Output Capacitance (SDA, RST/RST)
Input Capacitance (SCL, WP)
8
6
(4)
CIN
pF
VIN = 0V
Note: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
0.1 VCC to 0.9 VCC
10ns
5V
Input rise and fall times
Input and output timing levels 0.5VCC
Output load Standard output load
For VOL = 0.4V
1533Ω
and IOL = 3 mA
SDA
or
RESET
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
Parameter
Min.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
SCL Clock Frequency
400
tIN
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
tAA
0.1
0.9
tBUF
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
Data In Hold Time
0
Stop Condition Setup Time
Data Output Hold Time
0.6
50
20 +.1Cb(6)
20 +.1Cb(6)
0.6
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
300
300
tF
tSU:WP
tHD:WP
Cb
WP Hold Time
0
Capacitive load for each bus line
400
Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
FN8121.1
May 23, 2006
17
X4283, X4285
TIMING DIAGRAMS
Bus Timing
tF
tR
tHIGH
tLOW
SCL
tSU:STA
SDA IN
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
tAA tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
WP
tSU:WP
tHD:WP
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
(1)
Parameter
Min.
Typ.
Max.
Unit
(1)
tWC
Write Cycle Time
5
10
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8121.1
May 23, 2006
18
X4283, X4285
Power-Up and Power-Down Timing
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tR
tRPD
VRVALID
RESET
(X4285)
VRVALID
RESET
(X4283)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset Trip Point Voltage, X4283-4.5, X4285-4.5A
Reset Trip Point Voltage, X4283, X4285
Reset Trip Point Voltage, X4283-2.7A, X4285-2.7A
Reset Trip Point Voltage, X4283-2.7, X4285-2.7
4.5
4.62
4.38
2.92
2.62
4.75
4.5
3.0
V
4.25
2.85
2.55
2.7
tPURST
Power-up Reset Time out
VCC Detect to Reset/Output
VCC Fall Time
100
250
400
500
ms
ns
µs
µs
V
(8)
tRPD
(8)
tF
100
100
1
(8)
tR
VCC Rise Time
VRVALID
Reset Valid VCC
Note: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
tRSP
tRSP>tWDO
tRST
tRSP>tWDO
tRST
tRSP<tWDO
SCL
SDA
RESET
Note: All inputs are ignored during the active reset period (tRST).
FN8121.1
May 23, 2006
19
X4283, X4285
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
tWDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
OFF
250
650
1.5
100
450
1
400
850
2
ms
ms
sec
WD1 = 0, WD0 = 0
tRST
Reset Time Out
100
250
400
ms
V
Programming Timing Diagram (WEL = 1)
TRIP
VCC
(VTRIP
VTRIP
)
tTSU
tTHD
VP
WP
tVPH
tVPS
tVPO
SCL
SDA
tRP
00h
01h or 03h
00h
A0h
V
Programming Parameters
TRIP
Parameter
tVPS
Description
Min. Max. Unit
VTRIP Program Enable Voltage Setup time
VTRIP Program Enable Voltage Hold time
VTRIP Setup time
1
1
µs
µs
µs
ms
ms
µs
ms
V
tVPH
tTSU
tTHD
tWC
tVPO
tRP
1
VTRIP Hold (stable) time
10
VTRIP Write Cycle Time
10
18
VTRIP Program Enable Voltage Off time (Between successive adjustments)
VTRIP Program Recovery Period (Between successive adjustments)
Programming Voltage
0
10
15
VP
VTRAN
Vtv
VTRIP Programmed Voltage Range
2.55 4.75
-25 +25
V
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8121.1
May 23, 2006
20
X4283, X4285
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8121.1
May 23, 2006
21
X4283, X4285
Thin Shrink Small Outline Plastic Packages (TSSOP)
M8.173
N
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.120
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
3.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.116
0.169
0.05
0.80
0.19
0.09
2.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
8
8
7
NOTES:
0o
8o
0o
8o
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8121.1
May 23, 2006
22
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