X9438WS24-2.7 [INTERSIL]
Dual Digitally Controlled Potentiometer (XDCP) with Operational Amplifier; 双数控电位器（ XDCP ）与运算放大器
| 型号： | X9438WS24-2.7 |
| 厂家： | 
Intersil |
| 描述： | Dual Digitally Controlled Potentiometer (XDCP) with Operational Amplifier |
| 文件： | 总18页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9438
®
Programmable Analog
March 11, 2005
FN8199.0
PR
DESCRIPTION
Dual Digitally Controlled Potentiometer
(XDCP™) with Operational Amplifier
The X9438 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers, or using them as com-
plete stand-alone amplifiers.
FEATURES
• Two CMOS voltage operational amplifiers
• Two digitally controlled potentiometers
• Can be combined or used separately
• Amplifiers:
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The two-wire
serial port, common to both pots, allows the user to
program the connection of the wiper output to any of
the resistor nodes in the series string. The wiper posi-
tion is saved in the on board E2 memory to allow for
nonvolatile restoration of the wiper position.
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometers
—Dual 64 tap potentiometers
—R
= 10kΩ
total
—2-wire serial interface
—V = 2.7V to 5.5V
CC
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
VCC
RW0 RH0 RL0
V+
VNI0
Control and
Memory
+
–
VOUT0
SCL
SDA
A3
A2
A1
A0
WCR0
VINV0
VNI1
+
–
VOUT1
WP
WCR1
VINV1
RW1 RL1 RH1
VSS
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9438
PIN DESCRIPTIONS
Hos t Interface Pins
Serial Clock (SCL)
Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.
System Supply V and Ground V
.
CC
SS
The SCL input is used to clock data into and out of the
X9438.
The system supply V and its reference V is used
to bias the interface and control circuits.
CC
SS
Serial Data (SDA)
PIN CONFIGURATION
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor.
TSSOP
SOIC
VCC
RL0
1
V+
NC
A0
A3
1
24
23
22
21
20
19
18
17
16
15
24
SCL
2
VOUT0
VNI0
VINV0
A0
2
23
22
21
20
19
18
17
16
15
VINV0
VNI0
RH0
RW0
3
VINV1
3
4
VNI1
VOUT1
V-
4
Device Address (A - A )
0
3
VOUT0
A2
WP
5
5
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9438. A maximum of 16 devices may share the
same 2-wire serial bus.
V+
VCC
6
NC
6
X9438
X9438
SDA
7
7
VSS
RW1
RH1
RL1
A3
A1
RL0
RH0
RW0
8
SCL
VINV1
8
RL1
9
9
10
11
RH1
RW1
10
11
VNI1
VOUT1
V-
A2
14
13
A1
14
13
VSS
(1)
12
WR
12
SDA
Potentiometer Pins
R (R - R ), R (R - R )
H
H0
H1
L
L0
L1
PIN NAMES
The R and R inputs are equivalent to the terminal con-
H
L
nections on either end of a mechanical potentiometer.
Symbol
SCL
Description
Serial Clock
Serial Data
R
(R - R
)
W1
W
W0
SDA
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
A0 - A3
Device Address
R
H0 - RH1
,
Potentiometers (terminal equivalent)
Amplifier and Device Pins
RL0 - RL1
R
W0 - RW1
VNI(0,1)
VINV(0,1)
OUT0, VOUT1
Potentiometers (wiper equivalent)
Amplifier Input Voltages
Amplifier Input Voltage V (0,1) and V (0,1)
NI
INV
,
V
and V
are inputs to the noninverting (+) and
INV
NI
inverting (-) inputs of the operational amplifiers.
V
Amplifier Outputs
Amplifier Output Voltage V (0,1)
WP
Hardware Write Protection
Analog and Voltage Amplifier Supplies
System/Digital Supply Voltage
System Ground
OUT
V
is the voltage output pin of the operational
V+,V-
VCC
VSS
NC
OUT
amplifier.
Hardware Write Protect Input WP
No Connection
The WP pin, when low, prevents non-volatile writes to
the wiper counter registers.
Note: (1) Alternate designations for RH, RL, RW are VH, VL, VW
FN8199.0
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March 11, 2005
X9438
PRINCIPLES OF OPERATION
The X9438 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9438 will respond with a final acknowledge.
The X9438 is an integrated microcircuit incorporating
two resistor arrays, two operational amplifiers and
their associated registers and counters; and the serial
interface logic providing direct communication
between the host and the digitally controlled potenti-
ometers and operational amplifiers.
Operational Amplifier
The voltage operational amplifiers are CMOS rail-to-
rail output general purpose amplifiers. They are
designed to operate from dual (±) power supplies. The
amplifiers may be configured like any standard ampli-
fier. All pins are externally available to allow connec-
tions with the potentiometers or as stand alone
amplifiers.
Serial Interface
The X9438 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9438 will be considered a slave
device in all applications.
Potentiometer/Array Description
The X9438 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
). SDA state changes during
LOW
SCL HIGH are reserved for indicating start and stop
conditions.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R ) output. Within each individual array only one
W
Start Condition
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
All commands to the X9438 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
). The X9438 continuously
HIGH
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1). For the X9438 this is fixed
as 0101[B].
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
Figure 1. Address/Identification Byte Format
Device Type
Identifier
A3 A2 A1 A0
Device Address
0
1
0
1
FN8199.0
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March 11, 2005
X9438
The next four bits of the slave address are the device
address. The physical device address is defined by
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots and when applicable they point to
one of the four WCRs associated data registers. The
format is shown below in Figure 2.
the state of the A - A inputs. The X9438 compares
0
3
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9438 to respond with an acknowledge. The
A - A inputs can be actively driven by CMOS input
0
3
signals or tied to V or V
.
CC
SS
Figure 2. Instruction Byte Format
Acknowledge Polling
Register
Select
The disabling of the inputs, during the internal non-vol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9438 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9438 is
still busy with the write operation no ACK will be
returned. If the X9438 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
I3
I2
I1
I0
R1 R0
0
P0
WCR Select
Instructions
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the two regis-
ters that is to be acted upon when a register oriented
instruction is issued. The last bit (P0) selects which
one of the two potentiometers is to be affected by the
instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a data regis-
ter to a wiper counter register is essentially a write to a
static RAM. The response of the wiper to this action
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter Ack Polling
Issue
START
will be delayed t
. A transfer from the wiper counter
WRL
register (current wiper position) to a data register is a
write to non-volatile memory and takes a minimum of
Issue Slave
Issue STOP
Address
t
to complete. The transfer can occur between one
WR
of the two potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.
ACK
Returned?
No
Yes
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure
4. These instructions transfer data between the host
and the X9438; either between the host and one of the
data registers or directly between the host and the
wiper counter and analog control registers. These
instructions are: 1) Read Wiper Counter Register or
read the current wiper position of the selected pot, 2)
Write Wiper Counter Register, i.e. change current
wiper position of the selected pot; 3) Read Data Regis-
ter, read the contents of the selected non-volatile regis-
ter; 4) Write Data Register, write a new value to the
selected data register. The bit structures of the instruc-
tions are shown in Figure 6.
No
Further
Operation?
Yes
Issue
Instruction
Issue STOP
Prooceed
Prooceed
FN8199.0
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March 11, 2005
X9438
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
0
P0
A
C
K
S
T
O
P
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
0
P0 R1 R0
A
C
K
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9438 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
) while SDA is HIGH, the selected wiper will
HIGH
move one resistor segment towards the V terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
H
L
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 P1 P0 R1 R0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
E
C
n
N
C
1
N
C
2
N
C
n
FN8199.0
March 11, 2005
5
X9438
Figure 6. Instruction Set
Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register P .
0
S device type
device
addresses
instruction
opcode
WCR
addresses
register data
(sent by slave on SDA)
S
A
C
K
S
M S
A T
C O
K P
T
A
R
T
identifier
A
C
K
A A A A
3 2 1 0
P
0
D D D D D D
0 0
0 1 0 1
1 0 0 1 0 0 0
5 4 3 2 1 0
P0: 0 - WCR0, 1 - WCR1
Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register P .
0
S device type
device
addresses
instruction
opcode
WCR
addresses
register data
(sent by master on SDA)
S
A
C
K
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
A A A A
3 2 1 0
P
0
D D D D D D
5 4 3 2 1 0
0 1 0 1
1 0 1 0 0 0 0
0 0
P0: 0 - WCR0, 1 - WCR1
Read Data Register (DR)
Read the contents of the Register pointed to by P and R - R .
0
1
0
S device type
device
addresses
instruction WCR/DR
register data
(sent by master on SDA)
S
A
C
K
S
A
C
K
M S
A T
C O
K P
T
A
R
T
identifier
opcode
addresses
A A A A
3 2 1 0
R R
1 0
P
0
D D D D D D
0 0
0 1 0 1
1 0 1 1
0
5 4 3 2 1 0
R1 R0:
00 - R0,
01 - R2,
10 - R1
11 - R3
Write Data Register (DR)
Write new value to the Register pointed to by P and R - R .
0
1
0
S device type
device
addresses
instruction
opcode
WCR/DR
addresses
register data
(sent by master on SDA)
S
A
C
K
S
A
C
K
S S
T
A
R
T
identifier
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
A A A A
3 2 1 0
R
1
R
0
0
P
0
D D D D D D
0 0
0 1 0 1
1 1 0 0
5 4 3 2 1 0
Definitions:
SACK - Slave acknowledge, MACK - Master acknowledge, I/D - Increment/Decrement (1/0), R - Register,
P - Potentiometer
FN8199.0
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March 11, 2005
X9438
Figure 6. Instruction Set (continued)
Transfer Data Register to Wiper Counter Register
Transfer the contents of the Register pointed to by R - R to the WCR pointed to by P .
1
0
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR/DR
addresses
S
A
C
K
S S
A T
C O
K P
A A A A
R R
P
0
0
1
0
1
1
1
0
1
0
3
2
1
0
1
0
Transfer Wiper Counter Register to Data Register
Transfer the contents of the WCR pointed to by P to the Register pointed to by R - R .
0
1
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR/DR
addresses
S
A
C
K
S S
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
0
A A A A
R R
P
0
1
0
1
1
1
1
0
0
3
2
1
0
1
0
Global Transfer Data Register to Wiper Counter Register
Transfer the contents of all four Data Registers pointed to by R - R to their respective WCR.
1
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A T
C O
K P
A A A A
R R
1 0
0
1
0
1
0
0
0
1
0 0
3
2
1
0
Global Transfer Wiper Counter Register to Data Register
Transfer the contents of all WCRs to their respective data Registers pointed to by R - R .
1
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A T
C O
K P
HIGH-VOLTAGE
WRITE CYCLE
A A A A
R R
1 0
0
1
0
1
1
0
0
0
0 0
3
2
1
0
Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P .
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SDA)
S
A
C
K
S
S
T
O
P
A
C
K
A A A A
P
0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
1
0
0
0
0
.
.
.
.
3
2 1 0
P0: 0 or 1 only.
FN8199.0
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March 11, 2005
X9438
REGISTER OPERATION
The wiper counter register is a volatile register; that is,
its contents are lost when the X9438 is powered-down.
Although the registers are automatically loaded with the
value in R0 upon power-up, it should be noted this may
be different from the value present at power-down.
Both digitally controlled potentiometers share the
serial interface and share a common architecture.
Each potentiometer is associated with a Wiper
Counter Register (WCR), and four Data Registers.
Figure 7 illustrates the control, registers, and system
features of the device.
Data Registers (DR)
Each potentiometer has four non-volatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all oper-
ations changing data in one of these registers is a non-
volatile operation and will take a maximum of 10ms.
Figure 7. System Block Diagram
VH (0,1)
(DR0-DR3)0,1
WCR0,1
WP
VL (0,1)
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could store sys-
tem parameters or user preference data.
VW (0,1)
SCL
SDA
A0
Interface
and
Control
Circuitry
VINV (0,1)
VNI (0,1)
A1
A2
A3
REGISTER DESCRIPTIONS AND MEMORY MAP
Memory Map
+
–
VOUT (0,1)
WCRO
DR0
WCR1
DR0
Wiper Counter (WCR) and Analog Control Registers
(ACR)
DR1
DR1
The X9438 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equiva-
lent to a serial-in, parallel-out counter, with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the wiper counter regis-
ter can be altered in four ways: it may be written
directly by the host via the write WCR Instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
(DR) via the XFR data register instruction (parallel
load); it can be modified one step at a time by the
increment/decrement instruction (WCR only). Finally,
it is loaded with the contents of its data register zero
(R0) upon power-up.
DR2
DR2
DR3
DR3
Wiper Counter Register (WCR)
0
0
WP5 WP4 WP3 WP2 WP1 WP0
(volatile)
(LSB)
WP0-WP5 identify wiper position.
Data Registers (DR, R0 - R3)
Wiper Position or User Data
(Nonvolatile)
FN8199.0
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March 11, 2005
X9438
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
input with respect to V ......................... -1V to +7V
SS
Voltage on any V+ (referenced to V ) ................ +7V
SS
Voltage on any V- (referenced to V ) .................. -7V
SS
(V+) - (V-) .............................................................10V
Any R ....................................................................V+
H
Any R ......................................................................V-
L
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9438
Supply Voltage (V ) Limits
CC
5V ±10%
-40°C
X9438-2.7
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min. Typ. Max.
Unit
%
Test Conditions
25°C, each pot
RTOTAL End to end resistance
Power rating
-20
+20
50
mW
mA
Ω
IW
Wiper current
-3
+3
RW
Wiper resistance
40
100
250
+5.5
+5.5
-4.5
-2.7
V+
VCC = 5V, Wiper Current = 3mA
VCC = 2.7, Wiper Current = 1mA
100
Ω
Vv+
Vv-
Voltage on V+ pin
Voltage on V- pin
X9438
+4.5
+2.7
-5.5
-5.5
V-
V
X9438-2.7
X9438
V
X9438-2.7
VTERM Voltage on any RH or RL pin
Noise
V
dBv
%
-100
1.6
Ref: 1V
Resolution (4)
Absolute linearity (1)
Relative linearity (2)
-1
+1
MI(3) Vw(n)(actual) - Vw(n)(expected)
MI(3) Vw(n + 1) - [Vw(n) + MI
ppm/°C
±20 ppm/°C
-0.2
+0.2
]
Temperature coefficient of RTOTAL
Ratiometric temperature coefficient
±300
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot ( = LSB)
(4) Individual array resolutions
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X9438
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Industrial
Commercial
Symbol
VOS
Parameter
Condition
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
Min. Typ. Max. Min. Typ. Max.
Unit
mV
Input offset voltage
1
3
1
2
TCVOS
Input offset voltage temp.
coefficient
-10
-10
µV/°C
IB
Input bias current
Input offset current
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
50
25
50
25
pA
pA
dB
IOS
CMRR
Common mode
rejection ratio
V
CM = -1V to +1V
70
70
V-
70
70
V-
PSRR
VCM
Power supply
rejection ratio
V+/V- ±3V to ±5V
dB
Input common mode voltage
range
Tj = 25°C
V+
V+
V
AV
VO
Large signal voltage gain
Output voltage swing
VO = -1V to + 1V
30
50
30
50
V/mV
V-
V+
+0.1
+0.1
V
V
-.15
-.15
IO
IS
Output current
Supply current
V+/V- = ±5.5V
V+/V- = ±3.3V
50
30
50
30
mA
mA
V+/V- = ±5.0V
3
3
mA
mA
V+/V- = ±3.0V
1.5
1.5
GB
SR
ΦM
Gain-bandwidth prod
Slew rate
RL = 100k, CL = 50pf
RL = 100k, CL = 50pf
RL = 100k, CL = 50pf
1.0
1.5
80
1.0
1.5
80
MHz
V/µsec
Deg.
Phase margin
V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies. V and V
CC
SS
is the logic supply. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and Commercial (0 to 70°C)
versions of the part unless specified differently.
SYSTEM/DIGITAL D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC
VCC supply current (active)
400
µA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB
ILI
VCC current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
1
10
µA
µA
µA
V
SCL = SDA = VCC, Addr. = VSS
VIN = VSS to VCC
ILO
VIH
VIL
VOL
10
VOUT = VSS to VCC
VCC x 0.7
-0.5
VCC + 0.5
VCC x 0.1
0.4
V
Output LOW voltage
V
IOL = 3mA
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X9438
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Input/output capacitance (SDA)
Typical
Unit
pF
Test Conditions
CI/O
CIN
8
6
VI/O = 0V
VIN = 0V
Input capacitance (A0, A1, A2, A3, and SCL)
Potentiometer capacitance
pF
CL | CH | CW
10/10/25
pF
See SPICE Model
POWER-UP TIMING AND SEQUENCE
Power-up sequence(1): (1) VCC (2) V+ and V-
Power-down sequence: no limitation
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
CC x 0.5
Input rise and fall times
Input and output timing level
V
Note: (1) Applicable to recall and power consumption applications
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macro Model
RTOTAL
5V
2.7V
RL
CL
RH
1533Ω
CW
CH
SDA Output
100pF
100pF
RW
FN8199.0
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X9438
TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
tR
tF
SCL
SDA
tSU:STA
tHD:STA
tSU:STO
tR
tF
Input Timing
tCYC
tHIGH
SCL
SDA
tLOW
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tDH
tAA
DCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
tWRL
SDA
VWx
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X9438
DCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register Address
Inc/Dec
Inc/Dec
SDA
VWx
tWRID
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
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X9438
AC TIMING
Symbol
fSCL
Parameter
Min.
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock frequency
400
tCYC
Clock cycle time
2500
600
tHIGH
Clock high time
tLOW
Clock low time
1300
600
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
Start setup time
Start hold time
600
Stop setup time
600
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
100
(4)
tHD:DAT
0/30
tR
tF
300
300
900
tAA
SCL low to SDA data output valid time
SDA data output hold time
100
50
tDH
TI
Noise suppression time constant at SCL and SDA inputs
Bus free time (Prior to Any Transmission)
WP, A0, A1, A2 and A3 setup time
50
tBUF
tSU:WPA
tHD:WPA
1300
0
WP, A0, A1, A2 and A3 hold time
0
Note: (4) VCC = 5V/2.7V
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
tWR
High-voltage write cycle time (store instructions)
5
10
ms
DCP TIMING
Symbol
Parameter
Min.
Max.
Unit
tWRL
Wiper response time after instruction issued (All load instructions)
10
µs
V
RAMP (sample tester)
CC
Symbol
Parameter
Typ.
Max.
50
Unit
V/ms
trVCC
VCC Power-up rate
.2
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X9438
BASIC APPLICATIONS
I to V Converter
Attenuator
R3
R2
R1
R3
R2
R1
–
+
VO
–
+
VS
VO
R4
R1 = R3 = R4
R2 = 2R1
VO/IS = -R3(1 + R2/R1) + R2
VO = G VS
-1/2 ≤ G ≤ +1/2
Absolute Value Amplifier with Gain
Phase Shifter
2R
R1
R1
–
+
VS
VS
VO
R1
R
R
R
–
+
–
+
C
VO
R
A1
VO = |VS|
A2
R1
R
VO/VS = 180° - 2tan-1wRC
Function Generator
C
R2
R1
–
+
–
+
RA
}
}
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
FN8199.0
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15
X9438
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8199.0
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16
X9438
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0 - 8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8199.0
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March 11, 2005
X9438
Ordering Information
Device
X9438
Y
P
T
V
V
Limits
CC
Blank = 5V ±10%
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0
10kΩ
2.5kΩ
Pot 1
10kΩ
2.5kΩ
W =
Y =
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8199.0
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March 11, 2005
相关型号：
X9438WS24I
DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, SOIC-24
RENESAS
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