X9521_技术文档

X9521

®

Dual DCP, EEPROM Memory

Data Sheet

August 25, 2005

FN8207.1

DESCRIPTION

Fiber Channel/Gigabit Ethernet Laser

Diode Control for Fiber Optic Modules

The X9521 combines two Digitally Controlled Potentiom-

eters (DCP’s), and integrated EEPROM with Block

FEATURES

TM

Lock

protection. All functions of the X9521 are

accessed by an industry standard 2-Wire serial interface.

• Two Digitally Controlled Potentiometers (DCP’s)

—100 Tap - 10kΩ

—256 Tap - 100kΩ

—Non-Volatile

—Write Protect Function

The DCP’s of the X9521 may be utilized to control the

bias and modulation currents of the laser diode in a Fiber

Optic module. The 2kbit integrated EEPROM may be

used to store module definition data.

• 2kbit EEPROM Memory with Write Protect & Block

TM

Lock

The features of the X9521 are ideally suited to simplifying

the design of fiber optic modules which comply to the Gi-

gabit Interface Converter (GBIC) specification. The inte-

gration of these functions into one package significantly

reduces board area, cost and increases reliability of laser

diode modules.

• 2-Wire industry standard Serial Interface

—Complies to the Gigabit Interface Converter

(GBIC) specification

• Single Supply Operation

—2.7V to 5.5V

• Hot Pluggable

• 20 Ld TSSOP

BLOCK DIAGRAM

R

H1

W1

L1

WIPER

COUNTER

REGISTER

8

7 - BIT

NONVOLATILE

MEMORY

WP

PROTECT LOGIC

R

H2

W2

L2

WIPER

COUNTER

REGISTER

CONSTAT

REGISTER

DATA

REGISTER

4

SDA

8 - BIT

NONVOLATILE

MEMORY

COMMAND

DECODE &

2kbit

CONTROL

SCL

EEPROM

ARRAY

LOGIC

THRESHOLD

RESET LOGIC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9521

PIN CONFIGURATION

20 Pin TSSOP

Vcc

NC

R

20

19

18

17

H2

1

2

3

W2

R

NC

L2

4

5

6

16

15

14

13

12

11

WP

SCL

7

8

NC

R

H1

SDA

9

R

W1

L1

V

SS

10

PIN ASSIGNMENT

1

Name

Function

R

Connection to end of resistor array for (the 256 Tap) DCP 2.

H2

R

2

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.

Connection to other end of resistor array for (the 256 Tap) DCP2.

w2

R

3

L2

Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is

enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Pro-

tection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then

no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position

of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-

down” resistor, thus if left floating the write protection feature is disabled.

7

WP

Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input

and output.

8

9

SCL

Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the de-

vice. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.

SDA

Vss

10

11

12

13

20

Ground.

R

Connection to other end of resistor for (the 100 Tap) DCP 1.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1

Connection to end of resistor array for (the 100 Tap) DCP 1.

Supply Voltage.

L1

R

w1

R

H1

Vcc

4, 5, 6,

14, 15,

16, 17,

18, 19

NC

No connect.

SCL

SDA

Data Stable

Data Change

Data Stable

Figure 1. Valid Data Changes on the SDA Bus

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August 25, 2005

X9521

PRINCIPLES OF OPERATION

SERIAL INTERFACE

after transmitting eight bits. During the ninth clock cycle,

the receiver will pull the SDA line LOW to ACKNOWL-

EDGE that it received the eight bits of data. Refer to

Figure 3.

Serial Interface Conventions

The device will respond with an ACKNOWLEDGE after

recognition of a START condition if the correct Device

Identifier bits are contained in the Slave Address Byte. If

a write operation is selected, the device will respond with

an ACKNOWLEDGE after the receipt of each subse-

quent eight bit word.

The device supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is called the

master and the device being controlled is called the

slave. The master always initiates data transfers, and

provides the clock for both transmit and receive opera-

tions. Therefore, the X9521 operates as a slave in all

applications.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

ACKNOWLEDGE. If an ACKNOWLEDGE is detected

and no STOP condition is generated by the master, the

device will continue to transmit data. The device will ter-

Serial Clock and Data

Data states on the SDA line can change only while SCL

is LOW. SDA state changes while SCL is HIGH are

reserved for indicating START and STOP conditions.

See Figure 1. On power-up of the X9521, the SDA pin is

in the input mode.

Serial Start Condition

All commands are preceded by the START condition,

which is a HIGH to LOW transition of SDA while SCL is

HIGH. The device continuously monitors the SDA and

SCL lines for the START condition and does not respond

to any command until this condition has been met. See

Figure 2.

Serial Stop Condition

All communications must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH. The STOP condition is also used to

place the device into the Standby power mode after a

read sequence. A STOP condition can only be issued

after the transmitting device has released the bus. See

Figure 2.

Serial Acknowledge

An ACKNOWLEDGE (ACK) is a software convention

used to indicate a successful data transfer. The transmit-

ting device, either master or slave, will release the bus

SCL

SDA

Start

Stop

Figure 2. Valid Start and Stop Conditions

FN8207.1

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August 25, 2005

X9521

SCL

from

Master

1

8

9

Data Output

from

Transmitter

Data Output

from

Start

Acknowledge

Receiver

Figure 3. Acknowledge Response From Receiver

minate further data transmissions if an ACKNOWLEDGE

is not detected. The master must then issue a STOP

condition to place the device into a known state.

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally

selects the EEPROM array, while setting these bits to

111 selects the DCP structures in the X9521. The

CONSTAT Register may be selected using the Inter-

nal Device Address 010.

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

—The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W bit. This bit defines the operation to be

performed on the device being addressed (as defined

in the bits SA3 - SA1). When the R/W bit is “1”, then a

READ operation is selected. A “0” selects a WRITE

operation (Refer to Figure 4.)

The user addressable internal components of the X9521

can be split up into three main parts:

—Two Digitally Controlled Potentiometers (DCPs)

—EEPROM array

—Control and Status (CONSTAT) Register

Depending upon the operation to be performed on each

of these individual parts, a 1, 2 or 3 Byte protocol is used.

All operations however must begin with the Slave

Address Byte being issued on the SDA pin. The Slave

address selects the part of the X9521 to be addressed,

and specifies if a Read or Write operation is to be per-

formed.

SA7 SA6

SA3 SA2

SA5 SA4

SA1

SA0

R/W

1 0 1 0

READ /

WRITE

INTERNAL

DEVICE

ADDRESS

DEVICE TYPE

IDENTIFIER

It should be noted that in order to perform a write opera-

tion to either a DCP or the EEPROM array, the Write

Enable Latch (WEL) bit must first be set (See “BL1, BL0:

Block Lock protection bits - (Nonvolatile)” on page 12.)

Internally Addressed

Device

Internal Address

(SA3 - SA1)

EEPROM Array

CONSTAT Register

DCP

000

010

111

Slave Address Byte

Following a START condition, the master must output a

Slave Address Byte (Refer to Figure 4.). This byte con-

sists of three parts:

Bit SA0

Operation

WRITE

0

1

—The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).

The Device Type Identifier must always be set to 1010

in order to select the X9521.

READ

Figure 4. Slave Address Format

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X9521

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence (for either

the EEPROM array, the Non Volatile Memory of a DCP

(NVM), or the CONSTAT Register) has been correctly

issued (including the final STOP condition), the X9521

initiates an internal high voltage write cycle. This cycle

typically requires 5 ms. During this time, no further Read

or Write commands can be issued to the device. Write

Acknowledge Polling is used to determine when this high

voltage write cycle has been completed.

R

N

Hx

WIPER

COUNTER

REGISTER

(WCR)

“WIPER”

RESISTOR

ARRAY

DECODER

FET

SWITCHES

To perform acknowledge polling, the master issues a

START condition followed by a Slave Address Byte. The

Slave Address issued must contain a valid Internal

Device Address. The LSB of the Slave Address (R/W)

can be set to either 1 or 0 in this case. If the device is still

busy with the high voltage cycle then no ACKNOWL-

EDGE will be returned. If the device has completed the

write operation, an ACKNOWLEDGE will be returned

and the host can then proceed with a read or write opera-

tion. (Refer to Figure 5.).

2

1

0

NON

VOLATILE

MEMORY

(NVM)

R

Lx

Wx

Figure 6. DCP Internal Structure

DIGITALLY CONTROLLED POTENTIOMETERS

DCP Functionality

The X9521 includes two independent resistor arrays.

These arrays respectively contain 99 and 255 discrete

resistive segments that are connected in series. The

physical ends of each array are equivalent to the fixed

Byte load completed

by issuing STOP.

Enter ACK Polling

terminals of a mechanical potentiometer (R and R

inputs - where x = 1,2).

Hx

Lx

Issue START

At both ends of each array and between each resistor

segment there is a CMOS switch connected to the wiper

Issue Slave Address

Byte (Read or Write)

Issue STOP

(R ) output. Within each individual array, only one

x

w

switch may be turned on at any one time. These

switches are controlled by the Wiper Counter Register

(WCR) (See Figure 6). The WCR is a volatile register.

NO

ACK

returned?

On power-up of the X9521, wiper position data is auto-

matically loaded into the WCR from its associated Non

Volatile Memory (NVM) Register. The Table below

shows the Initial Values of the DCP WCR’s before the

contents of the NVM is loaded into the WCR.

YES

High Voltage Cycle

complete. Continue

command sequence?

NO

Issue STOP

DCP

R / 100 TAP

Initial Values Before Recall

V / TAP = 0

1

L

YES

R / 256 TAP

V / TAP = 255

H

2

Continue normal

Read or Write

command sequence

PROCEED

Figure 5.

Acknowledge Polling Sequence

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X9521

Vcc

Vcc (Max.)

V

TRIP

t

trans

pu

t

0

Maximum Wiper Recall time

Figure 7. DCP Power-up

The data in the WCR is then decoded to select and

enable one of the respective FET switches. A “make

before break” sequence is used internally for the FET

switches when the wiper is moved from one tap position

to another.

remains unchanged. Therefore, when Vcc to the device

is powered down then back up, the “wiper position”

reverts to that last position written to the DCP using a

nonvolatile write operation.

Both volatile and nonvolatile write operations are

executed using a three byte command sequence: (DCP)

Slave Address Byte, Instruction Byte, followed by a Data

Byte (See Figure 9).

Hot Pluggability

Figure 7 shows a typical waveform that the X9521 might

experience in a Hot Pluggable situation. On power-up,

Vcc applied to the X9521 may exhibit some amount of

ringing, before it settles to the required value.

A DCP Read operation allows the user to “read out” the

current “wiper position” of the DCP, as stored in the

associated WCR. This operation is executed using the

Random Address Read command sequence, consisting

of the (DCP) Slave Address Byte followed by an

Instruction Byte and the Slave Address Byte again (Refer

to Figure 10.).

The device is designed such that the wiper terminal

(R ) is recalled to the correct position (as per the last

Wx

stored in the DCP NVM), when the voltage applied to

Vcc exceeds V

for a time exceeding t .

pu

TRIP

Therefore, if t

settle above V

minal position is recalled by (a maximum) time: t

is defined as the time taken for Vcc to

(Figure 7): then the desired wiper ter-

trans

TRIP

Instruction Byte

+

trans

While the Slave Address Byte is used to select the DCP

devices, an Instruction Byte is used to determine which

DCP is being addressed.

t

. It should be noted that t

is determined by sys-

pu

trans

tem hot plug conditions.

DCP Operations

In total there are three operations that can be performed

on any internal DCP structure:

The Instruction Byte (Figure 8) is valid only when the

Device Type Identifier and the Internal Device

Address bits of the Slave Address are set to

1010111. In this case, the two Least Significant Bit’s

(I1 - I0) of the Instruction Byte are used to select the

particular DCP (0 - 2). In the case of a Write to any of

the DCPs (i.e. the LSB of the Slave Address is 0), the

Most Significant Bit of the Instruction Byte (I7), deter-

mines the Write Type (WT) performed.

—DCP Nonvolatile Write

—DCP Volatile Write

—DCP Read

A nonvolatile write to a DCP will change the “wiper

position” by simultaneously writing new data to the

associated WCR and NVM. Therefore, the new “wiper

position” setting is recalled into the WCR after Vcc of the

X9521 is powered down and then powered back up.

If WT is “1”, then a Nonvolatile Write to the DCP occurs.

In this case, the “wiper position” of the DCP is changed

by simultaneously writing new data to the associated

WCR and NVM. Therefore, the new “wiper position” set-

ting is recalled into the WCR after Vcc of the X9521 has

been powered down then powered back up

A volatile write operation to a DCP however, changes the

“wiper position” by writing new data to the associated

WCR only. The contents of the associated NVM register

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X9521

volatile or nonvolatile. If the Instruction Byte format is

valid, another ACKNOWLEDGE is then returned by the

X9521.

I7

I6

0

I5

0

I4

0

I3

0

I2

0

I1

P1

I0

P0

WT

Following the Instruction Byte, a Data Byte is issued to

the X9521 over SDA. The Data Byte contents is latched

into the WCR of the DCP on the first rising edge of the

clock signal, after the LSB of the Data Byte (D0) has

been issued on SDA (See Figure 25).

WRITE TYPE

DCP SELECT

†

WT

Description

Select a Volatile Write operation to be performed

on the DCP pointed to by bits P1 and P0

The Data Byte determines the “wiper position” (which

FET switch of the DCP resistive array is switched ON) of

the DCP. The maximum value for the Data Byte depends

upon which DCP is being addressed (see Table below).

0

Select a Nonvolatile Write operation to be per-

formed on the DCP pointed to by bits P1 and P0

1

†

This bit has no effect when a Read operation is being performed.

P1 - P0

DCPx

# Taps

Reserved

Max. Data Byte

0

1

0

1

0

1

Figure 8. Instruction Byte Format

x = 1

x = 2

100

256

Refer to Appendix 1

FFh

If WT is “0” then a DCP Volatile Write is performed. This

operation changes the DCP “wiper position” by writing

new data to the associated WCR only. The contents of

the associated NVM register remains unchanged. There-

fore, when Vcc to the device is powered down then back

up, the “wiper position” reverts to that last written to the

DCP using a nonvolatile write operation.

Reserved

Using a Data Byte larger than the values specified above

results in the “wiper terminal” being set to the highest tap

position. The “wiper position” does NOT roll-over to the

lowest tap position.

For DCP2 (256 Tap), the Data Byte maps one to one to

the “wiper position” of the DCP “wiper terminal”. There-

DCP Write Operation

A write to DCPx (x = 1,2) can be performed using the

three byte command sequence shown in Figure 9.

fore, the Data Byte 00001111 (15 ) corresponds to set-

10

ting the “wiper terminal” to tap position 15. Similarly, the

Data Byte 00011100 (28 ) corresponds to setting the

In order to perform a write operation on a particular DCP,

the Write Enable Latch (WEL) bit of the CONSTAT Reg-

ister must first be set (See “BL1, BL0: Block Lock protec-

tion bits - (Nonvolatile)” on page 12.)

10

“wiper terminal” to tap position 28. The mapping of the

Data Byte to “wiper position” data for DCP1 (100 Tap), is

shown in “APPENDIX 1” . An example of a simple C lan-

guage function which “translates” between the tap posi-

tion (decimal) and the Data Byte (binary) for DCP1, is

given in “APPENDIX 2” .

The Slave Address Byte 10101110 specifies that a Write

to a DCP is to be conducted. An ACKNOWLEDGE is

returned by the X9521 after the Slave Address, if it has

been received correctly.

It should be noted that all writes to any DCP of the X9521

are random in nature. Therefore, the Data Byte of con-

secutive write operations to any DCP can differ by an

arbitrary number of bits. Also, setting the bits (P1 = 0,

Next, an Instruction Byte is issued on SDA. Bits P1 and

P0 of the Instruction Byte determine which WCR is to be

written, while the WT bit determines if the Write is to be

1

0

1

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

S

T

A

R

T

A

C

K

WT

0

P1 P0

A

C

K

A

C

K

S

T

O

P

SLAVE ADDRESS BYTE

INSTRUCTION BYTE

Figure 9. DCP Write Command Sequence

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X9521

WRITE Operation

READ Operation

S

t

S

t

S

t

o

p

Signals from

the Master

Instruction

Slave

Address

Slave

Address

a

r

a

r

Byte

Data Byte

t

SDA Bus

P

0

10101110 ^W00000 ^P₁

10101111

T

A

C

K

A

C

K

A

C

K

Signals from

the Slave

DCPx

x = 1

x = 2

-

“Dummy” write

LSB

MSB

“-” = DON’T CARE

Figure 10. DCP Read Sequence

P0 = 0) or (P1 = 1, P0 = 1) are reserved sequences, and

will result in no ACKNOWLEDGE after sending an

Instruction Byte on SDA.

to be read. In this case, the state of the WT bit is “don’t

care”. If the Instruction Byte format is valid, then another

ACKNOWLEDGE is returned by the X9521.

The factory default setting of all “wiper position” settings

is with 00h stored in the NVM of the DCPs. This corre-

Following this ACKNOWLEDGE, the master immediately

issues another START condition and a valid Slave

address byte with the R/W bit set to 1. Then the X9521

issues an ACKNOWLEDGE followed by Data Byte, and

finally, the master issues a STOP condition. The Data

Byte read in this operation, corresponds to the “wiper

position” (value of the WCR) of the DCP pointed to by

bits P1 and P0.

sponds to having the “wiper teminal” R

(x=1,2) at the

WX

“lowest” tap position, Therefore, the resistance between

and R is a minimum (essentially only the Wiper

R

WX

LX

Resistance, R ).

W

DCP Read Operation

A read of DCPx (x = 1,2) can be performed using the

three byte random read command sequence shown in

Figure 10.

It should be noted that when reading out the data byte for

DCP1 (100 Tap), the upper most significant bit is an

“unknown”. For DCP2 (256 Tap) however, all bits of the

data byte are relevant (See Figure 10).

The master issues the START condition and the Slave

Address Byte 10101110 which specifies that a “dummy”

write” is to be conducted. This “dummy” write operation

sets which DCP is to be read (in the preceding Read

operation). An ACKNOWLEDGE is returned by the

X9521 after the Slave Address if received correctly. Next,

an Instruction Byte is issued on SDA. Bits P1 - P0 of the

Instruction Byte determine which DCP “wiper position” is

S

t

a

r

WRITE Operation

S

t

o

p

Signals from

the Master

Address

Byte

Slave

Address

Data

Byte

t

SDA Bus

0 1

0 0

0

1

0 0

A

C

K

A

C

K

A

C

K

Internal

Signalsfrom

the Slave

Device

Address

Figure 11. EEPROM Byte Write Sequence

FN8207.1

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August 25, 2005

X9521

S

t

S

t

o

p

(2 < n < 16)

a

r

Signals from

the Master

Address

Byte

Slave

Address

Data

(1)

Data

(n)

t

SDA Bus

0 1

0 0

0

1

0 0

A

C

K

A

C

K

A

C

K

A

C

K

Signals from

the Slave

Figure 12. EEPROM Page Write Operation

2kbit EEPROM ARRAY

EEPROM Page Write

Operations on the 2kbit EEPROM Array, consist of either

1, 2 or 3 byte command sequences. All operations on the

EEPROM must begin with the Device Type Identifier of

the Slave Address set to 1010000. A Read or Write to

the EEPROM is selected by setting the LSB of the Slave

Address to the appropriate value R/W (Read = “1”, Write

= ”0”).

In order to perform an EEPROM Page Write operation to

the EEPROM array, the Write Enable Latch (WEL) bit of

the CONSTAT Register must first be set (See “BL1, BL0:

Block Lock protection bits - (Nonvolatile)” on page 12.)

The X9521 is capable of a page write operation. It is initi-

ated in the same manner as the byte write operation; but

instead of terminating the write cycle after the first data

byte is transferred, the master can transmit an unlimited

number of 8-bit bytes. After the receipt of each byte, the

X9521 responds with an ACKNOWLEDGE, and the

address is internally incremented by one. The page

address remains constant. When the counter reaches

the end of the page, it “rolls over” and goes back to ‘0’ on

the same page.

In some cases when performing a Read or Write to the

EEPROM, an Address Byte may also need to be speci-

fied. This Address Byte can contain the values 00h to

FFh.

EEPROM Byte Write

In order to perform an EEPROM Byte Write operation to

the EEPROM array, the Write Enable Latch (WEL) bit of

the CONSTAT Register must first be set (See “BL1, BL0:

Block Lock protection bits - (Nonvolatile)” on page 12.)

For example, if the master writes 12 bytes to the page

starting at location 11 (decimal), the first 5 bytes are writ-

ten to locations 11 through 15, while the last 7 bytes are

written to locations 0 through 6. Afterwards, the address

counter would point to location 7. If the master supplies

more than 16 bytes of data, then new data overwrites the

previous data, one byte at a time (See Figure 13).

For a write operation, the X9521 requires the Slave

Address Byte and an Address Byte. This gives the

master access to any one of the words in the array. After

receipt of the Address Byte, the X9521 responds with an

ACKNOWLEDGE, and awaits the next eight bits of data.

After receiving the 8 bits of the Data Byte, it again

responds with an ACKNOWLEDGE. The master then

terminates the transfer by generating a STOP condition,

at which time the X9521 begins the internal write cycle to

the nonvolatile memory (See Figure 11). During this

internal write cycle, the X9521 inputs are disabled, so it

does not respond to any requests from the master. The

SDA output is at high impedance. A write to a region of

EEPROM memory which has been protected with the

Block-Lock feature (See “BL1, BL0: Block Lock

protection bits - (Nonvolatile)” on page 12.), suppresses

the ACKNOWLEDGE bit after the Address Byte.

The master terminates the Data Byte loading by issuing

a STOP condition, which causes the X9521 to begin the

nonvolatile write cycle. As with the byte write operation,

all inputs are disabled until completion of the internal

write cycle. See Figure 12 for the address, ACKNOWL-

EDGE, and data transfer sequence.

FN8207.1

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August 25, 2005

X9521

S

t

Signals from

the Master

S

t

o

p

Slave

Address

a

r

t

SDA Bus

1

01 0 0 0 0

A

C

K

Signals from

the Slave

Data

Figure 14. Current EEPROM Address Read Sequence

Upon receipt of the Slave Address Byte with the R/W bit

set to one, the device issues an ACKNOWLEDGE and

then transmits the eight bits of the Data Byte. The master

terminates the read operation when it does not respond

with an ACKNOWLEDGE during the ninth clock and then

issues a STOP condition (See Figure 14 for the address,

ACKNOWLEDGE, and data transfer sequence).

Stops and EEPROM Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

and receiving the subsequent ACKNOWLEDGE signal.

If the master issues a STOP within a Data Byte, or before

the X9521 issues a corresponding ACKNOWLEDGE,

the X9521 cancels the write operation. Therefore, the

contents of the EEPROM array does not change.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read oper-

ation, the master must either issue a STOP condition

during the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a STOP condition.

EEPROM Array Read Operations

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of the

Slave Address Byte is set to one. There are three basic

read operations: Current EEPROM Address Read, Ran-

dom EEPROM Read, and Sequential EEPROM Read.

Another important point to note regarding the “Current

EEPROM Address Read” , is that this operation is not

available if the last executed operation was an access to

a DCP or the CONSTAT Register (i.e.: an operation

using the Device Type Identifier 1010111 or 1010010).

Immediately after an operation to a DCP or CONSTAT

Register is performed, only a “Random EEPROM Read”

is available. Immediately following a “Random EEPROM

Read” , a “Current EEPROM Address Read” or “Sequen-

tial EEPROM Read” is once again available (assuming

that no access to a DCP or CONSTAT Register occur in

the interim).

Current EEPROM Address Read

Internally the device contains an address counter that

maintains the address of the last word read incremented

by one. Therefore, if the last read was to address n, the

next read operation would access data from address

n+1. On power-up, the address of the address counter is

undefined, requiring a read or write operation for initial-

ization.

5 bytes

7 bytes

address

11

address

15₁₀

address

= 6₁₀

10

address pointer

ends here

Addr = 7₁₀

Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.

FN8207.1

10

August 25, 2005

X9521

WRITE Operation

READ Operation

S

t

S

t

S

t

o

p

Signals from

the Master

Slave

Address

Byte

Slave

Address

a

r

a

r

t

SDA Bus

0

1

1 0 1 0 0 0 0

10 1 0 0 0 0

A

C

K

A

C

K

A

C

K

Signals from

the Slave

Data

“Dummy” Write

Figure 15. Random EEPROM Address Read Sequence

Address Byte, and then goes into standby mode after the

STOP bit. All bus activity will be ignored until another

START is detected.

Random EEPROM Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

issues the START condition and the Slave Address Byte,

receives an ACKNOWLEDGE, then issues an Address

Byte. This “dummy” Write operation sets the address

pointer to the address from which to begin the random

EEPROM read operation.

Sequential EEPROM Read

Sequential reads can be initiated as either a current

address read or random address read. The first Data

Byte is transmitted as with the other modes; however,

the master now responds with an ACKNOWLEDGE,

indicating it requires additional data. The X9521 contin-

ues to output a Data Byte for each ACKNOWLEDGE

received. The master terminates the read operation by

not responding with an ACKNOWLEDGE and instead

issuing a STOP condition.

After the X9521 acknowledges the receipt of the Address

Byte, the master immediately issues another START

condition and the Slave Address Byte with the R/W bit

set to one. This is followed by an ACKNOWLEDGE from

the X9521 and then by the eight bit word. The master ter-

minates the read operation by not responding with an

ACKNOWLEDGE and instead issuing a STOP condition

(Refer to Figure 15.).

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments through

the entire memory contents to be serially read during

one operation. At the end of the address space the

counter “rolls over” to address 00h and the device con-

tinues to output data for each ACKNOWLEDGE

received (Refer to Figure 16.).

A similar operation called “Set Current Address” also

exists. This operation is performed if a STOP is issued

instead of the second START shown in Figure 15. In this

case, the device sets the address pointer to that of the

S

Slave

Address

A

C

K

A

C

K

A

C

K

Signals from

the Master

t

o

p

SDA Bus

1

0 0 0

A

C

K

Signals from

the Slave

Data

(2)

Data

(n - 1)

Data

(1)

Data

(n)

(n is any integer greater than 1)

Figure 16. Sequential EEPROM Read Sequence

FN8207.1

August 25, 2005

11

X9521

The WEL bit is a volatile latch that powers up in the dis-

abled, LOW (0) state. The WEL bit is enabled / set by

writing 00000010 to the CONSTAT register. Once

enabled, the WEL bit remains set to “1” until either it is

reset to “0” (by writing 00000000 to the CONSTAT regis-

ter) or until the X9521 powers down, and then up again.

CS3

BL0

CS7 CS6

CS4

BL1

CS5

0

CS2 CS1 CS0

0

RWEL

WEL

NV

Writes to the WEL bit do not cause an internal high volt-

age write cycle. Therefore, the device is ready for

another operation immediately after a STOP condition is

executed in the CONSTAT Write command sequence

(See Figure 18).

Bit(s)

CS7 - CS5

BL1 - BL0

RWEL

Description

Always “0”(RESERVED)

Sets the Block Lock partition

Register Write Enable Latch bit

Write Enable Latch bit

RWEL: Register Write Enable Latch (Volatile)

WEL

The RWEL bit controls the (CONSTAT) Register Write

Enable status of the X9521. Therefore, in order to write

to any of the bits of the CONSTAT Register (except

WEL), the RWEL bit must first be set to “1”. The RWEL

bit is a volatile bit that powers up in the disabled, LOW

(“0”) state.

CS0

Always “0” (RESERVED)

NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).

Figure 17. CONSTAT Register Format

It must be noted that the RWEL bit can only be set, once

the WEL bit has first been enabled (See "CONSTAT

Register Write Operation").

CONTROL AND STATUS REGISTER

The Control and Status (CONSTAT) Register pro-

vides the user with a mechanism for changing and

reading the status of various parameters of the

X9521 (See Figure 17).

The RWEL bit will reset itself to the default “0” state, in

one of three cases:

—After a successful write operation to any bits of

the CONSTAT register has been completed (See

Figure 18).

The CONSTAT register is a combination of both volatile

and nonvolatile bits. The nonvolatile bits of the CON-

STAT register retain their stored values even when Vcc

is powered down, then powered back up. The volatile

bits however, will always power-up to a known logic state

“0” (irrespective of their value at power-down).

—When the X9521 is powered down.

—When attempting to write to a Block Lock protected

region of the EEPROM memory (See "BL1, BL0: Block

Lock protection bits - (Nonvolatile)", below).

A detailed description of the function of each of the CON-

STAT register bits follows:

BL1, BL0: Block Lock protection bits - (Nonvolatile)

WEL: Write Enable Latch (Volatile)

The Block Lock protection bits (BL1 and BL0) are

used to:

The WEL bit controls the Write Enable status of the

entire X9521 device. This bit must first be enabled before

ANY write operation (to DCPs, EEPROM memory array,

or the CONSTAT register). If the WEL bit is not first

enabled, then ANY proceeding (volatile or nonvolatile)

write operation to DCPs, EEPROM array, as well as the

CONSTAT register, is aborted and no ACKNOWLEDGE

is issued after a Data Byte.

—Inhibit a write operation from being performed to cer-

tain addresses of the EEPROM memory array

—Inhibit a DCP write operation (changing the “wiper

position”).

FN8207.1

12

August 25, 2005

X9521

SCL

SDA

CS0

CS2CS1

1

CS7 CS6

S

T

A

R

T

1

0

1

0

1

0

R/W A

1

A

C

K

CS5 CS4 CS3

A

C

K

S

T

O

P

C

K

SLAVE ADDRESS BYTE

ADDRESS BYTE

CONSTAT REGISTER DATA IN

Figure 18. CONSTAT Register Write Command Sequence

The region of EEPROM memory which is protected /

locked is determined by the combination of the BL1 and

BL0 bits written to the CONSTAT register. It is possible

to lock the regions of EEPROM memory shown in the

table below:

Only one data byte is allowed to be written for each

CONSTAT register Write operation. The user must issue

a STOP, after sending this byte to the register, to initiate

the nonvolatile cycle that stores the BP1and BP0 bits.

The X9521 will not ACKNOWLEDGE any data bytes

written after the first byte is entered (Refer to Figure 18.).

Protected Addresses

(Size)

Partition of array

locked

BL1 BL0

When writing to the CONSTAT register, the bits CS7-

CS5 and CS0 must all be set to “0”. Writing any other bit

sequence to bits CS7-CS5 and CS0 of the CONSTAT

register is reserved.

0

1

0

1

0

1

None (Default)

Upper 1/4

Upper 1/2

All

C0h - FFh (64 bytes)

80h - FFh (128 bytes)

00h - FFh (256 bytes)

Prior to writing to the CONSTAT register, the WEL and

RWEL bits must be set using a two step process, with

the whole sequence requiring 3 steps

If the user attempts to perform a write operation on a pro-

tected region of EEPROM memory, the operation is

aborted without changing any data in the array.

—Write a 02H to the CONSTAT Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation preceded

by a START and ended with a STOP).

When the Block Lock bits of the CONSTAT register are

set to something other than BL1 = 0 and BL0 = 0, then

the “wiper position” of the DCPs cannot be changed - i.e.

DCP write operations cannot be conducted:

—Write a 06H to the CONSTAT Register to set the Reg-

ister Write Enable Latch (RWEL) AND the WEL bit.

This is also a volatile cycle. The zeros in the data byte

are required. (Operation preceded by a START and

ended with a STOP).

BL1 BL0

DCP Write Operation Permissible

0

1

0

1

0

1

YES (Default)

—Write a one byte value to the CONSTAT Register that

has all the bits set to the desired state. The CONSTAT

register can be represented as 000st010 in binary,

where st are the Block Lock Protection (BL1 and BL0)

bits. This operation is proceeded by a START and

ended with a STOP bit. Since this is a nonvolatile write

cycle, it will typically take 5ms to complete. The RWEL

bit is reset by this cycle and the sequence must be

repeated to change the nonvolatile bits again. If bit 2 is

set to ‘1’ in this third step (000s t110) then the RWEL

bit is set, but the BL1 and BL0 bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and the

X9521 does not return an ACKNOWLEDGE.

NO

The factory default setting for these bits are BL1 = 0,

BL0 = 0.

IMPORTANT NOTE: If the Write Protect (WP) pin of the

X9521 is active (HIGH), then all nonvolatile write opera-

tions to both the EEPROM memory and DCPs are inhib-

ited, irrespective of the Block Lock bit settings (See "WP:

Write Protection Pin").

CONSTAT Register Write Operation

The CONSTAT register is accessed using the Slave

Address set to 1010010 (Refer to Figure 4.). Following

the Slave Address Byte, access to the CONSTAT regis-

ter requires an Address Byte which must be set to FFh.

FN8207.1

13

August 25, 2005

X9521

READ Operation

WRITE Operation

S

t

S

t

S

t

o

p

Signals from

the Master

Slave

Address

Byte

Slave

Address

a

r

a

r

t

CS7 … CS0

SDA Bus

0

1

10 1 0 0 1 0

1 0 1 0 0 1 0

A

C

K

A

C

K

A

C

K

Signals from

the Slave

Data

“Dummy” Write

Figure 19. CONSTAT Register Read Command Sequence

For example, a sequence of writes to the device CON-

STAT register consisting of [02H, 06H, 02H] will reset the

BL0 and BL0 bits in the CONSTAT Register to “0”.

DATA PROTECTION

There are a number of levels of data protection features

designed into the X9521. Any write to the device first

requires setting of the WEL bit in the CONSTAT register.

A write to the CONSTAT register itself, further requires

the setting of the RWEL bit. Block Lock protection of the

device enables the user to inhibit writes to certain regions

of the EEPROM memory, as well as to all the DCPs. One

further level of data protection in the X9521, is incorpo-

rated in the form of the Write Protection pin.

It should be noted that a write to any nonvolatile bit of

CONSTAT register will be ignored if the Write Protect

pin of the X9521 is active (HIGH) (See "WP: Write Pro-

tection Pin").

CONSTAT Register Read Operation

The contents of the CONSTAT Register can be read at

any time by performing a random read (See Figure 19).

Using the Slave Address Byte set to 10100101, and an

Address Byte of FFh. Only one byte is read by each reg-

ister read operation. The X9521 resets itself after the first

byte is read. The master should supply a STOP condition

to be consistent with the bus protocol.

WP: Write Protection Pin

When the Write Protection (WP) pin is active (HIGH), it

disables nonvolatile write operations to the X9521.

The table below (X9521 Write Permission Status) sum-

marizes the effect of the WP pin (and Block Lock), on the

write permission status of the device.

After setting the WEL and / or the RWEL bit(s) to a “1”,

a CONSTAT register read operation may occur, without

interrupting a proceeding CONSTAT register write

operation.

Additional Data Protection Features

In addition to the preceding features, the X9521 also

incorporates the following data protection functionality:

When reading the contents of the CONSTAT register,

the bits CS7 - CS5 and CS0 will always return “0”.

—The proper clock count and data bit sequence is

required prior to the STOP bit in order to start a nonvol-

atile write cycle.

X9521 Write Permission Status

Block Lock

Bits

Write to CONSTAT Register

Permitted

DCP Volatile Write

Permitted

DCP Nonvolatile

Write to EEPROM

BL0 BL1 WP

Write Permitted

Permitted

Volatile Bits

NO

Nonvolatile Bits

x

1

0

x

1

0

1

x

0

1

x

0

1

NO

YES

NO

YES

NO

0

Not in locked region

Yes (All Array)

YES

NO

YES

0

YES

FN8207.1

14

August 25, 2005

X9521

ABSOLUTE MAXIMUM RATINGS

Parameter

Min.

-65

Max.

+135

+150

+15

+7

Units

°C

V

Temperature under Bias

Storage Temperature

-65

Voltage on WP pin (With respect to Vss)

Voltage on other pins (With respect to Vss)

-1.0

V

Vcc

5

V

| Voltage on R - Voltage on R | (x = 1,2. Referenced to Vss)

D.C. Output Current (SDA)

Hx

Lx

0

mA

°C

V

Lead Temperature (Soldering, 10 seconds)

300

5.5

Supply Voltage Limits (Applied Vcc voltage, referenced to Vss)

2.7

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Units

Industrial

-40

+85

°C

NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended peri-

ods may affect device reliability

Figure 20. Equivalent A.C. Circuit

Vcc = 5V

2300Ω

SDA

100pF

Figure 21. DCP SPICE Macromodel

R

TOTAL

R

Hx

Lx

C

L

C

H

10pF

R

W

C

10pF

W

25pF

Wx

(x = 1,2)

R

FN8207.1

15

August 25, 2005

X9521

TIMING DIAGRAMS

Figure 22. Bus Timing

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

SU:STO

SU:ST

HD:DAT

t

HD:STA

SDA IN

t

BUF

A

DH

SDA OUT

Figure 23. WP Pin Timing

START

SCL

Clk 1

Clk 9

SDA IN

WP

t

HD:WP

SU:WP

Figure 24. Write Cycle Timing

SCL

8th bit of last byte

ACK

SDA

t

WC

Stop

Start

Condition

FN8207.1

16

August 25, 2005

X9521

Figure 25. DCP “Wiper Position” Timing

Rwx (x = 1,2)

R

wx(n + 1)

R

wx(n)

R

wx(n - 1)

t

wr

Time

n = tap position

SCL

SDA

1

0

1

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

S

T

A

R

T

A

C

K

WT

0

P1 P0

A

C

K

A

C

K

S

T

O

P

SLAVE ADDRESS BYTE

INSTRUCTION BYTE

FN8207.1

August 25, 2005

17

X9521

D.C. OPERATING CHARACTERISTICS

Symbol

Parameter

Min Typ

Max

Unit

Test Conditions / Notes

Current into V

CC

(X9521: Active)

(3)

(1)

f

= 400kHz

I

SCL

CC1

0.4

1.5

mA

Read memory array

Write nonvolatile memory

V

= V

CC

Current into V

SDA

CC

WP = Vss or Open/Floating

(X9521:Standby)

(2)

µA

CC2

(3)

50

V

= V (when no bus activity

SCL

else f

CC

With 2-Wire bus activity

= 400kHz)

SCL

No 2-Wire bus activity

(4)

Input Leakage Current (SCL, SDA)

Input Leakage Current (WP)

0.1

10

µA

V

= GND to V

CC.

IN

I

LI

V

= V to V

SS CC

analog pins floating

with all other

Analog Input Leakage

1

10

µA

ai

(5)

V

= GND to V

OUT

CC.

(2)

Output Leakage Current (SDA)

0.1

10

µA

LO

X9521 is in Standby

(6)

Input LOW Voltage (SCL, SDA, WP)

-0.5

2.0

0.8

V

IL

V

CC

(6)

Input HIGH Voltage (SCL,SDA, WP)

SDA Output Low Voltage

V

IH

+0.5

I

= 2.0mA

SINK

0.4

OLx

Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200nS after a STOP ending a read operation; or t after a STOP ending a write operation.

WC

Notes: 2.The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t

after a STOP that initiates

WC

a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address

Byte.

Notes: 3.Current through external pull up resistor not included.

Notes: 4.V_IN= Voltage applied to input pin.

Notes: 5.V_OUT= Voltage applied to output pin.

Notes: 6.V Min. and V Max. are for reference only and are not tested.

IL IH

FN8207.1

18

August 25, 2005

X9521

A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)

400kHz

Symbol

Parameter

Min

Max

Units

f

t

SCL Clock Frequency

0

400

kHz

SCL

(5)

IN

Pulse width Suppression Time at inputs

SCL LOW to SDA Data Out Valid

50

0.1

1.3

ns

µs

(5)

AA

0.9

(5)

Time the bus free before start of new transmission

t

BUF

Clock LOW Time

1.3

0.6

100

0

µs

ns

µs

LOW

Clock HIGH Time

HIGH

Start Condition Setup Time

Start Condition Hold Time

Data In Setup Time

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

Data In Hold Time

Stop Condition Setup Time

0.6

(5)

Data Output Hold Time

SDA and SCL Rise Time

SDA and SCL Fall Time

50

ns

t

DH

(5)

R

(2)

300

20 +.1Cb

(5)

F

t

20 +.1Cb

WP Setup Time

0.6

0

µs

pF

SU:WP

HD:WP

WP Hold Time

Cb

Capacitive load for each bus line

400

A.C. TEST CONDITIONS

Input Pulse Levels

0.1V

to 0.9V

CC

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

10ns

0.5V

CC

See Figure 20

NONVOLATILE WRITE CYCLE TIMING

(1)

Symbol

Parameter

Nonvolatile Write Cycle Time

Min.

Typ.

Max.

Units

(4)

5

10

ms

t

WC

CAPACITANCE (T = 25°C, f = 1.0 MHz, V

= 5V)

A

CC

Symbol

Parameter

Max

Units

Test Conditions

= 0V

(5)

V

Output Capacitance (SDA, V1RO, V2RO, V3RO)

Input Capacitance (SCL, WP)

8

pF

C

OUT

(5)

IN

V

= 0V

6

pF

IN

Notes: 1. Typical values are for T = 25°C and V

= 5.0V

CC

A

Notes: 2.Cb = total capacitance of one bus line in pF.

Notes: 3.Over recommended operating conditions, unless otherwise specified

Notes: 4.t

is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

WC

Notes: 5.This parameter is not 100% tested.

FN8207.1

19

August 25, 2005

X9521

POTENTIOMETER CHARACTERISTICS

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

%

Test Conditions/Notes

R

End to End Resistance Tolerance

-20

Vss

+20

TOL

RHx

RLx

V

R

Terminal Voltage (x = 1,2)

V

H

CC

R Terminal Voltage (x = 1,2)

L

V

CC

R

= 10kΩ (DCP1)

10

5

mW

TOTAL

(1)

P

R

Power Rating (6)

= 100kΩ (DCP2)

TOTAL

I

= 1mA, V

CC

= 5 V,

= Vss

W

200

400

Ω

V

= Vcc, V

RHx

(x = 1,2).

RLx

R

I

DCP Wiper Resistance

W

I

= 1mA, V

= 2.7 V,

W

CC

= Vcc, V

1200

4.4

Ω

V

= Vss

RHx

(x = 1,2)

RLx

Wiper Current (6)

Noise

mA

W

mV/

sqt(Hz)

R

= 10kΩ ( DCP1)

TOTAL

mV/

sqt(Hz)

= 100kΩ (DCP2)

TOTAL

(2)

(4)

MI

R

- R

-1

+1

w(n)(actual)

w(n)(expected)

]

w(n) + MI

Absolute Linearity

(3)

(4)

MI

- [R

w(n + 1)

Relative Linearity

= 10kΩ (DCP1)

= 100kΩ (DCP2)

±300

ppm/°C

pF

TOTAL

R

Temperature Coefficient

TOTAL

Potentiometer Capacitances

C /C /C

10/10/25

See Figure 21.

See Figure 25.

H

L

W

t

Wiper Response time (6)

200

75

µs

V

wcr

V

Vcc power-up DCP recall threshold

Vcc power-up DCP recall delay time (6)

TRIP

t

25

50

ms

PU

Notes: 1. Power Rating between the wiper terminal R

and the end terminals R or R - for ANY tap position n, (x = 1,2).

HX LX

WX(n)

Notes: 2.Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R

Ml Maximum (x = 1,2).

(actual) - R

(expected)) = ±1

wx(n)

Notes: 3.Relative Linearity is a measure of the error in step size between taps = R

- [R

+ Ml] = ±1 Ml (x = 0,1,2)

Wx(n + 1)

wx(n)

Notes: 4.1 Ml = Minimum Increment = R

/ (Number of taps in DCP - 1).

TOT

Notes: 5.Typical values are for T = 25°C and nominal supply voltage.

A

Notes: 6.This parameter is periodically sampled and not 100% tested.

FN8207.1

20

August 25, 2005

X9521

APPENDIX 1

DCP1 (100 Tap) Tap position to Data Byte translation Table

Data Byte

Tap

Position

Decimal

Binary

0

1

0

1

0000 0000

0000 0001

.

23

24

25

26

23

24

56

55

0001 0111

0001 1000

0011 1000

0011 0111

.

48

49

50

51

33

32

64

65

0010 0001

0010 0000

0100 0000

0100 0001

.

73

74

75

76

87

88

0101 0111

0101 1000

0111 1000

0111 0111

120

119

.

98

99

97

96

0110 0001

0110 0000

FN8207.1

21

August 25, 2005

X9521

APPENDIX 2

DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)

unsigned DCP1_TAP_Position(int tap_pos)

{

int block;

int i;

int offset;

int wcr_val;

offset= 0;

block = tap_pos / 25;

if (block < 0) return ((unsigned)0);

else if (block <= 3)

{

switch(block)

{ case (0): return ((unsigned)tap_pos) ;

case (1):

{

wcr_val = 56;

offset = tap_pos - 25;

for (i=0; i<= offset; i++) wcr_val-- ;

return ((unsigned)++wcr_val);

}

case (2):

{

wcr_val = 64;

offset = tap_pos - 50;

for (i=0; i<= offset; i++) wcr_val++ ;

return ((unsigned)--wcr_val);

}

case (3):

{

wcr_val = 120;

offset = tap_pos - 75;

for (i=0; i<= offset; i++) wcr_val-- ;

return ((unsigned)++wcr_val);

}

return((unsigned)01100000);

}

FN8207.1

22

August 25, 2005

X9521

APPENDIX 2

DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)

unsigned DCP100_TAP_Position(int tap_pos)

{

/* optional range checking

*/ if (tap_pos < 0) return ((unsigned)0);

else if (tap_pos >99) return ((unsigned) 96);

/* set to min val */

/* set to max val */

/* 100 Tap DCP encoding formula */

if (tap_pos > 74)

return ((unsigned) (195 - tap_pos));

else if (tap_pos > 49)

return ((unsigned) (14 + tap_pos));

else if (tap_pos > 24)

return ((unsigned) (81 - tap_pos));

else return (tap_pos);

}

FN8207.1

August 25, 2005

23

X9521

20-LEAD PLASTIC, TSSOP PACKAGE TYPE V

.025 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.252 (6.4)

.260 (6.6)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

(7.72)

(4.16)

.010 (.25)

Gage Plane

0° - 8 °

Seating Plane

(1.78)

(0.42)

.019 (.50)

.029 (.75)

DetailA (20X)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8207.1

24

August 25, 2005

X9521

ORDERING INFORMATION

Device

X9521

P

T

Temperature Range

I = Industrial -40°C to +85°C

Package

V20 = 20-Lead TSSOP

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8207.1

25

August 25, 2005


型号：	X9521
厂家：	Intersil
描述：	Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules 光纤通道/千兆以太网激光二极管控制光纤模块光纤二极管激光二极管以太网
文件：	总25页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9521 [INTERSIL]

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