X9523 [INTERSIL]
Laser Diode Control for Fiber Optic Modules; 激光二极管控制光纤模块
| 型号： | X9523 |
| 厂家： | 
Intersil |
| 描述： | Laser Diode Control for Fiber Optic Modules |
| 文件： | 总30页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9523
®
Laser Diode Control for Fiber Optic Modules
Data Sheet
March 10, 2005
FN8209.0
PRELIMINARY
DESCRIPTION
Dual DCP, POR, Dual Voltage Monitors
The X9523 combines two Digitally Controlled Potenti-
ometers (DCPs), V1 / Vcc Power-on Reset (POR) cir-
cuitry, qnd two programmable voltage monitor inputs
with software and hardware indicators. All functions of
the X9523 are accessed by an industry standard 2-Wire
serial interface.
FEATURES
• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Nonvolatile
—Write Protect Function
The DCPs of the X9523 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The programmable POR circuit may be
used to ensure that V1 / Vcc is stable before power is
applied to the laser diode / module. The programmable
voltage monitors may be used for monitoring various
module alarm levels.
• 2-Wire industry standard Serial Interface
• Power-On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
The features of the X9523 are ideally suited to simpli-
fying the design of fiber optic modules . The integra-
tion of these functions into one package significantly
reduces board area, cost and increases reliability of
laser diode modules.
• Hot Pluggable
• 20 Pin packages
TM
—XBGA
—TSSOP
BLOCK DIAGRAM
RH1
WIPER
COUNTER
REGISTER
RW1
RL1
PROTECT LOGIC
WP
7
- BIT
NONVOLATILE
MEMORY
DATA
REGISTER
8
SDA
COMMAND
DECODE &
RH2
RW2
RL2
CONSTAT
REGISTER
WIPER
COUNTER
REGISTER
CONTROL
SCL
LOGIC
THRESHOLD
RESET LOGIC
8 - BIT
NONVOLATILE
MEMORY
MR
2
V3RO
V2RO
V1RO
V3
-
+
VTRIP3
V2
-
+
VTRIP2
VTRIP1
POWER-ON /
LOW VOLTAGE
RESET
V1 / Vcc
+
-
GENERATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9523
DETAILED DEVICE DESCRIPTION
returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO out-
put (HIGH).
The X9523 combines two Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/Vcc power-on reset
control, V1/Vcc low voltage reset control, and two sup-
plementary voltage monitors in one package. These
functions are suited to the control, support, and monitor-
ing of various system parameters in fiber optic modules.
The combination of the X9523 fucntionality lowers sys-
tem cost, increases reliability, and reduces board space
requirements using Intersil’s unique XBGA™ packaging.
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out-
put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two moni-
tor outputs can be read out via the 2-wire serial port.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Intersil’s unique circuits allow for all internal trip volt-
ages to be individually programmed with high accu-
racy. This gives the designer great flexibility in
changing system parameters, either at the time of
manufacture, or in the field.
Applying voltage to V
activates the Power-on Reset
CC
circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V falls below the mini-
The device features a 2-Wire interface and software
protocol allowing operation on an I C™ compatible
CC
2
mum V
trip point. V1RO remains HIGH until V
CC
CC
serial bus.
PIN CONFIGURATION
XBGA
20 Pin TSSOP
1
2
3
4
V1 / Vcc
V1RO
RH2
RW2
20
19
18
17
1
2
3
4
V2RO V1 / Vcc
RL2
V3
RW2
RH2
A
B
C
D
E
RL2
V3
V2RO
V2
V2
NC
RH1
V1RO
V3RO
5
6
NC
NC
16
15
14
13
12
11
NC
NC
V3RO WP
MR
WP
SCL
SDA
MR
RL1
7
8
NC
SCL
SDA
VSS
RH1
RW1
VSS
9
RW1
RL1
10
Top View – Bumps Down
NOT TO SCALE
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March 10, 2005
X9523
PIN ASSIGNMENT
Pin
1
XBGA
B3
Name
Function
RH2
Connection to end of resistor array for (the 256 Tap) DCP 2.
Rw2
RL2
2
A3
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
3
A4
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When
the V3 input is higher than the V
level. Connect V3 to VSS when not used.
threshold voltage, V3RO makes a transition to a HIGH
4
5
B4
C3
V3
TRIP3
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than V
and goes LOW when V3 is less than VTRIP3. There is no delay circuitry
V3RO
TRIP3
on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates
a reset cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time
tpurst after MR has returned to it’s normally LOW state. The reset time can be selected using
bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
6
7
D3
C4
MR
WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Pro-
tection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Al-
so, when the Write Protection is enabled, and the device DCP Write Lock feature is active (i.e.
the DCP Write Lock bit is “1”), then no “write” (volatile or nonvolatile) operations can be per-
formedon the wiper position of any of the integrated Digitally Controlled Potentiometers
(DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protec-
tion feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for
data input and output.
8
9
D4
E4
SCL
SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires an
external pull up resistor.
10
11
12
13
E1
E3
E2
D1
Vss
RL1
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Rw1
RH1
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When
the V2 input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH
level. Connect V2 to VSS when not used.
17
18
B1
A1
V2
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is great-
er than VTRIP2, and goes LOW when V2 is less than VTRIP2. There is no power-up reset delay
circuitry on this pin. The V2RO pin requires the use of an external “pull-up” resistor.
V2RO
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active
whenever V1 / Vcc falls below VTRIP1. V1RO becomes active on power-up and remains ac-
tive for a time tpurst after the power supply stabilizes (tpurst can be changed by varying the
POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an
external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset
(MR) input pin.
19
20
B2
A2
V1RO
V1 / Vcc
NC
Supply Voltage.
No Connect.
14, 15,
16,
C1, C2,
D2
FN8209.0
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March 10, 2005
X9523
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera-
tions. Therefore, the X9523 operates as a slave in all
applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The trans-
mitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3.
Serial Clock and Data
Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1.On power-up of the X9523, the SDA pin is
in the input mode.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subse-
quent eight bit word.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter-
SCL
SDA
Start
Stop
Figure 2. Valid Start and Stop Conditions
FN8209.0
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March 10, 2005
X9523
SCL
from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from
Start
Acknowledge
Receiver
Figure 3. Acknowledge Response From Receiver
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9523. The CON-
STAT Register may be selected using the Internal
Device Address 010.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Nonvolatile Write Acknowledge Polling
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto-
col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9523 to
be addressed, and specifies if a Read or Write opera-
tion is to be performed.
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON-
STAT Register) has been correctly issued (including the
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
R/W
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).
1 0 1 0
READ /
WRITE
INTERNAL
DEVICE
ADDRESS
DEVICE TYPE
IDENTIFIER
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
Internally Addressed
Device
Internal Address
(SA3 - SA1)
010
111
CONSTAT Register
DCP
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9523.
RESERVED
All Others
Bit SA0
Operation
WRITE
0
1
READ
Figure 4. Slave Address Format
FN8209.0
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March 10, 2005
X9523
final STOP condition), the X9523 initiates an internal high
voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
RHx
N
WIPER
COUNTER
REGISTER
(WCR)
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no
ACKNOWLEDGE will be returned. If the device has
completed the write operation, an ACKNOWLEDGE will
be returned and the host can then proceed with a read or
write operation. (Refer to Figure 5.).
“WIPER”
RESISTOR
ARRAY
DECODER
FET
SWITCHES
2
1
0
NON
VOLATILE
MEMORY
(NVM)
RLx
RWx
Byte load completed
by issuing STOP.
Enter ACK Polling
Figure 6. DCP Internal Structure
Issue START
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
returned?
terminals of a mechanical potentiometer (R and R
Hx
Lx
inputs - where x = 1,2).
YES
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R ) output. Within each individual array, only one
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
High Voltage Cycle
complete. Continue
command sequence?
NO
x
w
Issue STOP
YES
On power-up of the X9523, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
Continue normal
Read or Write
command sequence
PROCEED
DCP
Initial Values Before Recall
R1 / 100 TAP
VL / TAP = 0
Figure 5.
Acknowledge Polling Sequence
R2 / 256 TAP
VH / TAP = 255
FN8209.0
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6
X9523
V1/Vcc
V1/Vcc (Max.)
V
TRIP1
t
t
trans
purst
t
0
Maximum Wiper Recall time
Figure 7. DCP Power-up
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1/Vcc to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
Hot Pluggability
Figure 7 shows a typical waveform that the X9523 might
experience in a Hot Pluggable situation. On power-up,
V1 / Vcc applied to the X9523 may exhibit some amount
of ringing, before it settles to the required value.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
The device is designed such that the wiper terminal
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
(R ) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
Wx
V1/Vcc exceeds V
for a time exceeding t
(the
purst
TRIP1
Power-on Reset time, set in the CONSTAT Register -
See “CONTROL AND STATUS REGISTER” on
page 10.).
Therefore, if ttrans is defined as the time taken for V1 /
Vcc to settle above V
(Figure 7): then the desired
TRIP1
Instruction Byte
wiper terminal position is recalled by (a maximum) time:
ttrans + tpurst. It should be noted that ttrans is determined
by system hot plug conditions.
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1/Vcc of
the X9523 is powered down and then powered back up.
If WT is “1”, then a Nonvolatile Write to the DCP occurs.
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
FN8209.0
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March 10, 2005
X9523
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WT
WRITE TYPE
DCP SELECT
Following the Instruction Byte, a Data Byte is issued to
the X9523 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 29).
WT†
Description
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
1
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
†
This bit has no effect when a Read operation is being performed.
Figure 8. Instruction Byte Format
P1- P0
DCPx
# Taps
Max. Data Byte
0
0
1
1
0
1
0
1
RESERVED
WCR and NVM. Therefore, the new “wiper position” set-
ting is recalled into the WCR after V1/Vcc of the X9523
has been powered down then powered back up.
x = 1
x = 2
100
256
Refer to Appendix 1
FFh
RESERVED
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when V1/Vcc to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
DCP Write Operation
fore, the Data Byte 00001111 (15 ) corresponds to set-
ting the “wiper terminal” to tap position 15. Similarly, the
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
10
Data Byte 00011100 (28 ) corresponds to setting the
10
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg-
ister must first be set (See “WEL: Write Enable Latch
(Volatile)” on page 10.).
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1”. An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2”.
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9523 after the Slave Address, if it has
been received correctly.
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Figure 9. DCP Write Command Sequence
FN8209.0
March 10, 2005
8
X9523
WRITE Operation
READ Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Instruction
Slave
Address
Slave
Address
a
r
a
r
Byte
Data Byte
t
t
SDA Bus
P
0
10101110 W 00000 P1
10101111
T
A
C
K
A
C
K
A
C
K
Signals from
the Slave
DCPx
x = 1
-
“Dummy” write
x = 2
LSB
MSB
“-” = DON’T CARE
Figure 10. DCP Read Sequence
It should be noted that all writes to any DCP of the
X9523 are random in nature. Therefore, the Data
Byte of consecutive write operations to any DCP can
differ by an arbitrary number of bits. Also, setting the
bits P1 = 1, P0 = 1 is a reserved sequence, and will
result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9523 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9523.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” RWX (x = 1,2) at the
“lowest” tap position, Therefore, the resistance between
RWX and RLX is a minimum (essentially only the Wiper
Resistance, RW).
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9523
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
S
t
a
r
WRITE Operation
S
t
o
p
Signals from
the Master
Address
Byte
Slave
Address
Data
Byte
t
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
Internal
Signalsfrom
the Slave
Device
Address
Figure 11. EEPROM Byte Write Sequence
FN8209.0
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March 10, 2005
X9523
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis-
ter) or until the X9523 powers down, and then up again.
CS3
CS7 CS6
CS4
0
CS5
CS2 CS1 CS0
POR1
NV
V2OS V3OS
DWLK RWEL
NV
WEL
POR0
NV
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 13).
Bit(s)
Description
POR1
V2OS
V1OS
CS4
Power-on Reset bit
V2 Output Status flag
V1 Output Status flag
RWEL: Register Write Enable Latch (Volatile)
Always set to “0” (RESERVED)
Sets the DCP Write Lock
Register Write Enable Latch bit
Write Enable Latch bit
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9523. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
DWLK
RWEL
WEL
POR0
Power-on Reset bit
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
Figure 12. CONSTAT Register Format
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
The RWEL bit will reset itself to the default “0” state, in
one of two cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 13).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register pro-
vides the user with a mechanism for changing and
reading the status of various parameters of the
X9523 (See Figure 12).
—When the X9523 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when
V1/Vcc is powered down, then powered back up. The
volatile bits however, will always power-up to a known
logic state “0” (irrespective of their value at power-down).
When the DCP Write Lock bit of the CONSTAT register
is set to “1”, then the “wiper position” of the DCPs can-
not be changed - i.e. DCP write operations cannot be
conducted:
A detailed description of the function of each of the CON-
STAT register bits follows:
DWLK
DCP Write Operation Permissible
0
1
YES (Default)
NO
WEL: Write Enable Latch (Volatile)
The factory default setting for this bit is DWLK = 0.
The WEL bit controls the Write Enable status of the
entire X9523 device. This bit must first be enabled before
ANY write operation (to DCPs, or the CONSTAT regis-
ter). If the WEL bit is not first enabled, then ANY pro-
ceeding (volatile or nonvolatile) write operation to DCPs
or the CONSTAT register, is aborted and no ACKNOWL-
EDGE is issued after a Data Byte.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9523 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
FN8209.0
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March 10, 2005
X9523
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 13. CONSTAT Register Write Command Sequence
POR1, POR0: Power-on Reset bits - (Nonvolatile)
Applying voltage to V activates the Power-on Reset
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
CC
circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the V threshold for a
—The device is powered down, then back up,
TRIP1
—The corresponding VxRO output becomes LOW.
period of time, t
(See Figure 25).
PURST
The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the tPURST delay time of
the Power-on Reset circuitry (See "VOLTAGE MONI-
TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK, POR1 and
POR0 bits. The X9523 will not ACKNOWLEDGE any
data bytes written after the first byte is entered (Refer to
Figure 13.).
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
Power-on Reset delay (tPUV1RO
)
POR1 POR0
0
0
1
1
0
1
0
1
50ms
100ms (Default)
200ms
When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON-
STAT register is a reserved operation.
300ms
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x = 2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre-
sponding VxRO output is HIGH.
—Write a 06H to the CONSTAT Register to set the Reg-
ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).
FN8209.0
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March 10, 2005
X9523
READ Operation
WRITE Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Slave
Address
Address
Byte
Slave
Address
a
r
a
r
t
t
CS7 … CS0
SDA Bus
0
1
10 1 0 0 1 0
1 0 1 0 0 1 0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
“Dummy” Write
Figure 14. CONSTAT Register Read Command Sequence
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, t is the DCP Write Lock
(DWLK) bit, and qr are the Power-on Reset delay time
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 14).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each reg-
ister read operation. The X9523 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
(t
) control bits (POR1 - POR0). This operation
PUV1RO
is proceeded by a START and ended with a STOP bit.
Since this is a nonvolatile write cycle, it will typically
take 5ms to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this third
step (qxys t11r) then the RWEL bit is set, but the
V2OS, V3OS, POR1, POR0, and DWLK bits remain
unchanged. Writing a second byte to the control regis-
ter is not allowed. Doing so aborts the write operation
and the X9523 does not return an ACKNOWLEDGE.
After setting the WEL and / or the RWEL bit(s) to a “1”,
a CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write
operation.
When performing a read operation on the CONSTAT
registerm, bit CS4 will always return a “0” value.
DATA PROTECTION
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to “0”.
There are a number of levels of data protection fea-
tures designed into the X9523. Any write to the device
first requires setting of the WEL bit in the CONSTAT
register. A write to the CONSTAT register itself, further
requires the setting of the RWEL bit. DCP Write Lock
protection of the device enables the user to inhibit
writes to all the DCPs. One further level of data protec-
tion in the X9523, is incorporated in the form of the
Write Protection pin.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect
pin of the X9523 is active (HIGH) (See "WP: Write
Protection Pin").
X9522 Write Permission Status
Write to CONSTAT Register
DWLK
(DCP Write Lock
bit status)
WP
Permitted
(Write Protect pin
status)
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Volatile Bits
NO
Nonvolatile Bits
1
0
1
0
1
1
0
0
NO
YES
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
FN8209.0
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X9523
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9523.
V
TRIPx
0V
Vx
The table below (X9523 Write Permission Status) sum-
marizes the effect of the WP pin (and DCP Write Lock),
on the write permission status of the device.
VxRO
0V
Additional Data Protection Features
V1 / Vcc
In addition to the preceding features, the X9523 also
incorporates the following data protection functionality:
VTRIP1
0 Volts
(x = 2,3)
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
Figure 16. Voltage Monitor Response
VOLTAGE MONITORING FUNCTIONS
V1 / Vcc Monitoring
The X9523 monitors the supply voltage and drives the
V1RO output HIGH (using an external “pull up” resistor)
It is recommended to stop communication to the device
while while V1RO is HIGH. Also, setting the Manual
Reset (MR) pin HIGH overrides the Power-on/Low
Voltage circuitry and forces the V1RO output pin HIGH
(See "Manual Reset").
if V1/Vcc is lower than V
threshold. The V1RO
TRIP1
output will remain HIGH until V1/Vcc exceeds V
TRIP1
for a minimum time of t
V1RO pin is driven to a LOW state. See Figure 25.
. After this time, the
PURST
Manual Reset
The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect-
ing a push-button directly from V1/Vcc to the MR pin.
For the Power-on/Low Voltage Reset function of the
X9523, the V1RO output may be driven HIGH down to a
V1/Vcc of 1V (V
). See Figure 25. Another feature
RVALID
of the X9523, is that the value of t
in software via the CONSTAT register (See “POR1,
POR0: Power-on Reset bits - (Nonvolatile)” on page 11.).
may be selected
PURST
V1RO remains HIGH for time t
after MR has
PURST
returned to its LOW state (See Figure 15). An external
“pull down” resistor is required to hold this pin (nor-
mally) LOW.
V1 / Vcc
V2 monitoring
The X9523 asserts the V2RO output HIGH if the volt-
VTRIP1
0 Volts
age V2 exceeds the corresponding V
threshold
TRIP2
(See Figure 16). The bit V2OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
MR
0 Volts
The V2RO output may remain active HIGH with V
down to 1V.
CC
V1RO
0 Volts
V3 monitoring
t
PURST
The X9523 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V threshold
Figure 15. Manual Reset Response
TRIP3
(See Figure 16). The bit V3OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V3RO output may remain active HIGH with V
down to 1V.
CC
FN8209.0
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X9523
VTRIPx
V1 / Vcc
V2, V3
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h
SDA
†
†
†
01h sets VTRIP1
A0h
Data Byte
†
S
T
A
R
T
09h sets VTRIP2
†
†
0Dh sets VTRIP3
All others Reserved.
Figure 17. Setting V
to a higher level (x = 1,2,3).
TRIPx
V
THRESHOLDS (X = 1,2,3)
Setting a Higher VTRIPx Voltage (x = 1,2,3)
TRIPX
To set a V
threshold to a new voltage which is
TRIPx
The X9523 is shipped with pre-programmed threshold
(V ) voltages. In applications where the required
thresholds are different from the default values, or if a
higher precision/tolerance is required, the X9523 trip
points may be adjusted by the user, using the steps
detailed below.
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
sponding input pin (V1/Vcc, V2 or V3). Then, a pro-
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by
TRIPx
TRIPx
Setting a VTRIPx Voltage (x = 1,2,3)
the Byte Address 01h for V
, 09h for V
, and
TRIP1
TRIP2
0Dh for V
gram V
, and a 00h Data Byte in order to pro-
. The STOP bit following a valid write
There are two procedures used to set the threshold
TRIP3
voltages (V
), depending if the threshold voltage
TRIPx
TRIPx
operation initiates the programming sequence. Pin WP
must then be brought LOW to complete the operation
(See Figure 18). The user does not have to set the
WEL bit in the CONSTAT register before performing
this write sequence.
to be stored is higher or lower than the present value.
For example, if the present V is 2.9 V and the
TRIPx
new V
is 3.2 V, the new voltage can be stored
TRIPx
directly into the V
cell. If however, the new setting
TRIPx
is to be lower than the present setting, then it is neces-
sary to “reset” the V
new value.
voltage before setting the
TRIPx
VP
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
†
00h
SDA
†
†
A0h
03h Resets VTRIP1
Data Byte
S
T
A
R
T
†
0Bh Resets VTRIP2
†
0Fh Resets VTRIP3
†
All others Reserved.
Figure 18. Resetting the V
Level
TRIPx
FN8209.0
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X9523
Setting a Lower V
Voltage (x = 1,2,3).
After applying the test voltage to the voltage monitor
input pin, the test voltage can be decreased (either in dis-
crete steps, or continuously) until the output of the volt-
age monitor circuit changes state. At this point, the error
between the actua measured, and desired threshold lev-
els is calculated.
TRIPx
In order to set V
to a lower voltage than the
TRIPx
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
must first be “reset” accord-
TRIPx
TRIPx
can be set to the desired
TRIPx
voltage using the procedure described in “Setting a
Higher V Voltage”.
For example, the desired threshold for V
is set to
TRIPx
TRIP2
3.0V, and a test voltage of 3.4V was applied to the input
pin V2 (after applying power to V1/Vcc). The input volt-
age is decreased, and found to trip the associated output
level of pin V2RO from a LOW to a HIGH, when V2
reaches 3.09V. From this, it can be calculated that the
programming error is 3.09 - 3.0 = 0.09V.
Resetting the VTRIPx Voltage (x = 1,2,3).
To reset a V
voltage, apply the programming volt-
TRIPx
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
, 0Bh for V
, and 0Fh for V
, followed
TRIP1
TRIP2
TRIP3
If the error between the desired and measured V
is
TRIPx
by 00h for the Data Byte in order to reset V
. The
TRIPx
less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
LOW to complete the operation (See Figure 18).The
user does not have to set the WEL bit in the CON-
STAT register before performing this write sequence.
iteration of the V
programming sequence can be
TRIPx
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
After being reset, the value of V
nal value of 1.7V.
becomes a nomi-
TRIPx
If the calculated error is greater than zero, then the
V
must first be “reset”, and then programmed to the
TRIPx
a value equal to the previously set V
minus the cal-
TRIPx
VTRIPx Accuracy (x = 1,2,3).
culated error. If it is the case that the error is less than
zero, then the V must be programmed to a value
The accuracy with which the V
thresholds are set,
TRIPx
TRIPx
can be controlled using the iterative process shown in
Figure 19.
equal to the previously set V
of the calculated error.
plus the absolute value
TRIPx
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x = 1,2,3)." ) .
Continuing the previous example, we see that the calcu-
lated error was 0.09V. Since this is greater than zero, we
must first “reset” the V
threshold, then apply a volt-
TRIP2
age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
The desired threshold voltage is then applied to the
appropriate input pin (V1/Vcc, V2 or V3) and the proce-
must apply V
= 2.91 V to pin V2 and execute the
TRIP2
dure described in Section “Setting a Higher V
Voltage“ must be followed.
TRIPx
programming sequence (See "Setting a Higher VTRIPx
Voltage (x = 1,2,3)" ) .
Once the desired V
threshold has been set, the
TRIPx
Using this process, the desired accuracy for a particu-
error between the desired and (new) actual set threshold
can be determined. This is achieved by applying V1/Vcc
to the device, and then applying a test voltage higher
than the desired threshold voltage, to the input pin of the
lar V
threshold may be attained using a succes-
TRIPx
sive number of iterations.
voltage monitor circuit whose V
was programmed.
TRIPx
For example, if V
was set to a desired level of 3.0V,
TRIP2
then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In the case of setting of V then
TRIP1
only V1/Vcc need be applied. In all cases, care should be
taken not to exceed the maximum input voltage limits.
FN8209.0
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March 10, 2005
X9523
Note: X = 1,2,3.
VTRIPx Programming
Let: MDE = Maximum Desired Error
NO
MDE+
Desired VTRIPx
<
present value?
Acceptable
Error Range
Desired Value
MDE–
YES
Execute
VTRIPx Reset
Sequence
Error = Actual – Desired
Set Vx = desired VTRIPx
Execute
Set Higher VTRIPx
Sequence
New Vx applied =
Old Vx applied - | Error |
New Vx applied =
Old Vx applied + | Error |
Execute
Reset VTRIPx
Sequence
Apply Vcc & Voltage
> Desired VTRIPx to Vx
Decrease Vx
Output
switches?
NO
YES
Actual VTRIPx
- Desired VTRIPx
= Error
Error < MDE–
Error >MDE+
| Error | < | MDE |
DONE
Figure 19. V
Setting / Reset Sequence (x = 1,2,3)
TRIPx
FN8209.0
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March 10, 2005
X9523
ABSOLUTE MAXIMUM RATINGS
Parameter
Min.
-65
Max.
+135
+150
+15
+7
Units
°C
°C
V
Temperature under Bias
Storage Temperature
-65
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
-1.0
-1.0
V
V1/Vcc
5
V
| Voltage on R - Voltage on R | (x = 0,1,2. Referenced to Vss)
D.C. Output Current (SDA,V1RO,V2RO,V3RO)
Hx
Lx
0
mA
°C
V
Lead Temperature (Soldering, 10 seconds)
300
Supply Voltage Limits (Applied V1/Vcc voltage, referenced to Vss)
2.7
5.5
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
0
Max.
70
Units
°C
Commercial
Industrial
-40
+85
°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect device reliability
Figure 20. Equivalent A.C. Circuit
V1 / Vcc = 5V
2300Ω
SDA
V2RO
V3RO
100pF
V1RO
Figure 21. DCP SPICE Macromodel
RTOTAL
RHx
RLx
CL
CH
10pF
RW
CW
25pF
10pF
(x=0,1,2)
RWx
FN8209.0
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March 10, 2005
X9523
TIMING DIAGRAMS
Figure 22. Bus Timing
t
t
t
t
F
HIGH
LOW
R
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Figure 23. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
Figure 24. Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
FN8209.0
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March 10, 2005
X9523
Figure 25. Power-Up and Power-Down Timing
t
t
F
R
V1/Vcc
0 Volts
V
TRIP1
t
PURST
t
PURST
t
RPD
V1RO
0 Volts
MR
0 Volts
Figure 26. Manual Reset Timing Diagram
MR
t
MRPW
0 Volts
t
t
PURST
MRD
V1RO
0 Volts
V1/Vcc
V1 / Vcc
V
TRIP1
Figure 27. V2, V3 Timing Diagram
t
t
Fx
Rx
Vx
V
TRIPx
t
t
RPDx
RPDx
t
RPDx
0 Volts
t
RPDx
VxRO
0 Volts
V1/Vcc
V
TRIP1
V
RVALID
0 Volts
Note : x = 2,3.
FN8209.0
March 10, 2005
19
X9523
Figure 28. V
Programming Timing Diagram (x = 1,2,3).
TRIPX
V Vcc, V2, V3
VTRIPx
tTSU
tTHD
VP
WP
t
VPS
tVPO
SCL
SDA
twc
00h
tVPH
NOTE : V1/Vcc must be greater than V2, V3 when programming.
Figure 29. DCP “Wiper Position” Timing
Rwx (x = 0,1,2)
R
wx(n + 1)
R
wx(n)
R
wx(n - 1)
twr
Time
n = tap position
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
FN8209.0
March 10, 2005
20
X9523
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min Typ
Max
Unit
Test Conditions / Notes
Current into VCC Pin
(X9523: Active)
(1)
fSCL = 400kHz
ICC1
Read memory array (3)
0.4
1.5
mA
Write nonvolatile memory
V
SDA = VCC
Current into VCC Pin
MR = Vss
(X9523:Standby)
With 2-Wire bus activity (3)
No 2-Wire bus activity
(2)
WP = Vss or Open/Floating
VSCL= VCC (when no bus activity
else fSCL = 400kHz)
ICC2
µA
50
50
Input Leakage Current (SCL, SDA, MR)
Input Leakage Current (WP)
0.1
10
10
µA
µA
VIN (4) = GND to VCC.
ILI
VIN = VSS to VCC with all other an-
alog pins floating
Iai
Analog Input Leakage
1
10
10
µA
VOUT (5) = GND to VCC.
X9523 is in Standby(2)
Output Leakage Current (SDA, V1RO,
V2RO, V3RO)
ILO
0.1
µA
VTRIP1PR
VTRIPxPR
VTRIP1 Programming Range
2.75
1.8
4.70
4.70
V
V
VTRIPx Programming Range (x = 2,3)
2.85
4.55
3.0
4.7
3.05
4.75
Factory shipped default option A
Factory shipped default option B
(6)
Pre - programmed VTRIP1 threshold
Pre - programmed VTRIP2 threshold
Pre - programmed VTRIP3 threshold
VTRIP1
V
V
V
1.65
2.85
1.8
3.0
1.85
3.05
Factory shipped default option A
Factory shipped default option B
(6)
VTRIP2
1.65
2.85
1.8
3.0
1.85
3.05
Factory shipped default option A
Factory shipped default option B
(6)
VTRIP3
VSDA = VSCL = VCC
Others=GND or VCC
V2 Input leakage current
V3 Input leakage current
1
1
IVx
µA
V
(7)
VIL
Input LOW Voltage (SCL, SDA, WP, MR)
Input HIGH Voltage (SCL,SDA, WP, MR)
-0.5
2.0
0.8
VCC
+0.5
(7)
VIH
V
V1RO, V2RO, V3RO, SDA Output Low
Voltage
VOLx
ISINK = 2.0mA
0.4
V
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation.
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that initiates a
WC
high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4. VIN = Voltage applied to input pin.
Notes: 5. VOUT = Voltage applied to output pin.
Notes: 6. See “ORDERING INFORMATION” on page 30.
Notes: 7. VIL Min. and VIH Max. are for reference only and are not tested
FN8209.0
March 10, 2005
21
X9523
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
400kHz
Symbol
fSCL
Parameter
Min
Max
Units
SCL Clock Frequency
0
400
kHz
(5)
tIN
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
50
ns
(5)
tAA
0.1
0.9
µs
(5)
tBUF
Time the bus free before start of new transmission
Clock LOW Time
1.3
1.3
0.6
0.6
0.6
100
0
µs
µs
µs
µs
µs
ns
µs
µs
ns
tLOW
tHIGH
Clock HIGH Time
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
0.6
50
(5)
tDH
(5)
20 +.1Cb (2)
tR
SDA and SCL Rise Time
300
300
ns
(5)
20 +.1Cb (2)
tF
SDA and SCL Fall Time
WP Setup Time
ns
µs
µs
pF
tSU:WP
tHD:WP
0.6
0
WP Hold Time
Cb(5)
Capacitive load for each bus line
400
A.C. TEST CONDITIONS
Input Pulse Levels
0.1V
to 0.9V
CC
CC
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
10ns
0.5V
CC
See Figure 20
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Nonvolatile Write Cycle Time
Min.
Typ.(1)
Max.
Units
(4)
tWC
5
10
ms
CAPACITANCE (T = 25°C, F = 1.0 MHZ, V = 5V)
A
CC
Symbol
Parameter
Max
Units
Test Conditions
OUT = 0V
VIN = 0V
(5)
V
COUT
Output Capacitance (SDA, V1RO, V2RO, V3RO)
Input Capacitance (SCL, WP, MR)
8
pF
pF
(5)
CIN
6
Notes: 1. Typical values are for TA = 25°C and VCC = 5.0V
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
FN8209.0
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March 10, 2005
X9523
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
%
Test Conditions/Notes
RTOL
End to End Resistance Tolerance
RH Terminal Voltage (x = 0,1,2)
RL Terminal Voltage (x = 0,1,2)
-20
Vss
Vss
+20
VCC
VCC
VRHx
VRLx
V
V
R
TOTAL = 10kΩ (DCP0, DCP1)
10
5
mW
mW
Power Rating (1)(6)
PR
RTOTAL = 100kΩ (DCP2)
IW = 1mA, VCC = 5V, VRHx = Vcc,
VRLx = Vss (x = 0,1,2).
200
400
400
Ω
RW
DCP Wiper Resistance
IW = 1mA, VCC = 2.7V,
1200
4.4
Ω
VRHx = Vcc, VRLx = Vss
(x = 0,1,2)
Wiper Current (6)
Noise
IW
mA
mV/
R
TOTAL = 10kΩ (DCP0, DCP1)
TOTAL = 100kΩ (DCP2)
sqt(Hz)
mV/
sqt(Hz)
R
Absolute Linearity (2)
Relative Linearity (3)
MI(4)
MI(4)
Rw(n)(actual) - Rw(n)(expected)
Rw(n + 1) - [Rw(n) + MI
-1
-1
+1
+1
]
RTOTAL = 10kΩ (DCP0, DCP1)
RTOTAL = 100kΩ (DCP2)
±300
±300
ppm/°C
ppm/°C
pF
R
TOTAL Temperature Coefficient
Potentiometer Capacitances
Wiper Response time(6)
CH/CL/CW
twr
10/10/25
See Figure 21.
See Figure 29.
200
µs
Notes: 1. Power Rating between the wiper terminal R
and the end terminals R or RLX - for ANY tap position n, (x = 0,1,2).
HX
WX(n)
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R
Ml Maximum (x = 0,1,2).
(actual) - R
(expected)) = ±1
wx(n)
wx(n)
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
- [R
+ Ml] = ±1 Ml (x = 0,1,2)
Wx(n+1)
wx(n)
Notes: 4. 1 Ml = Minimum Increment = R
/ (Number of taps in DCP - 1).
TOT
Notes: 5. Typical values are for TA = 25°C and nominal supply voltage.
Notes: 6. This parameter is periodically sampled and not 100% tested.
FN8209.0
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March 10, 2005
X9523
V
(X = 1,2,3) PROGRAMMING PARAMETERS (See Figure 28)
TRIPX
Parameter
Description
Min
10
Typ
Max
Units
µs
tVPS
VTRIPx Program Enable Voltage Setup time
tVPH
tTSU
tTHD
VTRIPx Program Enable Voltage Hold time
VTRIPx Setup time
10
µs
10
µs
VTRIPx Hold (stable) time
10
µs
VTRIPx Program Enable Voltage Off time
(Between successive adjustments)
tVPO
1
ms
twc
VP
VTRIPx Write Cycle time
Programming Voltage
5
10
15
ms
V
10
VTRIPx Program Voltage accuracy
(Programmed at 25oC.)
Vta
Vtv
-100
+100
+25
mV
mV
VTRIP Program variation after programming (-40 - 85oC).
(Programmed at 25oC.)
-25
+10
Notes:
The above parameters are not 100% tested.
V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 25, Figure 26, Figure 27)
Symbol
Description
Condition
Min.
25
Typ.
50
Max.
75
Units
ms
POR1 = 0, POR0 = 0
POR1 = 0, POR0 = 1
POR1 = 1, POR0 = 0
POR1 = 1, POR0 = 1
50
100
200
300
150
300
450
ms
(5)
tPURST
Power-on Reset delay time
100
150
ms
ms
(26)(2)(5)
(5)
See (1)(2)(4)
tMRD
MR to V1RO propagation delay
MR pulse width
5
µs
tMRDPW
500
ns
V Vcc, V2, V3 to V1RO, V2RO,
V3RO propagation
delay (respectively)
(5)
tRPDx
20
µs
(5)
tFx
V1/Vcc, V2, V3 Fall Time
20
20
mV/µs
mV/µs
(5)
tRx
V1/Vcc, V2, V3 Rise Time
V1/Vcc for V1RO, V2RO, V3RO
(5)
VRVALID
1
V
Valid (3)
.
Notes: 1. See Figure 26 for timing diagram.
Notes: 2. See Figure 20 for equivalent load.
Notes: 3. This parameter describes the lowest possible V1/Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to
their inputs (V1/Vcc, V2, V3).
Notes: 4. From MR rising edge crossing VIH, to V1RO rising edge crossing VOH
Notes: 5. The above parameters are not 100% tested.
.
FN8209.0
24
March 10, 2005
X9523
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0
1
0
1
0000 0000
0000 0001
.
.
.
.
.
.
23
24
25
26
23
24
56
55
0001 0111
0001 1000
0011 1000
0011 0111
.
.
.
.
.
.
48
49
50
51
33
32
64
65
0010 0001
0010 0000
0100 0000
0100 0001
.
.
.
.
.
.
73
74
75
76
87
88
0101 0111
0101 1000
0111 1000
0111 0111
120
119
.
.
.
.
.
.
98
99
97
96
0110 0001
0110 0000
FN8209.0
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March 10, 2005
X9523
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
FN8209.0
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March 10, 2005
X9523
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0);
else if (tap_pos >99) return ((unsigned) 96);
/* set to min val */
/* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
FN8209.0
March 10, 2005
27
X9523
20 Ball BGA (X9523)
a
a
l
j
m
1
2
3
4
4
3
2
1
A
B
C
D
E
A
B
C
D
E
b
b
k
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die Orientation mark
d
c
Ball Matrix
e
4
3
2
V1/VCC
V1RO
NC
1
Side View (Bump Side Down)
A
B
C
D
E
RL2
V3
RW2
RH2
V3RO
MR
V2RO
V2
WP
SCL
SDA
NC
NC
RH1
VSS
RL1
RW1
Millimeters
Nom
Inches
Symbol
Min
Max
Min
Nom
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
2.524
3.794
0.654
0.444
0.210
0.316
2.554
3.824
0.682
0.457
0.225
0.326
0.5
2.584
3.854
0.710
0.470
0.240
0.336
0.09938
0.14938
0.02575
0.01748
0.00827
0.01244
0.10056
0.15056
0.02685
0.01799
0.00886
0.01283
0.01969
0.01969
0.10174
0.15174
0.02795
0.01850
0.00945
0.01323
Body Thickness
Ball Height
Ball Diameter
Ball Pitch – X Axis
Ball Pitch – Y Axis
j
k
0.5
Ball to Edge Spacing –
Distance Along X
l
0.497
0.882
0.527
0.912
0.557
0.942
0.01957
0.03473
0.02075
0.03591
0.02193
0.03709
Ball to Edge Spacing –
Distance Along Y
m
FN8209.0
March 10, 2005
28
X9523
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.252 (6.4)
.260 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(7.72)
(4.16)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
(1.78)
(0.42)
.019 (.50)
.029 (.75)
DetailA (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8209.0
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March 10, 2005
X9523
ORDERING INFORMATION
X9523
y
-
P
T
Preset (Factory Shipped) V
(x = 1,2,3)
Threshold Levels
TRIPx
Device
A = Optimized for 3.3V system monitoring †
B = Optimized for 5V system monitoring †
Temperature Range
I = Industrial -40°C to +85°C
Package
V20 = 20-Lead TSSOP
B20 = 20-Lead XBGA
XBGA PART MARK CONVENTION
20 Lead XBGA
X9523B20I-A
X9523B20I-B
Top Mark
XACO
XACS
†
For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8209.0
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March 10, 2005
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