IRFSL9N60A [INFINEON]
SMPS MOSFET; 开关电源MOSFET
| 型号： | IRFSL9N60A |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET |
| 文件： | 总8页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 91814A
SMPS MOSFET
IRFSL9N60A
HEXFET® Power MOSFET
Applications
VDSS
600V
Rds(on) max
ID
9.2A
l Switch Mode Power Supply ( SMPS )
l Uninterruptable Power Supply
l High speed power switching
l This device is only for through hole
application.
0.75Ω
Benefits
G D S
l Low Gate Charge Qg results in Simple
Drive Requirement
T O -26 2
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
9.2
5.8
A
37
PD @TC = 25°C
Power Dissipation
170
W
W/°C
V
Linear Derating Factor
1.3
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
5.0
V/ns
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Applicable Off Line SMPS Topologies:
l Active Clamped Forward
l Main Switch
Notes through ꢀ are on page 8
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1
12/23/98
IRFSL9N60A
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
RDS(on)
VGS(th)
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
600 ––– –––
––– ––– 0.75
V
Ω
V
VGS = 10V, ID = 5.5A
VDS = VGS, ID = 250µA
VDS = 600V, VGS = 0V
VDS = 480V, VGS = 0V, TJ = 150°C
VGS = 30V
2.0
––– 4.0
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
IGSS
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
5.5 ––– –––
Conditions
VDS = 25V, ID = 3.1A
ID = 9.2A
gfs
S
Qg
––– ––– 49
––– ––– 13
––– ––– 20
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 400V
VGS = 10V, See Fig. 6 and 13
–––
–––
–––
–––
13 –––
25 –––
30 –––
22 –––
VDD = 300V
ID = 9.2A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 9.1Ω
RD = 35.5Ω,See Fig. 10
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 1400 –––
––– 180 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
–––
7.1 –––
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 480V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 480V ꢀ
––– 1957 –––
–––
–––
49 –––
96 –––
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
290
9.2
Units
mJ
EAS
IAR
Avalanche Current
A
EAR
Repetitive Avalanche Energy
17
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
0.75
40
Units
RθJC
RθJA
Junction-to-Ambient (PCB Mounted,steady-state)
–––
°C/W
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
9.2
37
––– –––
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.5
––– 530 800
––– 3.0 4.4
V
TJ = 25°C, IS = 9.2A, VGS = 0V
ns
TJ = 25°C, IF = 9.2A
Qrr
ton
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFSL9N60A
100
10
1
100
10
1
VGS
15V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.7V
BOTTOM 4.7V
4.7V
4.7V
20µs PULSE WIDTH
T = 150 C
20µs PULSE WIDTH
°
°
J
T = 25 C
J
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
9.2A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
°
T = 150 C
J
10
°
T = 25 C
J
1
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
GS
0.1
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
4.0
5.0
V
6.0
7.0
8.0 9.0
10.0
T , Junction Temperature ( C)
J
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFSL9N60A
20
16
12
8
2400
I
D
= 9.2A
V
C
C
C
= 0V,
f = 1M Hz
G S
iss
= C
= C
= C
+ C
+ C
,
C
S HORTED
gs
gd
ds
gd
ds
400V
= 300V
= 120V
V
V
V
=
rss
oss
DS
DS
DS
2000
1600
1200
800
400
0
gd
C
C
iss
oss
4
C
rss
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
0
10
20
30
40
50
1
10
100
1000
Q
, Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
100
10
1
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10us
°
T = 150 C
J
100us
1ms
°
T = 25 C
1
J
10ms
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
V
= 0 V
GS
0.1
0.2
0.1
0.5
0.7
1.0
1.2
10
100
1000
10000
V
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFSL9N60A
RD
10.0
8.0
6.0
4.0
2.0
0.0
VDS
VGS
10V
D.U.T.
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
T
75
100
125
150
°
, Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
P
DM
t
1
0.02
t
2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFSL9N60A
600
500
400
300
200
100
0
I
D
TOP
4.1A
5.8A
BOTTOM 9.2A
1 5V
DRIVER
L
V
G
DS
D.U.T
R
+
V
D D
-
I
A
AS
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
25
50
75
100
125
150
°
Starting T , Junction Temperature ( C)
V
(BR)DSS
J
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Fig 12b. Unclamped Inductive Waveforms
Same Type as D.U.T.
50KΩ
.2µF
12V
Q
G
.3µF
+
10 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
6
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IRFSL9N60A
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRFSL9N60A
Package Outline
TO-262 Outline
Part Marking Information
TO-262
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
ꢀCoss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 6.8mH
as Coss while VDS is rising from 0 to 80% VDSS
RG = 25Ω, IAS = 9.2A. (See Figure 12)
ISD ≤ 9.2A, di/dt ≤ 50A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C
,
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Data and specifications subject to change without notice. 12/98
8
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