AS7C25512PFS32A-100BC [ISSI]
Standard SRAM, 512KX32, 4ns, CMOS, PBGA119, BGA-119;
| 型号： | AS7C25512PFS32A-100BC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 512KX32, 4ns, CMOS, PBGA119, BGA-119 静态存储器 |
| 文件： | 总2页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2001
Advanced Information
AS7C25512PFS32A
AS7C25512PFS36A
®
2.5V 512K × 32/36 pipeline burst synchronous SRAM
Features
• 100-pin TQFP package
• 119-Ball BGA (7 x 17 Ball Grid Array Package)
• Byte write enables
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Organization: 524,288 words x 32/36 bits
• Fast clock speeds to 200MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
• 2.5V I/O operation
*
• NTD™ pipeline architecture available
(AS7C25512NTD32A/ AS7C25512NTD36A)
- Dual-cycle deselect also available ( AS7C25512PFD32A/
AS7C25512PFD36A)
• Pentium® compatible architecture and timing
*
®
* Pentium is a registered trademark of Intel Corporation. NTD™ is a
• Asynchronous output enable control
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic Block Diagram:
LBO
Pin Arrangements:
CLK
ADV
ADSC
ADSP
CLK
CE
Burst logic
CLR
512K × 32/36
Memory
18
16
18
19
array
D
CE
CLK
Q
A[18:0]
Address
register
DQP /NC
b
DQP /NC
c
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
b
DQ
c
2
DQ
DQ
3
b
c
36/32
36/32
GWE
BWE
d
V
V
4
D
Q
Q
Q
Q
DDQ
DDQ
SSQ
c
DQ
d
V
V
5
SSQ
Byte write
BW
DQ
DQ
6
registers
CLK
b
DQ
b
DQ
c
7
DQ
b
DQ
c
8
D
DQ
DQ
9
DQ
b
c
SSQ
DDQ
c
c
V
BW
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
c
Byte write
V
registers
DDQ
DQ
DQ
DQ
c
CLK
D
b
DQ
b
DQ
V
FT
b
SS
BW
b
NC
VDD
ZZ
Byte write
V
DD
TQFP 14 × 20 mm
512K x 32A/36A
registers
NC
CLK
V
SS
DQ
DQ
DQ
d
V
V
a
d
D
DQ
DQ
a
a
4
BW
a
V
Byte write
DDQ
DDQ
SSQ
d
registers
V
SSQ
CLK
D
DQ
DQ
a
DQ
a
DQ
d
CE0
CE1
CE2
OE
Output
registers
CLK
Q
Q
DQ
a
DQ
d
Input
registers
CLK
DQ
DQ
Enable
register
a
d
SSQ
DDQ
d
V
V
V
CE
CLK
SSQ
V
DDQ
DQ
DQ
DQ
d
a
DQ
a
D
Enable
delay
DQP /NC
a
DQP /NC
d
Power
down
ZZ
register
CLK
OE
DATA [35:0]
DATA [31:0]
FT
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
-200
-166
6
-100
10
Units
Minimum cycle time
5
ns
MHz
ns
Maximum clock frequency
200
3.0
280
100
30
166
3.5
230
70
100
4.0
150
50
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
mA
mA
mA
Maximum CMOS standby current (DC)
30
30
10/3/01; v.0.9.1
Alliance Semiconductor
1 of 2
Copyright © Alliance Semiconductor. All rights reserved.
AS7C25512PFS32A
AS7C25512PFS36A
®
Pin Configuration
119 BGA Top View
1
2
3
A
4
5
A
6
A
A
A
7
ADSP
ADSC
VDD
NC
A
B
C
D
E
VDDQ
NC
A
VDDQ
NC
A
A
A
FT
A
A
A
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQd
DQd
VDDQ
DQd
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
VDD
A
DQpb DQb
CE0
OE
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
F
ADV
GWE
VDD
CLK
NC
G
H
J
K
L
BWE
A1
M
N
P
DQd DQpd
A0
R
T
U
NC
NC
A
VDD
A
NC
TMS
NC
ZZ
VDDQ
TDI
TCK
TDO
NC
VDDQ
Note: For P/N AS7C25512PFS32A, 4 of the I/O Pins must be left open (N.C.)
10/3/01; v.0.9.1
Alliance Semiconductor
2 of 2
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