AS7C25512PFS32A-225TQC [ISSI]
Standard SRAM, 512KX32, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C25512PFS32A-225TQC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 512KX32, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总21页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2002
Advance Information
AS7C25512PFS32A
AS7C25512PFS36A
®
2.5V 512K × 32/ 36 pipelined burst synchronous SRAM
Features
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Boundary scan using IEEE 1149.1 JTAG function
• NTD™1 pipelined architecture available
(AS7C251MNTD18A, AS7C25512NTD32A/
AS7C25512NTD36A)
• Organization: 524,288 words × 32 or 36 bits
• Fast clock speeds to 250MHz in LVTTL/ LVCMOS
• Fast clock to data access: 2.6/ 2.8/ 3/ 3.4 ns
• Fast OEaccess time: 2.6/ 2.8/ 3/ 3.4 ns
• Fully synchronous register-to-register operation
• Single register flow-through mode
• Single-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package and 165-ball BGA
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
LBO
CLK
ADV
CLK
CE
CLR
Burst logic
ADSC
ADSP
512K × 32/ 36
Memory
19
17
19
19
array
D
CE
CLK
Q
A[18:0]
Address
register
36/ 32
36/ 32
GWE
BWE
D
Q
Q
Q
Q
DQd
Byte write
registers
BW
d
CLK
D
DQc
BW
c
Byte write
registers
CLK
D
DQb
BW
b
Byte write
registers
CLK
D
DQa
4
BW
a
Byte write
registers
CLK
CE0
CE1
CE2
OE
Output
registers
CLK
D
Q
Input
registers
CLK
Enable
register
CE
CLK
D
Q
Enable
delay
Power
down
ZZ
register
CLK
36/ 32
DQ[a:d]
OE
FT
Selection guide
-250
4
-225
4.4
-200
5
-166
6
Units
ns
Minimum cycle time
Maximum clock frequency
250
2.6
450
160
70
225
2.8
200
3.0
400
130
70
166
3.4
350
120
70
MHz
ns
Maximum pipelined clock access time
Maximum operating current
425
150
70
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
1 of 21
Copyright © Alliance Semiconductor. All rights reserved.
AS7C25512PFS32A
AS7C25512PFS36A
®
Pin and ball assignment
100-pin TQFP - top view
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Ball assignment for 165-ball BGA for 512K x 36
1
2
3
4
5
6
7
8
9
10
A
11
NC
A
B
C
NC
A
CE0
BWc
BWd
BWb
BWa
CE2
CLK
BWE ADSC
GWE OE
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQPc
DQc
DQc
DQc
DQc
FT
A
CE1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
NC
V
V
V
V
V
SS
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
SS
SS
SS
SS
VDD
V
V
V
SS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQc
DQc
DQc
DQc
NC
D
E
F
SS
SS
V
V
V
V
SS
DD
SS
SS
V
V
V
V
SS
DD
SS
SS
V
G
H
J
V
V
V
SS
DD
SS
SS
V
V
V
V
SS
DD
SS
SS
DQd
DQd
DQd
DQd
DQPd
NC
DQd
DQd
DQd
DQd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDD
VDD
VDD
VDD
Vss
Vss
Vss
Vss
NC
TDI
TMS
V
V
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
A
SS
SS
K
L
M
N
P
V
V
SS
SS
V
V
SS
SS
V
NC
SS
V
A
V
V
SS
SS
SS
NC
A
A11
A01
TDO
TCK
A
R
LBO
NC
A
A
A
A
A
A
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
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AS7C25512PFS32A
AS7C25512PFS36A
®
Functional description
The AS7C25512PFS32A/ 36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as
524,288 words x 32/ 36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 4/ 4.4/ 5/ 6 ns with clock access times (t ) of 2.6/ 2.8/ 3/ 3.4 ns enable 250, 225, 200, and 166 MHz bus frequencies.
CD
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe
(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed
by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high.
Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With
LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low. This device operates in single-cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WEsignals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS32A/ 36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Input capacitance
I/ O capacitance
Symbol
Signals
Address and control pins
I/ O pins
Test conditions
IN = 0V
OUT = 0V
Max
5
Unit
pF
C
V
IN
C
V
7
pF
I/ O
12/ 2/ 02, v. 0.9.1
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AS7C25512PFS32A
AS7C25512PFS36A
®
Signal descriptions
Pin
CLK
A0–A19
I/ O Properties Description
I
I
CLOCK Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.
SYNC
SYNC
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
DQ[a,b,c,d] I/ O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE0
I
I
SYNC
SYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges
when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/ write.
Global write enable. Asserted low to write all 32/ 36 and 18 bits. When high, BWE and
BW[a:d] control write enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If
any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d]
are inactive, the cycle is a read cycle.
BW[a,b,c,d]
I
SYNC
OE
I
I
ASYNC Asynchronous output enable. I/ O pins are driven when OE is active and chip is in read mode.
Count mode. When driven high, count sequence follows Intel XOR convention. When driven
STATIC
LBO
low, count sequence follows linear convention. This signal is internally pulled high.
TDO
TDI
O
I
SYNC
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA
only).
TMS
TCK
I
I
SYNC
Test Clock
STATIC
Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the
falling edge of TCK.
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if
unused or for pipelined operation.
FT
ZZ
I
I
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
Write enable truth table (per byte)
Function
GWE BWE BWa
BWb
X
BWc BWd
L
H
H
H
H
H
X
L
L
L
H
L
X
L
X
L
X
L
Write All Bytes
L
Write Byte a
L
H
H
L
H
L
Write Byte c and d
H
X
H
H
X
X
H
X
H
Read
H
ꢀꢁꢂꢃꢄX = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
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AS7C25512PFS32A
AS7C25512PFS36A
®
Burst sequence table
Interleaved burst address
A1 A0 A1 A0 A1 A0 A1 A0
Linear burst address
A1 A0 A1 A0 A1 A0 A1 A0
1st Address
2nd Address
3rd Address
4th Address
0 0
0 1
1 0
1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
1st Address
2nd Address
3rd Address
4th Address
0 0
0 1
1 0
1 1
0 1
1 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
Synchronous truth table
2
CE01
CE1
CE2 ADSP ADSC ADV BWn
OE Address accessed
CLK
Operation
DQ
H
L
X
L
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
F
X
X
X
X
X
L
NA
NA
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Lto H
Lto H
L to H
L to H
L to H
L to H
Lto H
L to H
Lto H
Deselect
Deselect
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z3
Hi−Z
Hi−Z3
Hi−Z
Q
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
F
H
L
Begin read
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
F
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
F
H
L
Next
Hi−Z
Q
H
H
L
F
Current
Current
Next
F
H
L
Hi−Z
Q
F
L
F
H
L
Next
Hi−Z
Q
H
H
X
L
F
Current
Current
External
Next
F
H
X
X
X
X
X
Hi−Z
D4
T
T
T
T
T
X
H
X
H
X
X
X
X
H
H
H
H
D
L
Next
D
H
H
Current
Current
D
D
1 X = don’t care, L = low, H = high
2 See "Write enable truth table (per byte)," on page 4 for more information.
3 Q in flow-through mode.
4 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
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Alliance Semiconductor
5 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
TQFP and BGA thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/ W
°C/ W
1–layer
4–layer
θ
θ
JA
JA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/ JESD51
22
Thermal resistance
θ
8
°C/ W
(junction to top of case)1
JC
1 This parameter is sampled
Absolute maximum ratings
Parameter
Symbol
Min
–0.3
–0.3
–0.3
–
Max
Unit
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/ O pins)
Power dissipation
VDD, VDDQ
+3.6
V
V
V
VDD + 0.3
VDDQ + 0.3
1.8
IN
V
V
IN
Pd
IOUT
stg (TQFP)
W
mA
oC
oC
oC
Short circuit output current
Storage temperature (TQFP)
Storage temperature (BGA)
Temperature under bias
–
20
T
–65
–65
–65
+150
Tstg (BGA)
+125
Tbias
+135
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
Recommended operating conditions
Parameter
Supply voltage for inputs
Supply voltage for I/ O
Ground supply
Symbol
VDD
Min
2.375
2.375
0
Nominal
Max
2.625
2.625
0
Unit
V
2.5
2.5
0
VDDQ
Vss
V
V
12/ 2/ 02, v. 0.9.1
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AS7C25512PFS32A
AS7C25512PFS36A
®
DC electrical characteristics
Parameter
Input leakage current
Output leakage current
Sym
Conditions
Min
-2
Max
Unit
µA
µA
V
| ILI|
VDD = Max, OV < VIN < VDD
2
| ILO
|
OE≥ V , VDD = Max, OV < VOUT < VDDQ
-2
2
VDD+0.3
VDDQ+0.3
0.7
IH
Address and control pins
I/ O pins
1.7
1.7
-0.3
-0.3
1.7
–
Input high (logic 1) voltage
Input low (logic 0) voltage
V
IH
V
Address and control pins
I/ O pins
V
V
IL
0.7
V
Output high voltage
Output low voltage
V
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
–
V
OH
V
0.7
V
OL
I
operating conditions and maximum limits
DD
Parameter
Sym
ICC
ISB
Conditions
CE0 = V , CE1 = V , CE2 = V , f = fMax
-250 -225 -200 -166 Unit
,
IL
IH
IL
Operating power supply current
450
160
70
425
150
70
400
130
70
350
120
70
mA
IOUT = 0 mA
Deselected, f = fMax, ZZ < V
IL
Deselected, f = 0, ZZ < 0.2V,
all V ≤ 0.2V or ≥ (VDD, VDDQ) – 0.2V
ISB1
IN
Standby power supply current
mA
Deselected, f = f
,
Max
ISB2
ZZ ≥ (VDD, VDDQ
all V ≤ V or ≥ V
IH
)
– 0.2V,
30
30
30
30
IN
IL
12/ 2/ 02, v. 0.9.1
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AS7C25512PFS32A
AS7C25512PFS36A
®
Timing characteristics over operating range
–250
–225
–200
–166
Parameter
Clock frequency
Sym
fMax
tCYC
Min Max Min Max Min Max Min Max Unit Notes1
–
4
250
–
–
4.4
6.9
–
225
–
–
5
200
–
–
6
166 MHz
Cycle time (pipelined mode)
–
–
ns
ns
ns
Cycle time (flow-through mode)
Clock access time (pipelined mode)
tCYCF 6.5
–
–
7.5
–
–
8.5
–
tCD
–
2.6
2.8
3.0
3.4
Clock access time (flow-through
mode)
tCDF
–
6.5
–
6.9
–
7.5
–
8.5
ns
Output enable low to data valid
Clock high to output low Z
tOE
tLZC
tOH
–
2.6
–
–
2.8
–
–
3.0
–
–
3.4
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
2,3,4
2
Data output invalid from clock high
Output enable low to output low Z
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
–
tLZOE
–
–
–
–
2,3,4
2,3,4
2,3,4
Output enable high to output high Z tHZOE
Clock high to output high Z tHZC
Output enable high to invalid output tOHOE
–
2.6
2.6
–
–
2.8
2.8
–
–
3.0
3.0
–
–
3.4
3.4
–
–
–
–
–
0
0
0
0
Clock high pulse width
Clock low pulse width
tCH
tCL
1.5
1.5
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
–
1.8
1.8
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
–
1.8
1.8
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
–
2.1
2.2
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
5
5
–
–
–
–
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 19.
tAS
–
–
–
–
6
tDS
–
–
–
–
6
tWS
tCSS
tAH
tDH
tWH
tCSH
–
–
–
–
6,7
6,8
6
–
–
–
–
–
–
–
–
–
–
–
–
6
–
–
–
–
6,7
6,8
6
–
–
–
–
tADVS 1.2
tADSPS 1.2
tADSCS 1.2
tADVH 0.3
tADSPH 0.3
tADSCH 0.3
–
–
–
–
–
–
–
–
6
–
–
–
–
6
–
–
–
–
6
–
–
–
–
6
–
–
–
–
6
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
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IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the
critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. It uses JEDEC-standard 2.5V I/ O logic levels.
The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Disabling the JTAG feature
If the JTAG function is not being implemented, its pins/ balls can be left unconnected. At power-up, the device will come up in a reset state
which will not interfere with the operation of the device.
TAP controller state diagram
TAP controller block diagram
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Test access port (TAP)
Test clock (TCK)
The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ ball unconnected if the
TAP is not used. The pin/ ball is pulled up internally, resulting in a logic high level.
12/ 2/ 02, v. 0.9.1
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Test data-in (TDI)
The TDI pin/ ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register,
see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test data-out (TDO)
The TDO output pin/ ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (V ) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and can
DD
be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP registers
Registers are connected between the TDI and TDO pins/ balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ ball on the rising edge of TCK. Data is
output on the TDO pin/ ball on the falling edge of TCK.
Instruction register
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/
balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the
controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation
of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit
register that can be placed between the TDI and TDO pins/ balls. This allows data to be shifted through the SRAM with minimal delay. The
bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/ balls on the SRAM. The x36 configuration has a 72-bit-long
register and the x18 configuration has a 53-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/ O ring when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/ balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/ RELOAD, and SAMPLE Z
instructions can be used to capture the contents of the I/ O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.
Identification (ID) register
The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with
a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.
12/ 2/ 02, v. 0.9.1
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TAP instruction set
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of
these instructions are reserved and should not be used.
Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot
preload the I/ O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD. Instead, it performs a capture of the I/ O ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During
this state, instructions are shifted through the instruction register through the TDI and TDO pins/ balls. To execute the instruction once it is
shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP
controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/ PRELOAD instruction has been loaded. Unlike the SAMPLE/ PRELOAD instruction, EXTEST places the SRAM
outputs in a high-Z state.
EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.
IDCODE
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register
between the TDI and TDO pins/ balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/ balls when the TAP controller is in
a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/ PRELOAD
When the SAMPLE/ PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of
data on the inputs and bidirectional pins/ balls is captured in the boundary scan register. Note that the SAMPLE/ PRELOAD is a 1149.1
mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore, is not fully
1149.1 compliant.
Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output
can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there
is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the
t
t
TAP controller’s capture setup plus hold time ( CS plus CH). The SRAM clock input might not be captured correctly if there is no way in a
design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is possible to capture all other signals and ignore
the value of the CK and CK# captured in the bounder scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/
PRELOAD instruction will have the same effect as the Pause-DR command.
BYPASS
The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between
TDI and TDO.
12/ 2/ 02, v. 0.9.1
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Reserved
Do not use a reserved instruction. These instructions are not implemented but are reserved for future use.
TAP timing diagram
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TAP AC electrical characteristics
o
o
For notes 1 and 2, +10 C ≤ T ≤ +110 C and +2.4V ≤ V ≤ +2.6V.
J
DD
Description
Symbol
Min Max Units
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
Output Times
tTHTH
fTF
tTHTL
tTLTH
100
ns
10 MHz
ns
40
40
ns
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
Setup Times
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
20
ns
ns
ns
10
10
TMS setup
tMVTH
1
tCS
10
10
ns
ns
Capture setup
Hold Times
TMS hold
tTHMX
tCH1
10
10
ns
ns
Capture hold
t
t
1 CS and CH refer to the setup and hold time requirements of latching data
from the boundary scan register.
2
Test conditions are specified using the load in the figure TAP AC output
load equivalent.
12/ 2/ 02, v. 0.9.1
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TAP AC test conditions
Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V
TAP AC output load equivalent
ꢅ#ꢈꢗ;
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing refer ence levels. . . . . . . . . . 1.25V
Output reference levels . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage. . . . 1.25V
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TAP DC electrical characteristics and operating conditions
o
o
(+10 C < T < +110 C and +2.4V < V < +2.6V unless otherwise noted)
J
DD
Description
Conditions
Symbol
Min
Max
VDD + 0.3
0.7
Units
V
Notes
1, 2
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
V
1.7
-0.3
-5.0
IH
V
IL
V
1, 2
0V ≤ V ≤ VDD
IL
5.0
µA
IN
I
Outputs disabled,
Output leakage current
ILO
-5.0
5.0
µA
0V ≤ V ≤ VDDQ(DQx)
IN
Output low voltage
Output low voltage
Output high voltage
Output high voltage
IOLC = 100µA
V
0.2
0.7
V
V
V
V
1
1
1
1
OL1
I
OLT = 2mA
IOHS = -100µA
OHT = -2mA
V
OL2
V
OH1
2.1
1.7
I
V
OH2
1. All voltage referenced to V (GND).
SS
t
2. Overshoot: V (AC) ≤ V + 1.5V for t ≤ KHKH/ 2
IH
DD
t
Undershoot:V (AC) ≥ -0.5 for t ≤ KHKH/ 2
IL
Power-up: V ≤ +2.6V and V ≤ 2.4V and V ≤ 1.4V for t ≤ 200ms
DDQ
IH
DD
During normal operation, V
must not exceed V . Control input signals (such as LD, R/ W, etc.) may not have pulsed widths less than
DD
DDQ
t
(Min) or operate at frequencies exceeding f (Max).
KHKL
KF
12/ 2/ 02, v. 0.9.1
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Identification register definitions
Instruction field
512K x 36
Description
Reserved for version number.
Revision number (31:28)
Device depth (27:23)
Device width (22:18)
Device ID (17:12)
xxxx
xxxxx/ xxxxx Defines the depth of 512K words.
xxxxx/ xxxxx Defines the width of x32 or x36 bits.
xxxxxx
Reserved for future use.
JEDEC ID code (11:1)
ID register presence indicator (0)
00000110100 Allows unique identification of SRAM vendor.
1
Indicates the presence of an ID register.
Scan register sizes
Register name
Instruction
Bypass
Bit size
3
1
ID
32
Boundary scan
x18:53
x36:72
Instruction codes
Instruction
Code
Description
Captures I/ O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.
EXTEST
000
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
IDCODE
001
Captures I/ O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high-Z state.
SAMPLE Z
Reserved
010
011
Do not use. This instruction is reserved for future use.
Captures I/ O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
SAMPLE/ PRELOAD
100
Reserved
Reserved
101
110
Do not use. This instruction is reserved for future use.
Do not use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
111
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165-ball BGA boundary scan order (x36)
Bit # s
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Signal Name
CLK
CE2
Ball ID
6B
6A
5B
5A
4A
4B
3B
3A
2A
2B
1C
1D
1E
1F
Bit # s
1
Signal Name
SA
Ball ID
11P
6N
2
SA
BWa
BWb
BWc
BWd
CE1
3
SA
8P
4
SA
8R
5
SA
9R
6
SA
9P
7
SA
10P
10R
11R
11N
11M
11L
11K
11J
CE0
8
SA
SA
9
SA
SA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
FT
1G
2D
2E
2F
10M
10L
10K
10J
2G
1H
1J
11H
11G
11F
11E
11D
10G
10F
10E
10D
11C
10A
10B
9A
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
SA
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
LBO
SA
1K
1L
1M
2J
2K
2L
2M
1N
1R
3P
SA
ADV
ADSP
ADSC
OE
SA
3R
4R
4P
9B
SA
8A
SA
8B
SA1
6P
BWE
GWE
7A
SA2
6R
7B
12/ 2/ 02, v. 0.9.1
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Key to switching waveforms
Rising input
Falling input
Undefined or don’t care
Timing waveform of read cycle
t
CYC
t
t
CL
CH
CLK
t
ADSPS
ADSPH
t
ADSP
ADSC
t
ADSCS
ADSCH
t
LOAD NEW ADDRESS
t
AS
t
AH
A1
A2
A3
Address
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
ADV inserts wait states
t
CD
t
t
HZC
HZOE
t
OH
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
Q(A1)
D
OUT
(pipelined
mode)
tOE
t
LZOE
Q(A3Ý11)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A1)
D
OUT
(flow-through
mode)
t
HZC
Read Suspend Read
Burst
Read
2Ý01
Burst
Read
Suspend
Read
Burst
Read
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
) Q(A )
Q(A1)
Read
Q(A2)
DSEL
2Ý10
) Q(A
2Ý10
) Q(A
2Ý11
Q(A1)
Q(A
) Q(A
)
Q(A
) Q(A
Note: Ý = XOR when LBO = high/ no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
16 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Timing waveform of write cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
t
ADSCS
t
ADSCH
ADSC
ADSC LOADS NEW ADDRESS
t
AS
t
AH
A1
A2
A3
Address
t
WS
t
WH
BWE
BW[a:d]
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
ADV SUSPENDS BURST
t
ADVH
ADV
OE
t
DS
t
DH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
D(A3Ý01)
D(A3Ý10)
Data In
ADV
Burst
Write
Read Q(A1) Suspend
Read
Q(A2)
Suspend
Write
ADV
Burst
Write
Suspend
Write
ADV
Burst
Write
ADV
Burst
Write
Write
3
D(A )
Burst
Write
3Ý01
D(A )
Write
D(A1)
2
2Ý01
D(A )
D(A
)
3Ý10
D(A
)
2Ý01
2Ý10
2Ý11
Q(A )
D(A
)
Q(A
)
Note: Ý = XOR when LBO = high/ no connect; Ý = ADD when LBO = low.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
17 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Timing waveform of read/ write cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
ADSPH
t
ADSP
t
AS
t
AH
A2
A3
A1
Address
t
WS
t
WH
GWE
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
t
DH
DS
D
IN
D(A2)
t
OE
t
LZC
t
OH
t
t
LZOE
HZOE
t
CD
D
OUT
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
(pipelined mode)
t
CDF
D
Q(A1)
Q(A3Ý11)
Q(A3Ý01)
Q(A3Ý10)
OUT
(flow-through mode)
DSEL
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
D(A )
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
Suspend
Read
2
3Ý11
)
Q(A
3Ý01
3Ý10
3Ý11
Q(A )
D(A
)
Q(A
)
Note: Ý = XOR when LBO = high/ no connect; Ý = ADD when LBO = low.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
18 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
AC test conditions
• Output load: For t , t
, t
, t , see Figure C. For all others, see Figure B.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+2.5V
319Ω/1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
+3.0V
D
V = V / 2
L DDQ
OUT
5 pF*
90%
10%
90%
10%
353Ω/1538Ω
30 pF*
GND
*including scope
and jig capacitance
GND
Figure C: Output load(B)
Figure A: Input waveform
Figure B: Output load (A)
Notes
1
2
3
4
5
6
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
is less than t
, and t
LZOE
is less than t at any given temperature and voltage.
HZC LZC
HZOE
CH
is measured as high if above VIH, and t is measured as low if below VIL.
CL
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to GWE, BWE, and BW[a:d].
7
8
Chip select refers to CE0, CE1, and CE2.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
19 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
0.05
Max
0.15
A1
A2
b
1.35
1.45
b
e
0.22
0.38
c
0.09
0.20
D
E
13.90
19.90
14.10
20.10
e
0.65 nominal
Hd
He
L
15.90
21.90
0.45
16.10
22.10
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
α
L1
L
A1 A2
165-ball BGA (ball grid array)
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12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
20 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Ordering information
Package & Width
250 MHz
225 MHz
200 MHz
166 MHz
AS7C25512PFS32A-
225TQC
AS7C25512PFS32A-
200TQC
AS7C25512PFS32A-
166TQC
AS7C25512PFS32A-
250TQC
TQFP x32
TQFP x36
BGA x32
AS7C25512PFS32A-
225TQI
AS7C25512PFS32A-
200TQI
AS7C25512PFS32A-
166TQI
AS7C25512PFS36A-
225TQC
AS7C25512PFS36A-
200TQC
AS7C25512PFS36A-
166TQC
AS7C25512PFS36A-
250TQC
AS7C25512PFS36A-
225TQI
AS7C25512PFS36A-
200TQI
AS7C25512PFS36A-
166TQI
AS7C25512PFS32A-
225BC
AS7C25512PFS32A-
200BC
AS7C25512PFS32A-
166BC
AS7C25512PFS32A-
250BC
AS7C25512PFS32A-
225BI
AS7C25512PFS32A-
200BI
AS7C25512PFS32A-
166BI
AS7C25512PFS36A-
225BC
AS7C25512PFS36A-
200BC
AS7C25512PFS36A-
166BC
AS7C25512PFS36A-
250BC
BGA x36
AS7C25512PFS36A-
225BI
AS7C25512PFS36A-
200BI
AS7C25512PFS36A-
166BI
Part numbering guide
AS7C
25
512
PF
S
32/ 36
A
–XXX
TQ or B
C/ I
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 25 = 2.5V
3. Organization: 512 = 512K
4. Pipelined/ flow-through mode (each device works in both modes)
5. Deselect: S = single cycle deselect
6. Organization: 32 = x 32; 36 = x 36
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP, B = BGA
10. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
21 of 21
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and
product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no
responsibility for any errors that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to
change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this
product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to
the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as
express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and
Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights
of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance
against all claims arising from such use.
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