AS7C33128PFS16B-133TQC [ISSI]
Standard SRAM, 128KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C33128PFS16B-133TQC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 128KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总14页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS7C33128PFS16B
AS7C33128PFS18B
October 2003
®
3.3V 128K × 16/18 pipeline burst synchronous SRAM
Features
•Byte write enables
•Multiple chip enables for easy expansion
•3.3V core power supply
•2.5V or 3.3V I/O operation with separate V
•Organization: 131,072 words × 16 or 18 bits
•Fast clock speeds to 200 MHz in LVTTL/LVCMOS
•Fast clock to data access: 3.0/3.5/4.0 ns
•Fast OE access time: 3.0/3.5/4.0 ns
•Fully synchronous register-to-register operation
•“Flow-through” or “Pipeline” mode
•Single-cycle deselect
DDQ
•30 mW typical standby power in power down mode
•NTD™1 pipeline architecture available
(AS7C33128NTD16B/AS7C33128NTD18B)
Dual-cycle deselect also available (AS7C33128PFD16B/
AS7C33128PFD18B)
•Pentium® compatible architecture and timing
•Asynchronous output enable control
•Economical 100-pin TQFP package
1. Pentium® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
1
Pin arrangement
Logic block diagram
LBO
CLK
ADV
CLK
CS
A
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Burst logic
128K × 16/18
Memory
array
ADSC
ADSP
NC
NC
V
2
CLR
3
V
4
DDQ
SSQ
NC
DDQ
17
Q
D
A[16:0]
V
V
5
SSQ
NC
Address
6
17
CS
15
17
register
DQpa/NC
DQa
DQa
NC
7
CLK
DQb
DQb
8
9
V
DDQ
V
10
11
SSQ
SSQ
16/18 16/18
V
V
DDQ
DQa
DQa
VSS
NC
DQb 12
DQb 13
FT 14
GWE
D
Q
BytDeQWb rite
BW
b
TQFP 14 × 20mm
registers
V
15
NC 16
17
DD
BWE
BW
CLK
V
DD
ZZ
V
D
Q
SS
BytDeQWa rite
registers
DQa
DQa
DQb 18
DQb 19
2
a
V
SSQ
V
20
21
DDQ
DDQ
CLK
V
V
SSQ
CE0
CE1
CE2
DQa
DQa
NC
DQb 22
DQb 23
OE
DEnable
Q
Input
Output
registers
register
DQpb/NC
24
registers
NC
NC 25
CE
CLK
CLK
CLK
V
DDQ
V
26
27
SSQ
SSQ
V
V
DDQ
DEnable
Q
NC
NC
NC
NC 28
NC 29
NC 30
Power
down
delay
ZZ
register
CLK
OE
16/18
DQ [a,b]
FT
Note: pins 24, 74 are NC for ×16.
Selection guide
–200
5
–166
6
–133
7.5
133
4
Units
ns
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
200
3
166
3.5
350
100
30
MHz
ns
400
120
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
10/29/03; v.1.0
Alliance Semiconductor
P. 1 of 14
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128PFS16B
AS7C33128PFS18B
®
Functional description
The AS7C33128PFS16B and AS7C33128PFS18B are high performance CMOS 2 Mbit synchronous Static Random
Access Memory (SRAM) devices organized as 131,072 words × 16 or 18 bits and incorporate a pipeline for highest
frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is
™1
suited for ASIC, DSP (TMS320C6X), and PowerPC -based systems in computing, datacom, instrumentation, and
telecommunications systems.
Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t ) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus
CD
frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two
ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV)
allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the
on-chip address register. When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer
is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers
by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive
edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock
edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both
address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH,
burst operations use a Pentium® count sequence. With LBO driven LOW the device uses a linear count sequence
suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global
write enable GWE writes all 16/18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when
GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn
signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output
buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register
when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are
sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated
with ADSC and ADSP follow.
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33128PFS16B and AS7C33128PFS18B operate from a 3.3V supply. I/Os use a separate power supply that
can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging.
1. PowerPC™ is a trademark International Business Machines Corporation
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Alliance Semiconductor
P. 2 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
Signals
Address and control pins
I/O pins
Test conditions
= 0V
Max
5
7
Unit
pF
C
V
IN
IN
C
V
= V = 0V
OUT
pF
I/O
IN
Write enable truth table (per byte)
GWE
BWE
BWn
X
WEn
T
L
H
H
H
X
L
H
L
L
T
X
F*
*
H
F
Key: *= valid read; n = a,b X = Don’t Care, L = Low, H = High, T=True, F=False; WE, WEn = internal write signal.
Burst Order
Interleaved Burst Order
Linear Burst Order
LBO=0
LBO=1
Starting Address
First increment
Second increment
Third increment
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
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Alliance Semiconductor
P. 3 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
Signal descriptions
Signal
CLK
I/O
I
Properties
CLOCK
Description
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are
asserted.
Data. Driven as output when the chip is enabled and OE is active.
A0–A16
DQ[a,b]
I
SYNC
I/O SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is
active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous
Truth Table for more information.
CE0
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively.
Sampled on clock edges when ADSC is active or when CE0 and ADSP are
active.
Address strobe (processor). Asserted LOW to load a new address or to
enter standby mode.
CE1, CE2
ADSP
I
I
SYNC
SYNC
Address strobe (controller). Asserted LOW to load a new address or to
enter standby mode.
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH,
BWE and BW[a,b] control write enable.
ADSC
ADV
GWE
I
I
I
SYNC
SYNC
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of
BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE =
HIGH and BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and
BWE = LOW the cycle is a write cycle. If all BW[a,b] are inactive, the cycle
is a read cycle.
BWE
I
I
SYNC
SYNC
BW[a,b]
Asynchronous output enable. I/O pins are driven when OE is active and
the chip is in read mode.
OE
I
I
ASYNC
STATIC
Selects Burst mode. When tied to V or left floating, device follows interleaved
DD
LBO
Burst order. When driven Low, device follows linear Burst order. This signal is
internally pulled High.
Selects Pipeline or Flow-through mode.When tied to V or left floating, enables
DD
FT
I
I
STATIC
ASYNC
Pipeline mode. When driven Low, enables single register Flow-through mode.
This signal is internally pulled High.
Snooze. Places device in low power mode; data is retained. Connect to
GND if unused.
ZZ
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
Symbol
, V
Min
–0.5
–0.5
–0.5
–
Max
+4.6
+ 0.5
DD
Unit
V
V
V
W
V
DD
DDQ
V
V
V
IN
V
+ 0.5
IN
DDQ
P
1.8
D
DC output current
Storage temperature (plastic)
Temperature under bias
I
T
T
–
–65
–65
50
+150
+135
mA
°C
°C
OUT
stg
bias
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
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P. 4 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
Synchronous truth table
Address
accessed
1
CE0
H
L
L
L
L
L
L
L
L
X
X
X
CE1
X
L
L
X
CE2 ADSP ADSC ADV WEn
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
CLK
L to H Deselect
L to H Deselect
L to H Deselect
L to H Deselect
L to H Deselect
Operation
DQ
X
X
X
H
H
L
X
L
H
L
H
L
L
X
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
NA
NA
NA
NA
NA
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
X
2
2
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
External
External
External
External
Next
L to H Begin read
L to H Begin read
L to H Begin read
L to H Begin read
L to H Cont. read
L to H Cont. read
L to H Suspend read
L to H Suspend read
L to H Cont. read
L to H Cont. read
L to H Suspend read
L to H Suspend read
L to H Begin write
L to H Cont. write
L to H Cont. write
L to H Suspend write
L to H Suspend write
L
L
X
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Next
H
H
L
Current
Current
Next
X
H
H
H
H
L
X
H
X
L
Next
H
H
X
L
L
H
H
Current
Current
External
Next
Next
Current
Current
H
X
X
X
X
X
Hi−Z
3
D
D
D
D
D
H
Key: X = Don’t Care, L = Low, H = High.
1See “Write enable truth table” on page 3 for more information.
2
Q in flow through mode
For write operation following a READ,
3
Recommended operating cOoEnmdusittbieoHnIGsH before the input data set up time and held HIGH throughout the input hold time.
Parameter
Symbol
Min
3.135
0.0
3.135
0.0
Nominal
Max
3.6
0.0
3.6
0.0
2.9
0.0
Unit
V
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
DD
Supply voltage
V
V
V
SS
V
DDQ
3.3V I/O supply voltage
2.5V I/O supply voltage
V
SSQ
V
2.35
0.0
DDQ
V
V
SSQ
V
2.0
–0.5
V
+ 0.3
DD
IH
V
2
V
0.8
+ 0.3
IL
1
Input voltages
V
2.0
–0.5
V
DDQ
IH
V
2
V
0.8
IL
Ambient operating
temperature
T
0
–
70
°C
A
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 VIL min = –2.0V for pulse width less than 0.2 × tRC
.
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Alliance Semiconductor
P. 5 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
TQFP thermal resistance
Description
Conditions
Symbol
Typical
46
Units
°C/W
Thermal resistance
(junction to ambient)
θ
θ
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
1
JA
Thermal resistance
(junction to top of case)
2.8
°C/W
1
JC
1 This parameter is sampled.
DC electrical characteristics
–200
–166
–133
Parameter
Symbol
Test conditions
Min Max Min Max Min Max
Unit
Input leakage
current
Output leakage
current
|I |
V
= Max, V = GND to V
–
–
2
2
–
–
2
2
–
–
2
2
µA
1
LI
DD
IN
DD
OE ≥ V , V = Max,
IH DD
V
|I
|
µA
LO
= GND to V
OUT
DD
CE0 = V , CE1 = V
, CE2 =
IL
IH
Operating power
supply current
2
I
V ,
–
400
-
350
–
325
mA
CC
IL
f = f
, I
= 0 mA
Max OUT
I
I
Deselected, f = f
Deselected, f = 0, ZZ ≤ 0.2V
, ZZ ≤ V
IL
–
–
120
30
–
–
100
30
–
–
90
30
SB
Max
SB1
Standby power
supply current
all V ≤ 0.2V or ≥ V – 0.2V
IN
DD
mA
V
Deselected, f = f
0.2V
, ZZ
≥
V
–
Max
DD
I
–
30
–
30
–
30
SB2
All V ≤ V or ≥ V
IN
IL
IH
V
V
I
I
= 8 mA
= –4 mA
–
2.4
0.4
–
–
2.4
0.4
–
–
2.4
0.4
–
OL
OL
Output voltage
OH
OH
1 LBO pin has an internal pull-up and input leakage = ±10 µA.
2 ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
–200
–166
–133
Parameter
Symbol
Test conditions
Min Max Min Max Min Max Unit
Output leakage
current
OE >VIH, VDD = Max,
VOUT = GND to VDD
|ILO
|
–1
1
–1
1
–1
1
µA
V
VOL
VOH
IOL = 2 mA
–
0.7
–
–
0.7
–
–
0.7
–
Output voltage
IOH = –2 mA
1.7
1.7
1.7
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Alliance Semiconductor
P. 6 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
Timing characteristics over operating range
–200
–166
–133
1
Parameter
Clock frequency
Sym
Min Max Min
Max
166
–
Min
–
Max
133
–
Unit
MHz
ns
ns
ns
Notes
f
t
t
t
–
5
200
–
–
–
6
9
–
Max
Cycle time (pipelined mode)
7.5
12
–
CYC
CYCF
CD
Cycle time (flow-through mode)
Clock access time (pipelined mode)
7.5
–
–
3.5
–
4.0
3.0
Clock access time (flow-through
mode)
t
–
6.5
–
8.0
–
10
ns
CDF
Output enable LOW to data valid
Clock HIGH to output Low Z
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
Clock HIGH pulse width
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
–
0
1.5
0
–
3.0
–
–
–
0
1.5
0
–
3.5
–
–
–
0
1.5
0
–
4.0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE
2,3,4
2
2,3,4
2,3,4
2,3,4
LZC
OH
–
–
–
LZOE
HZOE
HZC
OHOE
CH
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4.0
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
–
0
–
0
2.2
2.2
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
5
5
6
Clock LOW pulse width
CL
Address setup to clock HIGH
Data setup to clock HIGH
AS
6
DS
Write setup to clock HIGH
6,7
6,8
6
WS
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV setup to clock HIGH
CSS
AH
6
DH
6,7
6,8
6
6
6
6
6
6
WH
CSH
ADVS
ADSPS
ADSCS
ADVH
ADSPH
ADSCH
ADSP setup to clock HIGH
ADSC setup to clock HIGH
ADV hold from clock HIGH
ADSP hold from clock HIGH
ADSC hold from clock HIGH
–
–
–
–
–
–
1 See “Notes” on page 11..
10/29/03; v.1.0
Alliance Semiconductor
P. 7 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
tAS
tAH
LOAD NEW ADDRESS
A3
A1
A2
Address
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tCD
tHZOE
tOH
ADV INSERTS WAIT STATES
tHZC
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
DOUT
(pipelined mode)
tOE
tLZOE
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)
DOUT
(flow-through mode)
tHZC
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:b] is don’t care.
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Alliance Semiconductor
P. 8 of 14
AS7C33128PFS16B
AS7C33128PFS18B
®
Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
A1
A2
A3
Address
tWS
tWH
BWE
BWa,b
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV SUSPENDS BURST
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Data In
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
10/29/03; v.1.0
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AS7C33128PFS16B
AS7C33128PFS18B
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Timing waveform of read/write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
A2
A3
A1
Address
tWS
tWH
GWE
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDS
tDH
D(A2)
tHZOE
DIN
tOH
tLZC
tCD
Q(A1)
tLZOE
tOE
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
DOUT
(pipeline mode)
tCDF
Q(A3Ý11)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
DOUT
(flow-through mode)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
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AS7C33128PFS16B
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AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure
C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z0 = 50Ω
50
Ω
DOUT
353Ω / 1538Ω
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
90%
10%
90%
10%
5 pF*
30 pF*
GND
*including scope
and jig capacitanc
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
,
BWE
,
BW[a,b].
CE2
Chip select refers to CE0
,
CE1
,
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Package Dimensions
100-pin quad flat pack (TQFP)
Hd
D
c
α
b
e
L1
L
A1 A2
He
E
TQFP
Min
Max
A1
A2
b
0.05
0.15
1.35
1.45
0.22
0.38
c
0.09
0.20
D
13.90
19.90
14.10
20.10
E
e
0.65 nominal
Hd
He
L
15.85
21.80
0.45
16.15
22.20
0.75
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
10/29/03; v.1.0
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AS7C33128PFS16B
AS7C33128PFS18B
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Ordering information
Package
TQFP
Width
x16
–200 MHz
–166 MHz
–133 MHz
AS7C33128PFS16B-200TQC AS7C33128PFS16B-166TQC AS7C33128PFS16B-133TQC
AS7C33128PFS16B-200TQI AS7C33128PFS16B-166TQI AS7C33128PFS16B-133TQI
AS7C33128PFS18B-200TQC AS7C33128PFS18B-166TQC AS7C33128PFS18B-133TQC
AS7C33128PFS18B-200TQI AS7C33128PFS18B-166TQI AS7C33128PFS18B-133TQI
TQFP
x16
TQFP
x18
TQFP
x18
Part numbering guide
AS7C
33
128
PF
S
16/18
B
–XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM Prefix
2.Operating voltage: 33=3.3V
3.Organization: 128=128K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 16=x16; 18=x18
7.Production version: B= product revision
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
10/29/03; v.1.0
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Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33128PFS16B-18B
Document Version: v.1.0
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
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