AS7C332MFT18A-65TQCN [ISSI]
Standard SRAM, 2MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100;
| 型号： | AS7C332MFT18A-65TQCN |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 2MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100 静态存储器 |
| 文件： | 总23页 (文件大小：565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2004
AS7C332MFT18A
®
3.3V 2M × 18 Flow-through synchronous SRAM
Features
• Organization: 2,097152 words × 18 bits
• Fast clock to data access: 6.5/7.5/8.5 ns
• Fast OE access time: 3.5/3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package and 165-ball BGA
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Boundary scan using IEEE 1149.1 JTAG function
1
• NTD™ pipelined architecture available
(AS7C332MNTD18A, AS7C331MNTD32A/
AS7C331MNTD36A)
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their
respective owners.
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
Burst logic
2M x 18
CLR
Memory
array
21 19
21
21
Q
D
A[20:0]
Address
CS
register
CLK
18
18
2
GWE
BWb
D
DQb
Q
Byte Write
registers
BWE
BWa
CLK
D
Q
DQa
Byte Write
registers
CLK
CE0
CE1
OE
Output
D
Q
Q
Input
registers
Enable
register
CE
CLK
CE2
registers
CLK
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
OE
18
DQ[a,b]
Selection guide
-65
7.5
-75
8.5
-85
10
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6.5
7.5
8.5
270
130
110
ns
310
140
110
290
130
110
mA
mA
mA
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C332MFT18A
®
Pin and ball assignment
100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
NC
NC
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
NC
VSSQ
VDDQ
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
VSSQ
NC
NC
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
NC
VDD
NC
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
TQFP 14 x 20mm
VSSQ
VDDQ
27
28
29
30
NC
NC
NC
NC
NC
NC
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AS7C332MFT18A
®
Ball assignment for 165-ball BGA for 2M X 18
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE0
BWb
NC
CE2
BWE
ADSC
ADV
A
A
A
B
C
D
E
F
NC
NC
A
CE1
NC
BWa
CLK
GWE
OE
ADSP
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQb
DQb
DQb
DQb
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
NC
VDD
VDD
VDD
VDD
NC
NC
G
H
J
NC
V
NC
NC
SS
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
NC
NC
NC
A
V
V
V
V
V
Vss
Vss
Vss
Vss
NC
V
NC
DDQ
DDQ
DDQ
DDQ
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
NC
K
L
M
N
P
NC
NC
V
A
V
NC
DDQ
SS
SS
DDQ
1
A
A
TDI
TMS
A1
TDO
TCK
A
A
A
1
A
LBO
A
A0
A
A
A
A
R
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
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AS7C332MFT18A
®
Functional description
The AS7C332MFT18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as
2,097152 words × 18 bits.
Fast cycle times of 7.5/8.5/10 ns with clock access times (tCD) of 6.5/7.5/8.5 ns. Three chip enable (CE) inputs permit easy memory
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The
burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for
the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With
LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count
sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18
bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented
internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP
follow.
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C332MFT18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Test conditions
VIN = 0V
Min
Max
Unit
pF
-
-
5
7
CI/O
VOUT = 0V
pF
TQFP and BGA thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
θJA
θJA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
22
Thermal resistance
θJC
8
°C/W
(junction to top of case)1
1 This parameter is sampled
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AS7C332MFT18A
®
Signal descriptions
Description
Pin
CLK
I/O Properties
I
I
CLOCK
SYNC
SYNC
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
A,A0,A1
DQ[a,b]
I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE0
I
I
SYNC
SYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write
enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,
the cycle is a read cycle.
BW[a,b]
I
SYNC
OE
I
I
ASYNC
STATIC
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
LBO
TDO
TDI
O
I
SYNC
SYNC
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
TMS
I
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only).
Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
TCK
I
Test Clock
ZZ
I
-
ASYNC
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects
NC
Write enable truth table (per byte)
Function
GWE BWE
BWa
X
BWb
X
L
H
H
H
H
H
X
L
L
L
H
L
Write All Bytes
L
L
Write Byte a
Write Byte b
L
H
H
L
X
X
Read
H
H
Key: X = don’t care, L = low, H = high, n = a, b; BWE
,
BWn = internal write signal.
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AS7C332MFT18A
®
Burst sequence table
Interleaved burst address
A1 A0 A1 A0 A1 A0 A1 A0
Linear burst address
A1 A0 A1 A0 A1 A0 A1 A0
1st Address
2nd Address
3rd Address
4th Address
1st Address
0 0
0 1
1 0
1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
0 0
0 1
1 0
1 1
0 1
1 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
2nd Address
3rd Address
4th Address
Synchronous truth table
[2]
CE01
H
L
CE1
X
L
CE2
X
X
X
H
H
L
ADSP ADSC ADV WRITE
OE
Address accessed
NA
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
L
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
NA
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
H
L
Next
Hi−Z
Q
H
H
L
Current
Current
Next
H
L
Hi−Z
Q
L
H
L
Next
Hi−Z
Q
H
H
X
L
Current
Current
External
Next
H
X
X
X
X
X
Hi−Z
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next
H
H
L
Current
Current
L
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE HIGH. See "Write enable truth table (per byte)," on page 5 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
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AS7C332MFT18A
®
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
Symbol
DD, VDDQ
VIN
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
V
+4.6
VDD + 0.5
VDDQ + 0.5
1.8
V
VIN
V
Pd
W
Short circuit output current
IOUT
–
20
mA
oC
oC
oC
Storage temperature (TQFP)
Storage temperature (BGA)
T
stg (TQFP)
stg (BGA)
Tbias
–65
–65
–65
+150
T
+125
Temperature under bias
+135
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
3.135
0
Nominal
Max
3.465
3.465
0
Unit
V
3.3
3.3
0
VDDQ
Vss
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
3.3
2.5
0
VDDQ
Vss
V
V
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AS7C332MFT18A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current1
Output leakage current
Sym
Conditions
VDD = Max, OV < VIN < VDD
OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
|ILI|
2
2
|ILO
|
-2
µA
2
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
V
2
V
DDQ+0.3
Address and control pins
I/O pins
-0.3*
-0.5*
2.4
–
0.8
0.8
–
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
V
V
0.4
1 FT, LBO, and ZZ pins and the 165 BGA JTAG pins (TMS, TDI, and TCK) have an internal pull-up or pull-down, and input leakage = ±10 µa.
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current
Output leakage current
Sym
Conditions
VDD = Max, OV < VIN < VDD
OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
µA
V
|ILI|
2
2
|ILO
|
-2
1.7
1.7
-0.3*
-0.3*
1.7
–
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
DDQ+0.3
V
Address and control pins
I/O pins
0.7
0.7
–
V
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
V
0.7
V
*V min = -1.5 for pulse width less than 0.2 X t
IL
CYC
IDD operating conditions and maximum limits
Parameter
Sym
ICC
Conditions
-65
310
140
110
-75
290
130
110
-85
270
130
110
Unit
CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax
,
Operating power supply current1
mA
IOUT = 0 mA
ISB
Deselected, f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
ISB1
Standby power supply current
mA
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
ISB2
100
100
100
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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AS7C332MFT18A
®
Timing characteristics over operating range
–65
–75
–85
1
Parameter
Sym
Min
7.5
–
Max
Min
8.5
–
Max
–
Min
10
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
t
–
6.5
3.5
–
CYC
Clock access time
t
7.5
3.5
–
8.5
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
–
OE
t
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
2,3,4
2
LZC
t
–
–
–
OH
t
–
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
-
3.5
3.8
–
-
3.5
4.0
–
–
4.0
5.0
–
t
-
-
–
HZC
t
0
0
0
OHOE
t
2.2
2.2
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
3.0
3.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
–
6
–
–
–
6
Write setup to clock high
t
–
–
–
6,7
6,8
6
WS
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
t
–
–
–
CSS
t
–
–
–
AH
DH
WH
t
–
–
–
6
t
–
–
–
6,7
6,8
6
t
–
–
–
CSH
t
–
–
–
ADVS
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 20.
t
–
–
–
6
ADSPS
ADSCS
t
–
–
–
6
t
–
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
–
6
t
–
–
–
6
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IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard
1149.1-1990. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG feature
If the JTAG function is not being implemented, TCK should be grounded to avoid mid-level input. At power-up, the device
will come up in a reset state which will not interfere with the operation of the device.
TAP controller state diagram
TAP controller block diagram
TEST-LOGIC
RESET
1
0
0
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
RUN-TEST/
IDLE
Bypass Register
0
Selection
Circuitry
Selection
Circuitry
2
1 0
0
0
Instruction Register
TDI
TDO
1
1
.
. .
2
3130 29
Identification Register
1 0
1 0
CAPTURE-DR
0
CAPTURE-IR
0
x
. . . . .
2
1
Boundary Scan Register
SHIFT-DR
1
0
SHIFT-IR
1
0
1
1
EXIT1-IR
0
EXIT1-DR
0
TCK
TMS
TAP Controller
PAUSE-IR
1
PAUSE-DR
1
0
0
1
x = 75
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
UPDATE-DR
1
0
1
0
Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Test access port (TAP)
Test clock (TCK)
The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if
the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
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Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register,
see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test data-out (TDO)
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM
and can be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP registers
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only
one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK.
Data is output on the TDO pin/ball on the falling edge of TCK.
Instruction register
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO
pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and
also if the controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault
isolation of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-
bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay.
The bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long
register and the x18 configuration has a 53-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and
SAMPLE Z instructions can be used to capture the contents of the I/O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.
Identification (ID) register
The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded
with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.
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TAP instruction set
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of
these instructions are reserved and should not be used.
Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot
preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During
this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is
shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP
controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a high-Z state.
EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.
IDCODE
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register
between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR
state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller
is in a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a
snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a
1149.1 mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore,
is not fully 1149.1 compliant.
Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or
output can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet
the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in
a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and
ignore the value of the CK and CK# captured in the bounder scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a
SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
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BYPASS
The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed
between TDI and TDO.
RESERVED
Do not use a reserved instruction. These instructions are not implemented but are reserved for future use.
TAP timing diagram
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
THTH
THTL
TLTH
Test Mode Select
(TMS)
t
t
MVTH THMX
Test Data-In
(TDI)
t
TLOV
t
t
DVTH
THDX
t
TLOX
Test Data-Out
(TDO)
Undefined
Don’t care
TAP AC electrical characteristics
o
o
For notes 1 and 2, +10 C ≤ T ≤ +110 C and +2.4V ≤ V ≤ +2.6V.
J
DD
Description
Symbol
Min Max Units
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
Output Times
tTHTH
fTF
tTHTL
tTLTH
50
ns
MHz
ns
20
10
20
20
ns
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
Setup Times
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
ns
ns
ns
5
5
TMS setup
tMVTH
tCS1
5
5
ns
ns
Capture setup
Hold Times
TMS hold
tTHMX
tCH1
5
5
ns
ns
Capture hold
1 tCS and tCH refer to the setup and hold time requirements of latching
data from the boundary scan register.
2 Test conditions are specified using the load in the figure TAP AC output
load equivalent.
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TAP AC test conditions
TAP AC output load equivalent
VDDQ/2
Input pulse levels. . . . . . . . . . . . . . . VSS to VDD
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing reference levels. . . . . . . . . . VDDQ/2
Output reference levels . . . . . . . . . . . . . .VDDQ/2
Test load termination supply voltage. . . . . VDDQ/2
50Ω
TDO
20pF
ZO=50Ω
3.3V VDD, TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +3.135V < VDD < +3.465V unless otherwise noted)
Description
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
Conditions
Symbol
VIH
Min
2.0
Max
VDD + 0.3
0.8
Units
V
Notes
1, 2
VIL
-0.3
-5.0
V
1, 2
0V ≤ VIN ≤ VDD
ILI
5.0
µA
Outputs disabled,
0V ≤ VIN ≤ VDDQ(DQx)
Output leakage current
ILO
-5.0
5.0
µA
Output low voltage
Output low voltage
Output high voltage
Output high voltage
IOLC = 100µA
VOL1
VOL2
VOH1
VOH2
0.7
0.8
V
V
V
V
1
1
1
1
IOLT = 2mA
IOHS = -100µA
2.9
2.0
IOHT = -2mA
2.5V VDD, TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted)
Description
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
Conditions
Symbol
VIH
Min
1.7
Max
VDD + 0.3
0.7
Units
V
Notes
1, 2
VIL
-0.3
-5.0
V
1, 2
0V ≤ VIN ≤ VDD
ILI
5.0
µA
Outputs disabled,
0V ≤ VIN ≤ VDDQ(DQx)
Output leakage current
ILO
-5.0
5.0
µA
Output low voltage
Output low voltage
Output high voltage
Output high voltage
IOLC = 100µA
VOL1
VOL2
VOH1
VOH2
0.2
0.7
V
V
V
V
1
1
1
1
IOLT = 2mA
IOHS = -100µA
2.1
1.7
IOHT = -2mA
1. All voltage referenced to VSS(GND).
2. Overshoot: VIH(AC) ≤ VDD + 1.5V for t ≤ tKHKH/2
Undershoot:VIL(AC) ≥ -0.5 for t ≤ tKHKH/2
Power-up:VIH ≤ +2.6V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than
tKHKL(Min) or operate at frequencies exceeding fKF(Max).
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Identification register definitions
Instruction field
Revision number (31:28)
Device depth (27:23)
2M x 18
xxxx
Description
Reserved for version number.
xxxxx/xxxxx
xxxxx/xxxxx
xxxxxx
Defines the depth of 2M words.
Defines the width of x18 bits.
Reserved for future use.
Device width (22:18)
Device ID (17:12)
JEDEC ID code (11:1)
00000110100
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
ID register presence indicator (0)
Scan register sizes
Register name
Instruction
Bit size
3
1
Bypass
ID
32
Boundary scan
x18:76
Instruction codes
Instruction
Code
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
EXTEST
IDCODE
000
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM output drivers to a high-Z state.
SAMPLE Z
RESERVED
010
101
100
Do not use. This instruction is reserved for future use.
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
111, 011, 110
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165-ball BGA boundary scan exit order (x18)
Bit #s
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Signal Name
CLK
CE2
BWa
NC
Ball ID
6B
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
Bit #s
1
Signal Name
A
Ball ID
6N
2
A
8P
3
A
8R
4
A
9R
BWb
NC
5
A
9P
6
A
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
CE1
CE0
A
7
A
8
A
9
A
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ZZ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQPa
NC
10M
10L
10K
10J
NC
1G
2D
2E
2F
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
11B
10A
10B
9A
2G
1J
1K
1L
1M
1N
2K
2L
2M
2J
NC
NC
NC
NC
NC
A
NC
NC
A
2R
1R
3P
A
LBO
A
A
ADV
ADSP
ADSC
OE
A
3R
4R
4P
9B
A
8A
A
8B
A1
6P
BWE
GWE
7A
A0
6R
7B
Note 1 : NC and V pins included in the scan exit order are read as “X” (i.e. Don’t care)
SS
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Key to switching waveforms
Rising input
Falling input
Undefined or don’t care
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
ADSC
tADSCS
tADSCH
LOAD NEW ADDRESS
tAS
tAH
A1
A2
A3
Address
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
ADV inserts wait states
tOE
tHZOE
tOH
tLZOE
Q(A3Ý11)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A1)
DOUT
tCD
tHZC
Read Suspend Read
Burst
Read
Burst
Read
2Ý10
) Q(A
Suspend
Read
Burst
Read
2Ý11
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
)
Q(A1)
Read
Q(A2)
DSEL
2Ý01
) Q(A
2Ý10
) Q(A
Q(A1)
Q(A
)
Q(A
) Q(A
) Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a,b] is don’t care.
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Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
ADSC
tADSCS
tADSCH
ADSC LOADS NEW ADDRESS
A3
tAS
tAH
A1
A2
Address
tWS
tWH
BWE
BW[a,b]
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV SUSPENDS BURST
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10)
D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Data In
ADV
Burst
Write
Read Q(A1) Suspend
Read
Q(A2)
Suspend
Write
ADV
Burst
Write
Suspend
Write
ADV
Burst
Write
ADV
Burst
Write
Write
3
D(A )
Burst
Write
3Ý01
D(A )
Write
D(A1)
2
2Ý01
D(A )
D(A
)
3Ý10
D(A
)
2Ý01
2Ý10
2Ý11
Q(A )
D(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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Timing waveform of read/write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
A2
A3
A1
Address
tWS
tWH
GWE
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDH
tDS
DIN
D(A2)
tCD
tOH
tOE
tHZOE
DOUT
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tLZC
tLZOE
DSEL
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
D(A )
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
Suspend
Read
2
3Ý11
)
Q(A
3Ý01
3Ý10
3Ý11
Q(A )
D(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω/1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
5 pF*
90%
10%
90%
10%
353Ω/1538Ω
30 pF*
GND *including scope
and jig capacitance
GND
for 2.5V I/O
Figure C: Output load(B)
Figure A: Input waveform
Figure B: Output load (A)
Notes
1
2
3
4
5
6
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
CH is measured as high if above VIH, and tCL is measured as low if below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
,
BWE, and BW[a,b].
CE1, and CE2
Chip select refers to CE0
,
.
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Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
0.05
Max
0.15
A1
A2
b
1.35
1.45
b
e
0.22
0.38
c
0.09
0.20
D
13.90
19.90
14.10
20.10
E
e
0.65 nominal
Hd
He
L
15.85
21.80
0.45
16.15
22.20
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
α
L1
L
A1 A2
165-ball BGA (ball grid array)
Top
Bottom
A1 corner index area
1 2 3 4 5 6 7 8 9 10 11
11 10 9 8 7 6 5 4 3 2 1
A
B
C
A
B
C
A
B
D
E
F
D
E
F
All measurements are in mm.
G
H
J
K
L
M
N
P
R
G
H
J
K
L
M
N
P
R
Min
Typ
Max
1.00
A
B
C
D
E
F
16.90 17.00 17.10
C
14.00
14.90 15.00 15.10
10.00
0.26
1.00
15.00±0.10
A
0.35
1.26
0.45
0.40
1.36
0.50
0.45
1.46
0.55
G
H
I
D
10.00
E
15.00±0.10
D
0.20 Z
G
0.12 Z
H
F
/ 0.50±0.05
Ø
Ø
M Z X Y
M Z
Detail of Solder Ball
Side View
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Alliance Semiconductor
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AS7C332MFT18A
®
Ordering information
Package & Width
-65
-75
-85
AS7C332MFT18A-65TQC
AS7C332MFT18A-65TQI
AS7C332MFT18A-65BC
AS7C332MFT18A-65BI
AS7C332MFT18A-75TQC
AS7C332MFT18A-75TQI
AS7C332MFT18A-75BC
AS7C332MFT18A-75BI
AS7C332MFT18A-85TQC
AS7C332MFT18A-85TQI
AS7C332MFT18A-85BC
AS7C332MFT18A-85BI
TQFP x 18
BGA x 18
Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C332MFT18A-65TQCN)
Part numbering guide
AS7C
33
2M
FT
18
A
–XX
TQ or B
C/I
X
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33 = 3.3V
3.Organization: 2M = 2M
4.Flow-through mode
5.Organization: 18 = x 18
6.Production version: A = first production version
7.Clock speed
8.Package type: TQ = TQFP, B = BGA
9.Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
10. N = Lead free part
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Alliance Semiconductor
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AS7C332MFT18A
®
®
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All Rights Reserved
Part Number: AS7C332MFT18A
Document Version: v 1.0
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© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
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相关型号：
AS7C332MFT18A-65TQIN
Standard SRAM, 2MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
ISSI
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