AS7C33512FT18A-75TQIN [ISSI]
Standard SRAM, 512KX18, 7.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100;
| 型号： | AS7C33512FT18A-75TQIN |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 512KX18, 7.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2004
AS7C33512FT18A
®
3.3V 512K × 18 Flow-through synchronous SRAM
Features
• Organization: 524,288 words × 18 bits
• Fast clock to data access: 7.5/8.5/10ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
Burst logic
512K x 18
CLR
Memory
array
19 17
19
19
Q
D
A[18:0]
Address
CS
register
CLK
18
18
2
GWE
BWb
D
DQb
Q
Byte Write
registers
BWE
BWa
CLK
D
Q
DQa
Byte Write
registers
CLK
CE0
CE1
OE
Output
D
Q
Q
Input
registers
Enable
register
CE
CLK
CE2
registers
CLK
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
OE
18
DQ[a,b]
Selection guide
-75
8.5
7.5
300
110
30
-85
10
-10
12
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
275
100
30
10
ns
250
90
mA
mA
mA
30
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512FT18A
®
1,2
8 Mb Synchronous SRAM products list
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
AS7C33512PFS18A
AS7C33256PFS32A
AS7C33256PFS36A
AS7C33512PFD18A
AS7C33256PFD32A
AS7C33256PFD36A
AS7C33512FT18A
AS7C33256FT32A
AS7C33256FT36A
AS7C33512NTD18A
AS7C33256NTD32A
AS7C33256NTD36A
AS7C33512NTF18A
AS7C33256NTF32A
AS7C33256NTF36A
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
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AS7C33512FT18A
®
Pin assignment
100-pin TQFP - top view
A
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
2
NC
3
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
5
6
DQpa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
NC
7
DQb0
DQb1
VSSQ
VDDQ
8
9
10
11
DQb2 12
DQb3 13
NC 14
TQFP 14 × 20mm
VDD
15
VDD
ZZ
NC 16
VSS 17
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
DQb4 18
DQb5 19
VDDQ
VSSQ
20
21
DQb6 22
DQb7 23
DQpb 24
NC 25
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
26
27
NC 28
NC 29
NC 30
NC
NC
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AS7C33512FT18A
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Functional description
The AS7C33512FT18A is a high-performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM) device organized as
524,288 words × 18 bits.
Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10ns. Three chip enable (CE) inputs permit easy memory expansion.
Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst
advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for
the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With
LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count
sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18
bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented
internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP
follow.
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C33512FT18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in 100-pin TQFP.
TQFP Capacitance
Parameter
Input capacitance
Symbol
Test conditions
VIN = 0V
Min
Max
Unit
pF
*
CIN
-
-
5
7
*
I/O capacitance
CI/O
VOUT = 0V
pF
*
Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
θJA
θJA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
22
Thermal resistance
θJC
8
°C/W
(junction to top of case)1
1 This parameter is sampled
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AS7C33512FT18A
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Signal descriptions
Description
Pin
CLK
I/O Properties
I
I
CLOCK
SYNC
SYNC
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
A,A0,A1
DQ[a,b]
I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE0
I
I
SYNC
SYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write
enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,
the cycle is a read cycle.
BW[a,b]
I
SYNC
OE
I
I
ASYNC
STATIC
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
LBO
ZZ
I
-
ASYNC
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
NC
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
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AS7C33512FT18A
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Write enable truth table (per byte)
Function
GWE BWE
BWa
X
BWb
X
L
H
H
H
H
H
X
L
L
L
H
L
Write All Bytes
L
L
Write Byte a
Write Byte b
L
H
H
L
X
X
Read
H
H
Key: X = don’t care, L = low, H = high, n = a, b; BWE
,
BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
ZZ
H
L
OE
X
I/O Status
High-Z
L
Dout
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
Deselected
L
X
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Interleaved burst address (LBO = 1)
A1 A0 A1 A0 A1 A0 A1 A0
Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0
1st Address
2nd Address
3rd Address
4th Address
0 0
0 1
1 0
1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
1st Address
2nd Address
3rd Address
4th Address
0 0
0 1
1 0
1 1
0 1
1 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
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AS7C33512FT18A
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Synchronous truth table[4]
[2]
CE01
H
L
CE1
X
L
CE2
X
X
X
H
H
L
ADSP ADSC ADV WRITE
OE
X
X
X
X
X
L
Address accessed
NA
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
NA
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
H
L
Next
Hi−Z
Q
H
H
L
Current
Current
Next
H
L
Hi−Z
Q
L
H
L
Next
Hi−Z
Q
H
H
X
L
Current
Current
External
Next
H
X
X
X
X
X
Hi−Z
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next
H
H
L
Current
Current
L
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
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AS7C33512FT18A
®
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
Symbol
DD, VDDQ
VIN
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
V
+4.6
VDD + 0.5
VDDQ + 0.5
1.8
V
VIN
V
Pd
W
Short circuit output current
IOUT
Tstg
–
20
mA
oC
oC
Storage temperature
–65
–65
+150
Temperature under bias
Tbias
+135
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
3.135
0
Nominal
Max
3.465
3.465
0
Unit
V
3.3
3.3
0
VDDQ
Vss
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
3.3
2.5
0
VDDQ
Vss
V
V
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AS7C33512FT18A
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DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current1
Output leakage current
Sym
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
|ILI|
2
2
|ILO
|
-2
µA
2**
2**
-0.3*
-0.5*
2.4
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
V
V
DDQ+0.3
Address and control pins
I/O pins
0.8
0.8
–
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
V
V
–
0.4
1 LBO, and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µa.
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current
Output leakage current
Sym
Conditions
Min
-2
Max
Unit
µA
µA
V
|ILI|
VDD = Max, 0V < VIN < VDD
2
2
|ILO
|
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
-2
1.7**
1.7**
-0.3*
-0.3*
1.7
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
DDQ+0.3
V
Address and control pins
I/O pins
0.7
0.7
–
V
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
V
–
0.7
V
*V min = -1.5 for pulse width less than 0.2 X t
IL
CYC
**V max < V +1.5V for pulse width less than 0.2 X t
IH
DD
CYC
IDD operating conditions and maximum limits
Parameter
Sym
Conditions
-75
-85
-10
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
Operating power supply current1
ICC
300
275
100
250
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
ISB
110
90
f = fMax, ZZ < VIL
mA
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power supply current
ISB1
ISB2
30
30
30
30
30
30
Deselected, f = f , ZZ
≥
V
– 0.2V,
DD
Max
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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Timing characteristics over operating range
–75
–85
–10
1
Parameter
Sym
Min
8.5
–
Max
–
Min
10
–
Max
–
Min
12
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
t
CYC
Clock access time
t
7.5
3.5
–
8.5
4.0
–
10
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
–
OE
t
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
2,3,4
2
LZC
t
–
–
–
OH
t
–
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
-
3.5
4.0
–
–
4.0
5.0
–
–
4.0
5.0
–
t
-
–
–
HZC
t
0
0
0
OHOE
t
2.5
2.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
3.0
3.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
3.0
3.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
–
6
–
–
–
6
Write setup to clock high
t
–
–
–
6,7
6,8
6
WS
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
t
–
–
–
CSS
t
–
–
–
AH
DH
WH
t
–
–
–
6
t
–
–
–
6,7
6,8
6
t
–
–
–
CSH
t
–
–
–
ADVS
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 16.
t
–
–
–
6
ADSPS
ADSCS
t
–
–
–
6
t
–
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
–
6
t
–
–
–
6
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
Current during Snooze Mode
ZZ active to input ignored
I
30
mA
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
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Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
LOAD NEW ADDRESS
A3
tAS
tAH
A1
A2
tWH
Address
tWS
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
ADV inserts wait states
tOE
tHZOE
tOH
tLZOE
Q(A3Ý11)
Q(A3Ý10)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A1)
Dout
tCD
tHZC
Read Suspend Read
Burst
Read
Burst
Read
2Ý10
) Q(A
Suspend
Read
Burst
Read
2Ý11
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
) Q(A )
Q(A1)
Read
Q(A2)
DSEL
2Ý01
) Q(A
2Ý10
) Q(A
Q(A1)
Q(A
)
Q(A
) Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:b] is don’t care.
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Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
ADSC
tADSCS
tADSCH
ADSC LOADS NEW ADDRESS
A3
tAS
tAH
A1
A2
Address
tWS
tWH
BWE
BW[a:b]
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV SUSPENDS BURST
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10)
D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Din
ADV
Burst
Write
Read
Q(A1)
Suspend
Write
D(A1)
Read
Q(A2)
Suspend
Write
ADV
Burst
Write
Suspend
Write
ADV
Burst
Write
ADV
Burst
Write
Write
3
D(A )
Burst
Write
3Ý01
D(A )
2
2Ý01
D(A )
D(A
)
3Ý10
D(A
)
2Ý01
2Ý10
2Ý11
D(A )
D(A
)
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
A2
A3
A1
Address
tWS
tWH
BWE
BW[a:b]
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDH
tDS
Din
D(A2)
tOE
tCD
tLZC
tOH
tHZOE
tLZOE
Dout
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
Suspend
Read
3Ý11
Q(A )
2
D(A )
3Ý01
3Ý10
3Ý11
Q(A )
Q(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCH
tCL
CLK
tADSCS
tADSCH
ADSC
tAS
tAH
A9
A10
A5
A4
A7
A8
A3
A6
A1
A2
ADDRESS
BWE
tWS
tWH
BW[a:b]
tCSS
tCSH
CE0,CE2
CE1
OE
tCD
tOE
tOH
tHZOE
tLZOE
Q(A2)
Q(A9)
Q(A1)
Q(A3)
Q(A10)
Q(A4)
Dout
Din
tDH
tDS
D(A5)
D(A6)
D(A7)
D(A8)
READ
Q(A10)
WRITE
D(A7)
READ READ READ
Q(A1) Q(A2) Q(A3)
WRITE
D(A6)
WRITE
D(A8)
READ
Q(A9)
READ
Q(A4)
WRITE
D(A5)
Note: ADV is don’t care here.
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Timing waveform of power down cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
tWS
tWH
BWE
BW[a:b]
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
tLZOE
Din
tHZOE
tHZC
Dout
Q(A2)
Q(A1)
tPUS
Q(A2(Ý01))
tPDS
ZZ Recovery Cycle
Normal Operation Mode
ZZ
ZZ Setup Cycle
tZZI
tRZZI
ISB2
Isupply
Sleep
State
READ
READ
READ
READ
Q(A1) Q(A1Ý01)
Q(A2) Q(A2Ý01)
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AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω/1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
5 pF*
90%
10%
90%
10%
353Ω/1538Ω
30 pF*
GND *including scope
and jig capacitance
GND
for 2.5V I/O
Figure C: Output load(B)
Figure A: Input waveform
Figure B: Output load (A)
Notes
1
2
3
4
5
6
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
CH is measured as high if above VIH, and tCL is measured as low if below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
,
BWE, and BW[a,b].
CE1, and CE2
Chip select refers to CE0
,
.
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Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
0.05
Max
0.15
A1
A2
b
1.35
1.45
b
e
0.22
0.38
c
0.09
0.20
D
13.90
19.90
14.10
20.10
E
e
0.65 nominal
Hd
He
L
15.85
21.80
0.45
16.15
22.20
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
α
L1
L
A1 A2
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Ordering information
Package & Width
-75
-85
-10
AS7C33512FT18A-75TQC
AS7C33512FT18A-75TQI
AS7C33512FT18A-85TQC
AS7C33512FT18A-85TQI
AS7C33512FT18A-10TQC
AS7C33512FT18A-10TQI
TQFP x 18
Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33512FT18A-85TQCN)
Part numbering guide
AS7C
33
512
FT
18
A
–XX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33 = 3.3V
3.Organization: 512 = 512K
4.Flow-through mode
5.Organization: 18 = x 18
6.Production version: A = first production version
7.Clock Access Time : [-75=7.5ns, -85 = 8.5ns, -10=10ns]
8.Package type: TQ = TQFP
9.Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
10. N = Lead free part
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AS7C33512FT18A
®
®
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33512FT18A
Document Version: v 1.1
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best
data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility
or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance
products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express
agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms
and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction
or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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