AS7C33512NTD16A-166TQC [ISSI]
ZBT SRAM, 512KX16, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C33512NTD16A-166TQC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | ZBT SRAM, 512KX16, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2003
AS7C33512NTD16A
AS7C33512NTD18A
®
TM
3.3V 512K × 16/18 ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋ
Features
• Available in100-pin TQFP
• Byte write enables
• Organization: 524,288 words × 16 or 18 bits
™
• NTD 1 architecture for efficient bus operation
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/ O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• Self-timed WRITE cycles
• Fast clock speeds to 166 MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3.5/ 3.8/ 4.0/ 5.0 ns
• Fast OEaccess time: 3.5/ 3.8/ 4.0/ 5.0 ns
• Fully synchronous register-to-register operation
• Flow-through or pipelined mode
• “Interleaved” or “linear burst” modes
• Snooze mode for standby operation
• Asynchronous output enable control
™
1. NTD is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
19
19
Q
D
A[18:0]
Address
register
Burst logic
CLK
D
Q
Write delay
addr. registers
CLK
CE0
CE1
CE2
19
R/W
BWa
BWb
Control
logic
CLK
ADV / LD
FT
512K x 16/ 18
SRAM
LBO
ZZ
Array
CLK
16/ 18
16/ 18
Data
DQ [a:b]
Q
D
Input
Register
16/ 18
16/ 18
CLK
16/ 18
CLK
CEN
CLK
Output
Register
OE
16/ 18
DQ[a:b]
OE
Selection guide
-166
6
–150
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
6.6
150
3.8
425
110
30
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.5
475
130
30
100
5
MHz
ns
400
100
30
300
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512NTD16A
AS7C33512NTD18A
®
Pin arrangement for TQFP
A
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
2
NC
3
VDDQ
4
V
V
5
SSQ
SSQ
NC
NC
NC
6
DQpa/ NC
DQa
7
DQb
8
DQa
DQb
9
V
V
10
11
SSQ
SSQ
VDDQ
DQa
DQa
V
DDQ
DQb 12
DQb 13
FT 14
V
SS
TQFP 14 × 20mm*
NC
VDD 15
NC 16
VDD
ZZ
V
17
SS
DQa
DQa
VDDQ
DQb 18
DQb 19
VDDQ 20
V
V
21
SSQ
SSQ
DQa
DQa
NC
DQb 22
DQb 23
DQpb/ NC 24
NC 25
NC
V
V
26
27
SSQ
SSQ
VDDQ
NC
V
DDQ
NC 28
NC 29
NC 30
NC
NC
Note: Pins 24 and 74 are NC for x 16.
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
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AS7C33512NTD16A
AS7C33512NTD18A
®
Functional description
The AS7C33512NTD16A and 7C33512NTD18A are high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 524,288 words × 16 or 18 bits and incorporate a LATE LATE Write.
™
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced write operation that
improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to
the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
™
NTD devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-
™
through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD ,
write and read operations can be used in any order without producing dead bus cycles.
Assert R/ W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16- or 18-bit
writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device, two
clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations. It can be tied low for
normal operations. Outputs go to a high impedance state when the device is deselected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipelined mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/ LD (burst advance) input to perform burst read, write and deselect operations. When ADV/ LD is high, external addresses, chip
select, R/ W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD16A and 7C33512NTD18A operate with a 3.3V ± 5% power supply for the device core (V ). DQ circuits use a separate
DD
power supply (V ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP.
DDQ
Capacitance
Parameter
Input capacitance
I/ O capacitance
Symbol
Signals
Address and control pins
I/ O pins
Test conditions
IN = 0V
IN = VOUT = 0V
Max
5
Unit
pF
C
V
IN
C
V
7
pF
I/ O
Burst order
Interleaved Burst Order LBO=1
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address 0 0 0 1 1 0 1 1
0 0 1 1 1 0
Linear Burst Order LBO=0
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address 0 0
First increment 0 1
Second increment 1 0
Third increment 1 1
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
First increment 0 1
Second increment 1 0
Third increment 1 1
1 1
1 0
0 0
0 1
0 1
0 0
4/ 1/ 03, v.1.9.4
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AS7C33512NTD16A
AS7C33512NTD18A
®
Signal descriptions
Signal
I/ O Properties
Description
CLK
I
I
CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN
SYNC
SYNC
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/ LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b]
I
I/ O
CE0, CE1,
CE2
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/ LD is asserted. Are
ignored when ADV/ LD is high.
I
I
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new address
is loaded.
ADV/ LD
R/ W
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/ LD is high.
SYNC
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b]
OE
I
I
ASYNC Asynchronous output enable. I/ O pins are not driven when OE is inactive.
Count mode. When driven high, count sequence follows Intel XOR convention. When
STATIC driven low, count sequence follows linear convention. This input should be static when the
device is in operation.
LBO
I
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
FT
I
STATIC
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
NC
-
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–
Max
+4.6
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/ O pins)
Power dissipation
VDD, VDDQ
V
VDD + 0.5
VDDQ + 0.5
1.8
V
IN
V
V
IN
PD
W
DC output current
IOUT
Tstg
–
50
mA
° C
° C
Storage temperature (plastic)
Temperature under bias
–65
–65
+150
Tbias
+135
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
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AS7C33512NTD16A
AS7C33512NTD18A
®
Synchronous truth table
CE0
H
CE1
X
CE2
X
ADV/ LD
R/ W BW[a,b]
OE CEN Address source
CLK
Operation
L
L
L
L
L
H
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
NA
NA
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Begin read
X
L
X
X
X
H
NA
L
H
L
External
External
Burst counter
Stall
L
H
L
L
L to H Begin write
L to H Burst2
1
X
X
X
X
X
X
X
X
X
X
L to H Inhibit the CLK
1 Should be low for Burst write, unless a specific byte/ s need/ s to be inhibited
2 Refer to state diagram below.
Key: X = Don’t Care, L = low, H = high.
State diagram for NTD SRAM
Burst
Read
Burst
Read
Read
Read
Burst
Dsel
Dsel
Burst
Burst
Burst
Write
Write
Write
Burst
Write
Recommended operating conditions
Parameter
Symbol
Min
3.135
0.0
Nominal
Max
3.465
0.0
Unit
VDD
3.3
0.0
3.3
0.0
2.5
0.0
–
Supply voltage
V
V
V
V
V
SS
VDDQ
3.135
0.0
3.465
0.0
3.3V I/ O supply
voltage
V
SSQ
VDDQ
2.35
0.0
2.65
2.5V I/ O supply
voltage
V
0.0
SSQ
V
2.0
–0.52
VDD + 0.3
0.8
Address and
control pins
IH
V
–
IL
Input voltages1
V
2.0
–
VDDQ + 0.3
0.8
IH
I/ O pins
V
V
–0.52
0
–
IL
Ambient operating temperature
TA
–
70
° C
1 Input voltage ranges apply to 3.3V I/ O operation. For 2.5V I/ O operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 × t
.
IL
RC
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
5 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
° C/ W
° C/ W
1–layer
4–layer
θ
Thermal resistance
JA
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/ JESD51
(junction to ambient)1
θ
22
JA
JC
Thermal resistance
θ
8
° C/ W
(junction to top of case)1
1 This parameter is sampled.
DC electrical characteristics
–166
–150
–133
–100
Parameter
Symbol
Test conditions
Min Max Min Max Min Max Min Max Unit
Input leakage
current
1
| ILI|
VDD = Max, VIN = GND to VDD
–
–
2
2
–
–
2
2
–
–
2
2
–
–
2
2
µA
µA
Output leakage
current
OE ≥ V , VDD = Max,
IH
| ILO
|
VOUT = GND to VDD
Operating power
supply current
CE0 = V , CE1 = V , CE2 = V ,
2
IL
IH
IL
ICC
–
–
–
475
130
30
–
–
–
425
110
30
–
–
–
400
100
30
–
–
–
300 mA
90
f = fMax, IOUT = 0 mA
ISB
Deselected, f = fMax, ZZ ≤ V
IL
Deselected, f = 0, ZZ ≤ 0.2V
all V ≤ 0.2V or ≥ VDD – 0.2V
Standby power
supply current
ISB1
30
mA
IN
Deselected, f = f , ZZ
≥
V
– 0.2V
Max
DD
ISB2
–
30
–
30
–
30
–
30
All V ≤ V or ≥ V
IN
IL
IH
V
IOL = 8 mA, VDDQ = 3.465V
IOH = –4 mA, VDDQ = 3.135V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
V
OL
Output voltage
V
2.4
2.4
2.4
2.4
–
OH
1 LBO pin has an internal pull-up and input leakage = ±10 µA.
2 I give with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
DC electrical characteristics for 2.5V I/ O operation
–166
–150
–133
–100
Parameter
Symbol
Test conditions
OE ≥ V , VDD = Max,
Min Max Min Max Min Max Min Max Unit
Output leakage
current
IH
| ILO|
–1
1
–1
1
–1
1
–1
1
µA
V
VOUT = GND to VDD
V
IOL = 2 mA, VDDQ = 2.65V
IOH = –2 mA, VDDQ = 2.35V
–
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
OL
Output voltage
V
1.7
1.7
1.7
1.7
OH
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
6 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Timing characteristics for 3.3 V I/ O operation
–166
–150
–133
–100
Parameter
Symbol
fMax
tCYC
tCYCF
tCD
Unit Notes1
Min
Max Min
Max Min
Max Min
Max
Clock frequency
–
6
166
–
–
150
–
–
133
–
–
100 MHz
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
Clock high to output low Z
6.6
10
–
7.5
12
–
10
12
–
–
–
ns
ns
10
–
–
–
–
3.5
9
3.8
10
3.8
–
4.0
10
4.0
–
5.0 ns
12 ns
5.0 ns
tCDF
tOE
tLZC
tOH
–
–
–
–
–
3.5
–
–
–
–
0
0
0
0
–
–
–
ns 2,3,4
ns
ns 2,3,4
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
2
tLZOE
tHZOE
tHZC
tOHOE
tCH
–
–
–
–
3.5
3.5
–
–
3.8
3.8
–
–
4.0
4.0
–
–
4.5 ns 2,3,4
5.0 ns 2,3,4
–
–
–
–
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
2.2
1.5
1.5
1.5
1.5
–
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
3.5
3.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
5
5
Clock low pulse width
tCL
–
–
–
Address setup to clock high
tAS
–
–
–
6
Data setup to clock high
tDS
–
–
–
6
Write setup to clock high
tWS
–
–
–
6,7
6,8
6
Chip select setup to clock high
ADV/ LD setup to clock high
tCSS
–
–
–
tADVS 1.5
tCENS 1.5
–
–
–
Clock enable
ꢀ
setup to clock high
–
–
–
6
Address hold from clock high
Data hold from clock high
tAH
tDH
tWH
tCSH
0.5
0.5
0.5
0.5
–
–
–
6
–
–
–
6
Write hold from clock high
Chip select hold from clock high
ADV/ LD hold from clock high
Clock enable hold from clock high
1 Refer to “notes” on page 11.
–
–
–
6,7
6,8
6
–
–
–
tADVH 0.5
tCENH 0.5
–
–
–
–
–
–
6
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
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AS7C33512NTD16A
AS7C33512NTD18A
®
Timing characteristics for 2.5 V I/ O operation
–166
–150
–133
–100
Parameter
Symbol
fMax
tCYC
tCYCF
tCD
Unit Notes1
Min
Max Min
Max Min
Max Min
Max
Clock frequency
–
6
166
–
–
150
–
–
133
–
–
100 MHz
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
Clock high to output low Z
6.6
10
–
7.5
12
–
10
12
–
–
–
ns
ns
10
–
–
–
–
3.8
9
4.0
10
3.8
–
4.2
10
4.0
–
5.0 ns
12 ns
5.0 ns
tCDF
tOE
tLZC
tOH
–
–
–
–
–
3.5
–
–
–
–
0
0
0
0
–
–
–
ns 2,3,4
ns
ns 2,3,4
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
2
tLZOE
tHZOE
tHZC
tOHOE
tCH
–
–
–
–
3.5
3.5
–
–
3.8
3.8
–
–
4.0
4.0
–
–
4.5 ns 2,3,4
5.0 ns 2,3,4
–
–
–
–
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
2.2
1.7
1.7
1.7
1.7
–
2.5
2.5
1.7
1.7
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
0.7
0.7
–
2.5
2.5
1.7
1.7
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
0.7
0.7
–
3.5
3.5
2.0
2.0
2.0
2.0
2.0
2.0
0.7
0.7
0.7
0.7
0.7
0.7
5
5
Clock low pulse width
tCL
–
–
–
Address setup to clock high
tAS
–
–
–
6
Data setup to clock high
tDS
–
–
–
6
Write setup to clock high
tWS
–
–
–
6,7
6,8
6
Chip select setup to clock high
ADV/ LD setup to clock high
tCSS
–
–
–
tADVS 1.7
tCENS 1.7
–
–
–
Clock enable
ꢀ
setup to clock high
–
–
–
6
Address hold from clock high
Data hold from clock high
tAH
tDH
tWH
tCSH
0.7
0.7
0.7
0.7
–
–
–
6
–
–
–
6
Write hold from clock high
Chip select hold from clock high
ADV/ LD hold from clock high
Clock enable hold from clock high
1 Refer to “notes” on page 11.
–
–
–
6,7
6,8
6
–
–
–
tADVH 0.7
tCENH 0.7
–
–
–
–
–
–
6
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
8 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
Timing waveform of read/ write cycle
ꢀꢁꢂ
ꢀꢁꢃꢁ
ꢀꢁꢄ
ꢁꢄꢉ
ꢀꢁꢅꢆꢇ
ꢀꢁꢅꢆꢂ
ꢁꢅꢆ
ꢁꢅꢜ
t
ꢀꢁꢇꢇ
ꢁꢇꢂ
ꢁꢅꢊꢋꢌꢁꢅꢍ
ꢀꢎꢏꢐꢂ
ꢎꢏꢐꢑꢄꢏ
ꢀꢓꢇ
ꢀꢓꢂ
ꢒꢑꢓ
ꢀꢓꢇ
ꢀꢓꢂ
ꢛꢓꢘ
ꢇꢎꢇ
ꢀꢎꢂ
ꢎꢝ
ꢎ
ꢎꢞ
ꢎ!
ꢀꢁ
ꢎꢜ
ꢎꢍ
ꢎꢏꢏꢒꢅꢇꢇ
ꢀꢂꢚꢁ
ꢀꢏꢇ
ꢀꢁꢏ
ꢀꢈꢅ
ꢀꢄꢚꢁ
ꢀꢏꢂ
ꢀꢁꢂꢅꢄ
ꢆꢁꢂꢇꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢈꢄ
ꢀꢁꢂꢃÝꢄꢅꢆ
ꢆꢁꢂꢉꢄ
ꢆꢁꢂꢊꢄ
ꢀꢁꢂꢃÝ0ꢄꢅ
ꢏꢑꢔ
"#"$%#ꢘ$ꢙ
ꢀꢈꢂ
ꢀꢂꢚꢈꢅ
ꢀꢄꢚꢈꢅ
ꢈꢅ
ꢀꢁꢂꢅꢄ
ꢆꢁꢂꢇꢄ
ꢏꢑꢔ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢈꢄ
ꢆꢁꢂꢉꢄ
ꢆꢁꢂꢊꢄ
ꢀꢁꢂꢃÝꢆꢄꢅ
ꢀꢁꢂꢈꢋꢌꢃꢄ
&%ꢕ'(ꢀ)*ꢕ+,)
BURST
READ
Q(A4Ý01)
WRITE
D(A1)
WRITE
D(A5)
READ
Q(A6) D(A7)
WRITE
READ
Q(A3)
DSEL
BURST
WRITE
D(A2Ý01)
WRITE
D(A2)
ꢁꢕꢖꢖꢗꢘꢙ
READ
Q(A4)
Note: Ý = XOR when LBO = high/ No Connect; Ý = ADD when LBO = low.
BW[a:b] is don’t care.
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
9 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
NOP, stall and deselect cycles
ꢁꢄꢉ
ꢁꢅꢆ
ꢁꢅꢜ
ꢁꢅꢊꢋꢌꢁꢅꢍ
ꢎꢏꢐꢑꢄꢏ
ꢒꢑꢓ
ꢛꢓꢘ
ꢎꢜ
ꢎꢍ
ꢎꢝ
ꢎꢏꢏꢒꢅꢇꢇ
ꢆꢁꢂꢃꢄ
ꢇꢁꢂꢅÝꢄꢅꢆ
ꢇꢁꢂꢅÝꢅꢄꢆ
ꢀꢁꢂꢈꢄ
ꢏꢔ
"#"$%#ꢘ$ꢙ
ꢆꢁꢂꢃꢄ
ꢀꢁꢂꢈꢄ
ꢏꢔ
ꢇꢁꢂꢅÝꢄꢅꢆ
ꢇꢁꢂꢅÝ10ꢆ
&%ꢕ'(ꢀ)ꢕ+,)
BURST
DSEL
WRITE BURST
BURST
D(A2Ý10) NOP
D(A3)
WRITE
BURST
Q(A1Ý10)
STALL
DSEL
READ
Q(A1)
BURST
Q(A1Ý01)
ꢁꢕꢖꢖꢗꢘꢙ
D(A2)
NOP
D(A2Ý01)
Note: Ý = XOR when LBO = high/ No Connect; Ý = ADD when LBO = low.
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
10 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/ O;
/ +2.5V for 2.5V I/ O
319Ω/1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
V = 1.5V
+3.0V
L
D
OUT
90%
10%
90%
10%
5 pF*
for 3.3V I/ O;
353Ω/1538Ω
30 pF*
= V / 2
DDQ
GND
*including scope
and jig capacitance
GND
for 2.5V I/ O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This paracmeter measured with output load conditon in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
is less than t
and t
is less than t at any given temperature and voltage.
HZOE
LZOE HZC
LZC
5) t measured high above V and t measured as low below V
CH IH CL IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/ W, BW[a:b].
8) Chip select refers to CE0, CE1, CE2.
Package dimensions :100-pin quad flat pack (TQFP)
Hd
TQFP
D
Min
0.05
Max
0.15
A1
A2
b
b
e
1.35
1.45
0.22
0.38
α
0.09
0.20
c
13.80
19.80
14.20
20.20
D
E
He
E
0.65 nominal
e
15.80
21.80
0.45
16.20
22.20
0.75
Hd
He
L
A2
c
L1
L
A1
1.00 nominal
L1
0°
7°
α
Dimensions in millimeters
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
11 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Ordering information
Package
&Width
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C33512NTD16A-
166TQC
AS7C33512NTD16A- AS7C33512NTD16A- AS7C33512NTD16A-
150TQC 133TQC 100TQC
AS7C33512NTD16A- AS7C33512NTD16A- AS7C33512NTD16A-
150TQI 133TQI 100TQI
AS7C33512NTD18A- AS7C33512NTD18A- AS7C33512NTD18A-
150TQC 133TQC 100TQC
AS7C33512NTD18A- AS7C33512NTD18A- AS7C33512NTD18A-
TQFP x16
AS7C33512NTD16A-
166TQI
TQFP x16
TQFP x18
TQFP x18
AS7C33512NTD18A-
166TQC
AS7C33512NTD18A-
166TQI
150TQI
133TQI
100TQI
Part numbering guide
AS7C
33
512
NTD
16 or 18
A
–XXX
TQ
C/ I
1
2
3
4
5
6
7
8
9
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 512
= 512K
4. NTD™ = No-Turn Around Delay. Pipelined/ flow-through mode (each device works in both modes)
5. Organization: 16 = x 16, 18 = x 18
6. Production version: A = first production version
7. Clock speed (MHz)
8. Package type: TQ = TQFP
9. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
12 of 12
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相关型号：
AS7C33512NTD18A-100TQIN
ZBT SRAM, 512KX18, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
ALSC
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