IS25LP064A-QFLA1 [ISSI]
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE;
| 型号： | IS25LP064A-QFLA1 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE |
| 文件： | 总99页 (文件大小：1571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS25LP064A
IS25LP032A
64/32Mb
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD
I/O QPI DTR INTERFACE
DATA SHEET
IS25LP064A/032A
64/32Mb
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
FEATURES
Industry Standard Serial Interface
- IS25LP064A: 64Mbit/8Mbyte
- IS25LP032A: 32Mbit/4Mbyte
- 256 bytes per Programmable Page
- Supports standard SPI, Fast, Dual, Dual
I/O, Quad, Quad I/O, SPI DTR, Dual I/O
DTR, Quad I/O DTR, and QPI
- Double Transfer Rate (DTR) option
- Supports Serial Flash Discoverable
Parameters (SFDP)
Low Power with Wide Temp. Ranges
- Single 2.3V to 3.6V Voltage Supply
- 5 mA Active Read Current (typ.)
- 10 µA Standby Current (typ.)
- 5 µA Deep Power Down (typ.)
- Temp Grades:
Extended: -40°C to +105°C
Extended+: -40°C to +125°C(1)
Auto Grade: up to +125°C
Note:
1. Extended+ should not be used for Automotive.
Advanced Security Protection
- Software and Hardware Write Protection
- Power Supply lock protect
- 4x256-Byte dedicated security area
with OTP user-lockable bits
High Performance Serial Flash (SPI)
- 133Mhz Fast Read at Vcc=2.7V to 3.6V
- 104Mhz Fast Read at Vcc=2.3V to 3.6V
- 532MHz equivalent at QPI operation
- 50MHz Normal Read
- DTR (Dual Transfer Rate) up to 66MHz
- Selectable dummy cycles
- 128 bit Unique ID for each device (Call
Factory)
- Configurable drive strength
- Supports SPI Modes 0 and 3
- More than 100,000 erase/program cycles
- More than 20-year data retention
Industry Standard Pin-out & Packages(1),(2)
- B = 8-pin SOIC 208mil
- F = 8-pin VSOP 208mil
- K = 8-contact WSON 6x5mm
- L = 8-contact WSON 8x6mm
- M = 16-pin SOIC 300mil(3)
- G= 24-ball TFBGA 6x8mm 4x6(3)
- H = 24-ball TFBGA 6x8mm 5x5 (Call
Factory)(3)
Flexible & Efficient Memory Architecture
- Chip Erase with Uniform Sector/Block
Erase (4/32/64 Kbyte)
- Program 1 to 256 bytes per page
- Program/Erase Suspend & Resume
- KGD (Call Factory)
Notes:
1. Call Factory for other package options available.
2. For the RESET# pin option instead of HOLD# pin, call
Factory.
3. For the dedicated RESET# option, see the Ordering
Information
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous Read 8/16/32/64-Byte burst
Wrap
- Selectable burst length
- QPI for reduced instruction overhead
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
2
11/06/2015
IS25LP064A/032A
GENERAL DESCRIPTION
The IS25LP064A/032A Serial Flash memory offers a versatile storage solution with high flexibility and
performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems
that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-
wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip
Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock
frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to
66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)
commands that transfer addresses and read data on both edges of the clock. These transfer rates can
outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in
place) operation.
The memory array is organized into programmable pages of 256-bytes. This family supports page program
mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)
supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte
sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture
allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications
requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the
status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Multi I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI
mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
QPI
The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol
requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The
QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can
significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or
SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used
to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status
Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and
SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively
during QPI mode.
DTR
In addition to SPI and QPI features, the device also supports Fast READ DTR operation, which allows high data
throughput while running at lower clock frequencies. DTR READ mode uses both rising and falling edges of the
clock to drive output, resulting in reducing input and output cycles by half.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
3
11/06/2015
IS25LP064A/032A
TABLE OF CONTENTS
FEATURES..........................................................................................................................................................2
GENERAL DESCRIPTION ..................................................................................................................................3
TABLE OF CONTENTS.......................................................................................................................................4
1. PIN CONFIGURATION.................................................................................................................................7
2. PIN DESCRIPTIONS....................................................................................................................................9
3. BLOCK DIAGRAM......................................................................................................................................11
4. SPI MODES DESCRIPTION ......................................................................................................................12
5. SYSTEM CONFIGURATION......................................................................................................................14
5.1 BLOCK/SECTOR ADDRESSES ..........................................................................................................14
6. REGISTERS ...............................................................................................................................................15
6.1 STATUS REGISTER ............................................................................................................................15
6.2 FUNCTION REGISTER........................................................................................................................18
6.3 READ REGISTER.................................................................................................................................19
7. PROTECTION MODE.................................................................................................................................21
7.1 HARDWARE WRITE PROTECTION....................................................................................................21
7.2 SOFTWARE WRITE PROTECTION ....................................................................................................21
8. DEVICE OPERATION ................................................................................................................................22
8.1 NORMAL READ OPERATION (NORD, 03h) .......................................................................................24
8.2 FAST READ OPERATION (FRD, 0Bh) ................................................................................................26
8.3 HOLD OPERATION..............................................................................................................................28
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ...........................................................................28
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)...................................................................31
8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh)..................................................................32
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) ..........................................................................34
8.8 PAGE PROGRAM OPERATION (PP, 02h)..........................................................................................38
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................40
8.10 ERASE OPERATION .........................................................................................................................41
8.11 SECTOR ERASE OPERATION (SER, D7h/20h)...............................................................................42
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................43
8.13 CHIP ERASE OPERATION (CER, C7h/60h) .....................................................................................45
8.14 WRITE ENABLE OPERATION (WREN, 06h) ....................................................................................46
8.15 WRITE DISABLE OPERATION (WRDI, 04h).....................................................................................47
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ...................................................................48
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h).................................................................49
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)...............................................................50
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h).............................................................51
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
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IS25LP064A/032A
8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h) 52
8.21 PROGRAM/ERASE SUSPEND & RESUME......................................................................................53
8.22 ENTER DEEP POWER DOWN (DP, B9h).........................................................................................55
8.23 RELEASE DEEP POWER DOWN (RDPD, ABh)...............................................................................56
8.24 SET READ PARAMETERS OPERATION (SRP, C0h) ......................................................................57
8.25 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................59
8.26 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 61
8.27 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................62
8.28 READ UNIQUE ID NUMBER (RDUID, 4Bh) ......................................................................................63
8.29 READ SFDP OPERATION (RDSFDP, 5Ah) ......................................................................................64
8.30 NO OPERATION (NOP, 00h).............................................................................................................64
8.31 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ........................................................................................................................................................65
8.32 SECURITY INFORMATION ROW......................................................................................................66
8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h) .................................................................67
8.34 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) .............................................................68
8.35 INFORMATION ROW READ OPERATION (IRRD, 68h) ...................................................................69
8.36 FAST READ DTR MODE OPERATION (FRDTR, 0Dh).....................................................................70
8.37 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) ..................................................72
8.38 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) .................................................75
8.39 SECTOR LOCK/UNLOCK FUNCTIONS............................................................................................79
9. ELECTRICAL CHARACTERISTICS...........................................................................................................81
9.1 ABSOLUTE MAXIMUM RATINGS (1) ...................................................................................................81
9.2 OPERATING RANGE...........................................................................................................................81
9.3 DC CHARACTERISTICS......................................................................................................................82
9.4 AC MEASUREMENT CONDITIONS ....................................................................................................83
9.5 PIN CAPACITANCE .............................................................................................................................83
9.6 AC CHARACTERISTICS......................................................................................................................84
9.7 SERIAL INPUT/OUTPUT TIMING........................................................................................................86
9.8 POWER-UP AND POWER-DOWN ......................................................................................................88
9.9 PROGRAM/ERASE PERFORMANCE.................................................................................................89
9.10 RELIABILITY CHARACTERISTICS ...................................................................................................89
10.
PACKAGE TYPE INFORMATION.........................................................................................................90
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (B)............................90
10.2 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (K)......................................91
10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (L)......................................92
10.4 8-Pin 208mil VSOP Package (F) ........................................................................................................93
10.5 16-lead Plastic Small Outline package (300 mils body width) (M) .....................................................94
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
5
11/06/2015
IS25LP064A/032A
10.6 24-Ball Thin Profile Fine Pitch BGA 6x8mm 4x6 BALL ARRAY (G) ..................................................95
10.7 24-Ball Thin Profile Fine Pitch BGA 6x8mm 5x5 BALL ARRAY (H)...................................................96
ORDERING INFORMATION- Valid Part Numbers................................................................................97
11.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
6
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IS25LP064A/032A
1. PIN CONFIGURATION
CE#
1
Vcc
8
7
Vcc
8
CE# 1
HOLD# (IO3)(1)
SCK
SO (IO1)
2
(1)
SO (IO1)
2
7
6
5
HOLD# (IO3)
SCK
WP# (IO2)
GND
3
4
WP# (IO2)
GND
3
4
6
5
SI (IO0)
SI (IO0)
8-contact WSON 6x5mm
8-contact WSON 8x6mm
8-pin SOIC 208mil
8-pin VSOP 208mil
(1)
HOLD# (IO3)
Vcc
SCK
16
1
16-pin SOIC 300mil
SI (IO0)
NC
2
3
4
5
6
7
8
15
(2)
RESET#/NC
14
13
12
11
10
9
NC
NC
NC
NC
NC
NC
CE#
GND
WP# (IO2)
SO (IO1)
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Rev. A
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IS25LP064A/032A
Top View, Balls Facing Down
Top View, Balls Facing Down
A1
A2
A3
A4
(2)
A2
A3
A4
A5
NC
NC
NC
NC or RESET#
(2)
NC
NC
NC
NC or RESET#
B1
B2
B3
B4
B1
B2
B3
B4
B5
NC
SCK
GND
VCC
NC
SCK
GND
VCC
NC
C1
C2
C3
C4
C1
C2
C3
C4
C5
NC
CE#
NC
WP#(IO2)
NC
CE#
NC
WP#(IO2)
NC
D1
D2
D3
D4
(1)
HOLD# or
RESET# (IO3)
D1
D2
D3
D4
(1)
D5
NC
SO(IO1)
SI(IO0)
HOLD# or
RESET# (IO3)
NC
SO(IO1)
SI(IO0)
NC
E1
E2
E3
E4
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
24-ball TFBGA, 4x6 Ball Array (Package:G)
24-ball TFBGA, 5x5 Ball Array (Package:H)
Notes:
1. For RESET# (IO3) pin (or ball) option instead of HOLD# (IO3) pin (or ball), call Factory.
2. In case of 16-pin SOIC and 24-ball TFBGA packages, pin3/ball A4 will become NC or RESET# based on part
number. Below is the summary. Also see the Ordering Information on page 95.
Standard(1)
Dedicated RESET#(2)
RESET#
Pin3 or Ball A4
Pin1or Ball D4
NC
Hold#(IO3) or RESET#(IO3)
J or S
Hold#(IO3)
R or P
Part Number Option
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
8
11/06/2015
IS25LP064A/032A
2. PIN DESCRIPTIONS
For the device without dedicated RESET# function option on pin3/ball A4
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
When CE# is pulled low the device will be selected and brought out of standby
mode. The device is considered active and instructions can be written to, data read,
and written to the device. After power-up, CE# must transition from high to low
before a new instruction will be accepted.
CE#
INPUT
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
SI (IO0),
SO (IO1)
INPUT/OUTPUT
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the
WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are
write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the
Status Register is not write-protected regardless of WP# state.
WP# (IO2)
INPUT/OUTPUT
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
HOLD# or RESET#/Serial Data IO (IO3): When the QE bit of Status Register is set
to “1”, HOLD# pin or RESET# is not available since it becomes IO3. When QE=0,
the pin acts as HOLD# or RESET# and either one can be selected by the P7 bit
setting in Read Register. HOLD# will be selected if P7=0 (Default) and RESET# will
be selected if P7=1.
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
HOLD# (IO3) or
RESET# (IO3)
INPUT/OUTPUT
RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the
memory enters reset mode and output is High-Z. If RESET# is driven LOW while an
internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
SCK
Vcc
INPUT
POWER
GROUND
Unused
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
GND
NC
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
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11/06/2015
IS25LP064A/032A
For the device with dedicated RESET# function option on pin3/ball A4.
(pin1/ ball D4 will become HOLD# (IO3) pin, See the Ordering Information for the parts)
SYMBOL
TYPE
INPUT
DESCRIPTION
Same as the description in previous page
Same as the description in previous page
CE#
SI (IO0),
SO (IO1)
INPUT/OUTPUT
WP# (IO2)
INPUT/OUTPUT Same as the description in previous page
Hold/Serial Data IO (IO3): When the QE bit of Status Register is set to “1”, HOLD#
pin is not available since it becomes IO3. When QE=0 the pin acts as HOLD#.
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
HOLD# (IO3)
INPUT/OUTPUT
INPUT/OUTPUT
RESET: Dedicated RESET# function is available only for specific parts. The
RESET# pin (or ball) will be independent of the QE bit of Status Register.
The RESET# is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the
memory enters reset mode and output is High-Z. If RESET# is driven LOW while an
internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
RESET#
SCK
Vcc
INPUT
POWER
GROUND
Unused
Same as the description in previous page
Same as the description in previous page
Same as the description in previous page
Same as the description in previous page
GND
NC
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
10
11/06/2015
IS25LP064A/032A
3. BLOCK DIAGRAM
Control Logic
High Voltage Generator
Status
Register
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
CE#
SCK
WP#
(IO2)
Y-Decoder
SI
(IO0)
SO
(IO1)
(1)
HOLD# or RESET#
(IO3)
Memory Array
Address Latch &
Counter
Note1: For RESET# (IO3) pin option instead of HOLD# (IO3) pin, call Factory. In case of device with dedicated
RESET# function, RESET# is on pin3/ball A4. See the Ordering Information for the dedicated RESET# option.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11
11/06/2015
IS25LP064A/032A
4. SPI MODES DESCRIPTION
Multiple IS25LP064A/032A devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge
of Serial Clock (SCK), and the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SDI
SPI interface with
(0,0) or (1,1)
SCK
SCK SO SI
SCK SO SI
SCK SO SI
SPI Master
(i.e. Microcontroller)
SPI
SPI
SPI
Memory
Device
Memory
Device
Memory
Device
CS3
CS2
CS1
CE#
CE#
CE#
(1)
HOLD#(1)
HOLD#(1)
WP# HOLD#
WP#
WP#
Notes:
1. For RESET# (IO3) option instead of HOLD# (IO3), call Factory.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
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IS25LP064A/032A
Figure 4.2 SPI Mode Support
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
MSB
SI
SO
MSB
Figure 4.3 QPI Mode Support
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
3-byte Address
Mode Bits
Data 1
Data 2
Data 3
...
...
...
...
IO0
IO1
4
5
6
7
4
C4
C5
C6
C0
C1
C2
0
1
2
3
4
0
1
2
3
0
1
2
3
4
0
1
2
3
4
0
1
2
3
20
21
16
17
18
19
12
13
14
15
8
9
5
5
5
5
IO2
IO3
6
6
6
6
22
10
11
71
71
231
71
C71 C3
71
Note1: MSB (Most Significant Bit)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
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IS25LP064A/032A
5. SYSTEM CONFIGURATION
The memory array of the IS25LP064A/032A is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte
blocks (a block consists of eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25LP064A/032A
Block No.
(64Kbyte)
Block No.
(32Kbyte)
Sector Size
(Kbyte)
Memory Density
Sector No.
Address Range
Sector 0
4
:
000000h – 000FFFh
Block 0
Block 1
Block 2
Block 3
Block 4
:
:
Block 0
Block 1
:
:
:
Sector 15
4
4
:
00F000h - 00FFFFh
Sector 16
010000h – 010FFFh
:
:
:
:
:
Sector 31
4
4
:
01F000h - 01FFFFh
Sector 32
020000h – 020FFFh
32Mb
:
:
Block 2
:
:
:
Block 5
:
64Mb
Sector 47
4
02F000h – 02FFFFh
:
:
:
:
Sector 1008
4
:
3F0000h – 3F0FFFh
Block 126
:
:
Block 63
:
:
:
:
Block 127
:
Sector 1023
4
3FF000h – 3FFFFFh
:
:
:
Sector 2032
4
:
7F0000h – 7F0FFFh
Block 254
:
:
Block 127
:
:
:
Block 255
Sector 2047
4
7FF000h – 7FFFFFh
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6. REGISTERS
The IS25LP064A/032A has three sets of Registers: Status, Function and Read.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Table 6.1 & Table 6.2.
Table 6.1 Status Register Format
Bit 7
SRWD
0
Bit 6
QE
0
Bit 5
BP3
0
Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
Default
Table 6.2 Status Register Bit Definition
Read-
/Write
Bit
Name
Definition
Type
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Bit 0
WIP
R
Volatile
Volatile
Bit 1
WEL
R/W1
Bit 2
Bit 3
Bit 4
Bit 5
BP0
BP1
BP2
BP3
Block Protection Bit: (See Table 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
R/W
Non-Volatile
Quad Enable bit:
Bit 6
Bit 7
QE
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W
R/W
Non-Volatile
Non-Volatile
SRWD
Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.
The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0”
at factory. The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for write Status Register, program or
erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled and the write operations described in Table 6.3 are inhibited. When
the WEL bit is “1”, the write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction.
Each write register, program and erase instruction except for Set Read Register must be preceded by a WREN
instruction. The WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically reset after the
completion of any write operation.
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Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Operation
Name
Hex Code
02h
PP
Serial Input Page Program
Quad Input Page Program
Sector Erase
PPQ
32h/38h
D7h/20h
52h
SER
BER32 (32Kb)
BER64 (64Kb)
CER
Block Erase 32K
D8h
Block Erase 64K
C7h/60h
01h
Chip Erase
WRSR
WRFR
IRER
Write Status Register
Write Function Register
Erase Information Row
Program Information Row
42h
64h
IRP
62h
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not
write-protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register
(SRWD, QE, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is
set to “1” and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the
QE bit is set to “0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins
are enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.
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Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits
Status Register Bits
Protected Memory Area (IS25LP064A, 128Blocks)
BP3
0
BP2
0
BP1
0
BP0 TBS(T/B selection) = 0, Top area
TBS(T/B selection) = 1, Bottom area
0( None)
0
1
0
1
0
1
0
1
x
0( None)
0
0
0
1(1 block : 127th)
1(1 block : 0th)
0
0
1
2(2 blocks : 126th and 127th)
3(4 blocks : 124th to 127th)
4(8 blocks : 120th to 127th)
5(16 blocks : 112nd to 127th)
6(32 blocks : 96th to 127th)
7(64 blocks : 64th to 127th)
8~15(128 blocks : 0th to 127th) All blocks
2(2 blocks : 0th and 1st)
3(4 blocks : 0th to 3rd)
4(8 blocks : 0th to 7th)
0
0
1
0
1
0
0
1
0
5(16 blocks : 0th to 15th)
6(32 blocks : 0th to 31st)
7(64 blocks : 0th to 63rd)
8~15(128 blocks : 0th to 127th) All blocks
0
1
1
0
1
1
1
x
x
Status Register Bits
Protected Memory Area (IS25LP032A, 64Blocks)
BP3
0
BP2
0
BP1
0
BP0 TBS(T/B selection) = 0, Top area
TBS(T/B selection) = 1, Bottom area
0( None)
0
1
0
1
0
1
0
1
x
0( None)
0
0
0
1(1 block : 63rd)
1(1 block : 0th)
0
0
1
2(2 blocks : 62nd and 63rd)
3(4 blocks : 60th to 63rd)
4(8 blocks : 56th to 63rd)
5(16 blocks : 48th to 63rd)
6(32 blocks : 32nd to 63rd)
7(64 blocks : 0th to 63rd) All blocks
8~15(64 blocks : 0th to 63rd) All blocks
2(2 blocks : 0th and 1st)
3(4 blocks : 0th to 3rd)
0
0
1
0
1
0
4(8 blocks : 0th to 7th)
0
1
0
5(16 blocks : 0th to 15th)
6(32 blocks : 0th to 31st)
7(64 blocks : 0th to 63rd) All blocks
8~15(64 blocks : 0th to 63rd) All blocks
0
1
1
0
1
1
1
x
x
Note: x is don’t care
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6.2 FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6.
Table 6.5 Function Register Format
Bit 7
IRL3
0
Bit 6
IRL2
0
Bit 5
IRL1
0
Bit 4
IRL0
0
Bit 3
ESUS
0
Bit 2
PSUS
0
Bit 1
TBS
0
Bit 0
Reserved
0
Default
Table 6.6 Function Register Bit Definition
Read-
/Write
Bit
Name
Definition
Type
Bit 0
Reserved
Reserved
R
Reserved
Top/Bottom Selection. (See Table 6.4 for details)
“0” indicates Top area.
“1” indicates Bottom area.
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
Lock the Information Row 0:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 1:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 2:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 3:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Top/Bottom
Selection
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
R/W
OTP
Volatile
Volatile
OTP
PSUS
R
ESUS
R
IR Lock 0
IR Lock 1
IR Lock 2
IR Lock 3
R/W
R/W
R/W
R/W
OTP
OTP
OTP
Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.
Top/Bottom Selection: BP0~3 area assignment can be changed from Top (default) to Bottom by setting TBS
bit to “1”. However, once Bottom is selected, it cannot be changed back to Top since TBS bit is OTP. See Table
6.4 for details
The Program Suspend Status bit indicates when a Program operation has been suspended. The
PSUS changes to “1” after a suspend command is issued during the program operation. Once the suspended
Program resumes, the PSUS bit is reset to “0”.
ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is
“1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the
ESUS bit is reset to “0”.
IR Lock bit 0 ~ 3: The default is “0” so that the Information Row can be programmed. If the bit set to “1”, the
Information Row can’t be programmed. Once it set to “1”, it cannot be changed back to “0” since IR Lock bits are
OTP.
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6.3 READ REGISTER
Read Register format and Bit definitions pertaining to QPI mode are described below.
READ PARAMETER BITS
Table 6.7 defines all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (P7, P6, P5) bits
provide a method to set and control driver strength. The Dummy Cycle bits (P4, P3) define how many dummy
cycles are used during various READ modes. The wrap selection bits (P2, P1, P0) define burst length with wrap
around.
The SET READ PARAMETERS Operation (SRP, C0h) is used to set all the Read Register bits, and can thereby
define the output driver strength, number of dummy cycles used during READ modes, burst length with wrap
around.
Table 6.7 Read Parameter Table
P7
ODS2
1
P6
ODS1
1
P5
ODS0
1
P4
P3
P2
P1
P0
Dummy
Cycles
Dummy
Cycles
Wrap
Enable
Burst
Length
Burst
Length
Default (Volatile)
0
0
0
0
0
Table 6.8 Burst Length Data
P1
0
P0
8 bytes
0
1
0
1
16 bytes
32 bytes
64 bytes
0
1
1
Table 6.9 Wrap Function
P2
0
Wrap around boundary
Whole array regardless of P1 and P0 value
Burst Length set by P1 and P0
1
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Table 6.10 Read Dummy Cycles vs Max Frequency
P4,P3 = 00
Read Modes
P4,P3 = 01
P4,P3 = 10
P4,P3 = 11
Remark
Mode
(Default)
Normal Read
03h
0
8
0
8
0
8
0
8
Max. 50MHz
SPI
SPI
Max. 133MHz(1)
Fast Read (2)
0Bh
6
4
8(1)
(133MHz)
10(1)
(133MHz)
QPI
(104MHz)
(84MHz)
4
4
4
4
Max.66MHz
SPI
Fast Read DTR
0Dh
3
2
4
5
QPI
(51MHz)
(38MHz)
(64MHz)
(66MHz)
Fast Read Dual Output
3Bh
8
8
8
8
Max. 133MHz(1)
SPI
Fast Read Dual IO
BBh
4
4
8(1)
(133MHz)
8(1)
(133MHz)
SPI
(104MHz)
(104MHz)
Fast Read Dual IO DTR
BDh
2
2
4
4
SPI
(52MHz)
(52MHz)
(66MHz)
(66MHz)
Fast Read Quad Output
6Bh
8
8
8
8
Max. 133MHz(1)
SPI
Fast Read Quad IO
EBh
6
4
8(1)
(133MHz)
10(1)
(133MHz)
SPI , QPI
SPI , QPI
(104MHz)
(84MHz)
Fast Read Quad IO DTR
EDh
3
2
4
5
(51MHz)
(38MHz)
(64MHz)
(66MHz)
Notes:
1. Max frequency is 133 MHz at Vcc=2.7V~3.6V and 104MHz at Vcc=2.3V~3.6V.
2. RDUID, RDSFDP, IRRD instructions are also applied.
3. Dummy cycles in the table are including Mode bit cycles.
4. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bit cycles are same, then X
must be Hi-Z.
Table 6.11 Driver Strength Table
ODS2
ODS1
ODS0
Description
Reserved
12.50%
25%
Remark
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
37.50%
Reserved
75%
100%
50%
Default
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7. PROTECTION MODE
The IS25LP064A/032A supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD,
and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence
will be ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Low
Low
High
High
Status Register
Writable
0
1
0
1
Protected
Writable
Writable
Note: Before the execution of any program, erase or write Status/Function Register instruction, the Write Enable
Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not
enabled, the program, erase or write register instruction will be ignored.
7.2 SOFTWARE WRITE PROTECTION
The IS25LP064A/032A also provides a software write protection feature. The Block Protection (TBS, BP3, BP2,
BP1, BP0) bits allow part or the whole memory area to be write-protected.
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8. DEVICE OPERATION
The IS25LP064A/032A utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on
instructions and instruction codes. All instructions, addresses, and data are shifted in with the most significant bit
(MSB) first on Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is
latched on the rising edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR
mode after Chip Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction
code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type
of instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to
end the operation.
Table 8.1 Instruction Set
Instruction
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Name
NORD
FRD
Normal Read
Mode
A
A
A
<7:0>
SPI
03h
0Bh
Data out
<23:16>
<15:8>
Fast Read
Mode
SPI
QPI
A
A
A
<7:0>
Dummy(1)
Byte
Data out
<23:16>
<15:8>
A
A
A
<7:0>
Dual
Fast Read
Dual I/O
AXh(1),(2)
Dual
Dual
Data out
FRDIO
FRDO
FRQIO
SPI
SPI
BBh
3Bh
EBh
<23:16>
Dual
<15:8>
Dual
Fast Read
Dual Output
A
A
A
<7:0>
Dummy(1)
Byte
Dual
Data out
<23:16>
<15:8>
A
A
A
<7:0>
Quad
Fast Read
Quad I/O
SPI
QPI
AXh(1), (2)
Quad
Quad
Data out
<23:16>
Quad
<15:8>
Quad
Fast Read
Quad Output
A
A
A
<7:0>
Dummy(1)
Byte
Dummy(1)
Byte
Quad
Data out
FRQO
SPI
6Bh
0Dh
<23:16>
<15:8>
Fast Read
DTR Mode
SPI
QPI
A
A
A
<7:0>
Dual
Data out
FRDTR
<23:16>
<15:8>
A
A
A
<7:0>
Dual
Fast Read
Dual I/O DTR
AXh(1), (2)
Dual
Dual
Data out
FRDDTR
SPI
BDh
<23:16>
Dual
<15:8>
Dual
Fast Read
Quad I/O DTR
SPI
QPI
A
A
A
<7:0>
AXh(1), (2)
Quad
Quad
Data out
FRQDTR
PP
EDh
02h
<23:16>
<15:8>
Input Page
Program
SPI
QPI
A
A
A
<7:0>
PD
(256byte)
<23:16>
<15:8>
Quad Input
Page Program
32h
38h
A
A
A
<7:0>
Quad PD
(256byte)
PPQ
SPI
<23:16>
<15:8>
SPI
QPI
D7h
20h
A
A
A
<7:0>
SER
Sector Erase
<23:16>
<15:8>
BER32
(32Kb)
Block Erase
32K
SPI
QPI
A
A
A
<7:0>
52h
D8h
<23:16>
<15:8>
BER64
(64Kb)
Block Erase
64K
SPI
QPI
A
A
A
<7:0>
<23:16>
<15:8>
SPI
QPI
C7h
60h
CER
WREN
WRDI
RDSR
WRSR
Chip Erase
Write Enable
Write Disable
SPI
QPI
06h
04h
05h
01h
SPI
QPI
Read Status
Register
SPI
QPI
SR
Write Status
Register
SPI
QPI
WSR
Data
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Instruction
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Read Function
Register
SPI
QPI
Data
out
RDFR
WRFR
QPIEN
QPIDI
48h
42h
35h
F5h
Write Function
Register
SPI
QPI
WFR
Data
Enter
QPI mode
SPI
QPI
Exit
QPI mode
Suspend during
program/erase
SPI
QPI
75h
B0h
PERSUS
PERRSM
DP
Resume
program/erase
SPI
QPI
7Ah
30h
Deep Power
Down
SPI
QPI
B9h
ABh
Read ID /
Release
Power Down
RDID,
RDPD
SPI
QPI
XXh(3)
XXh(3)
XXh(3)
ID7-ID0
Set Read
Parameters
SPI
QPI
SRP
C0h
9Fh
Data in
Read JEDEC
ID Command
SPI
QPI
RDJDID
MF7-MF0
ID15-ID8
XXh(3)
ID7-ID0
Read
Manufacturer
& Device ID
00h
01h
MF7-MF0
ID7-ID0
ID7-ID0
SPI
QPI
RDMDID
90h
XXh(3)
MF7-MF0
Read JEDEC ID
QPI mode
RDJDIDQ
RDUID
RDSFDP
NOP
QPI
AFh
4Bh
5Ah
00h
MF7-MF0
ID15-ID8
ID7-ID0
Read
Unique ID
SPI
QPI
A(4)
<23:16>
A(4)
<15:8>
A(4)
<7:0>
Dummy
Byte
Data out
Data out
SPI
QPI
A
A
A
<7:0>
Dummy
Byte
SFDP Read
<23:16>
<15:8>
SPI
QPI
No Operation
Software
Reset
Enable
SPI
QPI
RSTEN
RST
66h
99h
64h
SPI
QPI
Software Reset
Erase
Information
Row
SPI
QPI
A
A
A
IRER
<23:16>
<15:8>
<7:0>
Program
Information
Row
Read
Information
SPI
QPI
A
A
A
<7:0>
PD
(256byte)
IRP
62h
68h
<23:16>
<15:8>
SPI
QPI
A
A
A
<7:0>
Dummy
Byte
IRRD
Data out
<23:16>
<15:8>
Row
SECUN-
LOCK
SPI
QPI
A
A
A
<7:0>
Sector Unlock
Sector Lock
26h
24h
<23:16>
<15:8>
SPI
QPI
SECLOCK
Notes:
1. The number of dummy cycles depends on the value setting in the Table 6.10 Read Dummy Cycles.
2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.
3. XX means “don’t care”.
4. A<23:9> are “don’t care” and A<8:4> are always “0”.
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8.1 NORMAL READ OPERATION (NORD, 03h)
The NORMAL READ (NORD) instruction is used to read memory contents of the IS25LP064A/032A at a
maximum frequency of 50MHz.
The NORD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first
memory location to be read. A total of 24 address bits are shifted in, but only AMSB (most significant bit) - A0 are
decoded. The remaining bits (A23 – AMSB+1) are ignored. The first byte addressed can be at any memory
location. Upon completion, any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole
memory array, can be read out in one NORMAL READ instruction. The address is automatically incremented by
one after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high
(VIH) after the data comes out. When the highest address of the device is reached, the address counter will roll
over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.
If the NORMAL READ instruction is issued while an Erase, Program or Write operation is in process (WIP=1)
the instruction is ignored and will not have any effects on the current operation.
Table 8.2 Address Key
Address
IS25LP064A
IS25LP032A
AMSB – A0
A23 - A0 (A23=X)
A23 - A0 (A23,A22=X)
X=Don’t Care
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Figure 8.1 Normal Read Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
...
SI
3
Instruction = 03h
2
1
0
23
22
High Impedance
SO
CE#
SCK
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
...
SI
Data Out 1
Data Out 2
SO
...
1
0
1
0
3
6
5
4
3
2
7
6
5
4
2
7
tV
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8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from
the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling
edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST
READ instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
29
...
28
29
30
31
Mode 3
Mode 0
SCK
SI
3-byte Address
...
3
Instruction = 0Bh
2
1
0
31
30
High Impedance
SO
CE#
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
...
SCK
SI
Dummy Cycles
Data Out
tV
SO
...
1
0
3
7
6
5
4
2
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FAST READ QPI OPERATION (FRD QPI, 0Bh)
The FAST READ QPI (FRD QPI) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ QPI instruction code (2 clocks) is followed by three address bytes (A23-A0—6clocks) and 6
dummy cycles (configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each bit
latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1
and IO0 lines, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ QPI instruction. The FAST
READ QPI instruction is terminated by driving CE# high (VIH).
If the FAST READ QPI instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored without affecting the current cycle.
Table 8.3 Instructions that Fast Read QPI sequence is applied to
Instruction Name
Operation
Hex Code
FRQIO
Fast Read Quad I/O
EBh
RDUID
Read Unique ID
SFDP Read
4Bh
RDSFDP
IRRD
5Ah
Read Information Row
68h
Figure 8.3 Fast Read QPI Sequence
CE#
0
1
2
3
4
5
6
7
8
9
...
13
14
15
16
17
...
Mode 3
Mode 0
SCK
tV
...
IO[3:0]
0Bh
Instruction
23:20 19:16 15:12 11:8 7:4 3:0
3-byte Address
7:4 3:0
Data 1
7:4 3:0
Data 2
6 Dummy Cycles
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.10 Read
Dummy Cycles.
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8.3 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the IS25LP064A/032A. When the device is selected and a
serial sequence is underway, HOLD# can be used to pause the serial communication with the master device
without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume
serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD).
Inputs to SI will be ignored while SO is in the high impedance state, during HOLD.
Note: HOLD is not supported in DTR mode or with QE=1 or for the specific parts that do not have HOLD# pin.
Timing graph can be referenced in AC Parameters Figure 9.4
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)
The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directly
from the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 – A0) and dummy cycles (configurable,
default is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the rising edge
of SCK. The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to alternate
between the two lines. Depending on the usage of AX read operation mode, a mode byte may be located after
address input.
The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK. The MSB is output on IO1, while simultaneously the
second bit is output on IO0. Figure 8.4 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as
described in Figure 8.5. When the code is different from AXh (where X is don’t care), the device exits the AX
read operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycle in Table 6.10 includes number of mode bit cycles. If dummy cycles is configured as 4 cycles, data output
will starts right after mode bit applied.
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
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Figure 8.4 Fast Read Dual I/O Sequence (with command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
...
18
19
20
21
Mode 3
Mode 0
SCK
4 Dummy Cycles
3-byte Address
...
IO0
IO1
2
3
Instruction = BBh
0
1
6
7
4
22
23
20
21
18
High Impedance
...
5
19
Mode Bits
CE#
SCK
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
...
tV
...
...
IO0
IO1
2
0
1
4
5
0
1
2
0
1
6
7
2
6
7
6
7
6
7
4
2
0
1
4
4
Data Out 1
Data Out 2
Data Out 3
3
5
3
3
5
3
5
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10. Read Dummy Cycles.
3. Since the number of dummy cycles and AX bit cycles are same in the above Figure, X should be Hi-Z to avoid I/O
contention.
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Figure 8.5 Fast Read Dual I/O AX Read Sequence (without command decode cycles)
CE#
...
0
1
2
3
11
12
13
14
15
16
17
18
19
20
21
...
Mode 3
Mode 0
SCK
4 Dummy Cycles
tV
3-byte Address
Data Out 1
Data Out 2
4
...
...
IO0
IO1
2
3
6
7
2
6
7
2
0
1
4
0
1
4
0
1
6
7
22
23
20
21
18
...
...
3
3
5
5
5
19
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bit cycles are same in the above Figure, X should be Hi-Z to avoid I/O
contention.
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8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)
The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.
The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),
transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte
addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT,
during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously the second bit is output on
IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction
is terminated by driving CE# high (VIH).
If the FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction
is ignored and will not have any effects on the current cycle.
Figure 8.6 Fast Read Dual Output Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
...
3
IO0
IO1
Instruction = 3Bh
2
1
0
23
22
High Impedance
CE#
SCK
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
...
tV
...
...
IO0
IO1
0
1
2
6
7
4
6
7
4
2
0
1
8 Dummy Cycles
Data Out 1
Data Out 2
3
5
5
3
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8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh)
The FRQO instruction is used to read memory data on four output pins each at up to a 133 MHz clock.
The FRQO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),
transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte
addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a
maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while
simultaneously the second bit is output on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is
terminated by driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction
is ignored and will not have any effects on the current cycle.
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Figure 8.7 Fast Read Quad Output Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
IO0
3-byte Address
...
3
Instruction = 6Bh
2
1
0
23
22
High Impedance
IO1
IO2
IO3
High Impedance
High Impedance
CE#
SCK
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
...
tV
...
IO0
IO1
IO2
IO3
0
4
4
0
4
0
4
0
8 Dummy Cycles
Data Out 1 Data Out 2 Data Out 3 Data Out 4
1
...
...
5
5
1
5
1
5
1
2
6
6
2
6
2
6
2
3
...
7
7
3
7
3
7
3
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8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)
The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be
executed directly from the SPI in some applications.
The FRQIO instruction code is followed by three address bytes (A23 – A0) and dummy cycles (configurable,
default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each group of four bits latched-in during
the rising edge of SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit
on IO0, and continue to shift in alternating on the four. Depending on the usage of AX read operation mode, a
mode byte may be located after address input.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits
shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3,
while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.8 illustrates the
timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consists of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX
read operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycle in Table 6.10 includes number of mode bit cycles. If dummy cycles is configured as 6 cycles, data output
will starts right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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Figure 8.8 Fast Read Quad I/O Sequence (with command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
3-byte Address
IO0
IO1
4
5
6
7
Instruction = EBh
High Impedance
0
1
2
3
4
5
6
7
0
1
2
3
20
21
22
23
16
17
18
19
12
13
14
15
8
9
IO2
IO3
10
11
Mode Bits
CE#
SCK
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
...
6 Dummy Cycles
Data Out 1 Data Out 2 Data Out 3 Data Out 4
Data Out 5 Data Out 6
tV
...
...
...
...
IO0
IO1
0
1
2
3
4
5
6
7
4
5
6
7
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
5
6
7
0
1
2
3
0
1
2
3
IO2
IO3
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
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Figure 8.9 Fast Read Quad I/O AX Read Sequence (without command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
Mode 3
Mode 0
SCK
6 Dummy Cycles
3-byte Address
Data Out 1 Data Out 2
tV
...
...
...
...
IO0
IO1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
4
5
6
7
20
21
22
23
16
17
18
19
12
13
14
15
8
9
0
1
2
3
IO2
IO3
10
11
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
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FAST READ QUAD I/O QPI OPERATION (FRQIO QPI, EBh)
The FRQIO QPI instruction is used to read memory data at up to a 133MHz clock.
The FRQIO QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRQIO instruction requires that the byte-long instruction code is shifted into the device only
via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQIO QPI instruction. In
addition, subsequent address and data out are shifted in/out via all four IO lines like the FRQIO instruction. In
fact, except for the command cycle, the FRQIO QPI operation is exactly same as the FRQIO.
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX
read operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycles in Table 6.10 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles, data
output will start right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO QPI instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
Figure 8.10 Fast Read Quad I/O QPI Sequence
CE#
...
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
...
Mode 3
Mode 0
SCK
tV
Mode Bits
7:4 3:0
...
IO[3:0]
23:20 19:16 15:12 11:8 7:4 3:0
3-byte Address
EBh
Instruction
7:4 3:0
Data 1
7:4 3:0
Data 2
6 Dummy Cycles
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.10 Read
Dummy Cycles.
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8.8 PAGE PROGRAM OPERATION (PP, 02h)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP3, BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is
write-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be
enabled through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line.
Program operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be
executed. The internal control logic automatically handles the programming voltages and timing. During a
program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of
the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has
completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
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Figure 8.11 Page Program Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
...
...
...
Mode 3
Mode 0
SCK
3-byte Address
Data In 1
Data In 256
SI
...
...
6
...
0
7
0
0
Instruction = 02h
7
23
22
High Impedance
SO
Figure 8.12 Page Program QPI Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
...
Mode 3
Mode 0
SCK
02h
23:20 19:16 15:12 11:8 7:4 3:0
3-byte Address
7:4 3:0
Data In 1
7:4 3:0 7:4 3:0
Data In 2 Data In 3
7:4 3:0
Data In 4
IO[3:0]
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8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a
single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must
be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input
Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before
the execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and
the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are
input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought
high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic
automatically handles the programming voltages and timing. During a program operation, all instructions will be
ignored except the RDSR instruction. The progress or completion of the program operation can be determined
by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is
still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
Figure 8.13 Quad Input Page Program Sequence
CE#
0
1
2
3
4
5
6
7
8
9
...
31
32
33
34
35
...
Mode 3
Mode 0
SCK
3-byte Address
Data In 1
Data In 2
...
...
...
...
IO0
IO1
...
4
5
6
7
Instruction = 32h/38h
High Impedance
0
1
2
3
4
5
6
7
0
1
2
3
23
22
0
IO2
IO3
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8.10 ERASE OPERATION
The memory array of the IS25LP064A/032A is organized into uniform 4 Kbyte sectors or 32/64 Kbyte uniform
blocks (a block consists of eight/sixteen adjacent sectors respectively).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without
affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation
erases the whole memory array of a device. A sector erase, block erase, or chip erase operation can be
executed prior to any programming operation.
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8.11 SECTOR ERASE OPERATION (SER, D7h/20h)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after
the completion of Sector Erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire
instruction sequence The SER instruction code, and three address bytes are input via SI. Erase operation will
start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and
timing.
During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction.
The progress or completion of the erase operation can be determined by reading the WIP bit in the Status
Register using a RDSR instruction.
If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been
completed.
Figure 8.14 Sector Erase Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
...
SI
3
Instruction = D7h/20h
High Impedance
2
1
0
23
22
SO
Figure 8.15 Sector Erase QPI Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
SCK
Mode 0
3-byte Address
23:20 19:16 15:12 11:8 7:4 3:0
D7h/20h
IO[3:0]
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8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64 Kbyte block. Before the execution of a BER instruction, the
Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically
after the completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic
automatically handles the erase voltage and timing.
Figure 8.16 Block Erase (64K) Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
...
SI
3
Instruction = D8h
2
1
0
23
22
High Impedance
SO
Figure 8.17 Block Erase (64K) QPI Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
3-byte Address
23:20 19:16 15:12 11:8 7:4 3:0
D8h
IO[3:0]
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Figure 8.18 Block Erase (32K) Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
SI
...
3
Instruction = 52h
2
1
0
23
22
High Impedance
SO
Figure 8.19 Block Erase (32K) QPI Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
3-byte Address
23:20 19:16 15:12 11:8 7:4 3:0
52h
IO[3:0]
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8.13 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the
Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset
after completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
Figure 8.20 Chip Erase Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction = C7h/60h
High Impedance
SI
SO
Figure 8.21 Chip Erase QPI Sequence
CE#
0
1
Mode 3
Mode 0
SCK
C7h/60h
IO[3:0]
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8.14 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to
the write-protected state after power-up. The WEL bit must be write enabled before any write operation,
including Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Status
Register, and Write Function Register operations. The WEL bit will be reset to the write-protected state
automatically upon completion of a write operation. The WREN instruction is required before any above
operation is executed.
Figure 8.22 Write Enable Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction = 06h
SI
High Impedance
SO
Figure 8.23 Write Enable QPI Sequence
CE#
0
1
Mode 3
Mode 0
SCK
06h
IO[3:0]
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8.15 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.24 Write Disable Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction = 04h
SI
High Impedance
SO
Figure 8.25 Write Disable QPI Sequence
CE#
0
1
Mode 3
Mode 0
SCK
04h
IO[3:0]
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8.16 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a
program, erase or write Status Register operation, all other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of
Status Register.
Figure 8.26 Read Status Register Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
SI
Instruction = 05h
tV
Data Out
SO
3
2
1
0
7
6
5
4
Figure 8.27 Read Status Register QPI Sequence
CE#
0
1
2
3
Mode 3
SCK
Mode 0
tV
IO[3:0]
05h
7:4 3:0
Data Out
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8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and
Status Register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, and
SRWD bits. Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into
the non-volatile QE bit.
Figure 8.28 Write Status Register Sequence
CE#
0
1
2
3
4
5
6
7
8
7
9
6
10
11
12
13
14
15
Mode 3
Mode 0
SCK
Data In
SI
Instruction = 01h
2
1
0
3
5
4
High Impedence
SO
Figure 8.29 Write Status Register QPI Sequence
CE#
0
1
2
3
Mode 3
Mode 0
SCK
IO[3:0]
01h
7:4 3:0
Data In
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8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)
The Read Function Register (RDFR) instruction provides access to the Function Register. Refer to Table 6.6
Function Register Bit Definition for more detail.
Figure 8.30 Read Function Register Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
SI
Instruction = 48h
tV
Data Out
SO
3
2
1
0
7
6
5
4
Figure 8.31 Read Function Register QPI Sequence
CE#
0
1
2
3
Mode 3
SCK
Mode 0
tV
IO[3:0]
48h
7:4 3:0
Data Out
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8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)
The Write Function Register (WRFR) instruction allows the user to change from top block area (default) to
bottom block area by setting TBS bit to “1”.
Also Information Row Lock bits (IRL3~IRL0) can be set to “1” individually by WRFR instruction in order to lock
Information Row. Since TBS bit and IRL bits are OTP, once it is set to “1”, it cannot be set back to “0” again.
Figure 8.32 Write Function Register Sequence
CE#
0
1
2
3
4
5
6
7
8
7
9
6
10
11
12
13
14
15
Mode 3
Mode 0
SCK
Data In
SI
Instruction = 42h
2
1
0
3
5
4
High Impedence
SO
Figure 8.33 Write Function Register QPI Sequence
CE#
0
1
2
3
Mode 3
SCK
Mode 0
IO[3:0]
42h
7:4 3:0
Data In
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8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h)
The Enter Quad Peripheral Interface (QPIEN) instruction, 35h, enables the Flash device for QPI mode operation.
Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power
cycle or an Exit Quad Peripheral Interface (QPIDI) instruction is sent to device.
The Exit Quad Peripheral Interface (QPIDI) instruction, F5h, resets the device to 1-bit SPI protocol operation. To
execute a QPIDI instruction, the host drives CE# low, sends the QPIDI command cycle, then drives CE# high.
The device just accepts QPI (2 clocks) command cycles.
Figure 8.34 Enter Quad Peripheral Interface (QPI) Mode Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction = 35h
SI
High Impedance
SO
Figure 8.35 Exit Quad Peripheral Interface (QPI) Mode Sequence
CE#
0
1
Mode 3
Mode 0
SCK
F5h
IO[3:0]
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8.21 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other
operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. (SPI/QPI all acceptable)
Function Register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing: 100µs
Resume to another suspend timing: 400µs
PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-Erase (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of Sector Erase and Block Erase operations. After the
Program/Erase Suspend, WEL bit will be disabled, therefore only read related, resume and reset commands
can be accepted. Refer to Table 8.3 for more detail.
To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the erase has been
suspended by changing the ESUS bit from “0” to “1”, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
the specified time tSUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.
PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of all array program operations. After the Program/Erase
Suspend command, WEL bit will be disabled, therefore only read related, resume and reset command can be
accepted. Refer to Table 8.3 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the programming has
been suspended by changing the PSUS bit from “0” to “1”, but the device will not accept another command until
it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or
wait the specified time tSUS
.
PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)
The Program/Erase Resume restarts the Program or Erase command that was suspended, and changes the
suspend status bit in the Function Register (ESUS or PSUS bits) back to “0”. To execute the Program/Erase
Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then
drives CE# high. A cycle is two nibbles long, most significant nibble first. To determine if the internal, self-timed
Write operation completed, poll the WIP bit in the Status Register, or wait the specified time tSE, tBE or tPP for
Sector Erase, Block Erase, or Page Programming, respectively. The total write time before suspend and after
resume will not exceed the uninterrupted write times tSE, tBE or tPP.
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Table 8.4 Instructions accepted during Suspend
Operation
Instruction Allowed
Operation
Suspended
Name
Hex Code
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
Program or Erase
NORD
FRD
03h
Read Data Bytes from Memory at Normal Read Mode
Read Data Bytes from Memory at Fast Read Mode
Fast Read Dual I/O
0Bh
BBh
3Bh
EBh
6Bh
0Dh
BDh
EDh
05h
FRDIO
FRDO
Fast Read Dual Output
FRQIO
FRQO
FRDTR
FRDDTR
FRQDTR
RDSR
Fast Read Quad I/O
Fast Read Quad Output
Fast Read DTR Mode
Fast Read Dual I/O DTR
Fast Read Quad I/O DTR
Read Status Register
RDFR
48h
Read Function Register
PERRSM
RDID
7Ah/30h
ABh
C0
Resume program/erase
Read Manufacturer and Product ID
Set Read Parameters (Volatile)
Read Manufacturer and Product ID by JEDEC ID Command
Read Manufacturer and Device ID
Read JEDEC ID QPI mode
Read Unique ID Number
SRP
RDJDID
RDMDID
RDJDIDQ
RDUID
RDSFDP
NOP
9Fh
90h
AFh
4Bh
5Ah
00h
SFDP Read
No Operation
RSTEN
RST
66h
Software reset enable
99h
Reset (Only along with 66h)
Read Information Row
IRRD
68h
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8.22 ENTER DEEP POWER DOWN (DP, B9h)
The Enter Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption
(enter into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the
Power-down mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction
is initiated by driving the CE# pin low and shifting the instruction code into the device. The CE# pin must be
driven high after the instruction has been latched, or Power-down mode will not engage. Once CE# pin driven
high, the Power-down mode will be entered within the time duration of tDP. While in the Power-down mode only
the Release from Power-down/RDID instruction, which restores the device to normal operation, will be
recognized. All other instructions are ignored, including the Read Status Register instruction which is always
available during normal operation. Ignoring all but one instruction makes the Power Down state a useful
condition for securing maximum write protection. It is available in both SPI and QPI mode.
Figure 8.36 Enter Deep Power Down Mode Sequence
CE#
SCK
tDP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SI
Instruction = B9h
High Impedance
SO
Figure 8.37 Enter Deep Power Down Mode QPI Sequence
tDP
CE#
0
1
Mode 3
Mode 0
SCK
B9h
IO[3:0]
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8.23 RELEASE DEEP POWER DOWN (RDPD, ABh)
The Release Deep Power-down/Read Device ID instruction is a multi-purpose command. To release the device
from the Power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code
“ABh” and driving CE# high.
Releasing the device from Power-down mode will take the time duration of tRES1 before normal operation is
restored and other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If
the Release Deep Power-down/RDID instruction is issued while an Erase, Program or Write cycle is in progress
(WIP=1) the instruction is ignored and will not have any effects on the current cycle.
Figure 8.38 Release Power Down Sequence
CE#
SCK
tRES1
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SI
Instruction = ABh
High Impedance
SO
Figure 8.39 Release Power Down QPI Sequence
tRES1
CE#
0
1
Mode 3
SCK
Mode 0
ABh
IO[3:0]
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8.24 SET READ PARAMETERS OPERATION (SRP, C0h)
Set Read Operational Driver Strength
This device supports configurable Operational Driver Strengths in both SPI and QPI modes by setting three bits
within the Read Register (ODS0, ODS1, ODS2). To set the ODS bits the SRP operation (C0h) instruction is
required. The device’s driver strength can be reduced as low as 12.50% of full drive strength. Details regarding
the driver strength can be found in Table 6.11.
Note: The default driver strength is set to 50%
Figure 8.40 Set Read Parameters Sequence
CE#
0
1
2
3
4
5
6
7
8
7
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
Data In
SI
Instruction = C0h
2
1
0
3
6
5
4
High Impedence
SO
Figure 8.41 Set Read Parameters QPI Sequence
CE#
0
1
2
3
Mode 3
Mode 0
SCK
IO[3:0]
C0h
7:4 3:0
Data In
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Read with “8/16/32/64-Byte Wrap Around”
The device is capable of burst read with wrap around in both SPI and QPI mode. The size of burst length is
configurable by using P0, P1, and P2 bits in Read Register. P2 bit (Wrap enable) enables the burst mode
feature. P0 and P1 define the size of burst. Burst lengths of 8, 16, 32, and 64 bytes are supported. By default,
address increases by one up through the entire array. By setting the burst length, the data being accessed can
be limited to the length of burst boundary within a 256 byte page. The first output will be the data at the initial
address which is specified in the instruction. Following data will come out from the next address within the burst
boundary. Once the address reaches the end of boundary, it will automatically move to the first address of the
boundary. CE# high will terminate the command.
For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from
address 00h and continue to 01h,..,07h, 00h, 01h… until CE# terminates the operation. If burst length of 8 and
initial address being applied is FEh(254d), following byte output will be from address FEh and continue to FFh,
F8h, F9h, FAh, FBh, FCh, FDh, and repeat from FEh until CE# terminates the operation.
The command, “SET READ PARAMETERS OPERATION (C0h)”, is used to configure the burst length. If the
following data input is one of “00h”,”01h”,”02h”, and ”03h”, the device will be in default operation mode. It will be
continuous burst read of the whole array. If the following data input is one of “04h”,”05h”,”06h”, and ”07h”, the
device will set the burst length as 8,16,32 and 64 respectively.
To exit the burst mode, another “C0h” command is necessary to set P2 to 0. Otherwise, the burst mode will be
retained until either power down or reset operation. To change burst length, another “C0h” command should be
executed to set P0 and P1 (Detailed information in Table 6.8 Burst Length Data). All read commands operate in
burst mode once the Read Register is set to enable burst mode.
Refer to Figures 8.40 and 8.41 for instruction sequence.
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8.25 READ PRODUCT IDENTIFICATION (RDID, ABh)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI
and QPI modes. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit
Electronic Signature, whose values are shown as table of Product Identification.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising
SCK edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDID instruction is ended by driving CE# high. The Device ID (ID7-ID0) outputs
repeatedly if additional clock cycles are continuously sent to SCK while CE# is at low.
Table 8.5 Product Identification
Manufacturer ID
ISSI Serial Flash
Instruction
Device Density
32Mb
(MF7-MF0)
9Dh
ABh
90h
9Fh
Memory Type + Capacity
(ID15-ID0)
Device ID (ID7-ID0)
15h
16h
6016h
6017h
64Mb
Figure 8.42 Read Product Identification Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
Mode 3
Mode 0
SCK
SI
Instruction = ABh
3 Dummy Bytes
Data Out
tV
Device ID
(ID7-ID0)
SO
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Figure 8.43 Read Product Identification Sequence (QPI)
CE#
0
1
2
3
4
5
6
7
8
9
Mode 3
Mode 0
SCK
tV
Device ID
(ID7-ID0)
ABh
6 Dummy Cycles
IO[3:0]
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8.26 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to
Table 8.5 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh in
SPI mode and QPI mode, AFh in QPI mode) is input, the Manufacturer ID is shifted out MSB first followed by
the 2-byte electronic ID (ID15-ID0) that indicates Memory Type and Capacity, one bit at a time. Each bit is
shifted out during the falling edge of SCK. If CE# stays low after the last bit of the 2-byte electronic ID, the
Manufacturer ID and 2-byte electronic ID will loop until CE# is pulled high.
and 2-byte electronic ID will loop until CE# is pulled high.
Figure 8.44 RDJDID (Read JEDEC ID in SPI Mode) Sequence
CE#
0
1
...
7
8
9
...
15
16
17
...
23
24
25
...
31
Mode 3
Mode 0
SCK
SI
Instruction = 9Fh
tV
Manufacturer ID
(MF7-MF0)
Capacity
(ID7-ID0)
Memory Type
(ID15-ID8)
SO
Figure 8.45 RDJDID and RDJDIDQ (Read JEDEC ID) Sequence in QPI Mode
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
tV
9Fh/AFh
IO[3:0]
7:4 3:0 7:4 3:0 7:4 3:0
MF7-MF0 ID15-ID8 ID7-ID0
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8.27 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)
The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the Manufacturer
and product ID of devices. Refer to Table 8.4 Product Identification for Manufacturer ID and Device ID. The
RDMDID instruction code is followed by two dummy bytes and one byte address (A7~A0), each bit being
latched-in on SI during the rising edge of SCK. If one byte address is initially set as A0 = 0, then the
Manufacturer ID is shifted out on SO with the MSB first followed by the Device ID (ID7- ID0). Each bit is shifted
out during the falling edge of SCK. If one byte address is initially set as A0 = 1, then Device ID will be read first
followed by the Manufacturer ID. The Manufacturer and Device ID can be read continuously alternating between
the two until CE# is driven high.
Figure 8.46 Read Product Identification by RDMDID Read Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
Mode 3
Mode 0
SCK
SI
Instruction = 90h
3-byte Address
tV
Device ID
(ID7-ID0)
Manufacturer ID
(MF7-MF0)
SO
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin is pulled high.
Figure 8.47 Read Product Identification by RDMDID QPI Read Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
Mode 3
Mode 0
SCK
tV
IO[3:0]
90h
Instruction
23:20 19:16 15:12 11:8 7:4 3:0
3-byte Address
7:4 3:0
7:4 3:0
Manufacturer
ID (MF7-MF0)
Device ID
(ID7-ID0)
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin is pulled high.
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8.28 READ UNIQUE ID NUMBER (RDUID, 4Bh)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is
unique to the device. The ID number can be used in conjunction with user software methods to help prevent
copying or cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the
instruction code (4Bh) followed by 3 address bytes and a dummy byte. After which, the 16-byte ID is shifted out
on the falling edge of SCK as shown below.
As a result, the sequence of RDUID instruction is same as FAST READ except for the instruction code. RDUID
QPI sequence is also same as FAST READ QPI except for the instruction code. Refer to the FAST READ QPI
operation.
Note: 16 bytes of data will repeat as long as CE# is low and SCK is toggling.
Figure 8.48 RDUID Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
Mode 3
Mode 0
SCK
SI
Instruction = 4Bh
3 Byte Address
Dummy Byte
tV
SO
Data Out
Table 8.6 Unique ID Addressing
A[23:16]
A[15:9]
XXh
A[8:4]
00h
A[3:0]
XXh
XXh
XXh
XXh
XXh
0h Byte address
1h Byte address
2h Byte address
XXh
00h
XXh
00h
XXh
00h
XXh
00h
Fh Byte address
Note: XX means “don’t care”.
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8.29 READ SFDP OPERATION (RDSFDP, 5Ah)
The Serial Flash Discoverable Parameters (SFDP) standard provides a consistent method of describing the
functions and features of serial Flash devices in a standard set of internal parameter tables. These parameters
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. For more details please refer to the JEDEC Standard JESD216A (Serial Flash
Discoverable Parameters).
The sequence of issuing RDSFDP instruction is same as FAST_READ: CE# goes low Send RDSFDP
instruction (5Ah) Send 3 address bytes on SI pin Send 1 dummy byte on SI pin Read SFDP code on
SO End RDSFDP operation by driving CE# high at any time during data out. Refer to ISSI’s Application note
for SFDP table. The data at the addresses that are not specified in SFDP table are undefined.
The sequence of RDSFDP instruction is same as FAST READ except for the instruction code. RDSFDP QPI
sequence is also same as FAST READ QPI except for the instruction code. Refer to the FAST READ QPI
operation.
Figure 8.49 RDSFDP (Read SFDP) Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
Mode 3
Mode 0
SCK
SI
Instruction = 5Ah
3 Byte Address
Dummy Byte
tV
SO
Data Out
8.30 NO OPERATION (NOP, 00h)
The No Operation command solely cancels a Reset Enable command and has no impact on any other
commands. It is available in both SPI and QPI modes. To execute a NOP, the host drives CE# low, sends the
NOP command cycle (00h), then drives CE# high.
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8.31 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET
The Software Reset operation is used as a system reset that puts the device in normal operating mode. During
the Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile
register. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The operation
requires the Reset-Enable command followed by the Reset command. Any command other than the Reset
command after the Reset-Enable command will disable the Reset-Enable.
Execute the CE# pin low sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives
CE# low again, sends the Reset command (99h), and pulls CE# high.
Only for the parts that have the RESET# function option, Hardware Reset function is available. For all packages
with RESET# (IO3) option except 16-pin SOIC/24-ball TFBGA with dedicated RESET# function, the RESET#
pin will be solely applicable in SPI mode and when the QE bit is disabled. For 16-pin SOIC/24-ball TFBGA
packages with dedicated RESET# function, the RESET# pin (or ball) is always applicable regardless of the QE
bit value.
The dedicated RESET# pin (or ball) has an internal pull-up resistor and may be left floating if not used The
RESET# pin (or ball) has the highest priority among all the input signals and will reset the device to its initial
power-on state regardless of the state of all other pins (CE#, IOs, SCK, and WP#).
In order to activate Hardware Reset, the RESET# pin (or ball) must be driven low for a minimum period of tRESET
(1µs). Drive RESET# low for a minimum period of tRESET will interrupt any on-going internal and external
operations, release the device from deep power down mode1, disable all input signals, force the output pin enter
a state of high impedance, and reset all the read parameters. If the RESET# pulse is driven for a period shorter
than 1µs, it may still reset the device, however the 1µs minimum period is recommended to ensure the reliable
operation. The required wait time after activating a HW Reset before the device will accept another instruction
(tHWRST) is the same as the maximum value of tSUS (100µs).
The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can
result in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset
timing may vary. Recovery from a Write operation will require more latency than recovery from other operations.
Note 1: The Status and Function Registers remain unaffected.
Figure 8.50 Software Reset Enable and Software Reset Sequence (RSTEN, 66h + RST, 99h)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
Instruction = 66h
High Impedance
Instruction = 99h
SI
SO
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Figure 8.51 Software Reset Enable and Software Reset QPI Sequence (RSTEN, 66h + RST, 99h)
CE#
0
1
0
1
Mode 3
Mode 0
SCK
66h
99h
IO[3:0]
8.32 SECURITY INFORMATION ROW
The security Information Row is comprised of an additional 4 x 256 bytes of programmable information. The
security bits can be reprogrammed by the user. Any program security instruction issued while an erase, program
or write cycle is in progress is rejected without having any effect on the cycle that is in progress.
Table 8.7 Information Row Valid Address Range
Address Assignment
A[23:16]
00h
A[15:8]
00h
A[7:0]
IRL0 (Information Row Lock0)
Byte address
Byte address
Byte address
Byte address
IRL1
IRL2
IRL3
00h
10h
00h
20h
00h
30h
Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.
When Function Register bit IRLx = “0”, the 256 bytes of the programmable memory array can be programmed.
When Function Register bit IRLx = “1”, the 256 bytes of the programmable memory array function as read only.
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8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device Send IRER instruction code Send
three address bytes Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE#
is pulled high, Erase operation will begin immediately. The internal control logic automatically handles the erase
voltage and timing. Refer to Figure 8.49 for IRER Sequence.
Figure 8.52 IRER (Information Row Erase) Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
...
SI
3
Instruction = 64h
2
1
0
23
22
High Impedance
SO
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8.34 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)
The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory
in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input.
Three address bytes has to be input as specified in the Table 8.6 Information Row Valid Address Range.
Program operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The
internal control logic automatically handles the programming voltages and timing. During a program operation,
all instructions will be ignored except the RDSR instruction. The progress or completion of the program
operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is
“1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The
previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the corresponding Information Row array which is one
of IR0~3.
Figure 8.53 IRP (Information Row Program) Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
...
...
...
Mode 3
Mode 0
SCK
3-byte Address
Data In 1
Data In 256
...
SI
...
...
6
0
7
0
0
Instruction = 62h
7
23
22
High Impedance
SO
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8.35 INFORMATION ROW READ OPERATION (IRRD, 68h)
The IRRD instruction is used to read memory data at up to a 133MHz clock.
The IRRD instruction code is followed by three address bytes (A23 - A0) and a dummy byte, transmitted via the
SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out
on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The address is automatically incremented by one after each byte of data is shifted out. Once the address
reaches the last address of each 256 byte Information Row, the next address will not be valid and the data of
the address will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte
with a valid starting address of each Information Row in order to read all data in the 4 x 256 byte Information
Row array. The IRRD instruction is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
The sequence of IRRD instruction is same as FAST READ except for the instruction code. IRRD QPI sequence
is also same as FAST READ QPI except for the instruction code. Refer to the FAST READ QPI operation.
Figure 8.54 IRRD (Information Row Read) Sequence
CE#
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
Mode 3
Mode 0
SCK
SI
Instruction = 68h
3 Byte Address
Dummy Cycles
tV
SO
Data Out
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8.36 FAST READ DTR MODE OPERATION (FRDTR, 0Dh)
The FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling edge
of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both
rising and falling edge of SCK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock,
and 2-bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the
falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR instruction. The
address counter rolls over to 0 when the highest address is reached.
The sequence of issuing FRDTR instruction is: CE# goes low Sending FRDTR instruction code (1bit per
clock) 3-byte address on SI (2-bit per clock) 4 dummy clocks on SI Data out on SO (2-bit per clock)
End FRDTR operation via driving CE# high at any time during data out.
While a Program/Erase/Write Status Register cycle is in progress, FRDTR instruction will be rejected without
any effect on the current cycle.
Figure 8.55 FRDTR Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
...
19
20
21
Mode 3
Mode 0
SCK
3-byte Address
SI
...
Instruction = 0Dh
23 22 21
19
0
20
18
17
High Impedance
SO
CE#
SCK
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
...
tV
4 Dummy
Cycles
SI
Data Out 1
Data Out 2
Data Out 3
Data Out ...
SO
...
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5
7
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FAST READ DTR QPI MODE OPERATION (FRDTR QPI, 0Dh)
The FRDTR QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRDTR instruction requires that the byte-long instruction code is shifted into the device only
via IO0 line in eight clocks. In addition, subsequent address and data out are shifted in/out via all four IO lines
unlike the FRDTR instruction. Eventually this operation is same as the FRQDTR QPI, but the only different thing
is that AX mode is not available in the FRDTR QPI operation.
The sequence of issuing FRDTR QPI instruction is: CE# goes low Sending FRDTR QPI instruction (4-bit per
clock) 24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) 3 dummy clocks (configurable,
default is 3 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) End FRDTR QPI operation
by driving CE# high at any time during data out.
If the FRDTR QPI instruction is issued while a Program/Erase/Write Status Register cycle is in progress
(WIP=1), the instruction will be rejected without any effect on the current cycle.
Figure 8.56 FRDTR QPI Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
...
Mode 3
Mode 0
SCK
IO0
3 Dummy Cycles
Data Data Data Data Data
Out Out Out Out Out
Instruction
= 0Dh
tV
3-byte Address
...
...
...
...
4
5
6
7
0
1
2
3
0
1
2
3
20 16 12 8
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO1
IO2
21 17 13 9
5
22 18 14 10 6
23 19 15 11 7
IO3
Notes:
1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
2. Sufficient dummy cycles are required to avoid I/O contention.
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8.37 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh)
The FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read mode. The
address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data (interleave
on dual I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency fT2. The 4-bit address
can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the rising
edge of clock, the other two bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR instruction.
The address counter rolls over to 0 when the highest address is reached. Once writing FRDDTR instruction, the
following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing FRDDTR instruction is: CE# goes low Sending FRDDTR instruction (1-bit per clock)
24-bit address interleave on IO1 & IO0 (4-bit per clock) 2 dummy clocks (configurable default is 2 clocks)
on IO1 & IO0 Data out interleave on IO1 & IO0 (4-bit per clock) End FRDDTR operation via pulling CE#
high at any time during data out (Please refer to Figure 8.57 for 2 x I/O Double Transfer Rate Read Mode
Timing Waveform).
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read
operation mode which enables subsequent FRDDTR execution skips command code. It saves cycles as
described in Figure 8.58. When the code is different from AXh, the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command. Since the number of dummy
cycles and AX bit cycles are same in this case, X should be Hi-Z to avoid I/O contention.
If the FRDDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),
the instruction will be rejected without any effect on the current cycle.
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Figure 8.57 FRDDTR Sequence (with command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
...
13
14
Mode 3
Mode 0
SCK
3-byte Address
2 Dummy Cycles
SI
...
...
Instruction = BDh
22 20 18 16 14 12 10
0
6 4
Mode Bits
High Impedance
SO
23 21 19 17 15 13 11
1
7
5
CE#
SCK
SI
15
16
17
18
19
20
21
22
23
24
25
26
27
28
...
tV
Data Out Data Out
Data Out Data Out
Data Out
Data Out
...
4
2
0
6
4
2
0
6
4
2
0
6
7
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
7
Mode Bits
SO
...
5
3
1
7
5
3
1
7
5
3
1
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bit cycles are same in the above Figure, X should be Hi-Z to avoid I/O
contention.
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Figure 8.58 FRDDTR AX Read Sequence (without command decode cycles)
CE#
...
0
1
2
6
7
8
9
10
11
12
13
14
15
...
Mode 3
Mode 0
SCK
SI
2 Dummy Cycles
tV
Data Out Data Out
Data Out
3-byte Address
...
...
...
...
22 20 18 16 14 12 10
0
1
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
7
4
5
Mode Bits
SO
7
5
3
1
7
5
3
1
7
5
3
1
23 21 19 17 15 13 11
7
5 3 1
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bit cycles are same in the above Figure, X should be Hi-Z to avoid I/O
contention.
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8.38 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh)
The FRQDTR instruction enables Double Transfer Rate throughput on quad I/O of the device in read mode. The
address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCK, and data (interleave on 4 I/O
pins) shift out on both rising and falling edge of SCK at a maximum frequency fQ2. The 8-bit address can be
latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at the rising edge of
clock, the other four bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out with a single FRQDTR instruction. The
address counter rolls over to 0 when the highest address is reached. Once writing FRQDTR instruction, the
following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing FRQDTR instruction is: CE# goes low Sending FRQDTR instruction (1-bit per clock)
24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) 3 dummy clocks (configurable, default is
3 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) End FRQDTR operation by driving
CE# high at any time during data out.
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read
operation mode which enables subsequent FRQDTR execution skips command code. It saves cycles as
described in Figure 8.60. When the code is different from AXh, the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),
the instruction will be rejected without any effect on the current cycle.
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Figure 8.59 FRQDTR Sequence (with command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
Mode 3
Mode 0
SCK
IO0
3 Dummy Cycles
3-byte Address
Instruction = EDh
High Impedance
20 16 12 8
4
0
1
4
0
1
IO1
IO2
21 17 13 9
5
5
6
7
22 18 14 10 6
23 19 15 11 7
2
3
2
3
IO3
Mode Bits
CE#
SCK
13
14
15
16
17
18
19
20
21
22
23
24
25
26
...
Data Data Data Data Data Data Data Data Data Data Data Data Data
Out Out Out Out Out Out Out Out Out Out Out Out Out
tV
IO0
...
...
...
...
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
IO2
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
IO3
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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Figure 8.60 FRQDTR AX Read Sequence (without command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
...
Mode 3
Mode 0
SCK
IO0
Data Data Data Data Data Data Data
tV Out Out Out Out Out Out Out
3 Dummy Cycles
3-byte Address
...
...
...
...
20 16 12 8
4
0
4
0
1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
21 17 13 9
5
1
2
3
5
6
7
22 18 14 10 6
23 19 15 11 7
2
3
IO3
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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FAST READ QUAD IO DTR QPI MODE OPERATION (FRQDTR QPI, EDh)
The FRQDTR QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRQDTR instruction requires that the byte-long instruction code is shifted into the device
only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQDTR QPI instruction.
In addition, subsequent address and data out are shifted in/out via all four IO lines like the FRQDTR instruction.
In fact, except for the command cycle, the FRQDTR QPI operation is exactly same as the FRQDTR.
The sequence of issuing FRQDTR QPI instruction is: CE# goes low Sending FRQDTR QPI instruction (4-bit
per clock) 24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) 3 dummy clocks (configurable,
default is 3 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) End FRQDTR QPI
operation by driving CE# high at any time during data out.
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read
operation mode which enables subsequent FRQDTR QPI execution skips command code. It saves cycles as
described in Figure 8.60. When the code is different from AXh, the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR QPI instruction is issued while a Program/Erase/Write Status Register cycle is in progress
(WIP=1), the instruction will be rejected without any effect on the current cycle.
Figure 8.61 FRQDTR QPI Sequence (with command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
...
Mode 3
Mode 0
SCK
IO0
3 Dummy Cycles
Data Data Data Data Data
Out Out Out Out Out
Instruction
= EDh
tV
3-byte Address
...
...
...
...
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
20 16 12 8
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO1
IO2
21 17 13 9
5
22 18 14 10 6
23 19 15 11 7
IO3
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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8.39 SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and
BP3 bits in the Status Register. Only one sector can be enabled at any time. To enable a different sector, a
previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is
followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining
sectors within the same block remain as read-only.
Figure 8.62 Sector Unlock Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
21
...
28
29
30
31
Mode 3
Mode 0
SCK
3-byte Address
...
SI
Instruction = 26h
3
2
1
0
23
22
High Impedance
SO
Figure 8.63 Sector Unlock QPI Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
SCK
Mode 0
Instruction
26h
3-byte Address
23:20 19:16 15:12 11:8 7:4 3:0
IO[3:0]
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SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.64 Sector Lock Sequence
CE#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction = 24h
SI
High Impedance
SO
Figure 8.65 Sector Lock QPI Sequence
CE#
0
1
Mode 3
Mode 0
SCK
24h
IO[3:0]
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9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65°C to +150°C
240°C 3 Seconds
260°C 3 Seconds
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
-0.5V to +6.0V
Standard Package
Lead-free Package
Surface Mount Lead Soldering Temperature
Input Voltage with Respect to Ground on All Pins
All Output Voltage with Respect to Ground
VCC
Electrostatic Discharge Voltage (Human Body Model)(2)
-2000V to +2000V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001
9.2 OPERATING RANGE
Part Number
IS25LP064A/032A
Operating Temperature (Extended Grade E)
Operating Temperature (Extended+ Grade E1)
Operating Temperature (Automotive Grade A1)
Operating Temperature (Automotive Grade A2)
Operating Temperature (Automotive Grade A3)
-40°C to 105°C
-40°C to 125°C
-40°C to 85°C
-40°C to 105°C
-40°C to 125°C
2.7V (VMIN) – 3.6V (VMAX); 3.0V (Typ), Max. 133MHz
2.3V (VMIN) – 3.6V (VMAX); 3.0V (Typ), Max. 104MHz
VCC Power Supply
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9.3 DC CHARACTERISTICS
(Under operating range)
Symbol
Parameter
Condition
Min
Typ(2)
5
Max
9
Units
NORD at 50MHz,
FRD Single at 133MHz
FRD Quad at 133MHz
FRD Quad DTR at 66MHz
7
11
VCC Active Read current(3)
ICC1
10
10
14
14
85°C
105°C
125°C
85°C
20(6)
22(6)
25
20(6)
22(6)
25
20(6)
22(6)
25
20(6)
22(6)
25
20(6)
30(6)
60
10(6)
15(6)
30
VCC Program Current
VCC WRSR Current
CE# = VCC
ICC2
ICC3
ICC4
ICC5
ISB1
ISB2
17
17
17
17
10
5
mA
CE# = VCC
105°C
125°C
85°C
VCC Erase Current
(SER/BER32K/BER64K)
CE# = VCC
105°C
125°C
85°C
VCC Erase Current (CE)
CE# = VCC
105°C
125°C
85°C
VCC Standby Current
CMOS
VCC = VMAX, CE# = VCC
105°C
125°C
85°C
µA
Deep power down current VCC = VMAX, CE# = VCC
105°C
125°C
CE# = VCC, RESET#(4) = VCC
Input Leakage Current
±1(5)
±1(5)
0.3VCC
VCC + 0.3
0.2
ILI
CE# = VCC, RESET#(4) = VCC
ILO
Output Leakage Current
(1)
VIL
Input Low Voltage
Input High Voltage
-0.5
(1)
VIH
0.7VCC
V
VOL
VOH
Output Low Voltage
VMIN < VCC < VMAX
Output High Voltage
IOL = 100 µA
IOH = -100 µA
VCC - 0.2
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may
overshoot VCC by +2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed 20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. Only for the dedicated RESET# pin (or ball).
5. The Max of ILI and ILO for the dedicated RESET# pin (or ball) is ±2 µA.
6. These parameters are characterized and are not 100% tested.
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9.4 AC MEASUREMENT CONDITIONS
Symbol Parameter
Min
Max
30
15
5
Units
pF
pF
ns
V
Load Capacitance up to 104MHz
Load Capacitance up to 133MHz
Input Rise and Fall Times
CL
TR,TF
VIN
Input Pulse Voltages
0.2VCC to 0.8VCC
VREFI
VREFO
Input Timing Reference Voltages
Output Timing Reference Voltages
0.3VCC to 0.7VCC
0.5VCC
V
V
Figure 9.1 Output test load & AC measurement I/O Waveform
0.8VCC
AC
Input
VCC/2
Measurement
1.8k
Level
0.2VCC
OUTPUT PIN
1.2k
15/30pf
9.5 PIN CAPACITANCE
Symbol
Parameter
Input Capacitance
Test Condition
Min
Typ
Max
Units
CIN
VIN = 0V
-
-
6
pF
pF
(CE#, SCK)
Input/Output Capacitance
(other pins)
CIN/OUT
VIN/OUT = 0V
-
-
8
Notes:
1. These parameters are characterized and are not 100% tested.
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9.6 AC CHARACTERISTICS
(Under operating range, refer to section 9.4 for AC measurement conditions)
Symbol
Parameter
Min
Typ(3)
Max
Units
Clock Frequency for fast read mode:
SPI, Dual, Dual I/O, Quad I/O, and
QPI.
Vcc=2.7V~3.6V
Vcc=2.3V~3.6V
0
133
MHz
fCT
0
0
104
MHz
MHz
Clock Frequency for fast read DTR:
SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and
QPI DTR.
fC2, fT2, fQ2
fC
66
50
Clock Frequency for read mode SPI
SCK Rise Time (peak to peak)
SCK Fall Time ( peak to peak)
0
MHz
V/ns
V/ns
(1)
tCLCH
0.1
(1)
tCHCL
0.1
For read mode
45% fC
tCKH
SCK High Time
For others
ns
ns
45% fCT/C2/T2/Q2
For read mode
45% fC
tCKL
SCK Low Time
For others
45% fCT/C2/T2/Q2
tCEH
tCS
CE# High Time
CE# Setup Time
CE# Hold Time
7
6
ns
ns
ns
tCH
6
Normal Mode
Data In Setup Time
2
tDS
ns
ns
ns
DTR Mode
1.5
2
Normal Mode
Data in Hold Time
tDH
DTR Mode
1.5
@ 133MHz (CL = 15pF)
Output Valid
7
8
tV
@ 104MHz (CL = 30pF)
tOH
Output Hold Time
2
ns
ns
ns
ns
ns
ns
ns
ns
ms
s
(1)
tDIS
Output Disable Time
8
tHLCH
tCHHH
tHHCH
tCHHL
HOLD Active Setup Time relative to SCK
HOLD Active Hold Time relative to SCK
HOLD Not Active Setup Time relative to SCK
HOLD Not Active Hold Time relative to SCK
HOLD to Output Low Z
5
5
5
5
(1)
tLZ
12
12
(1)
tHZ
HOLD to Output High Z
Sector Erase Time (4Kbyte)
70
0.1
0.15
8
300
0.5
1.0
23
Block Erase Time (32Kbyte)
Block Erase time (64Kbyte)
tEC
s
32Mb
Chip Erase Time
64Mb
s
16
45
tPP
Page Program Time
0.2
0.8
ms
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Symbol
Parameter
Min
Typ(3)
Max
3
Units
µs
(1)
tRES1
Release deep power down
Deep power down
(1)
tDP
3
µs
tW
Write Status Register time
Suspend to read ready
Software Reset recovery time
RESET# pin low pulse width
Hardware Reset recovery time
2
15
ms
µs
(1)
tSUS
100
100
(1)
tSRST
µs
(1),(4)
tRESET
1(2)
µs
(1),(4)
tHWRST
100
µs
Notes:
1. These parameters are characterized and not 100% tested.
2. If the RESET# pulse is driven for a period shorter than 1µs (tRESET minimum), it may still reset the device, however
the 1µs minimum period is recommended to ensure reliable operation.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
4. Only applicable to the parts that have the RESET# pin (or ball) option.
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9.7 SERIAL INPUT/OUTPUT TIMING
Figure 9.2 SERIAL INPUT/OUTPUT TIMING (Normal Mode) (1)
tCEH
CE#
tCS
tCH
tCKH
tCKL
SCK
SI
tDS
tDH
VALID IN
VALID IN
tV
tOH
VALID OUTPUT
tDIS
HI-Z
HI-Z
SO
Note1. For SPI Mode 0 (0,0)
Figure 9.3 SERIAL INPUT/OUTPUT TIMING (DTR Mode) (1)
tCEH
CE#
tCS
tCH
tCKH
tCKL
SCK
SI
tDS
tDH
VALID IN
VALID IN
VALID IN
tDIS
tOH
tV
tV
HI-Z
HI-Z
SO
Output
Output
Note1. For SPI Mode 0 (0,0)
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Figure 9.4 HOLD TIMING
CE#
tHLCH
tCHHL
tHHCH
SCK
tCHHH
tHZ
tLZ
SO
SI
HOLD#
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9.8 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding
a simple pull-up resistor on CE# is recommended.)
Power up timing
VCC
VCC(max)
All Write Commands are Rejected
Chip Selection Not Allowed
VCC(min)
Reset State
Device fully
accessible
tVCE
Read Access Allowed
V(write inhibit)
tPUW
Symbol
tVCE(1)
tPUW(1)
Parameter
Min.
1
Max
Unit
ms
ms
V
Vcc(min) to CE# Low
Power-up time delay to write instruction
Write Inhibit Voltage
1
10
(1)
VWI
2.1
Note: These parameters are characterized and not 100% tested.
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9.9 PROGRAM/ERASE PERFORMANCE
Parameter
Typ
70
Max
300
0.5
1.0
23
Unit
ms
s
Sector Erase Time (4Kbyte)
Block Erase Time (32Kbyte)
Block Erase Time (64Kbyte)
0.1
0.15
8
s
32Mb
64Mb
s
Chip Erase Time
16
45
0.2
8
0.8
40
ms
µs
Page Programming Time
Byte Program
Note: These parameters are characterized and not 100% tested.
9.10 RELIABILITY CHARACTERISTICS
Parameter
Endurance
Min
100,000
20
Max
Unit
Cycles
Years
mA
Test Method
-
-
JEDEC Standard A117
JEDEC Standard A117
JEDEC Standard 78
Data Retention
Latch-Up
-100
+100
Note: These parameters are characterized and not 100% tested.
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10. PACKAGE TYPE INFORMATION
10.1 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (B)
Note: Lead co-planarity is 0.1mm.
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10.2 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 6X5MM (K)
Note: Lead co-planarity is 0.08mm.
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10.3 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8X6MM (L)
Note: All dimensions are in millimeters. Lead co-planarity is 0.08mm.
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10.4 8-PIN 208MIL VSOP PACKAGE (F)
Note: Lead co-planarity is 0.1mm.
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10.5 16-LEAD PLASTIC SMALL OUTLINE PACKAGE (300 MILS BODY WIDTH) (M)
Note: Lead co-planarity is 0.08mm.
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10.6 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM 4X6 BALL ARRAY (G)
A1 Corner
Index Area
A1 Corner
Index Area
(TOP VIEW)
(BOTTOM VIEW)
Note: Lead co-planarity is 0.08mm.
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10.7 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM 5X5 BALL ARRAY (H)
Note: Lead co-planarity is 0.08mm.
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11. ORDERING INFORMATION- Valid Part Numbers
IS25LP 064 A -
J
B
L
E
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
E1 = Extended+ (-40°C to +125°C)
A1 = Automotive Grade (-40°C to +85°C)
A2 = Automotive Grade (-40°C to +105°C)
A3 = Automotive Grade (-40°C to +125°C)
PACKAGING CONTENT
L = RoHS compliant
PACKAGE Type(1),(2)
B = 8-pin SOIC 208mil
K = 8-contact WSON 6x5mm
L = 8-contact WSON 8x6mm
F = 8-pin VSOP 208mil
M = 16-pin SOIC 300mil
G = 24-ball TFBGA 6x8mm 4x6 ball array
H = 24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
W = KGD (Call Factory)
Option
J = Standard (No DTR Function)
D = 66MHz DTR Function in addition to Standard
R = Dedicated RESET# pin (or ball) option for 16-pin
SOIC/24-ball TFBGA
Q = QE bit set to 1
P = Dedicated RESET# pin and QE bit set to 1 for 16-pin
SOIC/24-ball TFBGA
S = RESET# (IO3) instead of Hold# (IO3)(2)
Die Revision
A = Revision A
Density
064 = 64 Megabit
032 = 32 Megabit
BASE PART NUMBER
IS = Integrated Silicon Solution Inc.
25LP = FLASH, 2.3V ~ 3.6V, QPI
Note:
1. Call Factory for other package options available.
2. For the RESET# (IO3) pin option instead of HOLD# (IO3) pin, call Factory.
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97
11/06/2015
IS25LP064A/032A
Density
Frequency (MHz)
Order Part Number(1)
IS25LP064A-JBLE
Package(2)
8-pin SOIC 208mil
IS25LP064A-JBLE1
IS25LP064A-JKLE1
IS25LP064A-JLLE1
IS25LP064A-JFLE1
IS25LP064A-JMLE1
IS25LP064A-JGLE1
IS25LP064A-JHLE1
IS25LP064A-QBLE1
IS25LP064A-QKLE1
IS25LP064A-QLLE1
IS25LP064A-QFLE1
IS25LP064A-QMLE1
IS25LP064A-QGLE1
IS25LP064A-RMLE1
IS25LP064A-PMLE1
IS25LP064A-RGLE1
IS25LP064A-RHLE1
IS25LP064A-PGLE1
IS25LP064A-DMLE1
IS25LP064A-DGLE1
IS25LP064A-JKLE
IS25LP064A-JLLE
IS25LP064A-JFLE
IS25LP064A-JMLE
IS25LP064A-JGLE
IS25LP064A-JHLE
IS25LP064A-QBLE
IS25LP064A-QKLE
IS25LP064A-QLLE
IS25LP064A-QFLE
IS25LP064A-QMLE
IS25LP064A-QGLE
IS25LP064A-RMLE
IS25LP064A-PMLE
IS25LP064A-RGLE
IS25LP064A-RHLE
IS25LP064A-PGLE
IS25LP064A-DMLE
IS25LP064A-DGLE
8-contact WSON 6x5mm
8-contact WSON 8x6mm
8-pin VSOP 208mil
16-pin SOIC 300mil
24-ball TFBGA 6x8mm 4x6 ball array
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
8-pin SOIC 208mil
8-contact WSON 6x5mm
8-contact WSON 8x6mm
8-pin VSOP 208mil
16-pin SOIC 300mil
24-ball TFBGA 6x8mm
16-pin SOIC 300mil(3)
16-pin SOIC 300mil(3)
24-ball TFBGA 6x8mm 4x6 ball array (3)
24-ball TFBGA 6x8mm 5x5 ball array (3) (Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (3)
16-pin SOIC 300mil
64Mb
133
24-ball TFBGA 6x8mm 4x6 ball array
8-pin SOIC 208mil (Call Factory)
8-contact WSON 6x5mm (Call Factory)
8-contact WSON 8x6mm (Call Factory)
16-pin SOIC 300mil (Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
8-pin SOIC 208mil (Call Factory)
8-contact WSON 6x5mm (Call Factory)
16-pin SOIC 300mil (Call Factory)
24-ball TFBGA 6x8mm (Call Factory)
16-pin SOIC 300mil(3)(Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (3) (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (3) (Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (3) (Call Factory)
16-pin SOIC 300mil(Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
KGD (Call Factory)
IS25LP064A-JBLA*
IS25LP064A-JKLA*
IS25LP064A-JLLA*
IS25LP064A-JMLA*
IS25LP064A-JGLA*
IS25LP064A-JHLA*
IS25LP064A-QBLA*
IS25LP064A-QKLA*
IS25LP064A-QMLA*
IS25LP064A-QGLA*
IS25LP064A-RMLA*
IS25LP064A-RGLA*
IS25LP064A-RHLA*
IS25LP064A-PGLA*
IS25LP064A-DMLA*
IS25LP064A-DGLA*
IS25LP064A-DHLA*
IS25LP064A-JWLE
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
98
11/06/2015
IS25LP064A/032A
Density
Frequency (MHz)
Order Part Number(1)
IS25LP032A-JBLE
Package(2)
IS25LP032A-JBLE1
IS25LP032A-JKLE1
IS25LP032A-JLLE1
IS25LP032A-JFLE1
IS25LP032A-JMLE1
IS25LP032A-JGLE1
IS25LP032A-JHLE1
IS25LP032A-RMLE1
IS25LP032A-PMLE1
IS25LP032A-RGLE1
IS25LP032A-PGLE1
IS25LP032A-DMLE1
IS25LP032A-DGLE1
IS25LP032A-DHLE1
8-pin SOIC 208mil
IS25LP032A-JKLE
IS25LP032A-JLLE
IS25LP032A-JFLE
IS25LP032A-JMLE
IS25LP032A-JGLE
IS25LP032A-JHLE
IS25LP032A-RMLE
IS25LP032A-PMLE
IS25LP032A-RGLE
IS25LP032A-PGLE
IS25LP032A-DMLE
IS25LP032A-DGLE
IS25LP032A-DHLE
8-contact WSON 6x5mm
8-contact WSON 8x6mm
8-pin VSOP 208mil
16-pin SOIC 300mil
24-ball TFBGA 6x8mm 4x6 ball array
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
16-pin SOIC 300mil(3)
16-pin SOIC 300mil(3)
24-ball TFBGA 6x8mm 4x6 ball array (3)
24-ball TFBGA 6x8mm 4x6 ball array (3)
16-pin SOIC 300mil
24-ball TFBGA 6x8mm 4x6 ball array
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
8-pin SOIC 208mil (Call Factory)
IS25LP032A-JBLA*
32Mb
133
IS25LP032A-JKLA*
IS25LP032A-JLLA*
IS25LP032A-JFLA*
IS25LP032A-JMLA*
IS25LP032A-JGLA*
IS25LP032A-JHLA*
IS25LP032A-RMLA*
IS25LP032A-RGLA*
IS25LP032A-RHLA*
IS25LP032A-PMLA*
IS25LP032A-PGLA*
IS25LP032A-PHLA*
IS25LP032A-DMLA*
IS25LP032A-DGLA*
IS25LP032A-DHLA*
IS25LP032B-JWLE
8-contact WSON 6x5mm (Call Factory)
8-contact WSON 8x6mm (Call Factory)
8-pin VSOP 208mil (Call Factory)
16-pin SOIC 300mil (Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
16-pin SOIC 300mil(3)(Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (3) (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (3) (Call Factory)
16-pin SOIC 300mil(3)(Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (3) (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (3) (Call Factory)
16-pin SOIC 300mil (Call Factory)
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
24-ball TFBGA 6x8mm 5x5 ball array (Call Factory)
KGD (Call Factory)
Notes:
1. A* = A1, A2, A3: Meets AEC-Q100 requirements with PPAP, E1= Extended+ non-Auto qualified
Temp Grades: E= -40 to 105°C, E1= -40 to 125°C, A1= -40 to 85°C, A2= -40 to 105°C, A3= -40 to 125°C
2. For RESET# pin option, call Factory.
3. The dedicated RESET# pin (or ball) on pin3/ball A4.
4. Call Factory for other package and option available
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
99
11/06/2015
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