IS25WD040-JKLA [ISSI]
2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory;
| 型号： | IS25WD040-JKLA |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory |
| 文件： | 总35页 (文件大小：764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS25WD020/040
2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory
With 80 MHz Dual-Output SPI Bus Interface
FEATURES
• Low Power Consumption
- Typical 2 mA active read current
- Typical 6 mA program/erase current
• Single Power Supply Operation
- Low voltage range: 1.65 V – 1.95 V
• Memory Organization
- IS25WD020: 256K x 8 (2 Mbit)
- IS25WD040: 512K x 8 (4 Mbit)
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
• Cost Effective Sector/Block Architecture
- 2Mb : Uniform 4KByte sectors / Four uniform
64KByte blocks
- 4Mb : Uniform 4KByte sectors / Eight uniform
64KByte blocks
• Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow
partial or entire memory to be configured as read-
only
• High Product Endurance
- Guaranteed 200,000 program/erase cycles per
single sector
- Minimum 20 years data retention
• Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 30 MHz clock rate for normal read
- Maximum 80 MHz clock rate for fast read
• Industrial Standard Pin-out and Package
- 8-pin SOIC 208mil
- 8-pin SOIC 150mil
- 8-pin VVSOP 150mil
- 8-pin WSON
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
- KGD (Call Factory)
• Sector, Block or Chip Erase Operation
- Lead-free (Pb-free) package
- Automotive Temperature Ranges Available
- Typical 1.7 ms sector, block or chip erase
GENERAL DESCRIPTION
The IS25WD020/040 are 2 Mbit / 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or
dual-output. The devices are designed to support a 30 MHz fclock rate in normal read mode, and 80 MHz in fast
read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage
ranging from 1.65 Volt to 1.95 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The IS25WD020/040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized
command codes and operations. The dual-output fast read operation provides and effective serial data rate of
160MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in
one program operation. These devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks.
The IS25WD020/040 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in 8-pin SOIC 208mil, 8-pin SOIC 150mil, 8-pin VVSOP 150mil and 8-pin WSON. The devices operate at
wide temperatures between -40°C to +105°C.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
1
07/31/2013
IS25WD020/040
CONNECTION DIAGRAMS
CE#
SO
1
2
8
7
Vcc
8 Vcc
CE#
SO
1
2
7
HOLD#
6 SCK
SIO
HOLD#
3
4
WP#
GND
WP#
GND
3
4
6
5
SCK
SIO
5
8-Contact WSON
8-Pin SOIC/VVSOP
PIN DESCRIPTIONS
SYMBOL TYPE
DESCRIPTION
CE#
INPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
SCK
SIO
SO
INPUT
INPUT/OUTPUT Serial Data Input/Output
OUTPUT
Serial Data Output
GND
Vcc
Ground
Device Power Supply
WP#
INPUT
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends
on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is
high, the devices are not write-protected.
HOLD#
INPUT
Hold: Pause serial communication by the master device without resetting
the serial sequence.
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Rev. F
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IS25WD020/040
BLOCK DIAGRAM
SIO
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Rev. F
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IS25WD020/040
SPI MODES DESCRIPTION
Multiple IS25WD020/040 devices can be connected on The difference between these two modes is the clock
the SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 1. The devices
support either of two SPI modes:
Mode 0 (0, 0)
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Mode 3 (1, 1)
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDIO
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
CE#
SO SIO
SCK
SO
SCK
CE#
SIO
SO SIO
SPI Master
(i.e. Microcontroller)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3
CS2
CS1
WP#
CE# WP#
WP#
HOLD#
HOLD#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
4
07/31/2013
IS25WD020/040
Figure 2. SPI Modes Supported
SCK
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SIO
Input mode
MSb
SO
MSb
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Rev. F
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07/31/2013
IS25WD020/040
SYSTEM CONFIGURATION
The IS25WD020/040 devices are designed to interface directly with the synchronous Serial Peripheral Interface
(SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers.
The devices have two superset features that can be enabled through specific software instructions and the
Configuration Register:
Table 1 illustrates the memory map of the devices. The Configuration Register controls how the memory is
mapped.
BLOCK/SECTOR ADDRESSES
Table 1. Block/Sector Addresses of IS25WD020/040
Block
Size
Sector
Size
Memory Density
Block No.
Sector No.
Address Range
(Kbytes)
(Kbytes)
Sector 0
4
000000h – 000FFFh
Sector 1
4
:
4
4
4
:
001000h – 001FFFh
Block 0
64
64
:
:
Sector 15
Sector 16
Sector 17
00F000h – 00FFFFh
010000h – 010FFFh
011000h – 011FFFh
2 Mbit
Block 1
:
:
4 Mbit
Sector 31
4
:
4
4
:
01F000h – 01FFFFh
:
:
64
64
:
:
64
:
:
:
:
:
:
:
Block 3
Block 4
:
030000h – 03FFFFh
040000h – 04FFFFh
:
:
:
:
4
Block 7
070000h – 07FFFFh
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Rev. F
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IS25WD020/040
REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and are allowed. The WEL bit is set by a Write Enable
Status Register Bit Definitions.
(WREN) instruction. Each write register, program and
erase instruction must be preceded by a WREN
instruction. The WEL bit can be reset by a Write
Disable (WRDI) instruction. It will automatically be the
The BP0, BP1, BP2, and SRWD are volatile memory
cells that can be written by a Write Status Register
(WRSR) instruction. The default value of the BP2, BP1, reset after the completion of a write instruction.
BP0 were set to “0” and SRWD bits was set to “0” at
factory. Once a “0” or “1”is written, it will not be
BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,
changed by device power-up or power-down, and can BP0) bits are used to define the portion of the memory
only be altered by the next WRSR instruction. The
Status Register can be read by the Read Status
area to be protected. Refer to Tables 7, 8 and 9 for the
Block Write Protection bit settings. When a defined
Register (RDSR). Refer to Table 10 for Instruction Set. combination of BP2, BP1 and BP0 bits are set, the
corresponding memory area is protected. Any program
The function of Status Register bits are described as
follows:
or erase operation to that area will be inhibited. Note:
a Chip Erase (CHIP_ER) instruction is executed
successfully only if all the Block Protection Bits are set
as “0”s.
WIP bit: The Write In Progress (WIP) bit is read-only,
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is
“0”, the device is ready for a write status register,
program or erase operation. When the WIP bit is “1”,
the device is busy.
SRWD bit: The Status Register Write Disable (SRWD)
bit operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
the WP# is pulled low (VIL), the volatile bits of Status
Register (SRWD, BP2, BP1, BP0) become read-only,
and a WRSR instruction will be ignored. If the SRWD is
set to “1” and WP# is pulled high (VIH), the Status
WEL bit: The Write Enable Latch (WEL) bit indicates
the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled, and all
write operations, including write status register, page
program, sector erase, block and chip erase operations Register can be changed by a WRSR instruction.
are inhibited. When the WEL bit is “1”, write operations
Table 5. Status Register Format
Bit 7
SRWD1
0
Bit 6
Bit 5
Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
Reserved
Default (flash bit)
0
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IS25WD020/040
REGISTERS (CONTINUED)
Table 6. Status Register Bit Definition
Read- Non-Volatile
Bit
Name
Definition
/Write
bit
Write In Progress Bit:
Bit 0
WIP
“0” indicates the device is ready
R
No
“1” indicates a write cycle is in progress and the device is busy
Write Enable Latch:
Bit 1
WEL
“0” indicates the device is not write enabled
“1” indicates the device is write enabled (default)
Block Protection Bit: (See Table 7 and Table 8 for details)
“0” indicates the specific blocks are not write-protected (default) R/W
“1” indicates the specific blocks are write-protected
R/W
No
Bit 2
Bit 3
Bit 4
BP0
BP1
BP2
N/A
Yes
Bits 5 – 6
Reserved: Always “0”s
N/A
Status Register Write Disable: (See Table 9 for details)
Bit 7
SRWD “0” indicates the Status Register is not write-protected (default)
“1” indicates the Status Register is write-protected
R/W
Yes
Table 8. Block Write Protect Bits for IS25WD020
Status Register Bits
Protected Memory Area
BP2
BP1
BP0
2 Mbit
Not used
Not used
Not used
Not used
0
0
1
1
0
1
0
1
None
Upper eight (block : 3): 030000h – 03FFFFh
Upper quarter (two blocks :2 and 3): 020000h – 03FFFFh
Upper half (four blocks :0 to 3): 000000h – 03FFFFh
Table 8-1. Block Write Protect Bits for IS25WD040
Status Register Bits
Protected Memory Area
4 Mbit
BP2
0
BP1
0
BP0
0
None
0
0
1
Upper eight (block : 7): 070000h – 07FFFFh
Upper quarter (two blocks :6 and 7): 060000h – 07FFFFh
Upper half (four blocks :4 to 7): 040000h – 07FFFFh
0
1
0
0
1
1
1
0
0
1
0
1
All Blocks (Block 0 to 7):
000000h – 07FFFFh
1
1
0
1
1
1
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IS25WD020/040
REGISTERS (CONTINUED)
PROTECTION MODE
The IS25WD020/040 have two types of write-
protection mechanisms: hardware and software.
These are used to prevent irrelevant operation in a
possibly noisy environment and protect the data
integrity.
Table 9. Hardware Write Protection on Status
Register
SRWD
WP#
Low
Low
High
High
Status Register
Writable
0
1
0
1
Protected
Writable
HARDWARE WRITE-PROTECTION
The devices provide two hardware write-protection
features:
Writable
a. When inputting a program, erase or write status
register instruction, the number of clock pulse is
checked to determine whether it is a multiple of eight
before the executing. Any incomplete instruction
command sequence will be ignored.
0. The Write Protection (WP#) pin provides a
hardware write protection method for BP2, BP1,
BP0 and SRWD in the Status Register. Refer to
the STATUS REGISTER description.
c. Write inhibit is 1.5 V, all write sequence will be
ignored when Vcc drop to 1.5 V and lower
SOFTWARE WRITE PROTECTION
The IS25WD020/040 also provides two software write
protection features:
a. Before the execution of any program, erase or write
status register instruction, the Write Enable Latch
(WEL) bit must be enabled by executing a Write
Enable (WREN) instruction. If the WEL bit is not
enabled first, the program, erase or write register
instruction will be ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part
or the whole memory area to be write-protected.
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IS25WD020/040
DEVICE OPERATION
The IS25WD020/040 utilize an 8-bit instruction
instruction code and is followed by address bytes, data
register. Refer to Table 10 Instruction Set for details of bytes, or both address bytes and data bytes,
the Instructions and Instruction Codes. All instructions, depending on the type of instruction. CE# must be
addresses, and data are shifted in with the most
driven high (VIH) after the last bit of the instruction
significant bit (MSB) first on Serial Data Input (SI). The sequence has been shifted in.
input data on SI is latched on the rising edge of Serial
Clock (SCK) after Chip Enable (CE#) is driven low
The timing for each instruction is illustrated in the
(VIL). Every instruction sequence starts with a one-byte following operational descriptions.
Table 10. Instruction Set
Instruction Name
Hex
Operation
Command Maximum
Code
Cycle
4 Bytes
1 Byte
Frequency
80 MHz
80 MHz
RDID
JEDEC ID READ
Abh Read Manufacturer and Product ID
9Fh Read Manufacturer and Product ID by JEDEC ID
Command
RDMDID
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FRDO
90h Read Manufacturer and Device ID
06h Write Enable
04h Write Disable
05h Read Status Register
01h Write Status Register
03h Read Data Bytes from Memory at Normal Read Mode
0Bh Read Data Bytes from Memory at Fast Read Mode
3Bh Fast Read Dual Output
4 Bytes
1 Byte
1 Byte
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
30 MHz
80 MHz
80 MHz
80 MHz
1 Byte
2 Bytes
4 Bytes
5 Bytes
5 Bytes
4 Bytes +
256B
PAGE_ PROG
02h Page Program Data Bytes Into Memory
SECTOR_ER
D7h/ Sector Erase
20h
4 Bytes
80 MHz
BLOCK_ER
CHIP_ER
D8h Block Erase
C7h/ Chip Erase
60h
4 Bytes
1 Byte
80 MHz
80 MHz
HOLD OPERATION
HOLD# is used in conjunction with CE# to select
the IS25WD020/040. When the devices are
selected and a serial sequence is underway,
HOLD# can be used to pause the serial
communication with the master device without
resetting the serial sequence. To pause, HOLD# is
brought low while the SCK signal is low. To resume
serial communication, HOLD# is brought high while
the SCK signal is low (SCK may still toggle during
HOLD). Inputs to Sl will be ignored while SO is in
the high impedance state.
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT
IDENTIFICATION) OPERATION
CE# goes high. The Device ID outputs repeatedly if
continuously send the additional clock cycles on SCK
while CE# is at low.
The Read Product Identification (RDID) instruction is
for reading out the old style of 8-bit Electronic
Signature, whose values are shown as table of ID
Definitions. This is not same as RDID or JEDEC ID
instruction. It’s not recommended to use for new
design. For new design, please use RDID or JEDEC ID
instruction.
Table 11. Product Identification
Product Identification
Data
The RDES instruction code is followed by three dummy
bytes, each bit being latched-in on SI during the rising
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDES instruction is ended by
First Byte
9Dh
7Fh
Manufacturer ID
Second Byte
Device ID 1
11h
Device ID:
Device ID 2
32h
IS25WD020
IS25WD040
12h
33h
Figure 3. Read Product Identification Sequence
CE#
7
9
46
0
1
8
38 39
47
54
31
SCK
SI
INSTRUCTION
1010 1011b
3 Dummy Bytes
HIGH IMPEDANCE
SO
Device ID1
Device ID1
Device ID1
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)
OPERATION
The JEDEC ID READ instruction allows the user to
by the first Manufacturer ID (9Dh) and the Device ID
read the manufacturer and product ID of devices. Refer (32h, in the case of the IS25WD020), each bit shifted
to Table 11 Product Identification for pFlash
Manufacturer ID and Device ID. After the JEDEC ID
out during the falling edge of SCK. If CE# stays low
after the last bit of the Device ID is shifted out, the
READ command is input, the second Manufacturer ID Manufacturer ID and Device ID will loop until CE# is
(7Fh) is shifted out on SO with the MSB first, followed pulled high.
Figure 4. Read Product Identification by JEDEC ID READ Sequence
CE#
0
7
8
15 16
23 24
31
SCK
SI
INSTRUCTION
1001 1111b
HIGH IMPEDANCE
SO
Manufacture ID2
Manufacture ID1
Device ID2
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)
OPERATION
The RDMDID instruction allows the user to read the
the Device ID (32h, in the case of the IS25WD020),
manufacturer and product ID of devices. Refer to Table and is shifted out on SO with the MSB first, each bit
11 Product Identification for pFlash Manufacturer ID
and Device ID. The RDMDID command is input,
followed by a 24-bit address pointing to an ID table.
shifted out during the falling edge of SCK. If CE# stays
low after the last bit of the Device ID is shifted out, the
Manufacturer ID and Device ID will loop until CE# is
The table contains the first Manufacturer ID (9Dh) and pulled high.
Figure 5. Read Product Identification by RDMDID READ Sequence
CE#
9
0
2
3
4
5
8
31
A0
1
6
7
10 11 28
29 30
SCK
SIO
...
3 - BYTE ADDRESS
2
1
INSTRUCTION = 1001 0000b
HIGH IMPEDANCE
23
3
...
22
21
SO
CE#
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
32
SCK
SIO
Manufacturer ID1
Device ID1
5
SO
0
2
1
6
7
3
3
4
4
7
6
5
2
1
0
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IS25WD020/040
CE#
48
50 51 52 53
56
49
54 55
SCK
SIO
Manufacturer ID2
SO
3
4
7
6
5
2
1
0
Note :
0. ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)
ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the erase, chip erase, page program and write status
Write Enable Latch (WEL) bit. The WEL bit of the
IS25WD020/040 is reset to the write –protected state
after power-up. The WEL bit must be write enabled
before any write operation, including sector, block
register operations. The WEL bit will be reset to the
write-protect state automatically upon completion of a
write operation. The WREN instruction is required
before any above operation is executed.
Figure 6. Write Enable Sequence
SIO
WRDI COMMAND (WRITE DISABLE) OPERATION
The Write Disable (WRDI) instruction resets the WEL
bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write
instruction, since the WEL bit is automatically reset.
Figure 7. Write Disable Sequence
SIO
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
RDSR COMMAND (READ STATUS REGISTER) OPERATION
The Read Status Register (RDSR) instruction provides instruction, which can be used to check the progress or
access to the Status Register. During the execution of completion of an operation by reading the WIP bit of
a program, erase or write status register operation, all Status Register.
other instructions will be ignored except the RDSR
Figure 8. Read Status Register Sequence
SIO
WRSR COMMAND (WRITE STATUS REGISTER) OPERATION
The Write Status Register (WRSR) instruction allows
the user to enable or disable the block protection and
status register write protection features by writing “0”s
or “1” s into the volatile BP2, BP1, BP0 and SRWD
bits.
Figure 9. Write Status Register Sequence
SIO
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
READ COMMAND (READ DATA) OPERATION
The Read Data (READ) instruction is used to read
memory data of a IS25WD020/040 under normal mode The first byte data (D7 – D0) addressed is then shifted
running up to 30 MHz.
out on the SO line, MSb first. A single byte of data, or
up to the whole memory array, can be read out in one
READ instruction. The address is automatically
The READ instruction code is transmitted via the Sl
line, followed by three address bytes (A23 – A0) of the incremented after each byte of data is shifted out. The
first memory location to be read. A total of 24 address read operation can be terminated at any time by driving
bits are shifted in, but only AMS (most significant
CE# high (VIH) after the data comes out. When the
address) – A0 are decoded. The remaining bits (A23 – highest address of the devices is reached, the address
AMS) are ignored. The first byte addressed can be at
any memory location. Upon completion, any data on
counter will roll over to the 000000h address, allowing
the entire memory to be read in one continuous READ
the Sl will be ignored. Refer to Table 12 for the related instruction.
Address Key.
Table 12. Address Key
Address
AN (AMS – A0)
Don’t Care Bits
IS25WD020
A17 – A0
IS25WD040
A18 – A0
A23 – A18
A23 – A19
Figure 12. Read Data Sequence
SIO
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
FAST_READ COMMAND (FAST READ DATA) OPERATION
The FAST_READ instruction is used to read memory
data at up to a 80 MHz clock.
The first byte addressed can be at any memory
location. The address is automatically incremented
The FAST_READ instruction code is followed by three after each byte of data is shifted out. When the highest
address bytes (A23 – A0) and a dummy byte (8
clocks), transmitted via the SI line, with each bit
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
latched-in during the rising edge of SCK. Then the first read with a single FAST_READ instruction. The
data byte addressed is shifted out on the SO line, with FAST_READ instruction is terminated by driving CE#
each bit shifted out at a maximum frequency fCT, during high (VIH).
the falling edge of SCK.
Figure 13. Fast Read Data Sequence
SIO
SIO
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IS25WD020/040
DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on bit (MSb) is output on SO, while simultaneously the
two output pins each at up to a 80 MHz clock.
second bit is output on SIO.
The FRDO instruction code is followed by three
address bytes (A23 – A0) and a dummy byte (8
clocks), transmitted via the SI line, with each bit
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
latched-in during the rising edge of SCK. Then the first address is reached, the address counter will roll over to
data byte addressed is shifted out on the SO and SIO
lines, with each pair of bits shifted out at a maximum
the 000000h address, allowing the entire memory to be
read with a single FRDO instruction. FRDO instruction
frequency fCT, during the falling edge of SCK. The first is terminated by driving CE# high (VIH).
Figure 14. Fast Read Dual-Output Sequence
CE#
9
0
2
3
4
5
8
31
1
6
7
10 11 28
29 30
SCK
SIO
...
3 - BYTE ADDRESS
2
1
INSTRUCTION = 0011 1011b
HIGH IMPEDANCE
23
3
0
...
22
21
SO
CE#
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
32
SCK
SIO
2
2
0
1
6
7
6
6
7
4
4
0
1
DATA OUT 1
DATA OUT 2
HIGH IMPEDANCE
SO
5
3
5
3
7
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
19
07/31/2013
IS25WD020/040
DEVICE OPERATION (CONTINUED)
PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION
The Page Program (PAGE_PROG) instruction allows
WIP bit in Status Register via a RDSR instruction. If
up to 256 bytes data to be programmed into memory in the WIP bit is “1”, the program operation is still in
a single operation. The destination of the memory to be progress. If WIP bit is “0”, the program operation has
programmed must be outside the protected memory
area set by the Block Protection (BP2, BP1, BP0) bits.
completed.
A PAGE_PROG instruction which attempts to program If more than 256 bytes data are sent to a device, the
into a page that is write-protected will be ignored.
Before the execution of PAGE_PROG instruction, the
address counter rolls over within the same page, the
previously latched data are discarded, and the last 256
Write Enable Latch (WEL) must be enabled through a bytes data are kept to be programmed into the page.
Write Enable (WREN) instruction.
The starting byte can be anywhere within the page.
When the end of the page is reached, the address will
wrap around to the beginning of the same page. If the
data to be programmed are less than a full page, the
data of all other bytes on the same page will remain
unchanged.
The PAGE_PROG instruction code, three address
bytes and program data (1 to 256 bytes) are input via
the Sl line. Program operation will start immediately
after the CE# is brought high, otherwise the
PAGE_PROG instruction will not be executed. The
internal control logic automatically handles the
programming voltages and timing. During a program
operation, all instructions will be ignored except the
RDSR instruction. The progress or completion of the
program operation can be determined by reading the
Note: A program operation can alter “1”s into “0”s, but
an erase operation is required to change “0”s back to
“1”s. A byte cannot be reprogrammed without first
erasing the whole sector or block.
Figure 15. Page Program Sequence
SIO
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
20
07/31/2013
IS25WD020/040
DEVICE OPERATION (CONTINUED)
ERASE OPERATION
operation can be determined by reading the WIP bit in
the Status Register using a RDSR instruction. If the
The memory array of the IS25WD020/040 is organized WIP bit is “1”, the erase operation is still in progress. If
into uniform 4 Kbyte sectors or 64 Kbyte uniform
blocks (a block consists of sixteen adjacent sectors).
Before a byte can be reprogrammed, the sector or
block that contains the byte must be erased (erasing
sets bits to “1”). In order to erase the devices, there are
three erase instructions available: Sector Erase
(SECTOR_ER), Block Erase (BLOCK_ER) and Chip
Erase (CHIP_ER). A sector erase operation allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases any
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to
any programming operation.
the WIP bit is “0”, the erase operation has been
completed.
BLOCK_ER COMMAND (BLOCK ERASE)
OPERATION
A Block Erase (BLOCK_ER) instruction erases a 64
Kbyte block of the IS25WD020/040. Before the
execution of a BLOCK_ER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable
(WREN) instruction. The WEL is reset automatically
after the completion of a block erase operation.
The BLOCK_ER instruction code and three address
bytes are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the
BLOCK_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 15 for Block Erase
Sequence.
SECTOR_ER COMMAND (SECTOR ERASE)
OPERATION
A SECTOR_ER instruction erases a 4 Kbyte sector.
Before the execution of a SECTOR_ER instruction, the
Write Enable Latch (WEL) must be set via a Write
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of sector an erase
operation.
CHIP_ER COMMAND (CHIP ERASE) OPERATION
A Chip Erase (CHIP_ER) instruction erases the entire
memory array of a IS25WD020/040. Before the
execution of CHIP_ER instruction, the Write Enable
Latch (WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automatically after
completion of a chip erase operation.
A SECTOR_ER instruction is entered, after CE# is
pulled low to select the device and stays low during the
entire instruction sequence The SECTOR_ER
instruction code, and three address bytes are input via
SI. Erase operation will start immediately after CE# is
pulled high. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
14 for Sector Erase Sequence.
The CHIP_ER instruction code is input via the SI.
Erase operation will start immediately after CE# is
pulled high, otherwise the CHIP_ER instruction will not
be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
16 for Chip Erase Sequence.
During an erase operation, all instruction will be
ignored except the Read Status Register (RDSR)
instruction. The progress or completion of the erase
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
21
07/31/2013
IS25WD020/040
DEVICE OPERATION (CONTINUED)
Figure 16. Sector Erase Sequence
SIO
Figure 17. Block Erase Sequence
SIO
Figure 18. Chip Erase Sequence
SIO
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
22
07/31/2013
IS25WD020/040
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias
Storage Temperature
-65oC to +125oC
-65oC to +125oC
Halogen-free Package 260oC 10 Seconds
Surface Mount Lead Soldering Temperature
Lead-free Package
260oC 10 Seconds
-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V
-0.5 V to +4.0 V
Input Voltage with Respect to Ground on All Pins (2)
All Output Voltage with Respect to Ground
VCC (2)
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only. The functional operation of the device conditions that exceed those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is
-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to
exceed 20 ns.
DC AND AC OPERATING RANGE
Part Number
IS25WD020/040
-40oC to 105oC
-40oC to 85oC
Operating Temperature (Extended Grade)
Operating Temperature (Automotive, A1 Grade)
Operating Temperature (Automotive, A2 Grade)
Vcc Power Supply
-40oC to 105oC
1.65 V – 1.95 V
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
23
07/31/2013
IS25WD020/040
DC CHARACTERISTICS
Applicable over recommended operating range from:
VCC = 1.65 V to 1.95 V (unless otherwise noted).
Symbol
ICC1
ICC2
ISB1
ISB2
ILI
Parameter
Condition
Min
Typ
2
Max
5
Units
mA
mA
A
mA
A
Vcc Active Read Current
Vcc Program/Erase Current
VCC = 1.95Vat 30 MHz, SO = Open
VCC = 1.95Vat 30 MHz, SO = Open
6
10
10
2
Vcc Standby Current CMOS VCC = 1.95V, CE# = VCC
Vcc Standby Current TTL
Input Leakage Current
Output Leakage Current
Input Low Voltage
VCC = 1.95V, CE# = VIH to VCC
VIN = 0V to VCC
VIN = 0V to VCC, TAC = 0oC to 85oC
1
ILO
1
A
V
VIL
-0.5
0.3
VCC
0.3
0.2
+
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
0.7VCC
V
V
V
VOL
VOH
IOL = 2.1 mA
1.65V < VCC < 1.95V
VCC
–
IOH = -100 A
0.2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
24
07/31/2013
IS25WD020/040
AC CHARACTERISTICS
Applicable over recommended operating range from VCC = 1.65 V to 1.95 V
CL = 1 TTL Gate and 10 pF (unless otherwise noted).
Symbol
fCT
Parameter
Min
0
Typ
Max
80
30
8
Units
MHz
MHz
ns
Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
fC
0
tRI
tFI
Input Fall Time
8
ns
tCKH
tCKL
tCEH
tCS
tCH
tDS
tDH
tHS
tHD
tV
SCK High Time
4
4
ns
SCK Low Time
ns
CE# High Time
25
10
5
ns
CE# Setup Time
ns
CE# Hold Time
ns
Data In Setup Time
Data in Hold Time
Hold Setup Time
2
ns
2
ns
15
15
ns
Hold Time
ns
Output Valid
8
ns
tOH
tLZ
Output Hold Time Normal Mode
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Sector/Block/Chip Erase Time
Page Program Time
VCC Set-up Time
0
ns
20
20
20
2
ns
tHZ
ns
tDIS
tEC
tPP
ns
1.7
2
ms
ms
s
3
tVCS
tw
50
Write Status Register time
2
ms
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
25
07/31/2013
IS25WD020/040
AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING (1)
SIO
Note: 1. For SPI Mode 0 (0,0)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
26
07/31/2013
IS25WD020/040
AC CHARACTERISTICS (CONTINUED)
HOLD TIMING
PIN CAPACITANCE (f = 1 MHz, T = 25°C )
Typ
4
Max
6
Units
pF
Conditions
VIN = 0 V
CIN
COUT
8
12
pF
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
27
07/31/2013
IS25WD020/040
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be is not guaranteed if, by this time, Vcc is still below
selected (CE# must follow the voltage applied on Vcc) Vcc(min). No Write Status Register, Program or Erase
until Vcc reaches the correct value:
instructions should be sent until the later of:
- Vcc(min) at Power-up, and then for a further delay of - tPUW after Vcc passed the VWI threshold
tVCE
- tVCE after Vcc passed the Vcc(min) level
0. Vss at Power-down
Usually a simple pull-up resistor on CE# can be used
At Power-up, the device is in the following state:
to insure safe and proper Power-up and Power-down. - The device is in the Standby mode
To avoid data corruption and inadvertent write
- The Write Enable Latch (WEL) bit is reset
operations during power up, a Power On Reset (POR)
circuit is included. The logic inside the device is held
reset while Vcc is less than the POR threshold value
At Power-down, when Vcc drops from the operating
voltage, to below the Vwi, all write operations are
(Vwi) during power up, the device does not respond to disabled
any instruction until a time delay of tPUW has elapsed and the device does not respond to any write
after the moment that Vcc rised above the Vwi
instruction.
threshold. However, the correct operation of the device
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed
Vcc(min)
Reset State
tVCE
Read Access Allowed
Device fully accessible
V (write inhibit)
tPUW
Time
Symbol
Parameter
Vcc(min) to CE# Low
Power-Up time delay to Write instruction
Min.
10
1
Max.
Unit
us
*1
tVCE
*1
tPUW
10
ms
Note : *1. These parameters are characterized only.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
28
07/31/2013
IS25WD020/040
PROGRAM/ERASE PERFORMANCE
Parameter
Unit Typ Max Remarks
Sector Erase Time
Block Erase Time
Chip Erase Time
ms
ms
ms
1.7
1.7
1.7
2
2
2
2
3
From writing erase command to erase completion
From writing erase command to erase completion
From writing erase command to erase completion
From writing program command to program completion
Page Programming Time ms
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS
Parameter
Min
200,000
20
Unit
Cycles
Years
Volts
Volts
mA
Test Method
Endurance
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
JEDEC Standard A115
JEDEC Standard 78
Data Retention
ESD – Human Body Model
ESD – Machine Model
Latch-Up
2,000
200
100 + ICC1
Note: These parameters are characterized and are not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
29
07/31/2013
IS25WD020/040
PACKAGE TYPE INFORMATION
JN
8-Pin SOIC 150mil Broad Small Outline Integrated Circuit Package (Unit: millimeters)
Note: Package dimensions are shown in mm
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
30
07/31/2013
IS25WD020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JV
8-Pin VVSOP 150mil (Unit: millimeters)
Note: Package dimensions are shown in mm
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
31
07/31/2013
IS25WD020/040
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
32
07/31/2013
IS25WD020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JB
8-Pin SOIC 208mil Broad Small Outline Integrated Circuit Package (Unit: millimeters)
Note: Package dimensions are shown in mm
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
33
07/31/2013
IS25WD020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JK
8-pin WSON Ultra-Thin Small Outline No-Lead Package (Unit: millimeters)
Note: Package dimensions are shown in mm
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
34
07/31/2013
IS25WD020/040
ORDERING INFORMATION:
Frequency
Density
Order Part Number
Package
(MHz)
IS25WD020-JBLE
IS25WD020-JNLE
IS25WD020-JVLE
IS25WD020-JKLE
IS25WD020-JBLA*
IS25WD020-JNLA*
IS25WD020-JVLA*
IS25WD020-JKLA*
IS25WD020-JWLE
IS25WD040-JNLE
IS25WD040-JBLE
IS25WD040-JVLE
IS25WD040-JKLE
IS25WD040-JNLA*
IS25WD040-JBLA*
IS25WD040-JVLA*
IS25WD040-JKLA*
IS25WD020-JWLE
8-pin SOIC 208mil
8-pin SOIC 150mil
8-pin VVSOP 150mil
8-pin WSON (5x6mm)
8-pin SOIC 208mil (Call Factory)
8-pin SOIC 150mil (Call Factory)
8-pin VVSOP 150mil (Call Factory)
8-pin WSON (5x6mm) (Call Factory)
KGD (Call Factory)
8-pin SOIC 150mil
8-pin SOIC 208mil
8-pin VVSOP 150mil
8-pin WSON (5x6mm)
2M
80
4M
80
8-pin SOIC 150mil (Call Factory)
8-pin SOIC 208mil (Call Factory)
8-pin VVSOP 150mil (Call Factory)
8-pin WSON (5x6mm) (Call Factory)
KGD (Call Factory)
A* = A1, A2 Automotive Temperature Ranges
Integrated Silicon Solution, Inc.- www.issi.com
Rev. F
35
07/31/2013
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