IS25WP256D-FHLA3_技术文档

IS25LP256D IS25WP256D

256Mb

SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI &

QUAD I/O QPI DTR INTERFACE

DATA SHEET

IS25LP256D

IS25WP256D

256Mb

SERIAL FLASH MEMORY WITH 166MHZ MULTI I/O SPI &

QUAD I/O QPI DTR INTERFACE

FEATURES

 Industry Standard Serial Interface

 Low Power with Wide Temp. Ranges

- Single Voltage Supply

- IS25LP256D: 256Mbit/32Mbyte

- IS25WP256D: 256Mbit/32Mbyte

- 3 or 4 Byte Addressing Mode

- Supports Standard SPI, Fast, Dual, Dual

I/O, Quad, Quad I/O, SPI DTR, Dual I/O

DTR, Quad I/O DTR, and QPI

- Software & Hardware Reset

- Supports Serial Flash Discoverable

Parameters (SFDP)

IS25LP: 2.30V to 3.60V

IS25WP: 1.65V to 1.95V

- 7.5 mA Active Read Current

- 10 µA Standby Current

- 1 µA Deep Power Down

- Temp Grades:

Extended: -40°C to +105°C

Auto Grade (A3): -40°C to +125°C

 Advanced Security Protection

 High Performance Serial Flash (SPI)

- Software and Hardware Write Protection

- Advanced Sector/Block Protection

- Top/Bottom Block Protection

- Power Supply Lock Protection

- 4x256 Byte Dedicated Security Area

with OTP User-lockable Bits

- 80MHz Normal Read

- Up to166Mhz Fast Read:

-166MHz at Vcc=2.7V to 3.6V ⁽¹⁾

-133MHz at Vcc=2.3V to 3.6V

-133MHz at Vcc=1.65V to 1.95V ⁽²⁾

- Up to 80MHz DTR (Dual Transfer Rate)

- Equivalent Throughput of 664 Mb/s

- Selectable Dummy Cycles

- 128 bit Unique ID for Each Device

(Call Factory)

 Industry Standard Pin-out & Packages

- Configurable Drive Strength

- Supports SPI Modes 0 and 3

- More than 100,000 Erase/Program Cycles

- More than 20-year Data Retention

- M =16-pin SOIC 300mil

- L = 8-contact WSON 8x6mm

- J = 8-contact WSON 8x6mm ⁽³⁾

- G = 24-ball TFBGA (4x6 ball array)

- H = 24-ball TFBGA (5x5 ball array)

- KGD (Call Factory)

 Flexible & Efficient Memory Architecture

- Chip Erase with Uniform Sector/Block

Erase (4/32/64 Kbyte)

- Program 1 to 256 Byte per Page

- Program/Erase Suspend & Resume

Note:

1. 166MHz at Mode 0 , and 133MHz at Mode 3

2. 104MHz with 3-byte address (24-bit address) fast read

operation

3. Exposed Pad Size = 3.4mmx4.3mm instead of

4.7mmx4.7mm

 Efficient Read and Program modes

- Low Instruction Overhead Operations

- Continuous Read 8/16/32/64 Byte

Burst Wrap

- Selectable Burst Length

- QPI for Reduced Instruction Overhead

- AutoBoot Operation

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

2

04/15/2019

IS25LP256D

IS25WP256D

GENERAL DESCRIPTION

The IS25LP256D and IS25WP256D Serial Flash memory offers a versatile storage solution with high flexibility

and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems

that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire

SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable

(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies

of up to 166MHz allow for equivalent clock rates of up to 664MHz (166MHz x 4) which equates to 83Mbytes/s of

data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer

addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash

memories allowing for efficient memory access to support XIP (execute in place) operation.

Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.

QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be

erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector

and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of

applications requiring solid data retention.

GLOSSARY

Standard SPI

In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),

Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,

addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the

status of the device. This device supports SPI bus operation modes (0,0) and (1,1).

Mutil I/O SPI

Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input

and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode

will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.

Quad I/O QPI

The device enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode uses four IO

pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI and SO pins

become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during QPI mode.

Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or Hardware/Software

Reset can also return the device into the standard SPI mode.

DTR

In addition to SPI and QPI features, the device also supports Fast READ DTR operation. Fast READ DTR operation

allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising

and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles

by half.

Programmable drive strength and Selectable burst setting.

The device offers programmable output drive strength and selectable burst (wrap) length features to increase the

efficiency and performance of READ operation. The driver strength and burst setting features are controlled by

setting the Read Registers. A total of six different drive strengths and four different burst sizes (8/16/32/64 Byte)

are available for selection.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

3

04/15/2019

IS25LP256D

IS25WP256D

TABLE OF CONTENTS

FEATURES...........................................................................................................................................................2

GENERAL DESCRIPTION ...................................................................................................................................3

TABLE OF CONTENTS........................................................................................................................................4

1. PIN CONFIGURATION..................................................................................................................................7

2. PIN DESCRIPTIONS.....................................................................................................................................9

3. BLOCK DIAGRAM.......................................................................................................................................11

4. SPI MODES DESCRIPTION .......................................................................................................................12

5. SYSTEM CONFIGURATION.......................................................................................................................14

5.1 BLOCK/SECTOR ADDRESSES ...........................................................................................................14

6. REGISTERS ................................................................................................................................................15

6.1 STATUS REGISTER .............................................................................................................................15

6.2 FUNCTION REGISTER.........................................................................................................................19

6.3 READ REGISTER AND EXTENDED REGISTER.................................................................................20

6.3.1 READ REGISTER .........................................................................................................................20

6.3.2 EXTENDED READ REGISTER.....................................................................................................23

6.4 AUTOBOOT REGISTER .......................................................................................................................25

6.5 BANK ADDRESS REGISTER ...............................................................................................................26

6.6 ADVANCED SECTOR/BLOCK PROTECTION (ASP) RELATED REGISTER.....................................27

6.6.1 ADVANCED SECTOR/BLOCK PROTECTION REGISTER (ASPR)............................................27

6.6.2 PASSWORD REGISTER ..............................................................................................................28

6.6.3 PPB LOCK REGISTER .................................................................................................................28

6.6.4 PPB REGISTER ............................................................................................................................29

6.6.5 DYB REGISTER............................................................................................................................29

7. PROTECTION MODE..................................................................................................................................30

7.1 HARDWARE WRITE PROTECTION.....................................................................................................30

7.2 SOFTWARE WRITE PROTECTION .....................................................................................................30

7.2.1 BLOCK PROTECTION BITS.........................................................................................................30

7.2.2 ADVANCED SECTOR/BLOCK PROTECTION (ASP) ..................................................................31

8. DEVICE OPERATION .................................................................................................................................38

8.1 COMMAND OVERVIEW .......................................................................................................................38

8.2 COMMAND SET SUMMARY ................................................................................................................39

8.3 NORMAL READ OPERATION (NORD, 03h or 4NORD, 13h)..............................................................48

8.4 FAST READ OPERATION (FRD, 0Bh or 4FRD, 0Ch)..........................................................................51

8.5 HOLD OPERATION...............................................................................................................................55

8.6 FAST READ DUAL I/O OPERATION (FRDIO, BBh or 4FRDIO, BCh).................................................56

8.7 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh or 4FRDO, 3Ch)..........................................60

8.8 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh or 4FRQO 6Ch) .........................................63

8.9 FAST READ QUAD I/O OPERATION (FRQIO, EBh or 4FRQIO, ECh)................................................66

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Rev A6

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04/15/2019

IS25LP256D

IS25WP256D

8.10 PAGE PROGRAM OPERATION (PP, 02h or 4PP, 12h).....................................................................73

8.11 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h or 4PPQ, 34h/3Eh).........................76

8.12 ERASE OPERATION ..........................................................................................................................77

8.13 SECTOR ERASE OPERATION (SER, D7h/20h or 4SER, 21h).........................................................78

8.14 BLOCK ERASE OPERATION (BER32K:52h or 4BER32K:5Ch, BER64K:D8h or 4BER64K:DCh)...80

8.15 CHIP ERASE OPERATION (CER, C7h/60h)......................................................................................83

8.16 WRITE ENABLE OPERATION (WREN, 06h) .....................................................................................84

8.17 WRITE DISABLE OPERATION (WRDI, 04h)......................................................................................85

8.18 READ STATUS REGISTER OPERATION (RDSR, 05h) ....................................................................86

8.19 WRITE STATUS REGISTER OPERATION (WRSR, 01h)..................................................................87

8.20 READ FUNCTION REGISTER OPERATION (RDFR, 48h)................................................................88

8.21 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)..............................................................89

8.22 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h).90

8.23 PROGRAM/ERASE SUSPEND & RESUME.......................................................................................91

8.24 ENTER DEEP POWER DOWN (DP, B9h)..........................................................................................94

8.25 RELEASE DEEP POWER DOWN (RDPD, ABh)................................................................................95

8.26 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h) .......................................96

8.27 SET EXTENDED READ PARAMETERS OPERATION (SERPNV: 85h, SERPV: 83h) .....................98

8.28 READ READ PARAMETERS OPERATION (RDRP, 61h)..................................................................99

8.29 READ EXTENDED READ PARAMETERS OPERATION (RDERP, 81h).........................................100

8.30 CLEAR EXTENDED READ REGISTER OPERATION (CLERP, 82h)..............................................101

8.31 READ PRODUCT IDENTIFICATION (RDID, ABh) ...........................................................................102

8.32 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)

...................................................................................................................................................................104

8.33 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h).......................105

8.34 READ UNIQUE ID NUMBER (RDUID, 4Bh) .....................................................................................106

8.35 READ SFDP OPERATION (RDSFDP, 5Ah) .....................................................................................107

8.36 NO OPERATION (NOP, 00h)............................................................................................................107

8.37 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE

RESET .......................................................................................................................................................108

8.38 SECURITY INFORMATION ROW.....................................................................................................109

8.39 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................110

8.40 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................111

8.41 INFORMATION ROW READ OPERATION (IRRD, 68h) ..................................................................112

8.42 FAST READ DTR MODE OPERATION (FRDTR, 0Dh or 4FRDTR, 0Eh)........................................113

8.43 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh or 4FRDDTR, BEh) ..................118

8.44 FAST READ QUAD I/O DTR MODE OPERATION IN SPI MODE (FRQDTR, EDh or 4FRQDTR,

EEh) ...........................................................................................................................................................122

8.45 SECTOR LOCK/UNLOCK FUNCTIONS...........................................................................................130

8.46 AUTOBOOT.......................................................................................................................................133

8.47 READ BANK ADDRESS REGISTER OPERATION (RDBR: 16h/C8h) ............................................137

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IS25LP256D

IS25WP256D

8.48 WRITE BANK ADDRESS REGISTER OPERATION (WRBRNV: 18h, WRBRV: 17h/C5h) .............138

8.49 ENTER 4-BYTE ADDRESS MODE OPERATION (EN4B, B7h) .......................................................139

8.50 EXIT 4-BYTE ADDRESS MODE OPERATION (EX4B, 29h)............................................................140

8.51 READ DYB OPERATION (RDDYB, FAh or 4RDDYB, E0h) .............................................................141

8.52 WRITE DYB OPERATION (WRDYB, FBh or 4WRDYB, E1h)..........................................................143

8.53 READ PPB OPERATION (RDPPB, FCh or 4RDPPB, E2h) .............................................................145

8.54 PROGRAM PPB OPERATION (PGPPB, FDh or 4PGPPB, E3h).....................................................146

8.55 ERASE PPB OPERATION (ERPPB, E4h) ........................................................................................148

8.56 READ ASP OPERATION (RDASP, 2Bh) ..........................................................................................149

8.57 PROGRAM ASP OPERATION (PGASP, 2Fh)..................................................................................150

8.58 READ PPB LOCK BIT OPERATION (RDPLB, A7h).........................................................................151

8.59 WRITE PPB LOCK BIT OPERATION (WRPLB, A6h).......................................................................152

8.60 SET FREEZE BIT OPERATION (SFRZ, 91h)...................................................................................153

8.61 READ PASSWORD OPERATION (RDPWD, E7h)...........................................................................154

8.62 PROGRAM PASSWORD OPERATION (PGPWD, E8h) ..................................................................155

8.63 UNLOCK PASSWORD OPERATION (UNPWD, E9h)......................................................................156

8.64 GANG SECTOR/BLOCK LOCK OPERATION (GBLK, 7Eh) ............................................................157

8.65 GANG SECTOR/BLOCK UNLOCK OPERATION (GBUN, 98h).......................................................158

9. ELECTRICAL CHARACTERISTICS..........................................................................................................159

9.1 ABSOLUTE MAXIMUM RATINGS ⁽¹⁾..................................................................................................159

9.2 OPERATING RANGE..........................................................................................................................159

9.3 DC CHARACTERISTICS.....................................................................................................................160

9.4 AC MEASUREMENT CONDITIONS ...................................................................................................161

9.5 PIN CAPACITANCE ............................................................................................................................161

9.6 AC CHARACTERISTIC .......................................................................................................................162

9.7 SERIAL INPUT/OUTPUT TIMING.......................................................................................................164

9.8 POWER-UP AND POWER-DOWN .....................................................................................................166

9.9 PROGRAM/ERASE PERFORMANCE................................................................................................167

9.10 RELIABILITY CHARACTERISTICS ..................................................................................................167

10.

PACKAGE TYPE INFORMATION........................................................................................................168

10.1 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8x6mm (L)..............168

10.2 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8x6mm (J)..............169

10.3 16-LEAD PLASTIC SMALL OUTLINE PACKAGE (300 MILS BODY WIDTH) (M)...........................170

10.4 24-BALL THIN PROFILE FINE PITCH BGA 6x8mm 4x6 BALL ARRAY (G)....................................171

10.5 24-BALL THIN PROFILE FINE PITCH BGA 6x8mm 5x5 BALL ARRAY (H) ....................................172

ORDERING INFORMATION – Valid Part Numbers.............................................................................173

11.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

6

04/15/2019

IS25LP256D

IS25WP256D

1. PIN CONFIGURATION

HOLD# (IO3)^(1,2)

HOLD# or RESET# (IO3)

SCK

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

Vcc

(3)

SI (IO0)

NC

RESET#/NC

Vcc

8

CE#

1

NC

HOLD# or

RESET# (IO3)⁽¹⁾

SO (IO1)

2

7

6

5

NC

SCK

NC

WP# (IO2)

GND

3

CE#

GND

WP# (IO2)

4

SI (IO0)

SO (IO1)

8-contact WSON 8x6mm

16-pin SOIC 300mil

Top View, Balls Facing Down

A1

A2

A3

A4

(3)

A2

A3

A4

A5

NC

RESET#(NC)

(3)

NC

NC RESET#/(NC)

NC

B1

B2

B3

B4

B1

B2

B3

B4

B5

NC

SCK

GND

VCC

NC

SCK

GND

VCC

NC

C1

C2

C3

C4

C1

C2

C3

C4

C5

NC

CE#

NC

WP#(IO2)

NC

CE#

NC

WP#(IO2)

NC

D1

D2

D3

D4

HOLD# or ^(1,2)

RESET# (IO3)

D1

D2

D3

D4

D5

NC

SO(IO1)

SI(IO0)

(1,2)

HOLD# or

RESET# (IO3)

NC

SO(IO1)

SI(IO0)

NC

E1

E2

E3

E4

E1

E2

E3

E4

E5

NC

F1

F2

F3

F4

NC

24-ball TFBGA, 4x6 Ball Array (Package:G)

24-ball TFBGA, 5x5 Ball Array (Package:H)

Notes:

1. The pin can be configured as Hold# or Reset# by setting P7 bit of the Read Register. Pin default is Hold#.

2. Dedicated RESET# pin is available in devices with a dedicated part number, in these devices Pin 1 (16-pin

SOIC) or ball D4 (24-ball TFBGA) are set to Hold# regardless of P7 setting of the Read Register.

Integrated Silicon Solution, Inc.- www.issi.com

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IS25LP256D

IS25WP256D

3. For compatibility, the pin can be disabled on dedicated part numbers by setting Bit0 (Dedicated RESET#

Disable) of the Function Register to “1” (default is “0” from factory on dedicated part numbers). An internal

pull-up resistor exists and the pin may be left floating if not used.

16-pin SOIC / 24-ball TFBGA

Pin1 / Ball D4

Device with HOLD#/RESET#

Device with dedicated RESET#

Hold#(IO3) or RESET#(IO3) by P7 bit setting

Hold#(IO3) only regardless of P7 bit setting

Pin3 / Ball A4

NC

J

RESET#

R or P

Part Number Option

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

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IS25LP256D

IS25WP256D

2. PIN DESCRIPTIONS

For the device with Hold#/RESET#

SYMBOL

TYPE

DESCRIPTION

Chip Enable: The Chip Enable (CE#) pin enables and disables the devices

operation. When CE# is high the device is deselected and output pins are in a high

impedance state. When deselected the devices non-critical internal circuitry power

down to allow minimal levels of power consumption while in a standby state.

When CE# is pulled low the device will be selected and brought out of standby mode.

The device is considered active and instructions can be written to, data read, and

written to the device. After power-up, CE# must transition from high to low before a

new instruction will be accepted.

CE#

INPUT

Keeping CE# in a high state deselects the device and switches it into its low power

state. Data will not be accepted when CE# is high.

Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):

This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI

instructions use the unidirectional SI (Serial Input) pin to write instructions,

addresses, or data to the device on the rising edge of the Serial Clock (SCK).

Standard SPI also uses the unidirectional SO (Serial Output) to read data or status

from the device on the falling edge of the serial clock (SCK).

SI (IO0),

SO (IO1)

INPUT/

OUTPUT

In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write

instructions, addresses or data to the device on the rising edge of the Serial Clock

(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI

instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.

Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from

being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the

WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are

write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status

Register is not write-protected regardless of WP# state.

INPUT/

OUTPUT

WP# (IO2)

When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available

since this pin is used for IO2.

HOLD# or RESET#/Serial Data IO (IO3): When the QE bit of Status Register is set

to “1”, HOLD# pin or RESET# is not available since it becomes IO3. When QE=0 the

pin acts as HOLD# or RESET# and either one can be selected by the P7 bit setting

in Read Register. HOLD# will be selected if P7=0 (Default) and RESET# will be

selected if P7=1.

The HOLD# pin allows the device to be paused while it is selected. It pauses serial

communication by the master device without resetting the serial sequence. The

HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin

will be at high impedance. Device operation can resume when HOLD# pin is brought

to a high state.

HOLD# or

RESET# (IO3)

INPUT/

OUTPUT

RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the memory

is in the normal operating mode. When RESET# is driven LOW, the memory enters

reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE,

PROGRAM, or ERASE operation is in progress, data may be lost.

Serial Data Clock: Synchronized Clock for input and output timing operations.

Power: Device Core Power Supply

SCK

Vcc

INPUT

POWER

GROUND

Unused

Ground: Connect to ground when referenced to Vcc

GND

NC

NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.

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IS25LP256D

IS25WP256D

For the device with dedicated RESET#

SYMBOL

TYPE

DESCRIPTION

CE#

INPUT

Same as the description in previous page

SI (IO0),

SO (IO1)

INPUT/

OUTPUT

Same as the description in previous page

INPUT/

OUTPUT

WP# (IO2)

HOLD#/Serial Data IO (IO3): When the QE bit of Status Register is set to “1”, HOLD#

pin is not available since it becomes IO3. When QE=0 the pin acts as HOLD#

regardless of the P7 bit of Read Register.

INPUT/

OUTPUT

The HOLD# pin allows the device to be paused while it is selected. It pauses serial

communication by the master device without resetting the serial sequence. The

HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin

will be at high impedance. Device operation can resume when HOLD# pin is brought

to a high state.

HOLD# (IO3)

RESET#: This pin is available only for dedicated parts (Call Factory for 24-ball

TFBGA 6x8mm packages).

The RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the

memory is in the normal operating mode. When RESET# is driven LOW, the memory

enters reset mode and output is High-Z. If RESET# is driven LOW while an internal

WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

RESET#

INPUT

SCK

Vcc

INPUT

POWER

GROUND

Unused

Same as the description in previous page

GND

NC

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Rev A6

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IS25LP256D

IS25WP256D

3. BLOCK DIAGRAM

Control Logic

High Voltage Generator

Status

Register

I/O Buffers and

Data Latches

256 Bytes

Page Buffer

CE#

SCK

WP#

(IO2)

Y-Decoder

SI

(IO0)

SO

(IO1)

HOLD# or RESET#⁽¹⁾

(IO3)

Memory Array

Address Latch &

Counter

Notes:

1. According to the P7 bit setting in Read Register, either HOLD# (P7=0) or RESET# (P7=1) pin can be selected.

2. SI and SO pins become bidirectional IO0 and IO1 respectively during Dual I/O mode and SI, SO, WP#, and

HOLD#/RESET# pins become bidirectional IO0, IO1, IO2, and IO3 respectively during Quad I/O or QPI mode.

3. In case of 16-pin SOIC and 24-ball TFBGA packages, dedicated RESET# function is supported without sharing with

HOLD# pin for the dedicated parts. See the Ordering Information for the dedicated RESET# pin

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

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IS25LP256D

IS25WP256D

4. SPI MODES DESCRIPTION

Multiple IS25LP256D devices or multiple IS25WP256D devices can be connected on the SPI serial bus and

controlled by a SPI Master, i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI

modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial

clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure

4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock

(SCK), and the output data is available from the falling edge of SCK.

Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SDO

SDI

SPI interface with

(0,0) or (1,1)

SCK

SCK SO SI

SPI Master

(i.e. Microcontroller)

SPI

Memory

Device

Memory

Device

Memory

Device

CS3

CS2

CS1

CE#

HOLD#

or RESET#

HOLD#

WP#

or RESET#

WP#

HOLD#

or RESET#

Notes:

1. According to the P7 bit setting in Read Register, either HOLD# (P7=0) or RESET# (P7=1) pin can be selected.

2. SI and SO pins become bidirectional IO0 and IO1 respectively during Dual I/O mode and SI, SO, WP#, and

HOLD#/RESET# pins become bidirectional IO0, IO1, IO2, and IO3 respectively during Quad I/O or QPI mode.

3. In case of 16-pin SOIC and 24-ball TFBGA packages, dedicated RESET# function is supported without sharing with

HOLD# pin for the dedicated parts. See the Ordering Information for the dedicated RESET# pin

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Figure 4.2 SPI Mode Support

SCK

Mode 0 (0,0)

SCK

Mode 3 (1,1)

MSB

SI

SO

MSB

Figure 4.3 QPI Mode Support

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

3-byte Address

Mode Bits

Data 1

Data 2

Data 3

...

IO0

IO1

4

5

6

7

4

C4

C5

C6

C0

C1

C2

0

1

2

3

4

0

1

2

3

0

1

2

3

4

0

1

2

3

4

0

1

2

3

20

21

16

17

18

19

12

13

14

15

8

9

5

IO2

IO3

6

22

10

11

7¹

23¹

7¹

C7¹C3

Note1: MSB (Most Significant Bit)

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5. SYSTEM CONFIGURATION

The memory array is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a block consists of

eight/sixteen adjacent sectors respectively).

Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.

5.1 BLOCK/SECTOR ADDRESSES

Table 5.1 Block/Sector Addresses

Memory

Density

Block No.

(64Kbyte)

Block No.

(32Kbyte)

Sector Size

(Kbyte)

Sector No.

Address Range

Sector 0

4

:

000000h - 000FFFh

Block 0

Block 1

Block 2

Block 3

Block 4

:

Block 0

Block 1

:

Sector 15

4

:

00F000h - 00FFFFh

Sector 16

010000h - 010FFFh

:

Sector 31

4

:

01F000h - 01FFFFh

Sector 32

020000h - 020FFFh

:

Block 2

:

Block 5

:

Sector 47

4

02F000h - 02FFFFh

:

Sector 4064

4

:

FE0000h – FE0FFFh

Block 508

:

Block 254

:

Block 509

Block 510

Sector 4079

4

:

FEF000h – FEFFFFh

Sector 4080

FF0000h – FF0FFFh

:

Block 255

:

Block 511

:

Sector 4095

4

FFF000h – FFFFFFh

:

Sector 8160

4

:

1FE0000h – 1FE0FFFh

Block 1020

:

Block 510

:

Block 1021

Block 1022

Block 1023

Sector 8175

4

:

1FEF000h – 1FEFFFFh

Sector 8176

1FF0000h – 1FF0FFFh

:

Block 511

:

Sector 8191

4

1FFF000h – 1FFFFFFh

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6. REGISTERS

The device has various sets of Registers: Status, Function, Read, Extended Read and Autoboot.

When the register is read continuously, the same data is output repeatedly until CE# goes HIGH.

6.1 STATUS REGISTER

Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.

Table 6.1 Status Register Format

Bit 7

SRWD

0

Bit 6

QE

0

Bit 5

BP3

0

Bit 4

BP2

0

Bit 3

BP1

0

Bit 2

BP0

0

Bit 1

WEL

0

Bit 0

WIP

0

Default

Table 6.2 Status Register Bit Definition

Read-

/Write

Bit

Name

Definition

Type

Write In Progress Bit:

"0" indicates the device is ready (default)

"1" indicates a write cycle is in progress and the device is busy

Write Enable Latch:

"0" indicates the device is not write enabled (default)

"1" indicates the device is write enabled

Bit 0

WIP

R

Volatile

Bit 1

WEL

R/W¹

R/W

Bit 2

Bit 3

Bit 4

Bit 5

BP0

BP1

BP2

BP3

Block Protection Bit: (See Tables 6.4 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

Non-Volatile

Quad Enable bit:

Bit 6

Bit 7

QE

“0” indicates the Quad output function disable (default)

“1” indicates the Quad output function enable

Status Register Write Disable: (See Table 7.1 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

R/W

Non-Volatile

SRWD

Note: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.

The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status

Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0” at

factory. The Status Register can be read by the Read Status Register (RDSR).

The function of Status Register bits are described as follows:

WIP bit: Write In Progress (WIP) is read-only, and can be used to detect the progress or completion of a Program,

Erase, Write/Set Non-Volatile/OTP Register, or Gang Sector/Block Lock/Unlock operation. WIP is set to “1” (busy

state) when the device is executing the operation. During this time the device will ignore further instructions except

for Read Status/Function/Extended Read Register and Software/Hardware Reset instructions. In addition to the

instructions, an Erase/Program Suspend instruction also can be executed during a Program or Erase operation.

When an operation has completed, WIP is cleared to “0” (ready state) whether the operation is successful or not

and the device is ready for further instructions.

WEL bit: Write Enable Latch (WEL) indicates the status of the internal write enable latch. When WEL is “0”, the

internal write enable latch is disabled and the Write operations described in Table 6.3 are inhibited. When WEL is

“1”, the Write operations are allowed. WEL is set by a Write Enable (WREN) instruction. Each Write Non-Volatile

Register, Program and Erase instruction must be preceded by a WREN instruction. The volatile register related

commands such as the Set Volatile Read Register, the Set Volatile Extended Read Register, the Write Volatile

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Bank Address Register, and WRDYB don’t require to set WEL to “1". WEL can be reset by a Write Disable (WRDI)

instruction. It will automatically reset after the completion of any Write operation.

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Table 6.3 Instructions requiring WREN instruction ahead

Instructions must be preceded by the WREN instruction

Name

Hex Code

02h

Operation

Serial Input Page Program (3-byte or 4-byte Address)

Serial Input Page Program (4-byte Address)

Quad Input Page Program (3-byte or 4-byte Address)

Quad Input Page Program (4-byte Address)

Sector Erase 4KB (3-byte or 4-byte Address)

Sector Erase 4KB (4-byte Address)

Block Erase 32KB (3-byte or 4-byte Address)

Block Erase 32KB (4-byte Address)

Block Erase 64KB (3-byte or 4-byte Address)

Block Erase 64KB (4-byte Address)

Chip Erase

PP

4PP

12h

PPQ

32h/38h

34h/3Eh

D7h/20h

21h

4PPQ

SER

4SER

BER32 (32KB)

4BER32 (32KB)

BER64 (64KB)

4BER64 (64KB)

CER

52h

5Ch

D8h

DCh

C7h/60h

01h

WRSR

Write Status Register

WRFR

42h

Write Function Register

SRPNV

SERPNV

IRER

65h

Set Read Parameters (Non-Volatile)

Set Extended Read Parameters (Non-Volatile)

Erase Information Row

85h

64h

IRP

62h

Program Information Row

WRABR

WRBRNV

PGPPB

4PGPPB

ERPPB

PGASP

WRPLB

SFRZ

15h

Write AutoBoot Register

18h

Write Non-Volatile Bank Address Register

Write PPB (3-byte or 4-byte Address)

Write PPB (4-byte Address)

FDh

E3h

E4h

Erase PPB

2Fh

Program ASP

A6h

Write PPB Lock Bit

91h

Set FREEZE bit

PGPWD

E8h

Program Password

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of

the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a defined

combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any program or

erase operation to that area will be inhibited.

Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.

SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)

signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-

protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register (SRWD, QE,

BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and

WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the QE

bit is set to “0”, the pin WP# and HOLD#/RESET# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins

are enabled.

WARNING: The QE bit must be set to “0” if WP# or HOLD#/RESET# pin (or ball) is tied directly to the power supply.

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Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits

Status Register Bits Protected Memory Area (256M, 512Blocks)

BP0 TBS(T/B selection) = 0, Top area TBS(T/B selection) = 1, Bottom area

BP3

0

BP2

0

BP1

0

1

0

1

0

1

0

1

0

1

x

0 ( None)

0

1 (1 block: 511^st)

1 (1 block: 0^th)

0

1

2 (2 blocks: 510^thand 511^st)

3 (4 blocks: 508^thto 511^st)

4 (8 blocks: 504^thto 511^st)

5 (16 blocks: 496^thto 511^st)

6 (32 blocks: 480^thto 511^st)

7 (64 blocks: 448^thto 511^st)

8 (128 blocks: 384^thto 511^st)

9 (256 blocks: 256^thto 511^st)

10-11 (512 blocks: 0^thto 511^st) All blocks

12-15 (512 blocks: 0^thto 511^st) All blocks

2 (2 blocks: 0^thand 1^st)

3 (4 blocks: 0^thto 3^rd)

0

1

0

1

0

4 (8 blocks: 0^thto 7^th)

0

1

0

5 (16 blocks: 0^thto 15^th)

6 (32 blocks: 0^thto 31^st)

7 (64 blocks: 0^thto 63^rd)

8 (128 blocks: 0^thto 127^th)

9 (256 blocks: 0^thto 255^th)

10-11 (512 blocks: 0^thto 511^st) All blocks

12-15 (512 blocks: 0^thto 511^st) All blocks

0

1

0

1

0

1

0

1

0

1

x

Note: x is don’t care

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6.2 FUNCTION REGISTER

Function Register Format and Bit definition are described in Table 6.5 and Table 6.6.

Table 6.5 Function Register Format

Bit 7

IRL3

0

Bit 6

IRL2

0

Bit 5

IRL1

0

Bit 4

IRL0

0

Bit 3

ESUS

0

Bit 2

PSUS

0

Bit 1

TBS

0

Bit 0

Dedicated

RESET# Disable

Default

0 or 1

Table 6.6 Function Register Bit Definition

Read

/Write

Bit

Name

Definition

Type

Dedicated RESET# Disable bit

Dedicated

RESET# Disable

R/W for 0

R for 1

Bit 0

“0” indicates Dedicated RESET# was enabled

“1” indicates Dedicated RESET# was disabled

Top/Bottom Selection. (See Table 6.4 for details)

“0” indicates Top area.

“1” indicates Bottom area.

Program suspend bit:

“0” indicates program is not suspend

“1” indicates program is suspend

Erase suspend bit:

OTP

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

TBS

R/W

R

OTP

Volatile

OTP

PSUS

ESUS

"0" indicates Erase is not suspend

"1" indicates Erase is suspend

Lock the Information Row 0:

“0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

R

IR Lock 0

IR Lock 1

IR Lock 2

IR Lock 3

R/W

Lock the Information Row 1:

“0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

Lock the Information Row 2:

“0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

Lock the Information Row 3:

OTP

“0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

OTP

Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.

Dedicated RESET# Disable bit: The default status of the bit is dependent on part number. The device with

dedicated RESET# can be programmed to “1” to disable dedicated RESET# function to move RESET# function to

Hold#/RESET# pin (or ball). So the device with dedicated RESET# can be used for dedicated RESET# application

and HOLD#/RESET# application.

TBS bit: BP0~3 area assignment can be changed from Top (default) to Bottom by setting TBS bit to “1”.

However, once Bottom is selected, it cannot be changed back to Top since TBS bit is OTP. See Table 6.4 for

details.

PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS

changes to “1” after a suspend command is issued during the program operation. Once the suspended Program

resumes, the PSUS bit is reset to “0”.

ESUS bit: The Erase Suspend Status bit indicates when an Erase operation has been suspended. The ESUS bit

is “1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the

ESUS bit is reset to “0”.

IR Lock bit 0 ~ 3: The default is “0” so that the Information Row can be programmed. If the bit is set to “1”, it cannot

be changed back to “0” again since IR Lock bits are OTP.

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6.3 READ REGISTER AND EXTENDED REGISTER

Read Register format and bit definitions are described below. Read Register and Extended Read Register consist

of a pair of rewritable non-volatile register and volatile register, respectively. During power up sequence, volatile

register will be loaded with the value of non-volatile value.

6.3.1 READ REGISTER

Table 6.7 and Table 6.8 define all bits that control features in SPI/QPI modes. HOLD#/RESET# pin selection (P7)

bit is used to select HOLD# pin or RESET# pin in SPI mode when QE=“0” for the device with HOLD#/RESET#.

When QE=1 or in QPI mode, P7 bit setting will be ignored since the pin becomes IO3.

For 16-pin SOIC or 24-ball TFBGA with dedicated RESET# device (Dedicated RESET# Disable bit in Functional

Register is “0”), HOLD# will be selected regardless of P7 bit setting when QE=“0” in SPI mode.

The SET READ PARAMETERS Operations (SRPNV: 65h, SRPV: C0h or 63h) are used to set all the Read Register

bits, and can thereby define HOLD#/RESET# pin (or ball) selection, dummy cycles, and burst length with wrap

around. SRPNV is used to set the non-volatile register and SRPV is used to set the volatile register.

Table 6.7 Read Register Parameter Bit Table

P7

P6

P5

P4

P3

P2

P1

P0

HOLD#/

RESET#

Dummy

Cycles

Dummy

Cycles

Dummy

Cycles

Dummy

Cycles

Wrap

Enable

Burst

Length

Burst

Length

Default

0

Table 6.8 Read Register Bit Definition

Read-

/Write

Bit

P0

P1

Name

Definition

Type

Non-Volatile

and Volatile

Non-Volatile

and Volatile

Burst Length

R/W

Burst Length Set Enable Bit:

"0" indicates disable (default)

"1" indicates enable

Burst Length

Set Enable

Non-Volatile

and Volatile

P2

Non-Volatile

and Volatile

Non-Volatile

and Volatile

Non-Volatile

and Volatile

Non-Volatile

and Volatile

P3

P4

P5

P6

Dummy Cycles

R/W

Number of Dummy Cycles:

Bits1 to Bit4 can be toggled to select the number of dummy cycles

(1 to 15 cycles)

HOLD#/RESET# function selection Bit:

"0" indicates the HOLD# function is selected (default)

"1" indicates the RESET# function is selected

HOLD#/

RESET#

Non-Volatile

and Volatile

P7

R/W

Table 6.9 Burst Length Data

P1

0

P0

0

8 bytes

16 bytes

32 bytes

64 bytes

0

1

0

1

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Table 6.10 Wrap Function

Wrap around boundary

P2

0

Whole array regardless of P1 and P0 value

Burst Length set by P1 and P0

1

Table 6.11 Read Dummy Cycles vs Max Frequency

For IS25LP256D (3.0V) ^{(6, 7)}

Fast Read

Quad

Output

Fast Read

Dual IO

BBh/BCh

Fast Read

Quad IO

EBh/ECh

Fast Read⁽⁵⁾

0Bh/0Ch

Dual

Output

3Bh/3Ch

FRDTR

0Dh/0Eh

FRDDTR

BDh/BEh

FRQDTR

EDh/EEh

Dummy

P[6:3]

Cycles^(2,3)

6Bh/6Ch

SPI

QPI

SPI

SPI, QPI

81MHz

23MHz

34MHz

46MHz

58MHz

69MHz

81MHz

93MHz

104MHz

122MHz

127MHz

139MHz

151MHz

162MHz

166MHz

SPI/QPI

SPI⁴

SPI, QPI

69MHz

11MHz

23MHz

34MHz

46MHz

58MHz

69MHz

80MHz

0

1

Default¹

166MHz

98MHz

81MHz

23MHz

34MHz

46MHz

58MHz

69MHz

81MHz

93MHz

104MHz

122MHz

127MHz

139MHz

151MHz

162MHz

166MHz

75MHz

104MHz

52MHz

145MHz

63MHz

80/69MHz

50/11MHz

63/23MHz

75/34MHz

80/46MHz

80/58MHz

80/69MHz

80/80MHz

60MHz

29MHz

40MHz

52MHz

60MHz

75MHz

80MHz

1

2

110MHz

122MHz

133MHz

145MHz

156MHz

166MHz

84MHz

80MHz

75MHz

3

98MHz

87MHz

4

133MHz

140MHz

150MHz

166MHz

104MHz

122MHz

133MHz

145MHz

156MHz

166MHz

98MHz

5

110MHz

122MHz

133MHz

145MHz

156MHz

166MHz

6

7

8

9

10

11

12

13

14

15

10

11

12

13

14

15

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For IS25WP256D (1.8V) ⁽⁸⁾

Fast Read

Quad

Output

Fast Read

Dual Output

3Bh/3Ch

Fast Read

Dual IO

BBh/BCh

Fast Read

Quad IO

EBh/ECh

Fast Read⁽⁵⁾

0Bh/0Ch

FRDTR

FRDDTR FRQDTR

Dummy

P[6:3]

0Dh/0Eh BDh/BEh EDh/EEh

Cycles^{(2, 3)}

6Bh/6Ch

SPI

QPI

SPI

SPI/QPI

SPI⁴

SPI

0

1

Default¹

133MHz

98MHz

81MHz

23MHz

34MHz

46MHz

58MHz

69MHz

81MHz

93MHz

133MHz

75MHz

104MHz

52MHz

133MHz

63MHz

81MHz

23MHz

34MHz

46MHz

58MHz

69MHz

81MHz

93MHz

104MHz

122MHz

127MHz

133MHz

80/69MHz

50/11MHz

63/23MHz

75/34MHz

80/46MHz

80/58MHz

80/69MHz

80/80MHz

60MHz

29MHz

40MHz

52MHz

60MHz

75MHz

80MHz

69MHz

11MHz

23MHz

34MHz

46MHz

58MHz

69MHz

80MHz

1

2

110MHz

122MHz

133MHz

84MHz

80MHz

75MHz

3

98MHz

87MHz

4

133MHz

104MHz

122MHz

133MHz

98MHz

5

110MHz

122MHz

133MHz

6

7

8

133MHz 104MHz

133MHz 122MHz

133MHz 127MHz

133MHz 133MHz

9

10

11

12

13

14

15

10

11

12

13

14

15

Notes:

1. Default dummy cycles are as follows.

Command

QPI mode

Dummy Cycles

Operation

Comment

SPI mode

0Bh/0Ch

3Bh/3Ch

6Bh/6Ch

BBh/BCh

EBh/ECh

0Dh/0Eh

BDh/BEh

EDh/EEh

SPI mode

QPI mode

Fast Read

0Bh/0Ch

8

4

6

8

4

6

-

Fast Read Dual Output

Fast Read Quad Output

Fast Read Dual IO

-

Fast Read Quad IO

Fast Read DTR

EBh/ECh⁽⁹⁾

0Dh/0Eh

-

6

-

Fast Read Dual IO DTR

Fast Read Quad IO DTR

EDh/EEh⁽⁹⁾

6

2. Enough number of dummy cycles must be applied to execute properly the AX read operation.

3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bits cycles are same, then X

must be Hi-Z.

4. QPI mode is not available for FRDDTR command.

5. RDUID, RDSFDP, IRRD instructions are also applied.

6. Max frequency is 166MHz at Vcc=2.7V~3.6V, Mode 0

7. Max frequency is 133MHz at Vcc=2.7V~3.6V, Mode 3 and 133MHz at Vcc=2.3V~3.6V at Mode 0

8. Max frequency is 104MHz with 3-byte address (24-bit address) fast read operation.

9. EBh/ECh command and EDh/EEh command are not supported in QPI mode for 1.8V device.

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6.3.2 EXTENDED READ REGISTER

Table 6.12 and Table 6.13 define all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (EB7,

EB6, EB5) bits provide a method to set and control driver strength. The four bits (EB3, EB2, EB1, EB0) are read-

only bits and may be checked to know what the WIP status is or whether there is an error during an Erase, Program,

or Write/Set Register operation. These bits are not affected by SERPNV or SERPV commands. EB4 bit remains

reserved for future use.

The SET EXTENDED READ PARAMETERS Operations (SERPNV: 85h, SERPV: 83h) are used to set all the

Extended Read Register bits, and can thereby define the output driver strength used during READ modes. SRPNV

is used to set the non-volatile register and SRPV is used to set the volatile register.

Table 6.12 Extended Read Register Bit Table

EB7

ODS2

1

EB6

ODS1

1

EB5

ODS0

1

EB4

Reserved

1

EB3

Reserved

-

EB2

P_ERR

0

EB1

PROT_E

0

EB0

WIP

0

Default

Table 6.13 Extended Read Register Bit Definition

Read-

/Write

Bit

Name

Definition

Type

Write In Progress Bit:

EB0

WIP

Has exactly same function as the bit0 (WIP) of Status Register

“0”: Ready, “1”: Busy

Protection Error Bit:

"0" indicates no error

"1" indicates protection error in an Erase or a Program operation

R

Volatile

EB1

EB2

PROT_E

P_ERR

Volatile

Program Error Bit:

"0" indicates no error

"1" indicates an Program operation failure or protection error

EB3

EB4

Reserved

R

Reserved

Non-Volatile

and Volatile

Non-Volatile

and Volatile

Non-Volatile

and Volatile

EB5

EB6

EB7

ODS0

ODS1

ODS2

R/W

Output Driver Strength:

Output Drive Strength can be selected according to Table 6.14

Table 6.14 Driver Strength Table

ODS2

ODS1

ODS0

Description

Reserved

12.50%

25%

Remark

0

1

0

1

0

1

0

1

0

1

0

1

0

1

37.50%

Reserved

75%

100%

50%

Default

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WIP bit: The definition of the WIP bit is exactly same as the one of Status Register.

PROT_E bit: The Protection Error bit indicates whether an Erase or Program operation has attempted to modify a

protected array sector or block, or to access a locked Information Row region. When the bit is set to “1” it indicates

that there was an error or errors in previous Erase or Program operations. See Table 6.15 for details.

P_ERR bit: The Program Error bit indicates whether a Program operation has succeeded or failed, or whether a

Program operation has attempted to program a protected array sector/block or a locked Information Row region.

When the bit is set to “1” it indicates that there was an error or errors in previous Program or Write/Set Non-Volatile

Register operations. See Table 6.15 for details.

Table 6.15 Instructions to set PROT_E bit and P_ERR bit

Instructions

Description

The commands will set the P_ERR if there is a failure in the operation. Attempting to program

within the protected array sector/block or within an erase suspended sector/block will result in

a programming error with P_ERR and PROT_E set to “1”.

PP/4PP/PPQ/4PPQ/PGPPB/

4PGPPB/PGPWD

The command will set the P_ERR if there is a failure in the operation. In attempting to program

IRP

within a locked Information Row region, the operation will fail with P_ERR and PROT_E set to

1.

The command will set the P_ERR if there is a failure in the operation. Attempting to program

ASPR[2:1] after the Protection Mode is selected or attempting to program ASPR[2:1] = 00b

will result in a programming error with P_ERR and PROT_E set to “1”.

PGASP

UNPWD

If the UNPWD command supplied password does not match the hidden internal password, the

UNPWD operation fails in the same manner as a programming operation on a protected

sector/block and sets the P_ERR and PROT_E to “1”.

The update process for the non-volatile register bits involves an erase and a program operation

on the non-volatile register bits. If either the erase or program portion of the update fails, the

related error bit (P_ERR) will be set to “1”.

Only for WRSR command, when Status Register is write-protected by SRWD bit and WP# pin,

attempting to write the register will set PROT_E to “1”.

WRSR/WRABR/SRPNV/

SERPNV/WRBRNV

WRFR

The commands will set the P_ERR if there is a failure in the operation.

PROT_E will be set to “1” when the user attempts to erase a protected main memory

sector/block or a locked Information Row region. Chip Erase (CER) command will set PROT_E

if any blocks are protected by Block Protection bits (BP3~BP0). But Chip Erase (CER)

SER/4SER/BER32K/

4BER32K/BER64K/

4BER64K/CER/IRER/ERPPB command will not set PROT_E if sectors/blocks are protected by ASP (DYB bits or PPB bits)

only.

Notes:

1. OTP bits in the Function Register and TBPARM (OTP bit) in the ASP Register may only be programmed to “1”.

Writing of the bits back to “0” is ignored and no error is set.

2. Read only bits and partially protected bits by FREEZE bit in registers are never modified by a command so that the

corresponding bits in the Write/Set Register command data byte are ignored without setting any error indication.

3. Once the PROT_E and P_ERR error bits are set to “1”, they remains set to “1” until they are cleared to “0” with a

Clear Extended Read Register (CLERP) command. This means that those error bits must be cleared through the

CLERP command. Alternatively, Hardware Reset, or Software Reset may be used to clear the bits.

4. Any further command will be executed even though the error bits are set to “1”.

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6.4 AUTOBOOT REGISTER

AutoBoot Register Bit (32 bits) definitions are described in Table 6.16.

Table 6.16 AutoBoot Register Parameter Bit Table

Default

Bits

Symbols

Function

Type

Description

Value

AutoBoot Start

Address

Non-

Volatile

32 byte boundary address for the start of boot code

access

AB[31:5]

ABSA

0000000h

Number of initial delay cycles between CE# going

low and the first bit of boot code being transferred,

and it is the same as dummy cycles of FRD (QE=0)

or FRQIO (QE=1).

Example: The number of initial delay cycles is 8

(QE=0) or 6 (QE=1) when AB[4:1]=0h (Default

setting).

AutoBoot Start

Delay

Non-

Volatile

AB[4:1]

AB0

ABSD

ABE

0h

0

AutoBoot

Enable

Non-

Volatile

1 = AutoBoot is enabled

0 = AutoBoot is not enabled

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6.5 BANK ADDRESS REGISTER

Related Commands: Read Volatile Bank Address Register (RDBR 16h/C8h), Write Volatile Bank Address Register

(WRBRV 17h/C5h), Write Non-Volatile Bank Address Register (WRBRNV 18h), Enter 4-byte Address Mode (EN4B

B7h), and Exit 4-byte Address Mode (EX4B 29h).

Bank Address Register Bit (8 bits) definitions are described in Table 6.17 and Table 6.18.

Table 6.17 Bank Address Register Bit Table

BA7

EXTADD

0

BA6

Reserved

0

BA5

Reserved

0

BA4

Reserved

0

BA3

Reserved

0

BA2

Reserved

0

BA1

Reserved

0

BA0

BA24

0

Default

Table 6.18 Bank Address Register Bit Definition

Read-

/Write

Bit

Name

Definition

Type

Enables 128Mb segment selection in 3-byte addressing

"0" indicates lower 128Mb segment is selected.

"1" indicates upper 128Mb segment is selected.

Non-Volatile

and Volatile

BA0

BA24

R/W

BA1

BA2

BA3

BA4

BA5

BA6

Reserved

R

Reserved

3-byte or 4-byte addressing selection Bit:

"0" indicates 3-byte addressing.

"1" indicates 4-byte addressing.

Non-Volatile

and Volatile

BA7

EXTADD

R/W

BA24: The Bank Address Register supplies additional high order bits of the main flash array byte boundary address

for legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits

of address (above A23) for all 3-byte address commands when EXTADD=0. The Bank Address is not used when

EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address.

EXTADD: Extended Address (EXTADD) controls the address field size for legacy SPI commands. When shipped

from factory, it is cleared to “0” for 3 bytes (24 bits) of address. When set to “1”, the legacy commands will require

4 bytes (32 bits) for the address field.

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6.6 ADVANCED SECTOR/BLOCK PROTECTION (ASP) RELATED REGISTER

6.6.1 ADVANCED SECTOR/BLOCK PROTECTION REGISTER (ASPR)

Related Commands: Read ASP (RDASP 2Bh) and Program ASP (PGASP 2Fh).

Advanced Sector/Block Protection (ASP) Register Bit (16 bits) definitions are described in Tables 6.19 and 6.20.

Table 6.19 Advanced Sector/Block Protection Register (ASPR) Bit Table

15

TBPARM

1

7 to 14

6

5

4

3

2

1

0

Reserve

d

Reserve

d

Reserve

d

Reserve

d

Reserve

d

Reserve

d

PWDMLB PSTMLB

Default

1

Table 6.20 Advanced Sector/Block Protection Register (ASPR) Bit Definition

Read-

/Write

Bit

Name

Definition

Type

0

Reserved

R

Reserved

Persistent Protection Mode Lock Bit

1

PSTMLB

“0” = Persistent Protection Mode permanently enabled.

“1” = Persistent Protection Mode not permanently enabled.

Password Protection Mode Lock Bit

R/W

OTP

2

PWDMLB

Reserved

TBPARM

“0” = Password Protection Mode permanently enabled.

“1” = Password Protection Mode not permanently enabled.

R/W

R

OTP

Reserved

OTP

3:14

15

Reserved

Configures Parameter Sectors location

“0” = 4KB physical sectors at top, (high address)

“1” = 4KB physical sectors at bottom (Low address)

R/W

The Advanced Sector/Block Protection Register (ASPR) is used to permanently configure the behavior of Advanced

Sector/Block Protection (ASP) features and parameter sectors location.

PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) bits: When shipped from the factory, all devices default ASP to the

Persistent Protection Mode, with all sectors unprotected, when power is applied. The device programmer or host

system must then choose which sector/block protection method to use. Programming either of the Protection Mode

Lock Bits locks the part permanently in the selected mode:

 ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.

 ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.

 ASPR[2:1] = 01 = Password Protection Mode permanently selected.

 ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure

and the program operation will abort. It will result in a programming error with P_ERR set to 1.

As a result, PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to zero.

ASPR programming rules:

 If the Password Protection Mode is chosen, the password must be programmed prior to setting the

corresponding bit.

 Once the Protection Mode is selected, the ASPR[2:1] bits are permanently protected from programming and no

further change to the ASPR[2:1] is allowed. Attempting to program ASPR[2:1] after selected will result in a

programming error with P_ERR set to 1. The programming time of the ASPR is the same as the typical page

programming time. The system can determine the status of the ASPR programming operation by reading the

WIP bit in the Status Register or Extended Read Register.

 TBPARM bit can be programmed even after ASPR[2:1] bits are programmed while the FREEZE bit in the PPB

Lock Register is “0”.

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TBPARM bit: TBPARM defines the logical location of the parameter block. The parameter block consists of thirty-

two 4KB sectors, which replace two 64KB blocks. When TBPARM is set to a “0” the parameter block is in the top

of the memory array address space. When TBPARM is set to a “1” the parameter block is at the Bottom of the

array. TBPARM is OTP and set to a “1” when shipped from factory. If TBPARM is programmed to “0”, an attempt

to change it back to “1” will fail and ignore the Program.

The desired state of TBPARM must be selected during the initial configuration of the device during system

manufacture; before the first program or erase operation on the main flash array. TBPARM must not be

programmed after programming or erasing is done in the main flash array.

TBS can be programmed independent of TBPARM. Therefore, the user can elect to store parameter information

from the bottom of the array and protect boot code starting at the top of the array, and vice versa. Or the user can

select to store and protect the parameter information starting from the top or bottom together.

6.6.2 PASSWORD REGISTER

Related Commands: Read Password (RDPWD E7h), Program Password (PGPWD E8h), and Unlock Password

(UNPWD, E9h).

Table 6.21 Password Register Bit Definition

Read-

Bit

Name

Definition

Default

Type

/Write

64 bit hidden password:

The password is no longer readable after the password

protection mode is selected by programming ASPR bit 2

to zero.

FFFFFFFF-

FFFFFFFFh

0:63

PSWD

R/W

OTP

6.6.3 PPB LOCK REGISTER

Related Commands: Read PPB Lock Bit (RDPLB A7h), Write PPB Lock Bit (WRPLB A6h), and Set FREEZE Bit

(SFRZ 91h).

Table 6.22 PPB Lock Register Bit Definition

Read-

Bit

Name

Definition

Default

Type

/Write

PPB Lock bit: Protect PPB Array

“0” = PPB array protected until next power cycle

or Hardware Reset

Persistent: 1

Password: 0

0

PPBLK

R/W

Volatile

“1” = PPB array may be programmed or erased.

1:6

Reserved Reserved

Reserved

0

R

Reserved

Lock current state of BP3-0 bits in Status Register, TBS in

Function Register and TBPARM in ASPR, and

Information Row (IR) regions.

“1” = Locked

7

FREEZE

R/W

Volatile

“0” = Un-locked

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PPBLK bit: The PPB Lock bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs, when

set to 1, it allows the PPBs to be changed. The WRPLB command is used to clear the PPB Lock bit to 0. The PPB

Lock bit must be cleared to 0 only after all the PPBs are configured to the desired settings.

In Persistent Protection mode, the PPB Lock bit is set to 1 during POR or Hardware Reset. When cleared to 0, no

software command sequence can set the PPB Lock bit to 1, only another Hardware Reset or power-up can set the

PPB Lock bit.

In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or Hardware Reset. The PPB Lock

bit can only be set to 1 by the Unlock Password command.

FREEZE bit: FREEZE bit, when set to “1”, locks the current state of BP3-0 in Status Register, TBS in the Function

Register, TBPARM in the Advanced Sector/Block Protection Register, and the Information Row. This prevents

writing, programming, or erasing these areas. As long as FREEZE remains cleared to logic “0”, BP3-0 in Status

Register, TBS in the Function Register, and TBPARM in the Advanced Sector/Block Protection Register are

writable and the Information Row is programmable. Once FREEZE has been written to a logic “1” it can only be

cleared to a logic “0” by a power-on cycle or a Hardware Reset. Software Reset will not affect the state of FREEZE.

The FREEZE is volatile and the default state of FREEZE after power-on is “0”. The FREEZE can be set to “1” by a

SFRZ command.

6.6.4 PPB REGISTER

Related Commands: Read PPB (RDPPB FCh or 4RDPPB E2h)), Program PPB (PGPPB FDh or 4PGPPB E3h),

and Erase PPB (ERPPB E4h).

Table 6.23 PPB Register Bit Definition

Read-

/Write

Bit

Name

Definition

Default

Type

Read or Program per sector/block PPB:

00h = PPB for the sector/block addressed by the RDPPB or

PGPPB command is programmed to “0”, protecting

that sector/block from program or erase operations.

FFh = PPB for the sector/block addressed by the RDPPB

or

0:7

PPB

FFh

R/W

Non-Volatile

PGPPB command is erased to “1”, not protecting

that sector/block from program or erase operations.

6.6.5 DYB REGISTER

Related Commands: Read DYB (RDDYB FAh or 4RDDYB E0h) and Write DYB (WRDYB FBh or 4WRDYB E1h).

Table 6.24 DYB Register Bit Definition

Read-

/Write

Bit

Name

Definition

Default

Type

Read or Write per sector/block DYB:

00h = DYB for the sector/block addressed by the RDDYB

or

WRDYB command is cleared to “0”, protecting that

sector/block from program or erase operations.

FFh = DYB for the sector/block addressed by the RDDYB

or

0:7

DYB

FFh

R/W

Volatile

WRDYB command is set to “1”, not protecting that

sector/block from program or erase operations.

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7. PROTECTION MODE

The device supports hardware and software write-protection mechanisms.

7.1 HARDWARE WRITE PROTECTION

The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD, and

QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.

Write inhibit voltage (V_WI) is specified in the section 9.7 POWER-UP AND POWER-DOWN. All write sequence will

be ignored when Vcc drops to V_WI.

Table 7.1 Hardware Write Protection on Status Register

SRWD

WP#

Low

High

Status Register

Writable

0

1

0

1

Protected

Writable

Note: Before the execution of any program, erase or Write Status/Function Register instruction, the Write Enable Latch

(WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the

program, erase or write register instruction will be ignored.

7.2 SOFTWARE WRITE PROTECTION

The device also provides two kinds of software write protection feature. One is Block Protection by Block Protection

bits (BP3, BP2, BP1, BP0) and another is Advanced Sector/Block Protection (ASP). When Block Protection is

enabled (i.e., any BP3-0 are set to “1”), Advanced Sector/Block Protection (ASP) can still be used to protect

sectors/blocks not protected by the Block Protection scheme. In the case that both ASP and Block Protection are

used on the same sector/block the logical OR of ASP and Block Protection related to the sector/block is used.

Warning: ASP and Block Protection should not be used concurrently. Use one or the other, but not both.

7.2.1 BLOCK PROTECTION BITS

The device provides a software write protection feature. The Block Protection bits (BP3, BP2, BP1, BP0) allow part

or the whole memory area to be write-protected. For details, see 6.1 Status Register.

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7.2.2 ADVANCED SECTOR/BLOCK PROTECTION (ASP)

There are two ways to implement software Advanced Sector/Block Protection on this device: Password Protection

method or Persistent Protection methods. Through these two protection methods, user can disable or enable the

programming or erasing operation to any or all blocks including 32 top 4K sectors or 32 bottom 4K sectors. The

Figure 7.1 shows an overview of these methods.

Every main flash array block/top sector/bottom sector has a non-volatile (PPB) and a volatile (DYB) protection bit

associated with it. When either bit is 0, the sector is protected from program and erase operations.

The PPB bits are protected from program and erase when the PPB Lock bit is “0”. The PPB bits are erased so that

all main flash array sectors are unprotected when shipped from factory.

There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection.

The Persistent Protection Mode sets the PPB Lock bit to “1” during power up or Hardware Reset so that the PPB

bits are unprotected. There is a WRPLB command to clear the PPB Lock bit to “0” to protect the PPB bits. There

is no command in the Persistent Protection method to set the PPB Lock bit therefore the PPB Lock bit will remain

at “0” until the next power up or Hardware Reset. The Persistent Protection method allows boot code the option of

changing sector protection by programming or erasing the PPB, then protecting the PPB from further change for

the remainder of normal system operation by clearing the PPB Lock bit. This is sometimes called Boot-code

controlled sector protection.

The Password Protection Mode requires use of a password to control PPB protection. In the Password Protection

Mode, the PPB Lock bit is cleared to “0” during power up or Hardware Reset to protect the PPB bits. A 64-bit

password may be permanently programmed and hidden for the Password Protection Mode. The UNPWD command

can be used to provide a password for comparison with the hidden password. If the password matches the PPB

Lock bit is set to “1” to unprotect the PPB. The WRPLB command can be used to clear the PPB Lock bit to “0”.

After clearing the PPB Lock bit to “0”, the UNPWD command can be used again to unprotect the PPB.

The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so

as to permanently select the method used.

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Figure 7.1 Advanced Sector/Block Protection

ASP Register Bits (OTP)

Password Protection

Mode (ASPR[2]=0

Persistent Protection

Mode (ASPR[1]=0

64-bit Password

(OTP)

PPB Lock Bit

(Volatile)

0 = Locked 1 = Unocked

DYB

Memory Array

PPB

1. The bit defaults to “1” (Persistent Protection mode)

or “0” (Password Protection mode) upon reset.

2. “0” locks all PPB bits to their current state.

3. Password Protection mode requires a password to

set PPB Lock bit to “1” to enable program or

erase of PPB bits.

4. Persistent Protection mode only allows PPB Lock

bit to be cleared to “0” to prevent program or erase

PPB bits. Power off or hardware reset is required to

set PPB Lock bit to “1”.

DYB 0

DYB 1

DYB 2

DYB 3

Sector/Block 0

Sector/Block 1

Sector/Block 2

Sector/Block 3

PPB 0

PPB 1

PPB 2

PPB 3

DYB N-3

DYB N-2

DYB N-1

DYB N

Sector/Block N-3

Sector/Block N-2

Sector/Block N-1

Sector/Block N

PPB N-3

PPB N-2

PPB N-1

PPB N

1. 0 = Sector/Block Protected

1 = Sector/Block Unprotected

2. PPB bits are programmed individually,

but erased collectively

1 = Sector/Block Unprotected (default)

2. DYBs are volatile and defaults to “1”

after power-up

Note:

1. 256M: N = 541 = 32 (32 Top 4K sectors or 32 Bottom 4K sectors) + 510 (510 64K blocks) - 1

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Table 7.2 PPB/DYB and Sector/Block mapping (TBPARM = 1)

Sector

Size

(Kbyte)

Memory

Density

PPB

Group

DYB

Group

Block No.

(64Kbyte)

Sector No.

Address Range

PPB 0

DYB 0

Sector 0

4

:

000000h - 000FFFh

:

Block 0

Block 1

:

PPB 15

DYB 15

Sector 15

4

:

00F000h - 00FFFFh

PPB 16

DYB 16

Sector 16

010000h - 010FFFh

:

PPB 31

DYB 31

Sector 31

4

:

01F000h - 01FFFFh

Sector 32

020000h - 020FFFh

:

PPB 32

:

DYB 32

:

Block 2

:

Sector 47

4

02F000h - 02FFFFh

:

Sector 4064

4

:

FE0000h – FE0FFFh

:

PPB 284

DYB 284

Block 254

:

Sector 4079

4

:

FEF000h – FEFFFFh

Sector 4080

FF0000h – FF0FFFh

:

PPB 285

:

DYB 285

:

Block 255

:

Sector 4095

4

FFF000h – FFFFFFh

:

Sector 8160

4

:

1FE0000h – 1FE0FFFh

:

PPB 540

DYB 540

Block 510

:

Sector 8175

4

:

1FEF000h – 1FEFFFFh

Sector 8176

1FF0000h – 1FF0FFFh

:

PPB 541

DYB 541

Block 511

:

Sector 8191

4

1FFF000h – 1FFFFFFh

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Table 7.3 PPB/DYB and Sector/Block mapping (TBPARM = 0)

Sector

Size

(Kbyte)

Memory

Density

PPB

Group

DYB

Group

Block No.

(64Kbyte)

Sector No.

Address Range

Sector 0

4

:

000000h - 000FFFh

:

PPB 0

PPB 1

DYB 0

DYB 1

Block 0

Block 1

:

Sector 15

4

:

00F000h - 00FFFFh

Sector 16

010000h - 010FFFh

:

Sector 31

4

:

01F000h - 01FFFFh

Sector 32

020000h - 020FFFh

:

PPB 2

:

DYB 2

:

Block 2

:

Sector 47

4

02F000h - 02FFFFh

:

Sector 4064

4

:

FE0000h – FE0FFFh

:

256Mb

PPB 254

DYB 254

Block 254

:

Sector 4079

4

:

FEF000h – FEFFFFh

Sector 4080

FF0000h – FF0FFFh

:

PPB 255

:

DYB 255

:

Block 255

:

Sector 4095

4

FFF000h – FFFFFFh

:

PPB 510

DYB 510

Sector 8160

4

:

1FE0000h – 1FE0FFFh

:

Block 510

:

PPB 525

DYB 525

Sector 8175

4

:

1FEF000h – 1FEFFFFh

PPB 525

DYB 526

Sector 8176

1FF0000h – 1FF0FFFh

:

Block 511

:

PPB 541

DYB 541

Sector 8191

4

1FFF000h – 1FFFFFFh

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Persistent Protection Bits (PPBs)

The Persistent Protection Bits (PPBs) are unique for each sector/block and non-volatile (refer to Figure 7.1, Table

7.2, and Table 7.3). It is programmed individually but must be erased as a group, similar to the way individual words

may be programmed in the main array but an entire sector/block must be erased at the same time. The PPBs have

the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the

device, and therefore do not require system monitoring. Programming a PPB bit requires the typical page

programming time. Erasing all the PPBs requires typical sector erase time. During PPB bit programming and PPB

bit erasing, status is available by reading the Status Register or Extended Read Register. Reading of a PPB bit

requires the initial access time of the device.

Notes:

1. Each PPB is individually programmed to “0” and all are erased to “1” in parallel.

2. The PPB Lock bit must be cleared first before changing the status of a PPB.

3. While programming PPB, array data cannot be read from any sectors/blocks.

4. When reading the PPB of the desired sector/block the address should be location zero within the sector/block. The high

order address bits not used must be zero.

5. There are no means for individually erasing a specific PPB and no specific sector/block address is required for this operation.

6. The state of the PPB for a given sector/block can be verified by using a PPB Read command.

7. When the parts are first shipped, the PPBs are cleared (erased to “1”).

Dynamic Protection Bits (DYBs)

Dynamic Protection Bits (DYBs) are volatile and unique for each sector/block and can be individually modified.

DYBs only control the protection for unprotected sectors/blocks that have their PPBs cleared (erased to “1”). By

issuing the Write DYB command, the DYBs are cleared to “0” or set to “1”, thus placing each sector/block in the

protected or unprotected state respectively. This feature allows software to easily protect sectors/blocks against

inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. The DYBs

can be set or cleared as often as needed as they are volatile bits.

Persistent Protection Bit (PPB) Lock Bit

The PPB Lock bit is a volatile bit for protecting all PPB bits. When cleared to “0”, it locks all PPBs and when set to

“1”, it allows the PPBs to be changed. . If the PPB Lock bit is “0”, the PPB Program or Erase command does not

execute and fails without programming or erasing the PPB.

In Persistent Protection mode, the PPB Lock bit is set to “1” during power up or Hardware Reset. When cleared to

“0”, no software command sequence can set the PPB Lock bit to “1”, only another Hardware Reset or power-up

can set the PPB Lock bit.

In the Password Protection mode, the PPB Lock bit is cleared to “0” during power up or a Hardware Reset during

power up or a Hardware Reset during power up or a Hardware Reset. The PPB Lock bit can only be set to “1” by

the Password Unlock command.

The PPB Lock bit must be cleared to “0” only after all PPBs are configured to the desired settings.

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Sector/Block Protection States Summary

Each sector in specific blocks and each of all other blocks except for the specific blocks can be in one of the

following protection states:

 Unlocked – The sector/block is unprotected and protection can be changed by a simple command. The

protection state defaults to unprotected after a power cycle, software reset, or hardware reset.

 Dynamically Locked – A sector/block is protected and protection can be changed by a simple command. The

protection state is not saved across a power cycle.

 Persistently Locked – A sector/block is protected and protection can only be changed if the PPB Lock bit is set

to “1”. The protection state is non-volatile and saved across a power cycle or reset. Changing the protection

state requires programming and or erase of the PPB bits.

Table 7.4 contains all possible combinations of the DYB, PPB, and PPB Lock bit relating to the status of the

sector/block. In summary, if the PPB Lock bit is locked (cleared to “0”), no changes to the PPBs are allowed. The

PPB Lock bit can only be unlocked (set to “1”) through a Hardware Reset or power cycle.

Table 7.4 Sector/Block Protection States

Protection Bit values

Assigned Sector/Block State

PPB

DYB

1

Unprotected

Protected

“0” = Locked or Protected

“1” = Unlocked or Unprotected

1

0

1

0

1

Changeable

NOT changeable

Changeable

PPB Lock Bit

0

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Persistent Protection Mode

The Persistent Protection Mode sets the PPB Lock bit to “1” during power up or Hardware Reset so that the PPB

bits are unprotected by a device Hardware Reset. Software Reset does not affect the PPB Lock bit. The WRPLB

command can clear the PPB Lock bit to “0” to protect the PPB. There is no command to set the PPB Lock bit

therefore the PPB Lock bit will remain at “0” until the next power up or Hardware Reset.

Password Protection Mode

The Password Protection Mode allows an even higher level of security than the Persistent Protection Mode by

requiring a 64-bit password for unlocking the device PPB Lock bit. In addition to this password requirement, after

power up or Hardware Reset, the PPB Lock bit is cleared to “0” to maintain the password mode of operation.

Successful execution of the Unlock Password command by entering the entire password sets the PPB Lock bit to

“1”, allowing for sector/block PPBs modifications.

Notes:

1. The password is all “1”s when shipped from Factory. It is located in its own memory space and is accessible through the use

of the Program Password and Read Password commands.

2. Once the Password is programmed and verified, the Password Protection Mode Lock Bit (ASPR[2]=0) in ASP Register must

be programmed in order to prevent reading or modifying the password. After the Password Protection Mode Lock Bit is

programmed, all further Program and Read commands to the password region are disabled and these commands are

ignored so that there is no means to verify what the password is. Password verification is only allowed before selecting the

Password Protection Mode.

3. The Program Password Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a

“0” results in the cell left as a “0” with no programming error.

4. All 64-bit password combinations are valid as a password.

5. The Protection Mode Lock Bits in ASP Register are not erasable because they are OTP.

6. The exact password must be entered in order for the unlocking function to occur. If the password provided by Unlock

Password command does not match the hidden internal password, the unlock operation fails in the same manner as a

programming operation on a protected sector/block. The P_ERR and PROT_E are set to 1 and the PPB Lock bit remains

cleared to 0. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the lack of a

valid password.

7. The Unlock Password command cannot be accepted any faster than once every 100μs ± 20μs. This makes it take an

unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly

match a password. The Read Status Register command or the Read Extended Read Register may be used to read the WIP

bit to determine when the device has completed the Unlock Password command or is ready to accept a new password

command. When a valid password is provided the Unlock Password command does not insert the 100μs delay before

returning the WIP bit to zero.

8. If the password is lost after selecting the Password Protection Mode, there is no way to set the PPB Lock bit.

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8. DEVICE OPERATION

8.1 COMMAND OVERVIEW

The device utilizes an 8-bit instruction register. Refer to Table 8.4. Instruction Set for details on instructions and

instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on

Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising

edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR mode after Chip Enable

(CE#) is driven low (V_IL). Every instruction sequence starts with a one-byte instruction code and is followed by

address bytes and/or dummy cycles (configurable) and/or data bytes, depending on the type of instruction. CE#

must be driven high (V_IH) after the last bit of the instruction sequence has been shifted in to end the operation.

Commands are structured as follows:

 Each command begins with a byte (eight bits) instruction.

 The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.

 The SPI interface with Multiple IO provides the option for each transfer of address and data information to be

done one, two, or four bits in parallel. This enables a tradeoff between the number of signal connections (IO bus

width) and the speed of information transfer. If the host system can support a two or four bit wide IO bus the

memory performance can be increased by using the instructions that provide parallel two bit (dual) or parallel

four bit (quad) transfers.

 The width of all transfers following the instruction are determined by the instruction sent.

 All single bit or parallel bit groups are transferred in most to least significant bit order.

 Some instructions send Mode Bits following the address to indicate that the next command will be of the same

type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction

byte, only a new address and mode bits. This reduces the time needed to send each command when the same

command type is repeated in a sequence of commands.

 The address or Mode Bits may be followed by Dummy Cycles before read data is returned to the host.

 Dummy Cycles may be zero to several SCK cycles. In fact, Mode Bits will be counted as a part of Dummy

Cycles.

 All instruction, address, Mode, and data information is transferred in byte granularity. Addresses are shifted into

the device with the Most Significant Byte first. All data is transferred with the lowest address byte sent first.

Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.

 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands

are accepted during an embedded operation. These are discussed in the individual command descriptions.

While a program, erase, or write operation is in progress, it is recommended to check that the Write In Progress

(WIP) bit is “0” before issuing most commands to the device, to ensure the new command can be accepted.

 Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

 Following are some general signal relationship descriptions to keep in mind.

– The host always controls the Chip Enable (CE#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit

wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory

alternately drive the IO0-IO3 signals during Dual and Quad transfers.

– All commands begin with the host selecting the memory by driving CE# low before the first rising edge of

SCK. CE# is kept low throughout a command and when CE# is returned high the command ends.

Generally, CE# remains low for 8-bit transfer multiples to transfer byte granularity information. All commands

will not be accepted if CE# is returned high not at an 8-bit boundary.

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8.2 COMMAND SET SUMMARY

Extended Addressing

To accommodate addressing above 128Mb (24-bit), there are three options:

1. New instructions with 4-byte (32-bit) address. See Table 8.2.

2. 4-byte addressing with the 3-byte address instructions:

For backward compatibility to the 3-byte address instructions, the standard instructions can be used in

conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]) or Enter 4-byte Address Mode to switch

from 3 bytes to 4 bytes of address field. When EXTADD bit is set to 1 or Enter 4-byte Address Mode command

is issued only in the case that EXTADD bit = 0, the instructions are changed to require 4-byte (32-bit) for the

address field. See Table 8.3.

3. 3-byte addressing with the 3-byte address instructions:

For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction with

the Bank Address Register. See Table 8.3.

 The Bank Address Register is used to switch between 128Mbit (16Mbyte) banks of memory, the standard 3-

byte address selects an address within the bank selected by the Bank Address Register.

o The host system writes the Bank Address Register to access beyond the first 128Mbit of memory.

o This applies to read, erase, and program commands.

 The Bank Address Register provides the high order (4th) byte of address, which is used to address the

available memory at addresses greater than 128Mbit.

 Bank Address Register bits are volatile.

o On power up, the default is Bank0 (the lowest address 16 Mbytes).

 For Read, the device will continuously transfer out data until the end of the array.

o There is no bank to bank delay.

o The Bank Address Register is not updated.

o The Bank Address Register value is used only for the initial address of an access.

Table 8.1 Bank Address Map

Bank Address Register Bit 0

Bank

Memory Array Address Range

0

1

0

1

00000000h

01000000h

00FFFFFFh

01FFFFFFh

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Table 8.2 New Instruction Set with 4-byte address

Instruction Name

Operation

Code

Address Mode

4NORD

4FRD

4-byte Address Normal Read Mode

4-byte Address Fast Read Mode

4-byte Address Fast Read Dual I/O

4-byte Address Fast Read Dual Output

4-byte Address Fast Read Quad I/O

4-byte Address Fast Read Quad Output

4-byte Address Fast Read DTR Mode

4-byte Address Fast Read Dual I/O DTR

4-byte Address Fast Read Quad I/O DTR

4-byte Address Serial Input Page Program

4-byte Address Quad Input Page Program

4-byte Address Sector Erase

13h

0Ch

BCh

3Ch

ECh

6Ch

0Eh

BEh

EEh

12h

4-byte Address

4FRDIO

4FRDO

4FRQIO

4FRQO

4FRDTR

4FRDDTR

4FRQDTR

4PP

4PPQ

34h/3Eh

21h

4SER

4BER32 (32KB)

4BER64 (64KB)

4SECUNLOCK

4RDDYB

4WRDYB

4RDPPB

4PGPPB

4-byte Address Block Erase 32KB

4-byte Address Block Erase 64KB

4-byte Address Sector Unlock

5Ch

DCh

25h

4-byte Address Read DYB

E0

4-byte Address Write DYB

E1

4-byte Address Read PPB

E2

4-byte Address Program PPB

E3

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Table 8.3 Instruction Set with 3-byte or 4-byte address according to EXTADD Bit setting

Address Mode

EXTADD (BAR[7] = 1

Instruction Name

Operation

Code

EXTADD (BAR[7]) = 0

3-byte Address

NORD

FRD

Normal Read Mode

Fast Read Mode

03h

0Bh

BBh

3Bh

EBh

6Bh

0Dh

BDh

EDh

02h

4-byte Address

FRDIO

Fast Read Dual I/O

Fast Read Dual Output

Fast Read Quad I/O

Fast Read Quad Output

Fast Read DTR Mode

Fast Read Dual I/O DTR

Fast Read Quad I/O DTR

Serial Input Page Program

Quad Input Page Program

Sector Erase

FRDO

FRQIO

FRQO

FRDTR

FRDDTR

FRQDTR

PP

PPQ

32h/38h

D7h/20h

52h

SER

BER32 (32KB)

BER64 (64KB)

SECUNLOCK

RDDYB

WRDYB

RDPPB

PGPPB

Block Erase 32KB

Block Erase 64KB

Sector Unlock

D8h

26h

Read DYB

FA

Write DYB

FB

Read PPB

FC

Program PPB

FD

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Table 8.4 All Instruction Set

Instruction

Name

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Normal Read

Mode

(3-byte Address)

A

<7:0>

NORD

SPI

03h

Data out

<23:16>

<15:8>

Normal Read

Mode

(4-byte Address)

A

<7:0>

NORD

4NORD

FRD

03h

13h

0Bh

0Ch

BBh

BCh

3Bh

3Ch

EBh

ECh

6Bh

6Ch

Data out

<31::24>

<23:16>

<15:8>

4-byte Address

Normal Read

Mode

A

<7:0>

<31::24>

<23:16>

<15:8>

Fast Read

Mode

(3-byte Address)

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

<23:16>

<15:8>

Fast Read

Mode

(4-byte Address)

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

FRD

Data out

<31::24>

<23:16>

<15:8>

4-byte Address

Fast Read

Mode

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

4FRD

<31::24>

<23:16>

<15:8>

Fast Read

Dual I/O

(3-byte Address)

A

<7:0>

Dual

AXh^(1),(2)

Dual

Data out

FRDIO

4FRDIO

FRDO

4FRDO

FRQIO

4FRQIO

FRQO

4FRQO

SPI

<23:16>

Dual

<15:8>

Dual

Fast Read

Dual I/O

(4-byte Address)

A

<7:0>

Dual

A

AXh^(1),(2)

Dual

Data out

<23:16>

Dual

<15:8>

Dual

<31::24>

4-byte Address

Fast Read

Dual I/O

A

<7:0>

Dual

A

AXh^(1),(2)

Dual

Data out

<23:16>

Dual

<15:8>

Dual

<31::24>

Fast Read

Dual Output

(3-byte Address)

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

<23:16>

<15:8>

Fast Read

Dual Output

(4-byte Address)

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

<31::24>

<23:16>

<15:8>

4-byte Address

Fast Read

Dual Output

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

<31::24>

<23:16>

<15:8>

Fast Read

Quad I/O

(3-byte Address)

A

<7:0>

Quad

SPI

QPI

AXh^{(1), (2)}

Quad

Data out

<23:16>

Quad

<15:8>

Quad

Fast Read

Quad I/O

(4-byte Address)

A

<7:0>

Quad

SPI

QPI

AXh^{(1), (2)}

Quad

Data out

<31::24>

Quad

<23:16>

Quad

<15:8>

Quad

4-byte Address

Fast Read

Quad I/O

A

<7:0>

Quad

SPI

QPI

AXh^{(1), (2)}

Quad

Data out

<31::24>

Quad

<23:16>

Quad

<15:8>

Quad

Fast Read

Quad Output

(3-byte Address)

A

<7:0>

Dummy⁽¹⁾

Byte

Quad

Data out

SPI

<23:16>

<15:8>

Fast Read

Quad Output

(4-byte Address)

A

<7:0>

Dummy⁽¹⁾

Byte

Quad

Data out

<31::24>

<23:16>

<15:8>

4-byte Address

Fast Read

Quad Output

A

<7:0>

Dummy⁽¹⁾

Byte

Quad

Data out

<31::24>

<23:16>

<15:8>

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Instruction

Name

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Fast Read

DTR Mode

(3-byte Address)

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

FRDTR

4FRDTR

FRDDTR

4FRDDTR

FRQDTR

4FRQDTR

PP

0Dh

<23:16>

<15:8>

Fast Read

DTR Mode

(4-byte Address)

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

0Dh

0Eh

<31::24>

<23:16>

<15:8>

4-byte Address

Fast Read

DTR Mode

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

<31::24>

<23:16>

<15:8>

Fast Read

Dual I/O DTR

(3-byte Address)

A

<7:0>

Dual

AXh^{(1), (2)}

Dual

Data out

SPI

BDh

<23:16>

Dual

<15:8>

Dual

Fast Read

Dual I/O DTR

(4-byte Address)

A

<7:0>

Dual

A

AXh^{(1), (2)}

Dual

Data out

BDh

<23:16>

Dual

<15:8>

Dual

<31::24>

4-byte Address

Fast Read

Dual I/O DTR

A

<7:0>

Dual

A

AXh^{(1), (2)}

Dual

Data out

BEh

<23:16>

Dual

<15:8>

Dual

<31::24>

Fast Read

Quad I/O DTR

SPI

QPI

A

<7:0>

AXh^{(1), (2)}

Quad

Data out

EDh

<23:16>

<15:8>

(3-byte Address)

Fast Read

Quad I/O DTR

(4-byte Address)

SPI

QPI

A

<7:0>

AXh^{(1), (2)}

Quad

Data out

EDh

<31::24>

<23:16>

<15:8>

4-byte Address

Fast Read

Quad I/O DTR

SPI

QPI

A

<7:0>

AXh^{(1), (2)}

Quad

Data out

EEh

<31::24>

<23:16>

<15:8>

Input Page

Program

(3-byte Address)

SPI

QPI

A

<7:0>

PD

(256byte)

02h

<23:16>

<15:8>

Input Page

Program

(4-byte Address)

SPI

QPI

A

<7:0>

PD

(256byte)

PP

02h

<31::24>

<23:16>

<15:8>

4-byte Address

Input Page

Program

SPI

QPI

A

<7:0>

PD

(256byte)

4PP

12h

<31::24>

<23:16>

<15:8>

Quad Input

Page Program

(3-byte Address)

A

<7:0>

Quad PD

(256byte)

PPQ

SPI

32h/38h

34h/3Eh

<23:16>

<15:8>

Quad Input

Page Program

(4-byte Address)

A

<7:0>

Quad PD

(256byte)

PPQ

<31::24>

<23:16>

<15:8>

4-byte Address

Quad Input

Page Program

A

<7:0>

Quad PD

(256byte)

4PPQ

<31::24>

<23:16>

<15:8>

Sector Erase

(3-byte Address)

SPI

QPI

A

<7:0>

SER

D7h/20h

21h

<23:16>

<15:8>

Sector Erase

(4-byte Address)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

4-byte Address

Sector Erase

SPI

QPI

A

<7:0>

4SER

<31::24>

<23:16>

<15:8>

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Instruction

Name

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Block Erase

32Kbyte

(3-byte Address)

BER32

(32KB)

SPI

QPI

A

<7:0>

52h

<23:16>

<15:8>

Block Erase

32Kbyte

(4-byte Address)

BER32

(32KB)

SPI

QPI

A

<7:0>

52h

5Ch

D8h

DCh

<31::24>

<23:16>

<15:8>

4-byte Address

Block Erase

32Kbyte

4BER32

(32KB)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

Block Erase

64Kbyte

(3-byte Address)

BER64

(64KB)

SPI

QPI

A

<7:0>

<23:16>

<15:8>

Block Erase

64Kbyte

(4-byte Address)

BER64

(64KB)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

4-byte Address

Block Erase

64Kbyte

4BER64

(64KB)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

SPI

QPI

CER

WREN

WRDI

Chip Erase

Write Enable

Write Disable

C7h/60h

06h

SPI

QPI

SPI

QPI

04h

Read Status

Register

SPI

QPI

RDSR

WRSR

RDFR

WRFR

QPIEN

QPIDI

05h

Data out

Data in

Data out

Data in

Write Status

Register

SPI

QPI

01h

Read Function

Register

SPI

QPI

48h

Write Function

Register

SPI

QPI

42h

Enter

QPI mode

SPI

QPI

35h

Exit

QPI mode

F5h

Suspend during

program/erase

SPI

QPI

PERSUS

PERRSM

DP

75h/B0h

7Ah/30h

B9h

Resume

program/erase

SPI

QPI

Deep Power

Down

SPI

QPI

Read ID /

Release

Power Down

RDID,

RDPD

SPI

QPI

ABh

65h

XXh⁽³⁾

Data in

XXh⁽³⁾

ID7-ID0

Set Read

Parameters

(Non-Volatile)

SPI

QPI

SRPNV

SRPV

Set Read

Parameters

(Volatile)

SPI

QPI

C0h/63h

85h

Set Extended

Read Parameters

(Non-Volatile)

SPI

QPI

SERPNV

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Instruction

Name

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Set Extended

Read Parameters

(Volatile)

SPI

QPI

SERPV

RDRP

83h

Data in

Read Read

Parameters

(Volatile)

SPI

QPI

61h

81h

Data out

Read Extended

Read Parameters

(Volatile)

SPI

QPI

RDERP

Clear Extended

Read Register

SPI

QPI

CLERP

82h

9Fh

Read JEDEC

ID Command

SPI

QPI

RDJDID

MF7-MF0

XXh⁽³⁾

ID15-ID8

XXh⁽³⁾

ID7-ID0

00h

01h

MF7-MF0

ID7-ID0

Read

Manufacturer

& Device ID

SPI

QPI

RDMDID

90h

AFh

MF7-MF0

Read JEDEC

ID

RDJDIDQ

QPI

MF7-MF0

ID15-ID8

ID7-ID0

QPI mode

Read

Unique ID

SPI

QPI

A⁽⁴⁾

<23:16>

A⁽⁴⁾

<15:8>

A⁽⁴⁾

<7:0>

Dummy

Byte

RDUID

RDSFDP

NOP

4Bh

5Ah

00h

Data out

A

<7:0>

Dummy

Byte

SFDP Read

SPI

<23:16>

<15:8>

SPI

QPI

No Operation

Software

Reset

Enable

SPI

QPI

RSTEN

RST

66h

99h

64h

SPI

QPI

Software Reset

Erase

Information

Row

SPI

QPI

A

IRER

<23:16>

<15:8>

<7:0>

Program

Information

Row

SPI

QPI

A

<7:0>

PD

(256byte)

IRP

62h

68h

<23:16>

<15:8>

Read

Information

Row

SPI

QPI

A

<7:0>

Dummy

Byte

IRRD

Data out

<23:16>

<15:8>

Sector Unlock

(3-byte Address)

SPI

QPI

A

<7:0>

SECUNLOCK

4SECUNLOCK

SECLOCK

RDABR

26h

25h

24h

14h

15h

<23:16>

<15:8>

Sector Unlock

(4-byte Address)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

4-byte Address

Sector Unlock

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

SPI

QPI

Sector Lock

Read AutoBoot

Register

SPI

QPI

Data out

1

Data out

2

Data out

3

Data out

4

Write AutoBoot

Register

SPI

QPI

WRABR

Data in 1

Data in 2

Data in 3

Data in 4

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IS25LP256D

IS25WP256D

Instruction

Name

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Read Bank

Address Register

(Volatile)

SPI

QPI

RDBR

WRBRV

WRBRNV

16h/C8h

Data out

Write Bank

Address Register

(Volatile)

SPI

QPI

17h/C5h

18h

Data in

Write Bank

Address Register

(Non-Volatile)

SPI

QPI

Enter 4-byte

Address Mode

SPI

QPI

EN4B

EX4B

B7h

29h

FAh

E0h

FBh

E1h

FCh

E2h

Exit 4-byte

Address Mode

SPI

QPI

Read DYB

(3-byte Address)

SPI

QPI

A

<7:0>

RDDYB

4RDDYB

WRDYB

4WRDYB

RDPPB

4RDPPB

Data out

<23:16>

<15:8>

Read DYB

(4-byte Address)

SPI

QPI

A

<7:0>

Data out

<31::24>

<23:16>

<15:8>

4-byte Address

Read DYB

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

Write DYB

(3-byte Address)

SPI

QPI

A

<7:0>

Data in

<23:16>

<15:8>

Write DYB

(4-byte Address)

SPI

QPI

A

<7:0>

Data in

<31::24>

<23:16>

<15:8>

4-byte Address

Write DYB

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

Read PPB

(3-byte Address)

A

<7:0>

SPI

Data out

<23:16>

<15:8>

Read PPB

(4-byte Address)

A

<7:0>

Data out

<31::24>

<23:16>

<15:8>

4-byte Address

Read PPB

A

<7:0>

<31::24>

<23:16>

<15:8>

Program PPB

(Individually)

(3-byte Address)

SPI

QPI

A

<7:0>

PGPPB

4PGPPB

FDh

E3h

<23:16>

<15:8>

Program PPB

(Individually)

(4-byte Address)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

4-byte Address

Program PPB

(Individually)

SPI

QPI

A

<7:0>

<31::24>

<23:16>

<15:8>

Erase PPB (as

a group)

SPI

QPI

ERPPB

RDASP

PGASP

RDPLB

WRPLB

SFRZ

E4h

2Bh

2Fh

A7h

A6h

91h

SPI

QPI

Data out

(2 byte)

Read ASP

SPI

QPI

PD

(2 byte)

Program ASP

Read PPB Lock

Bit

SPI

QPI

Data out

Write PPB Lock

Bit

SPI

QPI

SPI

QPI

Set FREEZE bit

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Rev A6

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IS25LP256D

IS25WP256D

Instruction

Name

Operation

Mode

Byte0

E7h

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

SPI

QPI

Data out

(8 byte)

RDPWD

PGPWD

UNPWD

Read Password

Program

Password

SPI

QPI

PD

(8 byte)

E8h

Unlock

Password

SPI

QPI

Data in

(8 byte)

E9h

Set all DYB bits

(Gang Sector/

Block Lock)

SPI

QPI

GBLK

7Eh

98h

Clear all DYB bits

(Gang Sector/

Block Unlock)

SPI

QPI

GBUN

Notes:

1. The number of dummy cycles depends on the value setting in the Table 6.11 Read Dummy Cycles.

2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.

3. XX means “don’t care”.

4. A<23:9> are “don’t care” and A<8:4> are always “0”.

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Rev A6

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IS25LP256D

IS25WP256D

8.3 NORMAL READ OPERATION (NORD, 03h or 4NORD, 13h)

The Normal Read (NORD) instruction is used to read memory contents at a maximum frequency of 80MHz.

 03h (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 03h (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 13h is followed by a 4-byte address (A31-A0)

The Normal Read instruction code is transmitted via the SI line, followed by three (A23 - A0) or four (A31 – A0)

address bytes of the first memory location to be read as above. A total of 24 or 32 address bits are shifted in, but

only AVMSB (Valid Most Significant Bit) - A₀are decoded. The remaining bits (A31 – AVMSB+1) are ignored. The first

byte addressed can be at any memory location. Upon completion, any data on the SI will be ignored. Refer to Table

8.5 for the related Address Key.

The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole memory

array, can be read out in one Normal Read instruction. The address is automatically incremented by one after each

byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the

data comes out. When the highest address of the device is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read in one continuous Read instruction.

If the Normal Read instruction is issued while an Erase, Program or Write operation is in process (WIP=1) the

instruction is ignored and will not have any effects on the current operation.

Table 8.5 Address Key

Valid Address

256Mb

A23-A0

A24-A0 (A31-A25=X)⁽²⁾

Mode

3 byte address

4 byte address

A_VMSB⁽²⁾–A₀

Notes:

1. X=Don’t Care

2. A_VMSBis a Valid MSB. In 4 byte address for 256Mb, A31 is an MSB, and A24 is a Valid MSB.

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IS25LP256D

IS25WP256D

Figure 8.1 Normal Read Sequence (03h [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = 03h

2

1

0

23

22

High Impedance

SO

CE#

SCK

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

...

SI

Data Out 1

Data Out 2

SO

...

1

0

1

0

3

6

5

4

3

2

7

6

5

4

2

7

t_V

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Rev A6

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IS25LP256D

IS25WP256D

Figure 8.2 Normal Read Sequence (03h [EXTADD=1] or 13h, 4-byte address)

CE#

36

37

38

39

0

1

2

3

4

5

6

7

8

9

10

29

...

Mode 3

Mode 0

SCK

4-byte Address

...

SI

3

Instruction = 03h/13h

2

1

0

31

30

High Impedance

SO

CE#

SCK

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

...

SI

Data Out 1

Data Out 2

SO

...

1

0

1

0

3

6

5

4

3

2

7

6

5

4

2

7

t_V

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Rev A6

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IS25LP256D

IS25WP256D

8.4 FAST READ OPERATION (FRD, 0Bh or 4FRD, 0Ch)

The Fast Read (FRD, 4FRD) instruction is used to read memory data at up to a 166MHz clock.

 0Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 0Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 0Ch is followed by a 4-byte address (A31-A0)

The Fast Read instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK.

Then the first data byte from the address is shifted out on the SO line, with each bit shifted out at a maximum

frequency fCT, during the falling edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single Fast Read instruction. The Fast Read

instruction is terminated by driving CE# high (VIH).

If the Fast Read instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction

is ignored without affecting the current cycle.

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IS25LP256D

IS25WP256D

Figure 8.3 Fast Read Sequence (0Bh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

3

Instruction = 0Bh

2

1

0

23

22

High Impedance

SO

CE#

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

...

SCK

SI

Dummy Cycles

Data Out

t_V

SO

...

1

0

3

7

6

5

4

2

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

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Rev A6

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IS25LP256D

IS25WP256D

Figure 8.4 Fast Read Sequence (0Bh [EXTADD=1] or 0Ch, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

29

...

36

37

38

39

Mode 3

Mode 0

SCK

SI

4-byte Address

...

3

Instruction = 0Bh/0Ch

High Impedance

2

1

0

31

30

SO

CE#

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

...

SCK

SI

Dummy Cycles

Data Out

t_V

SO

...

1

0

3

7

6

5

4

2

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

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Rev A6

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IS25LP256D

IS25WP256D

FAST READ OPERATION IN QPI MODE (FRD, 0Bh or 4FRD, 0Ch)

The Fast Read (FRD) instruction in QPI mode is used to read memory data at up to a 166MHz clock.

 0Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 0Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 0Ch is followed by a 4-byte address (A31-A0)

The Fast Read instruction code (2 clocks) is followed by three (6 clocks) or four (8 clocks) address bytes as above

and 6 dummy cycles (configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each

bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1

and IO0 lines, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single Fast Read QPI instruction. The Fast Read

QPI instruction is terminated by driving CE# high (VIH).

If the Fast Read instruction in QPI mode is issued while an Erase, Program or Write cycle is in process (WIP=1)

the instruction is ignored without affecting the current cycle.

The Fast Read sequence in QPI mode is also applied to the commands in the following table 8.6. However, only

3-byte address mode QPI sequence is applied for RDUID, RDSFDP, and IRRD commands.

Table 8.6 Instructions that Fast Read sequence in QPI Mode is applied to

Instruction Name

FRQIO

Operation

Fast Read Quad I/O

Hex Code

EBh

RDUID

Read Unique ID

SFDP Read

4Bh

RDSFDP

IRRD

5Ah

Read Information Row

68h

Figure 8.5 Fast Read QPI Sequence (0Bh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

...

13

14

15

16

17

...

Mode 3

Mode 0

SCK

t_V

...

IO[3:0]

0Bh

Instruction

23:20 19:16 15:12 11:8 7:4 3:0

3-byte Address

7:4 3:0

Data 1

7:4 3:0

Data 2

6 Dummy Cycles

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy

Cycles.

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IS25LP256D

IS25WP256D

Figure 8.6 Fast Read Sequence In QPI Mode (0Bh [EXTADD=1] or 0Ch, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

...

15

16

17

...

Mode 3

Mode 0

SCK

t_V

...

IO[3:0]

0Bh/0Ch 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0

Instruction 4-byte Address

7:4 3:0

Data 1

6 Dummy Cycles

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy

Cycles.

8.5 HOLD OPERATION

HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence is

underway, HOLD# can be used to pause the serial communication with the master device without resetting the

serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,

HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored

while SO is in the high impedance state, during HOLD.

Note: HOLD is not supported in DTR mode or with QE=1 or when RESET# is selected for the HOLD# or RESET# pin.

Timing graph can be referenced in AC Parameters Figure 9.4.

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IS25LP256D

IS25WP256D

8.6 FAST READ DUAL I/O OPERATION (FRDIO, BBh or 4FRDIO, BCh)

The Fast Read Dual I/O (FRDIO, 4FRDIO) instruction allows the address bits to be input two bits at a time. This

may allow for code to be executed directly from the SPI in some applications.

 BBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 BBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 BCh is followed by a 4-byte address (A31-A0)

The FRDIO/4FRDIO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the

rising edge of SCK. The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to

alternate between the two lines. Depending on the usage of AX read operation mode, a mode byte may be located

after address input.

The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum

frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second

bit is output on IO0. Figures 8.7 and 8.8 illustrates the timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDIO/4FRDIO instruction. The

FRDIO/4FRDIO instruction is terminated by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8

bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO/4FRDIO execution.

M7 to M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah),

it enables the AX read operation and subsequent FRDIO/4FRDIO execution skips command code. It saves cycles

as described in Figures 8.9 and 8.10. When the code is different from AXh (where X is don’t care), the device exits

the AX read operation. After finishing the read operation, device becomes ready to receive a new command. SPI

or QPI mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of

dummy cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 4 cycles, data

output will start right after mode bit is applied.

If the FRDIO/4FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not affect the current cycle.

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IS25LP256D

IS25WP256D

Figure 8.7 Fast Read Dual I/O Sequence (BBh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

...

18

19

20

21

Mode 3

Mode 0

SCK

4 Dummy Cycles

3-byte Address

...

IO0

IO1

2

3

Instruction = BBh

0

1

6

7

4

22

23

20

21

18

High Impedance

...

5

19

Mode Bits

CE#

SCK

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

...

t_V

...

IO0

2

0

1

4

5

0

1

2

0

1

6

7

2

6

7

6

7

6

7

4

2

0

1

4

Data Out 1

Data Out 2

Data Out 3

IO1

3

5

3

5

3

5

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

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IS25LP256D

IS25WP256D

Figure 8.8 Fast Read Dual I/O Sequence (BBh [EXTADD=1] or BCh, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

...

22

23

24

25

Mode 3

Mode 0

SCK

4 Dummy Cycles

4-byte Address

...

IO0

IO1

2

3

Instruction = BBh/BCh

0

1

6

7

4

30

31

28

29

26

High Impedance

...

5

27

Mode Bits

CE#

SCK

26

27

28

29

30

31

32

33

34

35

36

37

38

39

36

41

...

t_V

...

IO0

IO1

2

0

1

4

5

0

1

2

0

1

6

7

2

6

7

6

7

6

7

4

2

0

1

4

Data Out 1

Data Out 2

Data Out 3

3

5

3

5

3

5

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

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IS25LP256D

IS25WP256D

Figure 8.9 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=0], 3-byte address)

CE#

...

0

1

2

3

11

12

13

14

15

16

17

18

19

20

21

...

Mode 3

Mode 0

SCK

4 Dummy Cycles

t_V

3-byte Address

Data Out 1

Data Out 2

4

...

IO0

IO1

2

3

6

7

2

6

7

2

0

1

4

0

1

4

0

1

6

7

22

23

20

21

18

...

3

5

19

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

Figure 8.10 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=1] or BCh, 4-byte address)

CE#

...

0

1

2

3

15

16

17

18

19

20

21

22

23

24

25

...

Mode 3

Mode 0

SCK

4 Dummy Cycles

t_V

4-byte Address

Data Out 1

Data Out 2

4

...

IO0

IO1

2

3

6

7

2

6

7

2

0

1

4

0

1

4

0

1

6

7

30

31

28

29

26

...

3

5

27

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

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Rev A6

59

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IS25LP256D

IS25WP256D

8.7 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh or 4FRDO, 3Ch)

The FRDO/4FRDO instruction is used to read memory data on two output pins each at up to a 166MHz clock.

 3Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 3Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 3Ch is followed by a 4-byte address (A31-A0)

The FRDO/4FRDO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK.

Then the first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a

maximum frequency f_CT, during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously, the

second bit is output on IO0.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDO/4FRDO instruction. The instruction

FRDO/4FRDO is terminated by driving CE# high (VIH).

If the FRDO/4FRDO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not have any effects on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

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04/15/2019

IS25LP256D

IS25WP256D

Figure 8.11 Fast Read Dual Output Sequence (3Bh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

3

IO0

IO1

Instruction = 3Bh

2

1

0

23

22

High Impedance

CE#

SCK

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

...

t_V

...

IO0

IO1

0

1

2

6

7

4

6

7

4

2

0

1

8 Dummy Cycles

Data Out 1

Data Out 2

3

5

3

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

61

04/15/2019

IS25LP256D

IS25WP256D

Figure 8.12 Fast Read Dual Output Sequence (3Bh [EXTADD=1] or 3Ch, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

29

...

36

37

38

39

Mode 3

Mode 0

SCK

4-byte Address

...

3

IO0

IO1

Instruction = 3Bh/3Ch

High Impedance

2

1

0

31

30

CE#

SCK

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

...

t_V

...

IO0

IO1

0

1

2

6

7

4

6

7

4

2

0

1

8 Dummy Cycles

Data Out 1

Data Out 2

3

5

3

5

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

62

04/15/2019

IS25LP256D

IS25WP256D

8.8 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh or 4FRQO 6Ch)

The FRQO/4FRQO instruction is used to read memory data on four output pins each at up to a 166 MHz clock.

A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Output instruction.

 6Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 6Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 6Ch is followed by a 4-byte address (A31-A0)

The FRQO/4FRQO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising

edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with

each group of four bits shifted out at a maximum frequency f_CT, during the falling edge of SCK. The first

bit (MSB) is output on IO3, while simultaneously the second bit is output on IO2, the third bit is output on

IO1, etc.

The first byte addressed can be at any memory location. The address is automatically incremented after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over

to the 000000h address, allowing the entire memory to be read with a single FRQO/4FRQO instruction.

FRQO/4FRQO instruction is terminated by driving CE# high (VIH).

If a FRQO/4FRQO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not have any effects on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

63

04/15/2019

IS25LP256D

IS25WP256D

Figure 8.13

Fast Read Quad Output Sequence (6Bh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

SCK

IO0

Mode 0

3-byte Address

...

3

Instruction = 6Bh

2

1

0

23

22

High Impedance

IO1

IO2

IO3

High Impedance

CE#

SCK

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

...

t_V

...

IO0

IO1

IO2

IO3

0

4

0

4

0

4

0

8 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3 Data Out 4

1

...

5

1

5

1

5

1

2

6

2

6

2

6

2

3

...

7

3

7

3

7

3

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

64

04/15/2019

IS25LP256D

IS25WP256D

Figure 8.14

Fast Read Quad Output Sequence (6Bh [EXTADD=1] or 6Ch, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

29

...

36

37

38

39

Mode 3

SCK

IO0

Mode 0

4-byte Address

...

3

Instruction = 6Bh/6Ch

2

1

0

31

30

High Impedance

IO1

IO2

IO3

CE#

SCK

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

...

t_V

...

IO0

IO1

IO2

IO3

0

4

0

4

0

4

0

8 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3 Data Out 4

1

...

5

1

5

1

5

1

2

6

2

6

2

6

2

3

...

7

3

7

3

7

3

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

65

04/15/2019

IS25LP256D

IS25WP256D

8.9 FAST READ QUAD I/O OPERATION (FRQIO, EBh or 4FRQIO, ECh)

The FRQIO/4FRQIO instruction allows the address bits to be input four bits at a time. This may allow for

code to be executed directly from the SPI in some applications.

A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad I/O instruction.

 EBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 EBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 ECh is followed by a 4-byte address (A31-A0)

The FRQIO/4FRQIO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each group of four bits

latched-in during the rising edge of SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on

IO1, the next bit on IO0, and continue to shift in alternating on the four. Depending on the usage of AX read

operation mode, a mode byte may be located after address input.

The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted

out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while

simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figures 8.15 and 8.16 illustrates

the timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented after each byte

of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h

address, allowing the entire memory to be read with a single FRQIO/4FRQIO instruction. FRQIO/4FRQIO

instruction is terminated by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8

bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO/4FRQIO execution.

M7 to M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah),

it enables the AX read operation and subsequent FRQIO/4FRQIO execution skips command code. It saves cycles

as described in Figures 8.17 and 8.18. When the code is different from AXh (where X is don’t care), the device

exits the AX read operation. After finishing the read operation, device becomes ready to receive a new command.

SPI or QPI mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number

of dummy cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles,

data output will start right after mode bits and 4 additional dummy cycles are applied.

If the FRQIO/4FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not have any effects on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

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IS25LP256D

IS25WP256D

Figure 8.15 Fast Read Quad I/O Sequence (EBh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

3-byte Address

IO0

IO1

4

5

6

7

Instruction = EBh

High Impedance

0

1

2

3

4

5

6

7

0

1

2

3

20

21

22

23

16

17

18

19

12

13

14

15

8

9

IO2

IO3

10

11

Mode Bits

CE#

SCK

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

...

6 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3 Data Out 4

Data Out 5 Data Out 6

t_V

...

IO0

0

1

2

3

4

5

6

7

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

IO1

IO2

IO3

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

67

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IS25LP256D

IS25WP256D

Figure 8.16 Fast Read Quad I/O Sequence (EBh [EXTADD=1] or ECh, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

4-byte Address

IO0

IO1

4

5

6

7

Instruction = EBh/ECh

High Impedance

0

1

2

3

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

8

9

IO2

IO3

10

11

CE#

SCK

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

...

6 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3

Data Out 4 Data Out 5

t_V

...

IO0

IO1

0

1

2

3

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

4

5

6

7

IO2

IO3

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

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IS25LP256D

IS25WP256D

Figure 8.17 Fast Read Quad I/O AX Read Sequence (EBh [EXTADD=0], 3-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

...

Mode 3

Mode 0

SCK

6 Dummy Cycles

3-byte Address

Data Out 1 Data Out 2

t_V

...

IO0

IO1

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

4

5

6

7

20

21

22

23

16

17

18

19

12

13

14

15

8

9

0

1

2

3

IO2

IO3

10

11

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

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Rev A6

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IS25LP256D

IS25WP256D

Figure 8.18 Fast Read Quad I/O AX Read Sequence (EBh [EXTADD=1] or ECh, 4-byte address)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

...

Mode 3

Mode 0

SCK

6 Dummy Cycles

4-byte Address

Data Out 1

t_V

...

IO0

IO1

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

8

9

IO2

IO3

10

11

Mode Bits

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

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IS25LP256D

IS25WP256D

FAST READ QUAD I/O OPERATION IN QPI MODE (FRQIO, EBh or 4FRQIO, ECh)

The FRQIO/4FRQIO instruction in QPI mode is used to read memory data at up to a 166MHz clock.

It is not required to set QE bit to “1”.before Fast Read Quad I/O instruction in QPI mode.

The FRQIO/4FRQIO instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two

clocks are required, while the FRQIO/4FRQIO instruction requires that the byte-long instruction code is shifted into

the device only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQIO/4FRQIO

QPI instruction. In addition, subsequent address and data out are shifted in/out via all four IO lines like the

FRQIO/4FRQIO instruction. In fact, except for the command cycle, the FRQIO/4FRQIO operation in QPI mode is

exactly same as the FRQIO/4FRQIO operation in SPI mode.