IS31AP4066D [ISSI]
DUAL 1.3W STEREO AUDIO AMPLIFIER; 双1.3W立体声音频放大器
| 型号： | IS31AP4066D |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | DUAL 1.3W STEREO AUDIO AMPLIFIER |
| 文件： | 总14页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS31AP4066D
DUAL 1.3W STEREO AUDIO AMPLIFIER
December 2011
GENERAL DESCRIPTION
KEY SPECIFICATIONS
The IS31AP4066D is a dual bridge-connected audio
power amplifier which, when connected to a 5V supply,
will deliver 1.3W to an 8Ω load.
PO at RL = 8Ω, VDD = 5V
THD+N = 1% ---------------------- 1.3W (Typ.)
THD+N = 10% --------------------- 1.6W (Typ.)
PO at RL = 8Ω, VDD = 4V
THD+N = 1% ----------------------- 0.81W (Typ.)
Shutdown current ------------------- 0.3μA (Typ.)
Supply voltage range --------------- 2.7V ~ 5.5V
QFN-16 (3mm × 3mm) package
The IS31AP4066D features a low-power consumption
shutdown mode and thermal shutdown protection. It
also utilizes circuitry to reduce “click-and-pop” during
device turn-on.
APPLICATIONS
FEATURES
Cell phones, PDA, MP4,PMP
Portable and desktop computers
Desktops audio system
Suppress “click-and-pop”
Thermal shutdown protection circuitry
Micro power shutdown mode
Multimedia monitors
TYPICAL APPLICATION CIRCUIT
R2
20K
VCC
VCC
C3
SHUTDOWN
WORKING
1uF
2,11
VDD
15 SHUTDOWN
INA
BNC
C1
R1
4
8
9
INA
-
-OUTA
3
1
20K
0.22uF
+
+OUTA
-
+
BYPASS
C4
+
-
1uF
+OUTB 12
-OUTB 10
INB
BNC
+
-
C2
R3
INB
20K
0.22uF
GND
5,6,7,13,14,16
R4
20K
Figure 1 Typical Application Circuit
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Rev.A, 11/29/2011
IS31AP4066D
PIN CONFIGURATION
Package
Pin Configuration (Top View)
+OUTA
VDD
1
2
3
4
12 +OUTB
11 VDD
QFN-16
-OUTA
INA
10 -OUTB
9
INB
PIN DESCRIPTION
No.
Pin
Description
1
+OUTA
VDD
Left channel +output.
Supply voltage.
Left channel –output.
Left channel Input.
GND.
2,11
3
-OUTA
INA
4
5~7,13,14,16
GND
Bypass capacitor which provides the
common mode voltage.
8
BYPASS
9
INB
Right channel input.
Right channel –output.
Right channel +output.
10
12
-OUTB
+OUTB
————————————
Shutdown control, hold low for shutdown
mode.
15
SHUTDOWN
Thermal Pad
Connect to GND.
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev.A, 11/29/2011
IS31AP4066D
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Order Part No.
Package
QTY/Reel
IS31AP4066D-QFLS2-TR
QFN-16, Lead-free
2500
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Rev.A, 11/29/2011
IS31AP4066D
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD
-0.3V ~ +6.0V
Voltage at any input pin
Junction temperature, TJMAX
Storage temperature range, Tstg
Operating temperature ratings
Solder information, Vapor Phase (60s)
Infrared (15s)
-0.3V ~ VDD+0.3V
-40°C ~ +150°C
-65°C ~ +150°C
−40°C ~ +85°C
215°C
220°C
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
The following specifications apply for VDD= 5V, unless otherwise noted.
Limits apply for TA = 25°C. (Note 1 or specified)
Symbol
Parameter
Supply voltage
Quiescent power supply current VIN = 0V, Io = 0A
Condition
Typ.
Limit
Unit
2.7
5.5
V(min)
V(max)
VDD
IDD
ISD
3.9
0.3
10.0
mA(max)
GND applied to the shutdown
Shutdown current
2.5
μA(max)
pin
VIH
VIL
Shutdown input voltage high
Shutdown input voltage low
Turn on time
1.4
0.4
V(min)
V(max)
ms
TWU
1μF bypass cap(C4) (Note 2)
120.0
ELECTRICAL CHARACTERISTICS OPERATION
The following specifications apply for VDD= 5V, unless otherwise noted.
Limits apply for TA = 25°C. (Note 2 or specified)
Symbol
Parameter
Condition
Typ.
Limit
25.0
Unit
Vos
Output offset voltage VIN = 0V
5.0
1.3
1.6
mV(max)
W(min)
W(min)
THD+N = 1%, f = 1kHz, RL= 8Ω
THD+N = 10%, f = 1kHz, RL = 8Ω
Po
Output power
Total
distortion +noise
harmonic
THD+N
1kHz, Avd = 2, R = 8Ω, Po = 1W
0.1
%
Input floating, 217Hz, Vripple = 200mVp-p
C4 = 1μF, RL = 8Ω
80.0
70.0
60.0
60.0
dB
dB
dB
dB
Input floating 1kHz, Vripple = 200mVp-p
C4 = 1μF, RL = 8Ω
Power
rejection ratio
supply
PSRR
Input GND 217Hz, Vripple = 200mVp-p
C4 = 1μF, RL =8Ω
Input GND 1kHz Vripple = 200mVp-p
C4 = 1μF, RL = 8Ω
Xtalk
VNO
Channel separation
f = 1kHz, C4 = 1μF
-100.0
7.0
dB
Output noise voltage 1kHz, A-weighted
μV
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Rev.A, 11/29/2011
IS31AP4066D
ELECTRICAL CHARACTERISTICS
The following specifications apply for VDD= 3V, unless otherwise noted.
Limits apply for TA = 25°C. (Note 1 or specified)
Symbol
Parameter
Condition
Typ.
Limit
Unit
Quiescent
current
power
supply
IDD
VIN = 0V, IO = 0A
2.6
0.1
6.5
mA(max)
ISD
VIH
VIL
Shutdown current
GND applied to the shutdown pin
2.2
1.1
0.4
μA(max)
V(min)
V(max)
ms
Shutdown input voltage high
Shutdown input voltage low
Turn on time
TWU
1μF bypass cap(C4) (Note 2)
110
ELECTRICAL CHARACTERISTICS OPERATION
The following specifications apply for VDD= 3V, unless otherwise noted.
Limits apply for TA = 25°C. (Note 2 or specified)
Symbol
Parameter
Condition
Typ.
Limit
25.0
Unit
Vos
Output offset voltage VIN=0V
2.5
0.5
mV
W
THD+N = 1%, f = 1kHz, RL= 8Ω
Po
Output power
THD+N = 10%, f = 1kHz, RL = 8Ω
0.6
0.1
W
%
Total harmonic
distortion+noise
THD+N
1kHz, Avd = 2, RL = 8Ω, Po = 0.3W
Input floating, 217Hz, Vripple = 200mVp-p
C4 = 1μF, RL = 8Ω
75.0
70.0
62.0
62.0
dB
dB
dB
dB
Input floating 1kHz, Vripple = 200mVp-p
C4 = 1μF, RL = 8Ω
Power supply
rejection ratio
PSRR
Input GND 217Hz, Vripple = 200mVp-p
C4 = 1μF, RL =8Ω
Input GND 1kHz Vripple = 200mVp-p
C4 = 1μF, RL = 8Ω
Xtalk
VNO
Channel separation
f = 1kHz, C4 = 1μF
-100.0
7.0
dB
uV
Output noise voltage 1kHz, A-weighted
Note1: All parameters are production tested at 25°C, functional operation of the device and parameters specified over other temperature range,
are guaranteed by design, characterization and process control.
Note 2: Guaranteed by design.
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IS31AP4066D
TYPICAL PERFORMANCE CHARACTERISTICS
Vcc = 5V
Vcc = 3V
R
L
R
L
f = 1kHz
f = 1kHz
Figure 2 THD+N vs. Output Power
Figure 3 THD+N vs. Output Power
Vcc = 5V
Vcc = 3V
R
L
R
L
Po = 1W
Po=300mW
Figure 4 THD+N vs. Frequency
Figure 5 THD+N vs. Frequency
Vcc = 5V
Vcc = 3V
R
L
RL
Input GND
Input GND
Figure 7 PSRR vs. Frequency
Figure 6 PSRR vs. Frequency
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Rev.A, 11/29/2011
IS31AP4066D
Vcc = 5V
Vcc = 5V
RL
R
L
Input Floating
Figure 9 Crosstalk vs. Frequency
Figure 8 PSRR vs. Frequency
Vcc = 3V
Vcc = 5V
R
L
R
L
Input Floating
A-Weighting
Figure 11 Noise Floor
Figure 10 PSRR vs. Frequency
Vcc = 3V
Vcc = 5V
R
L
R
L
Figure 13 Frequency Response
Figure 12 Frequency Response
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Rev.A, 11/29/2011
IS31AP4066D
Vcc = 3V
Vcc = 3V
RL
R
L
A-Weighting
Figure 14 Crosstalk vs. Frequency
Figure 15 Noise Floor
RL
Top Side
Bottom Side
Vcc = 5V
R
L
f = 1kHz
Output Power (W)
Figure 17 Power Dissipation vs. Output Power
Figure 16 Dropout Voltage vs. Supply Voltage
R
L
f = 1kHz
THD+N = 10%
THD+N = 1%
Figure18 Output Power vs. Supply Voltage
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Rev.A, 11/29/2011
IS31AP4066D
APPLICATION INFORMATION
EXPOSED-DAP PACKAGE PCB MOUNTING
CONSIDERATIONS
amplifier’s half-supply bias voltage across the load.
This increases internal IC power dissipation and may
permanently damage loads such as speakers.
The IS31AP4066D’s QFN (die attach paddle) package
provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered.
This allows rapid heat transfer from the die to the
surrounding PCB copper traces, ground plane and,
finally, surrounding air.
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier. Equation
(2) states the maximum power dissipation point for a
single ended amplifier operating at a given supply
voltage and driving a specified output load.
The QFN package must have it’s DAP soldered to a
copper pad on the PCB. The DAP’s PCB copper pad is
connected to a large plane of continuous unbroken
copper. This plane forms a thermal mass and heat sink
and radiation area. Place the heat sink area on either
outside plane in the case of a two-sided PCB, or on an
inner layer of a board with more than two layers.
PDMAX = (VDD)2/(2π2RL) Single-Ended
(2)
However, a direct consequence of the increased power
delivered to the load by a bridge amplifier is higher
internal power dissipation for the same conditions.
The IS31AP4066D has two operational amplifiers per
channel. The maximum internal power dissipation per
channel operating in the bridge mode is four times that
of a single-ended amplifier. From Equation (3),
assuming a 5V power supply and an 8Ω load, the
maximum single channel power dissipation is 0.63W or
1.26W for stereo operation.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 2, the IS31AP4066D consists of
two pairs of operational amplifiers, forming a
two-channel (channel A and channel B) stereo
amplifier. External feedback resistors R2, R4 and input
resistors R1 and R3 set the closed-loop gain of Amp A
(-out) and Amp B (-out) whereas two internal 20kΩ
resistors set Amp A’s (+out) and Amp B’s (+out) gain at
1. The IS31AP4066D drives a load, such speaker,
connected between the two amplifier outputs, −OUTA
and +OUTA.
P
DMAX = 4×(VDD)2/(2π2RL) Bridge Mode(3)
The IS31AP4066D’s power dissipation is twice that
given by Equation (2) or Equation (3) when operating
in the single-ended mode or bridge mode, respectively.
Twice the maximum power dissipation point given by
Equation (3) must not exceed the power dissipation
given by Equation (4):
Figure 2 shows that Amp A’s (-out) output serves as
Amp A’s (+out) input. This results in both amplifiers
producing signals identical in magnitude, but 180° out
of phase. Taking advantage of this phase difference, a
load is placed between −OUTA and +OUTA and driven
differentially (commonly referred to as “bridge mode”).
This results in a differential gain of
PDMAX' = (TJMAX − TA)/θJA
(4)
The IS31AP4066D’s TJMAX = 150°C. In the QFN
package soldered to a DAP pad that expands to a
copper area of 5in2 on a PCB, the IS31AP4066D’s θJA
is 23°C/W. At any given ambient temperature TA, use
Equation (4) to find the maximum internal power
dissipation supported by the IC packaging.
A
VD = 2×(Rf/Ri)
(1)
or
Rearranging Equation (4) and substituting PDMAX for
A
VD = 2×(R2/R1)
PDMAX' results in Equation (5). This equation gives the
Bridge mode amplifiers are different from single-ended
amplifiers that drive loads connected between a single
amplifier’s output and ground. For a given supply
voltage, bridge mode has a distinct advantage over the
single-ended configuration: its differential output
doubles the voltage swing across the load. This
produces four times the output power when compared
to a single-ended amplifier under the same conditions.
This increase in attainable output power assumes that
the amplifier is not current limited
maximum ambient temperature that still allows
maximum stereo power dissipation without violating
the IS31AP4066D’s maximum junction temperature.
TA = TJMAX – 2×PDMAX θJA
(5)
For a typical application with a 5V power supply and an
8Ω load, the maximum ambient temperature that
allows maximum stereo power dissipation without
exceeding the maximum junction temperature is
approximately 85°C for the QFN package.
Another advantage of the differential bridge output is
no net DC voltage across the load. This is
T
JMAX = PDMAX θJA + TA
(6)
Equation (6) gives the maximum junction temperature
JMAX. If the result violates the IS31AP4066D’s 150°C,
reduce the maximum junction temperature by reducing
the power supply voltage or increasing the load
resistance. Further allowance should be made for
accomplished by biasing channel A’s and channel B’s
outputs at half-supply. This eliminates the coupling
capacitor that single supply, single ended amplifiers
require. Eliminating an output coupling capacitor in a
single-ended configuration forces a single-supply
T
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Rev.A, 11/29/2011
IS31AP4066D
increased ambient temperatures.
SELECTING PROPER EXTERNAL COMPONENTS
The above examples assume that a device is a surface
mount part operating around the maximum power
dissipation point. Since internal power dissipation is a
function of output power, higher ambient temperatures
are allowed as output power or duty cycle decreases.
Optimizing the IS31AP4066D’s performance requires
properly selecting external components. Though the
IS31AP4066D operates well when using external
components with wide tolerances, best performance is
achieved by optimizing component values.
If the result of Equation (2) is greater than that of
Equation (3), then decrease the supply voltage,
increase the load impedance, or reduce the ambient
temperature. If these measures are insufficient, a heat
sink can be added to reduce θJA. The heat sink can be
created using additional copper area around the
package, with connections to the ground pin(s), supply
pin and amplifier output pins. The θJA is the sum of θJC,
θCS, and θSA. (θJC is the junction-to-case thermal
impedance, θCS is the case-to-sink thermal impedance,
and θSA is the sink-to-ambient thermal impedance.)
The IS31AP4066D is unity-gain stable, giving a
designer maximum design flexibility. The gain should
be set to no more than a given application requires.
This allows the amplifier to achieve minimum THD+N
and maximum signal-to-noise ratio. These parameters
are compromised as the closed-loop gain increases.
However, low gain demands input signals with greater
voltage swings to achieve maximum output power.
Fortunately, many signal sources such as audio
CODECs have outputs of 1VRMS (2.83VP-P). Please
refer to the Audio Power Amplifier Design section for
more information on selecting the proper gain.
POWER SUPPLY BYPASSING
INPUT CAPACITOR VALUE SELECTION
As with any power amplifier, proper supply bypassing
is critical for low noise performance and high power
supply rejection. Applications that employ a 5V
regulator typically use a 10μF in parallel with a 0.1μF
filter capacitor to stabilize the regulator’s output,
reduce noise on the supply line, and improve the
supply’s transient response. However, their presence
does not eliminate the need for a local 1.0μF tantalum
bypass capacitance connected between the
IS31AP4066D’s supply pins and ground. Keep the
length of leads and traces that connect capacitors
between the IS31AP4066D’s power supply pin and
ground as short as possible.
Amplifying the lowest audio frequencies requires high
value input coupling capacitors (C1 and C2) in Figure 2.
A high value capacitor can be expensive and may
compromise space efficiency in portable designs. In
many cases, however, the speakers used in portable
systems, whether internal or external, have little ability
to reproduce signals below 150 Hz. Applications using
speakers with this limited frequency response reap
little improvement by using large input capacitor.
Besides effecting system cost and size, C1 and C2
have an effect on the IS31AP4066D’s click and pop
performance. When the supply voltage is first applied,
a transient (pop) is created as the charge on the input
capacitor changes from zero to a quiescent state. The
magnitude of the pop is directly proportional to the
input capacitor’s size. Higher value capacitors need
more time to reach a quiescent DC voltage (usually
MICRO-POWER SHUTDOWN
The voltage applied to the SHUTDOWN pin controls
the IS31AP4066D’s shutdown function. Activate
micro-power shutdown by applying GND to the
SHUTDOWN pin. When active, the IS31AP4066D’s
micro-power shutdown feature turns off the amplifier’s
bias circuitry, reducing the supply current. The low
0.3μA typical shutdown current is achieved by applying
a voltage that is as near as GND as possible to the
SHUTDOWN pin.
VDD/2) when charged with a fixed current. The
amplifier’s output charges the input capacitor through
the feedback resistors, R2 and R4. Thus, pops can be
minimized by selecting an input capacitor value that is
no higher than necessary to meet the desired −3dB
frequency.
There are a few ways to control the micro-power
shutdown. These include using a single-pole,
single-throw switch, a microprocessor, or a
A shown in Figure 2, the input resistors (R1 and R3)
and the input capacitors (C1 and C2) produce a −3dB
high pass filter cutoff frequency that is found using
Equation (7).
microcontroller. When use a switch, connect an
external 100k resistor between the SHUTDOWN pin
and GND. Select normal amplifier operation by closing
the switch. Opening the switch sets the SHUTDOWN
pin to ground through the 100k resistor, which
activates the micropower shutdown. The switch and
resistor guarantee that the SHUTDOWN pin will not
float. This prevents unwanted state changes. In a
system with a microprocessor or a microcontroller, use
a digital output to apply the control voltage to the
SHUTDOWN pin. Driving the SHUTDOWN pin with
active circuitry eliminates the pull up resistor.
f
-3dB= 1/2πRinCin= 1/2π R1C1
(7)
As an example when using a speaker with a low
frequency limit of 150Hz, C1, using Equation (7) is
0.053μF. The 0.33μF C1 shown in Figure 2 allows the
IS31AP4066D to drive high efficiency, full range
speaker whose response extends below 30Hz.
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IS31AP4066D
BYPASS CAPACITOR VALUE SELECTION
The gain of the internal amplifiers remains unity until
the voltage on the bypass pin reaches 1/2 VDD. As
soon as the voltage on the bypass pin is stable, the
device becomes fully operational. Although the
BYPASS pin current cannot be modified, changing the
size of C4 alters the device’s turn-on time and the
magnitude of “clicks and pops”. Increasing the value of
C4 reduces the magnitude of turn-on pops. However,
this presents a tradeoff: as the size of C4 increases,
the turn-on time increases. There is a linear
Besides minimizing the input capacitor size, careful
consideration should be paid to value of C4, the
capacitor connected to the BYPASS pin. Since C4
determines how fast the IS31AP4066D settles to
quiescent operation, its value is critical when
minimizing turn-on pops. The slower the
IS31AP4066D’s outputs ramp to their quiescent DC
voltage (nominally 1/2 VDD), the smaller the turn-on
pop. Choosing C4 equal to 1.0μF along with a small
value of C1 (in the range of 0.1μF to 0.39μF),
produces a click-less and pop-less shutdown function.
As discussed above, choosing C1 no larger than
necessary for the desired bandwith helps minimize
clicks and pops. Connecting a 1μF capacitor, C4,
between the BYPASS pin and ground improves the
internal bias voltage’s stability and improves the
amplifier’s PSRR.
relationship between the size of C4 and the turn-on
time. Here are some typical turn-on times for various
values of C4 (all tested at VDD=5V):
C4
TON
0.01μF
0.1μF
13ms
26ms
0.22μF
0.47μF
1.0μF
44ms
OPTIMIZING CLICK AND POP REDUCTION
PERFORMANCE
68ms
The IS31AP4066D contains circuitry that minimizes
turn-on and shutdown transients or “clicks and pop”.
For this discussion, turn-on refers to either applying
the power supply voltage or when the shutdown mode
is deactivated. When the part is turned on, an internal
current source changes the voltage of the BYPASS pin
in a controlled, linear manner. Ideally, the input and
outputs track the voltage applied to the BYPASS pin.
120 ms
In order eliminate “clicks and pops”; all capacitors must
be discharged before turn-on. Rapidly switching VDD
on and off may not allow the capacitors to fully
discharge, which may cause “clicks and pops”.
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IS31AP4066D
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
150°C
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
Time 25°C to peak temperature
6°C/second max.
8 minutes max.
Figure 19 Classification Profile
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IS31AP4066D
TAPE AND REEL INFORMATION
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Rev.A, 11/29/2011
IS31AP4066D
PACKAGE INFORMATION
QFN-16
Note: All dimensions in millimeters unless otherwise stated.
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Rev.A, 11/29/2011
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