IS31IO7326 [ISSI]

DEBOUNCED 8Ã8 KEY-SCAN CONTROLLER; 抖8A ?? 8按键扫描控制器


型号：	IS31IO7326
厂家：	INTEGRATED SILICON SOLUTION, INC
描述：	DEBOUNCED 8Ã8 KEY-SCAN CONTROLLER 抖8A ?? 8按键扫描控制器控制器
文件：	总14页 (文件大小：369K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IS31IO7326

DEBOUNCED 8×8 KEY-SCAN CONTROLLER

January 2012

GENERAL DESCRIPTION

FEATURES

The IS31IO7326 is a 64 key, key-scan controller. It

offloads the burden of keyboard scanning from the host

processor. The IS31IO7326 supports keypad matrix of

up to 8×8. Key press and release events are encoded

into a byte format and loaded into a key event register

for retrieval by the host processor.



2.4V to 5.5V operation

400kHz I²C serial interface

Available for multi-key press detect

Low 0.3μA (typ.) standby current

Operate in -40°C to +125°C

Pb-free 4mm × 4mm QFN-24 package

The IS31IO7326 integrates a debounce function which

rejects false or transient key switch activities. The

_______

interrupt output (INT) is used to signify if there are any

keypad activities.

APPLICATIONS



Keypad of QWERTY type phones

PDAs, games, and other handheld applications

To minimize power, the IS31IO7326 automatically

enters a low power standby mode when there is no

keypad, I/O, or host activity.

The IS31IO7326 is available in a Pb-free 4mm × 4mm

QFN-24 package.

TYPICAL APPLICATION CIRCUIT

VBattery

100k

VBattery

PP0

VCC

PP1

PP2

PP3

PP4

PP5

PP6

PP7

1 F

0.1 F

V_DD

4.7k 4.7k 4.7k

SCL

^SDAIS31IO7326

Micro

Controller

INT

OD0

OD1

OD2

OD3

OD4

OD5

OD6

OD7

RST

100k

AD0

AD1

GND

Figure 1 Typical Application Circuit

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

PIN CONFIGURATION

Package

Pin Configuration (Top View)

QFN-24

PIN DESCRIPTION

No.

Description

1~4, 14~17

PP0~PP7

OD0~OD7

GND

Output ports.

5~8, 10~13

Input ports.

Ground.

AD0

Address setting.

I2C serial clock.

I2C serial data.

SCL

SDA

VCC

_______

Power supply voltage.

Interrupt output, active low.

Reset input, active low.

Address setting.

Connect to GND.

INT

________

RST

AD1

Thermal Pad

time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the

product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not

authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

ORDERING INFORMATION

Industrial Range: -40°C to +125°C

Order Part No.

Package

QFN-24, Lead-free

QTY/Reel

2500

IS31IO7326-QFLS4-TR

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

ABSOLUTE MAXIMUM RATINGS

Supply voltage, V_CC

-0.3V ~ +6.0V

Voltage at any input pin (Except PP0-PP7)

-0.3V ~ V_CC+0.3V

________

_______

-0.3V ~ +6.0V

SCL, SDA, AD, RST, INT, OD0-OD3

PP0–PP3

PP source output current

PP/OD sink current

-0.3V ~ V_CC+0.3V

±100mA

120mA

SDA sink current

10mA

_______

10mA

INT sink current

Continuous power dissipation (T_A= 70°C) 24-Pin QFN (Derate

33.2mW/°C over 70°C)

2.65W

Maximum junction temperature, T_JMAX

Storage temperature range, T_STG

Operating temperature range, T_A

Solder information, vapor phase (60s)

infrared (15s)

150°C

-65°C ~ +150°C

−40°C ~ +125°C

215°C

220°C

ESD HBM

4kV

Note:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

T_A= -40°C ~ +125°C, V_CC= 2.4V ~ 5.5V, unless otherwise noted. Typical values are at T_A= 25°C, V_CC= 3.3V.

(Note 1)

Symbol

Parameter

Supply voltage

Condition

Min.

Typ. Max. Units

V_CC

2.4

5.5

V_POR

Power-on-reset voltage

V_CCfalling

2.35

Standby current

(Interface idle)

SCL,SDA and other digital inputs

at V_CC

I_STB

I+

0.3

6.5

1.9

μA

Supply current

(Interface running)

f_SCL= 400kHz

other digital inputs at V_CC

V_IH

V_IL

Logic “1” input voltage

Logic “0” input voltage

1.4

0.4

________

SDA, SCL, AD0, AD1, RST ,

OD0~OD7 at V_CCor GND

I_IH, I_IL

Input leakage current

Input capacitance

-0.2

+0.2

μA

________

C_IN

(Note 2)

SDA, SCL, AD0, AD1, RST,

OD0~OD7, PP0~PP7

_CC= 2.5V, I_SINK= 10mA

200

240

250

180

Logic “0” output voltage

PP0~PP7

V_OL

V_CC= 3.3V, I_SINK= 15mA

V_CC= 5.0V, I_SINK= 20mA

I_SINK= 5mA

_______

V_OL

Output low-voltage INT

INT

Configuration Register bit SD = 0

Configuration Register bit SD = 1

Time to scan key matrix

completely

t_SCAN

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

TIMING CHARACTERISTICS

T_A= -40°C ~ +125°C, V_CC= 2.4V ~ 5.5V, unless otherwise noted. Typical values are at T_A= 25°C, V_CC= 3.3V.

(Note 3)

Symbol

Parameter

Serial-clock frequency

Condition

Min.

Typ.

Max.

Units

f_SCL

400

kHz

Bus free time between a STOP and a

START condition

t_BUF

1.3

μs

t_{HD, STA}

t_{SU, STA}

t_{SU, STO}

t_{HD, DAT}

t_{SU, DAT}

t_LOW

Hold time (repeated) START condition

Repeated START condition setup time

STOP condition setup time

Data hold time

0.6

μs

(Note 3)

0.9

Data setup time

100

1.3

0.7

SCL clock low period

t_HIGH

SCL clock high period

Rise time of both SDA and SCL signals,

receiving

t_R

t_F

(Note 4)

20 + 0.1Cb

300

Fall time of both SDA and SCL signals,

receiving

300

250

t_{F, TX}

t_SP

C_b

Fall time of SDA transmitting

Pulse width of spike suppressed

Capacitive load for each bus line

(Note 4)

(Note 5)

20 + 0.1Cb

400

________

t_W

500

RST pulse width

________

RST rising to START condition setup

time

μs

RST

PORT AND INTERRUPT TIMING CHARACTERISTICS

T = -40°C ~ +125°C, V_CC= 2.4V ~ 5.5V, unless otherwise noted. Typical values are at T_A= 25°C, V_CC= 3.3V

(Note 3)

Symbol

Parameter

Port output data valid

Condition

Min.

Typ.

Max.

Untis

t_PV

t_PSU

t_PH

t_IV

C_L≤ 100pF

μs

Port input setup time

Port input hold time

_______

INT input data valid time

_______

t_IR

INT reset delay time from acknowledge

Note 1: All parameters are tested at T_A= 25°C. Specifications over temperature are guaranteed by design.

Note 2: Guaranteed by design.

Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the

undefined region of SCL’s falling edge.

Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × V_CCand 0.7× V_CC

Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

DETAILED DESCRIPTION

I2C INTERFACE

After the last bit of the chip address is sent, the master

checks for the IS31IO7326’s acknowledge. The master

releases the SDA line high (through a pull-up resistor).

Then the master sends an SCL pulse. If the

IS31IO7326 has received the address correctly, then it

holds the SDA line low during the SCL pulse. If the SDA

line is not low, then the master should send a “STOP”

signal (discussed later) and abort the transfer.

The IS31IO7326 uses a serial bus, which conforms to

the I2C protocol, to control the chip’s functions with two

wires: SCL and SDA. The IS31IO7326 has a 7-bit slave

____

address (A7:A1), followed by the R/W bit, A0. Set A0 to

“0” for a write command and set A0 to “1” for a read

command. The bit A2:A1 are selected by the

connection of AD1/AD0 pin.

Following acknowledge of IS31IO7326, the register

address byte is sent, most significant bit first.

The complete slave address is:

IS31IO7326 must generate another acknowledge

indicating that the register address has been received.

Table 1 Slave Address:

An 8-bit data byte is sent next, most significant bit first.

Each data bit should be valid while the SCL level is

stable high. After the data byte is sent, the IS31IO7326

must generate another acknowledge to indicate that

the data was received.

Bit

A7:A3

10110

Default

AD1

AD0

0/1

AD1/AD0 connects to VCC, AD1/AD0=1;

AD1/AD0 connects to GND, AD1/AD0=0;

The “STOP” signal ends the transfer. To signal “STOP”,

the SDA signal goes high while the SCL signal is high

(Figure 4).

The SCL line is uni-directional. The SDA line is

bi-directional (open-collector) with a pull-up resistor

(typically 4.7kΩ). The maximum clock frequency

specified by the I2C standard is 400kHz. In this

discussion, the master is the microcontroller and the

slave is the IS31IO7326.

WRITING TO THE REGISTERS

Transmit data to the IS31IO7326 by sending the device

slave address and setting the LSB to “0”. The

command byte is sent after the address and

determines which registers receive the data following

the command byte (Figure 2).

The timing diagram for the I2C is shown in Figure 3.

The SDA is latched in on the stable high level of the

SCL. When there is no interface activity, the SDA line

should be held high.

READING PORT REGISTERS

The “START” signal is generated by lowering the SDA

signal while the SCL signal is high (Figure 4). The start

signal will alert all devices attached to the I2C bus to

check the incoming address against their own chip

address.

To read the device data, the bus master must first send

____

the IS31IO7326 address with the R/W bit set to “0”,

followed by the command byte, which determines

which register is accessed. After a restart, the bus

master must then send the IS31IO7326 address with

____

The 8-bit chip address is sent next, most significant bit

first. Each address bit must be stable while the SCL

level is high.

the R/W bit set to “1”. Data from the register defined by

the command byte is then sent from the IS31IO7326 to

the master (Figure 6).

Figure 2 Writing to IS31IO7326

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

SDA

SU,STA

HD,STA

SU,STO

BUF

SU,DAT

HD,DAT

LOW

HIGH

SCL

HD,STA

Stop

Start

Condition

Restart Condition

Start Condition

Figure 3 Interface Timing

Figure 4 START and STOP Conditions

Figure 5 Acknowledge Signal

Figure 6 Reading I/O Ports of IS31IO7326

KEY PRESS/RELEASE

INT

16ms

9ms

(6ms/8ms)

(3ms/4ms)

_______

Figure 7 I N T Timing

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

Table 2 Register Function

Address

08h

Name

Function

Default

Table

Configuration Register

Key Status Register

Configure the keypad scan function

0001 0000

0000 0000

Contains the information of the key

events

10h

Table 3 08h Configuration Register

Bit D7 D6:D5 D4 D3 D2 D1:D0

Table 4 10h Key Status Register

Bit

D5:D0

Name Reserved

Default

ACI

DE SD LE

Name

Default

000000

The Configuration Register is used to configure the

keypad scan function.

The Key Status Register contains the information of the

key events that have been debounced (see the Table 5

of the key mapping).

_______

ACI

Auto Clear INT

Indicate Data Number

_______

Auto clear INT disabled

_______

One key event to report

More than one key to report

Auto clear INT in 5ms

_______

Auto clear INT in 10ms

Key State

Key released

Key pressed

Input Port Filter Enable

Input port filter disable

Input port filter enable

Key Mapping

Key Scan Debounce Time

KM denotes which of the 64 keys have been

debounced and the keys are numbered as shown in

the Table 5.

Double debounce time (6ms, 8ms)

Normal debounce time (3ms, 4ms)

When the Key Status Register is read over (DN=0), the

Long-pressed Key Detect Enable

_______

Disable

Enable

Long-pressed Key Detect Delay Time

20ms

40ms

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Rev.A, 12/19/2011

IS31IO7326

Table 5 Key Mapping (D5:D0)

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

OD0

OD1

OD2

OD3

OD4

OD5

OD6

OD7

000000

001000

010000

011000

100000

101000

110000

111000

000001

001001

010001

011001

100001

101001

110001

111001

000010

001010

010010

011010

100010

101010

110010

111010

000011

001011

010011

011011

100011

101011

110011

111011

000100

001100

010100

011100

100100

101100

110100

111100

000101

001101

010101

011101

100101

101101

110101

111101

000110

001110

010110

011110

100110

101110

110110

111110

000111

001111

010111

011111

100111

101111

110111

111111

Examples

_______

1. If the key PP1-OD3 pressed only, and other keys keep released state, the INT asserts, the data in Key Status

_______

2. If the key PP4-OD6 released only, and other keys keep released state, the INT asserts, the data in Key Status

_______

3. If the key PP2-OD4 and PP3-OD7 are pressing, then PP2-OD4 released, the INT asserts, the first data in Key

Status Register would be “1010 0010”, the second data would be “0111 1011”. Then judge the MSB (bit DN) in

_______

the second data is “0”. Data has read over, and INT goes to high.

_______

We must read over the data in Key Status Register when the I N T asserts. When judge the MSB (bit DN) in the data is “0”, stop reading the

Key Status Register. If there are some keys connected to the same OD port pressing at the same time, IS31IO7326 only can detect the first

pressed key and others will ignore.

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

APPLICATION INFORMATION

INPUT AND OUTPUT PORT STRUCTURE

If a change of the state of the keypad is detected, the

keypad would be scanned thrice between the

debounce delay. When the state changes have been

A 100kΩ pull-up resistor will force input port high at

V_Battery

reliably captured, the key event(s) are encoded and

_______

V+

written to temporary key status registers. The INT

asserts when the key event(s) is (are) stored. Reading

the Key Status Register reports the key events in the

order of lowest encoding value to the highest (see

_______

PP0~PP7

Output

Dirver

Table 5). The INT will remain low until all of the key

events are read, with one exception: When the

_______

Auto-Clear INT is enabled, if all of the key event data

_______

is not read before the programmed time, the INT will

return high after the programmed time. However the

temporary key status registers will remain unchanged

and the key event data may continue to be read until

another key event is detected.

GND

Figure 8 Output Port Structure

DEBOUNCE

When the bit SD of the Configuration Register (08h) is

set to “0” and there is a change of the state of the

keypad, the keypad scans first and stores the data in

temporary registers, then waits for about 6ms (3ms)

and scans again, then waits for another 8ms (4ms) and

scans a final time. If the results are the same, the data

is latched into the temporary key status registers and

_______

the INT asserted. Otherwise, the scan is halted and

Figure 9 Input Port Structure

the device returns to standby mode. No data is latched

_______

into the temporary key status registers and the INTis

not asserted.

POWER-ON RESET

LONG-PRESSED KEY DETECT

The IS31IO7326 contains an integral power-on-reset

circuit that ensures all registers are reset to a known

state on power-up. When V_CCrises above 2.4V, the

circuit releases the registers and the I2C interface for

When the bit LE of the Configuration Register (08h) is

set to “0”, this function is disabled. When LE is set to

“1”, this function is enabled. When a key is pressed for

normal operation. When V_CCdrops to less than V_POR

the IS31IO7326 resets all register contents to the

default value.

a long period of time, the chip automatically scans

_______

again after the INT is deasserted. When the key is still

_______

________

pressed, the INT asserts again and the key event is

latched into the temporary key status registers. The

RST I2C RESET CONTROL

________

scanning continues until all of the keys are released.

_______

The active-low RST input voids any I2C transaction

The delay time between the INT deasserting to the

next scan beginning is set by the Configuration

involving the IS31IO7326, forcing the IS31IO7326 into

the I2C STOP condition. A reset does not affect the

interrupt output.

_______

STANDBY MODE

KEY EVENT INTERRUPT (INT)

When the serial interface is idle, the IS31IO7326

automatically enters standby mode, drawing minimal

supply current.

Once there is key event code latched in the temporary

key status registers, the device produces an interrupt

_______

signal to the MCU on the INT pin. When the INT is

asserted, any keypad state changes are ignored. The

KEYPAD AUTO SCAN

_______

INT will remain low until all of the key events are read,

The IS31IO7326 can support an 8×8 matrix keypad

scan. The 8 input ports (OD ports) need a 100kΩ

pull-up resistor for each column, the 8 output ports (PP

ports) for the rows pull low in standby mode.

_______

with one exception: When the Auto-Clear INT is

enabled, if all of the key event data is not read before

_______

the programmed time, the INT will return high after

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Rev.A, 12/19/2011

IS31IO7326

the programmed time. However the temporary key

status registers will remain unchanged and the key

event data may continue to be read until another key

event is detected. After all of the key events have been

read, the device returns to standby mode waiting for

the next scan.

THE INPUT PORT FILTER

The bit DE of the Configuration Register (08h) is used

to enable the input port filter. When DE is set to “0”, the

input port filter is disabled, and the chip responds to

any changes at the input port. When DE is set to “1”,

the input port filter is enabled and any glitch shorter

than 100ns is filtered. If the input pulse width is greater

than 100ns, the chip responds (Figure 10).

_______

AUTO-CLEAR INT FUNCTION

When the ACI bits of the Configuration Register (08h)

are set to “01” or “10”, this function is enabled. Setting

the ACI bits to “00” disables the function. When

_______

enabled, the INT would be cleared in 5ms or 10ms

after it asserts if there is no read of the Key Status

_______

registers does not change when the INT goes low. The

Key Status Register can be read regardless of whether

_______

the INT is high or not. However, when the INT is

cleared and there is new key event activity before the

old key event data is read, the temporary key status

_______

Figure 10 Input port debounce function

registers are rewritten and the INT asserts again. In

this case, the previous key event data is lost and only

the new key event(s) can be read.

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Rev.A, 12/19/2011

IS31IO7326

CLASSIFICATION REFLOW PROFILES

Profile Feature

Pb-Free Assembly

Preheat & Soak

150°C

Temperature min (Tsmin)

Temperature max (Tsmax)

Time (Tsmin to Tsmax) (ts)

200°C

60-120 seconds

Average ramp-up rate (Tsmax to Tp)

3°C/second max.

Liquidous temperature (TL)

Time at liquidous (tL)

217°C

60-150 seconds

Peak package body temperature (Tp)*

Max 260°C

Time (tp)** within 5°C of the specified

classification temperature (Tc)

Max 30 seconds

Average ramp-down rate (Tp to Tsmax)

Time 25°C to peak temperature

6°C/second max.

8 minutes max.

Figure 11 Classification profile

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Rev.A, 12/19/2011

IS31IO7326

TAPE AND REEL INFORMATION

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326

PACKAGE INFORMATION

QFN-24

Note: All dimensions in millimeters unless otherwise stated.

Integrated Silicon Solution, Inc. – www.issi.com

Rev.A, 12/19/2011

IS31IO7326 [ISSI]

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