IS41C16105-60TLI [ISSI]
Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50/44;
| 型号： | IS41C16105-60TLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50/44 存储 内存集成电路 光电二极管 动态存储器 |
| 文件： | 总18页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS41C16105
IS41LV16105
1M x 16 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
ISSI
FEBRUARY 2000
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs; tristate I/O
The ISSI IS41C16105 and IS41LV16105 are 1,048,576 x
16-bithigh-performanceCMOS DynamicRandomAccessMemo-
ries. FastPageModeallows1,024randomaccesseswithinasingle
row with access cycle time as short as 20 ns per 16-bit word. The
ByteWritecontrol,ofupperandlowerbyte,makestheIS41C16105
ideal for use in 16-, 32-bit wide data bus systems.
• RefreshInterval:
— 1,024 cycles/16 ms
• Refresh Mode:
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
These features make the IS41C16105 and IS41LV16105 ideally
suitedforhigh-bandwidthgraphics,digitalsignalprocessing,high-
performancecomputingsystems,andperipheralapplications.
• JEDEC standard pinout
• Single power supply:
— 5V 10ꢀ (IS41C16105)
— 3.3V 10ꢀ (IS41LV16105)
The IS41C16105 and IS41LV16105 are packaged in a
42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II).
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30oC to 85oC
• Industrail Temperature Range -40oC to 85oC
KEY TIMING PARAMETERS
Parameter
-50
50
13
25
20
84
-60
60
Unit
ns
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
15
ns
PIN CONFIGURATIONS
30
ns
44(50)-Pin TSOP (Type II)
42-PinSOJ
25
ns
104
ns
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
44
43
42
41
40
39
38
37
36
35
34
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
2
2
3
3
4
4
5
5
PIN DESCRIPTIONS
6
6
7
7
8
A0-A9
I/O0-15
WE
Address Inputs
8
9
9
10
11
I/O8
Data Inputs/Outputs
Write Enable
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
OE
Output Enable
LCAS
UCAS
OE
WE
RAS
NC
RAS
UCAS
LCAS
Vcc
Row Address Strobe
A9
A9
Upper Column Address Strobe
Lower Column Address Strobe
Power
NC
A8
A8
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
GND
NC
Ground
VCC
GND
VCC
GND
No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
TRUTHTABLE
Function
RAS
H
LCAS UCAS
WE
X
OE
X
Addresst
R
/tC
I/O
High-Z
Standby
H
L
L
H
L
X
Read:Word
Read:LowerByte
L
H
L
ROW/COL
ROW/COL
D
OUT
L
H
H
L
LowerByte, DOUT
UpperByte,High-Z
Read:UpperByte
L
H
L
H
L
ROW/COL
LowerByte,High-Z
UpperByte, DOUT
Write:Word(EarlyWrite)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
D
IN
Write:LowerByte(EarlyWrite)
H
LowerByte,DIN
UpperByte,High-Z
Write:UpperByte(EarlyWrite)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
LowerByte,High-Z
UpperByte,DIN
H→L
L→H
D
OUT, DIN
HiddenRefresh
Read(2)
L→H→L
L→H→L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
D
D
OUT
OUT
Write(1,3)
RAS-OnlyRefresh
CBRRefresh(4)
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H→L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
Functional Description
Write Cycle
The IS41C16105 and IS41LV16105 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressedthroughthe16addressbits. Theseareentered
ten bits (A0-A9) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
nine bits.
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
The IS41C16105 and IS41LV16105 has two CAS con-
trols, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
TheIS41C16105andIS41LV16105CASfunctionisdeter-
mined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16105 and IS41LV16105 both
BYTE READ and BYTE WRITE cycle capabilities.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
Memory Cycle
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci-
fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
IOUT
PD
Output Current
50
1
mA
W
Power Dissipation
TA
Commercial Operation Temperature
Extended Temperature
Industrail Temperature
0 to +70
–30 to +85
–40 to +85
°C
°C
°C
TSTG
Storage Temperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
Input Low Voltage
5V
3.3V
2.4
2.0
—
—
VCC + 1.0
VCC + 0.3
V
V
5V
3.3V
–1.0
–0.3
—
—
0.8
0.8
Commercial Ambient Temperature
Extended Ambient Temperature
Industrail Ambient Temperature
0
–30
–40
—
—
—
70
85
85
°C
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Input Capacitance: A0-A9
Max.
Unit
pF
CIN1
5
7
7
CIN2
CIO
Input Capacitance: RAS, UCAS, LCAS, WE, OE
pF
Data Input/Output Capacitance: I/O0-I/O15
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz,
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
ELECTRICALCHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
–5
–5
2.4
—
5
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
5
µA
V
VOH
VOL
ICC1
IOH = –5.0 mA (5V)
IOH = –2.0 mA (3.3V)
—
0.4
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
V
RAS, LCAS, UCAS ≥ VIH
Commerical
5V
3.3V
5V
—
—
—
—
3
3
4
4
mA
mA
Extended/Idustrial
RAS, LCAS, UCAS ≥ VCC – 0.2V
RAS, LCAS, UCAS,
3.3V
ICC2
ICC3
Standby Current: CMOS
5V
3.3V
—
—
2
2
mA
mA
Operating Current:
-50
-60
—
—
160
145
Random Read/Write(2,3,4)
AveragePowerSupplyCurrent
Address Cycling, tRC = tRC (min.)
ICC4
ICC5
Operating Current:
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
—
—
90
80
mA
mA
mA
Fast Page Mode(2,3,4)
AveragePowerSupplyCurrent
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
160
145
RAS-Only(2,3)
AveragePowerSupplyCurrent
ICC6
Refresh Current:
CBR(2,3,5)
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
—
—
160
145
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
ACCHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
84
—
—
—
50
30
8
—
50
13
25
10K
—
104
—
—
—
60
40
10
9
—
60
15
30
10K
—
tRAC
tCAC
tAA
tRAS
tRP
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
tCAS
tCP
10K
—
10K
—
9
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
38
12
0
—
40
14
0
—
37
—
45
—
8
—
10
0
—
0
—
—
8
—
10
40
—
Column-Address Hold Time
30
—
—
(referenced to RAS)
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
10
25
5
25
—
—
—
—
—
—
15
13
—
—
—
—
—
—
12
30
5
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
37
0
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
37
0
5
5
3
3
tOE
Output Enable Time(15, 16)
—
20
5
—
20
5
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
5
10
5
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
0
0
Read Command Hold Time
0
0
(referenced to RAS)(12)
tRCH
tWCH
Read Command Hold Time
0
8
—
—
0
—
—
ns
ns
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Units
tWCR
Write Command Hold Time
40
—
50
—
ns
(referenced to RAS)(17)
tWP
Write Command Pulse Width(17)
8
10
13
8
—
—
—
—
—
—
—
10
10
15
10
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tWPZ
tRWL
tCWL
tWCS
tDHR
tACH
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
0
39
15
39
15
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
8
—
10
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
Fast Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width
50
—
56
5
100K
30
60
—
68
5
100K
35
ns
ns
ns
ns
ns
Access Time from CAS Precharge(15)
READ-WRITE Cycle Time(24)
Data Output Hold after CAS LOW
tPRWC
tCOH
tOFF
—
—
—
—
Output Buffer Turn-Off Delay from
1.6
12
1.6
15
CAS or RAS(13,15,19, 29)
tWHZ
Output Disable Delay from WE
3
10
3
10
ns
ns
tCLCH
Last CAS going LOW to First CAS
10
—
10
—
returning HIGH(23)
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
5
8
0
—
—
—
5
10
0
—
—
—
ns
ns
ns
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
tT
Auto Refresh Period (1,024 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
16
50
—
16
50
ms
ns
1
1
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V 10ꢀ)
One TTL Load and 50 pF (Vcc = 3.3V 10ꢀ)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V 10ꢀ);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V 10ꢀ)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V 10ꢀ, 3.3V 10ꢀ)
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonicmanner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. AssumesthattRCD - tRCD (MAX). IftRCD isgreaterthanthemaximumrecommendedvalueshowninthistable, tRAC willincreasebythe
amount that tRCD exceeds the value shown.
8. Assumes that tRCD • tRCD (MAX).
9. IfCASisLOWatthefallingedgeof RAS, dataoutwillbemaintainedfromthepreviouscycle. Toinitiateanewcycleandclearthedata
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS
(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.IftRWD •tRWD (MIN),
tAWD •tAWD (MIN)andtCWD •tCWD (MIN), thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindatareadfromtheselected
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. IfOE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtOD andtOEH met(OEHIGHduringWRITEcycle)inordertoensure
thattheoutputbufferswillbeopenduringtheWRITEcycle. TheI/OswillprovidethepreviouslywrittendataifCASremainsLOWand
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
FAST-PAGE-MODE READ CYCLE
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLC
t
Open
Open
Valid Data
I/O
OE
tOE
tOD
t
OES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tCAS
tPRWC
tCAS
tRSH
tCAS
tCRP
tRCD
tAR
tCRP
tCP
tCP
UCAS/LCAS
ADDRESS
tCPWD
tRAL
tCPWD
tRAD
tCAH
tCAH
tCAH
tRAH
tASR
tASC
tASC
tASC
Row
Column
Column
Column
tCWL
tRWD
tCWL
tRWL
tCWL
tAWD
tCWD
tAWD
tCWD
tAWD
tCWD
tRCS
tWP
tWP
tWP
WE
OE
tAA
tAA
tCAC
tAA
tCAC
tCAC
tOEA
tOEA
tOEA
tOEZ
tOEZ
tOED
tOEZ
tOED
tRAC
tCLZ
tOED
tDH
tDH
tDH
tDS tCLZ
tDS
tCLZ
OUT
tDS
I/O0-I/O15
OUT
IN
IN
IN
OUT
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tRSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
tASC
ADDRESS
Row
Column
Row
t
CWL
RWL
t
tWCR
tWCS
tWCH
tWP
WE
I/O
t
t
DHR
tDH
DS
Valid Data
Don’t Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tRSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
tRAL
t
t
RAH
tCAH
tASC
tACH
ADDRESS
WE
Row
Column
Row
tRWD
tCWL
tRCS
t
CWD
t
RWL
t
AWD
t
WP
tAA
tRAC
tCAC
tCLZ
tDS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
tOD
tOEH
tOE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
FAST PAGE MODE EARLY WRITE CYCLE
tRASP
tRP
RAS
tRHCP
tRSH
tCAS
tCSH
tCAS
tPC
tCAS
tCRP
tRCD
tAR
tCRP
tCP
tCP
UCAS/LCAS
ADDRESS
tRAL
tRAD
tCAH
tCAH
tCAH
tRAH
tASR
tASC
tASC
tASC
Row
Column
Column
Column
tCWL
tWCH
tCWL
tWCH
tCWL
tWCH
tWCS
tWCS
tWCS
tWP
tWP
tWP
WE
OE
tWCR
tDHR
tDS
tDS
tDS
tDH
tDH
tDH
Valid DIN
Valid DIN
Valid DIN
I/O0-I/O15
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tASC
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tRAH
tASR
tCAH
tRCH
tASC
tRCS
ADDRESS
WE
Row
Column
Column
tRCS
tAA
tRAC
tCAC
tCLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
OE
tOE
tOD
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
tCRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
I/O
Open
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
t
CRP
t
RCD
t
RSH
tCHR
UCAS/LCAS
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
ORDERING INFORMATION : 5V
Commercial Range: 0⋅C to 70⋅C
Speed (ns) Order Part No.
Package
50
IS41C16105-50K 400-mil SOJ
IS41C16105-50T 400-mil TSOP (Type II)
60
IS41C16105-60K 400-mil SOJ
IS41C16105-60T 400-mil TSOP (Type II)
Extended Range: -30⋅C to 85⋅C
Speed (ns) Order Part No.
Package
50
IS41C16105-50KE 400-mil SOJ
IS41C16105-50TE 400-mil TSOP (Type II)
60
IS41C16105-60KE 400-mil SOJ
IS41C16105-60TE 400-mil TSOP (Type II)
Industrial Range: -40⋅C to 85⋅C
Speed (ns) Order Part No.
Package
50
IS41C16105-50KI 400-mil SOJ
IS41C16105-50TI 400-mil TSOP (Type II)
60
IS41C16105-60KI 400-mil SOJ
IS41C16105-60TI 400-mil TSOP (Type II)
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. A
03/03/00
IS41C16105
IS41LV16105
®
ISSI
ORDERING INFORMATION : 3.3V
Commercial Range: 0⋅C to 70⋅C
Speed (ns) Order Part No.
Package
50
IS41LV16105-50K 400-mil SOJ
IS41LV16105-50T 400-mil TSOP (Type II)
60
IS41LV16105-60K 400-mil SOJ
IS41LV16105-60T 400-mil TSOP (Type II)
Extended Range: -30⋅C to 85⋅C
Speed (ns) Order Part No.
Package
50
IS41LV16105-50KE 400-mil SOJ
IS41LV16105-50TE 400-mil TSOP (Type II)
60
IS41LV16105-60KE 400-mil SOJ
IS41LV16105-60TE 400-mil TSOP (Type II)
Industrial Range: -40⋅C to 85⋅C
Speed (ns) Order Part No.
Package
50
IS41LV16105-50KI 400-mil SOJ
IS41LV16105-50TI 400-mil TSOP (Type II)
60
IS41LV16105-60KI 400-mil SOJ
IS41LV16105-60TI 400-mil TSOP (Type II)
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
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