IS41C16256-25T-TR [ISSI]
DRAM;
| 型号： | IS41C16256-25T-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | DRAM 动态存储器 |
| 文件： | 总22页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS41C16256
IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI
NOVEMBER 2005
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs
TheISSI ISꢁ1C1ꢂ25ꢂandISꢁ1LV1ꢂ25ꢂare2ꢂ2,1ꢁꢁx1ꢂ-bit
high-performanceCMOSDynamicRandomAccessMemory. Both
productsofferacceleratedcycleaccessEDOPageMode. EDO
PageModeallows512randomaccesseswithinasinglerowwith
accesscycletimeasshortas10nsper1ꢂ-bitword.TheByteWrite
control, of upper and lower byte, makes the ISꢁ1C1ꢂ25ꢂ and
ISꢁ1LV1ꢂ25ꢂidealforusein1ꢂand32-bitwidedatabussystems.
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
andHidden
• JEDECstandardpinout
• Singlepowersupply
5V 10ꢀ (ISꢁ1C1ꢂ25ꢂ)
ThesefeaturesmaketheISꢁ1C1ꢂ25ꢂandISꢁ1LV1ꢂ2ꢂ ideally
suited for high band-width graphics, digital signal processing,
high-performancecomputingsystems,andperipheralapplications.
3.3V 10ꢀ (ISꢁ1LV1ꢂ25ꢂ)
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30oC to 85oC
• Industrial Temperature Range -ꢁ0oC to 85oC
The ISꢁ1C1ꢂ25ꢂ and IS41LV16256 are packaged in ꢁ0-pin
ꢁ00-mil SOJ and TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
-25
-35
-50
-60
Unit
(5V only)
Max. RAS Access Time (tRAC)
25
35
10
18
12
ꢂ0
50
1ꢁ
25
20
90
ꢂ0
15
ns
ns
ns
ns
ns
Max. CAS Access Time (tCAC)
10
12
10
ꢁ5
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
30
25
110
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
40
39
38
37
36
35
34
33
32
31
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
2
2
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
PIN DESCRIPTIONS
3
3
4
4
A0-A8 Address Inputs
5
5
6
I/O0-15 Data Inputs/Outputs
6
7
7
WE
Write Enable
8
8
9
OE
Output Enable
9
10
I/O8
10
11
12
13
14
15
16
17
18
19
20
RAS
UCAS
LCAS
Vcc
Row Address Strobe
UpperColumnAddressStrobe
LowerColumnAddressStrobe
Power
NC
NC
WE
RAS
NC
A0
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
NC
LCAS
UCAS
OE
LCAS
UCAS
OE
WE
RAS
NC
A8
A8
A0
A7
A7
GND
NC
Ground
A1
A6
A1
A6
No Connection
A2
A5
A2
A5
A3
A4
A3
A4
VCC
GND
VCC
GND
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
262,144 x 16
ADDRESS
BUFFERS
A0-A8
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
TRUTHTABLE
Function
RAS
LCAS UCAS WE
OE Address tR/tC I/O
Standby
H
L
L
H
L
L
H
L
X
H
H
X
L
L
X
High-Z
Read: Word
Read: Lower Byte
ROW/COL
ROW/COL
DOUT
H
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
DIN
Write: Lower Byte (Early Write)
H
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
H→L L→H
DOUT, DIN
EDO Page-Mode Read(2) 1st Cycle:
2nd Cycle:
L
L
L
H→L H→L
H→L H→L
L→H L→H
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
DOUT
DOUT
DOUT
Any Cycle:
EDO Page-Mode Write(1) 1st Cycle:
2nd Cycle:
L
L
H→L H→L
H→L H→L
L
L
X
X
ROW/COL
NA/COL
DIN
DIN
EDO Page-Mode
Read-Write(1,2)
1st Cycle:
2nd Cycle:
L
L
H→L H→L H→L L→H
H→L H→L H→L L→H
ROW/COL
NA/COL
DOUT, DIN
DOUT, DIN
Hidden Refresh2)
Read L→H→L
Write L→H→L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
DOUT
DOUT
RAS-Only Refresh
CBR Refresh(3)
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H→L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
Functional Description
Refresh Cycle
The ISꢁ1C1ꢂ25ꢂ and ISꢁ1LV1ꢂ25ꢂ is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered nine bits (A0-A8) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first nine bits and CAS is used the
latter nine bits.
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. Byclockingeachofthe512rowaddresses(A0through
A8) withRAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
The ISꢁ1C1ꢂ25ꢂ and ISꢁ1LV1ꢂ25ꢂ has two CAS con-
trols, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 25ꢂK x
1ꢂ DRAMs. The key difference is that each CAS controls
its corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
The ISꢁ1C1ꢂ25ꢂ and ISꢁ1LV1ꢂ25ꢂ CAS function is
determinedbythefirstCAS(LCASorUCAS)transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the ISꢁ1C1ꢂ25ꢂ both BYTE READ and
BYTE WRITE cycle capabilities.
EDOpagemodeoperationpermitsall512columnswithin
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
InEDOpagemode,duetotheextendeddatafunction,the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci-
fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RASsignal).
Write Cycle
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
ꢁ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
-0.5 to ꢁ.ꢂ
V
V
VCC
Supply Voltage
5V
3.3V
–1.0 to +7.0
-0.5 to ꢁ.ꢂ
V
V
IOUT
PD
Output Current
Power Dissipation
50
1
mA
W
TA
CommercialTemperature
ExtendedTemperature
IndustrialTemperature
0 to +70
–30 to +85
–ꢁ0 to +85
°C
°C
°C
TSTG
StorageTemperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
SupplyVoltage
5V
3.3V
ꢁ.5
3.0
5.0
3.3
5.5
3.ꢂ
V
VIH
VIL
TA
Input High Voltage
Input Low Voltage
5V
3.3V
5V
3.3V
2.ꢁ
2.0
–1.0
–0.3
0
–30
–ꢁ0
—
—
—
—
—
—
—
VCC + 1.0
VCC + 0.3
V
V
0.8
0.8
70
85
85
CommercialAmbientTemperature
ExtendedAmbientTemperature
IndustrialAmbientTemperature
°C
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Input Capacitance: A0-A8
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Max.
Unit
CIN1
CIN2
CIO
5
7
7
pF
pF
pF
Data Input/Output Capacitance: I/O0-I/O15
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz,
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
ELECTRICALCHARACTERISTICS(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
InputLeakageCurrent
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
–10
10
µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
–10
10
µA
0V ≤ VOUT ≤ Vcc
VOH
VOL
ICC1
Output High Voltage Level
Output Low Voltage Level
Stand-byCurrent:TTL
IOH = –2.5 mA
2.ꢁ
—
—
V
V
IOL = +2.1 mA
0.ꢁ
RAS, LCAS, UCAS ≥ VIH Commercial 5V
—
—
—
—
2
3
1
2
mA
Industrial
Commercial 3V
5V
Industrial
RAS, LCAS, UCAS ≥ VCC – 0.2V
3V
ICC2
ICC3
Stand-byCurrent:CMOS
5V
3V
—
—
1
0.5
mA
mA
OperatingCurrent:
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-25
-35
-50
-ꢂ0
—
—
—
—
2ꢂ0
230
180
170
RandomRead/Write(2,3,ꢁ)
Average Power Supply Current
ICCꢁ
ICC5
OperatingCurrent:
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-25
-35
-50
-ꢂ0
—
—
—
—
250
220
170
1ꢂ0
mA
mA
mA
EDOPageMode(2,3,ꢁ)
Average Power Supply Current
RefreshCurrent:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-25
-35
-50
-ꢂ0
—
—
—
—
2ꢂ0
230
180
170
RAS-Only(2,3)
Average Power Supply Current
ICCꢂ
RefreshCurrent:
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-25
-35
-50
-ꢂ0
—
—
—
—
2ꢂ0
230
180
170
CBR(2,3,5)
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
ꢁ. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
ꢂ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
ACCHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25
-35
-50
-60
Min. Max. Units
Symbol Parameter
Min. Max.
Min. Max
Min. Max.
t
RC
RAC
CAC
AA
RAS
RP
CAS
CP
CSH
RCD
ASR
RAH
ASC
CAH
AR
Random READ or WRITE Cycle Time
Access Time from RAS(ꢂ, 7)
Access Time from CAS(ꢂ, 8, 15)
Access Time from Column-Address(ꢂ)
RAS Pulse Width
ꢁ5
—
—
—
25
15
ꢁ
—
25
10
12
10K
—
ꢂ0
—
—
—
35
20
ꢂ
—
35
10
18
10K
—
90
—
—
—
50
30
8
—
50
1ꢁ
25
10K
—
110
—
—
—
ꢂ0
ꢁ0
10
10
ꢂ0
20
0
—
ꢂ0
15
30
10K
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
RAS Precharge Time
CAS Pulse Width(2ꢂ)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
t
10K
—
10K
—
10K
—
10K
—
t
ꢁ
5
8
t
25
10
0
—
35
11
0
—
50
19
0
—
—
t
17
—
28
—
3ꢂ
—
ꢁ5
—
t
t
ꢂ
—
ꢂ
—
8
—
10
0
—
t
0
—
0
—
0
—
—
t
5
—
ꢂ
—
8
—
10
ꢁ0
—
t
Column-Address Hold Time
19
—
30
—
ꢁ0
—
—
(referenced to RAS)
t
RAD
RAL
RPC
RSH
CLZ
CRP
OD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
8
12
0
20
—
—
—
—
—
12
8
10
18
0
20
—
—
—
—
—
12
10
—
—
—
—
—
1ꢁ
25
0
25
—
—
—
—
—
12
15
—
—
—
—
—
15
30
0
30
—
—
—
—
—
12
15
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
7
8
1ꢁ
3
15
3
t
3
3
t
5
5
5
5
t
2
3
3
3
t
OE /tOEA Output Enable Time(15, 1ꢂ)
0
0
0
—
10
10
5
t
OEHC
OEP
OES
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
10
5
—
—
—
—
—
10
10
5
10
10
5
t
t
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
tRCS
0
0
0
0
t
RRH
RCH
Read Command Hold Time
0
0
0
0
(referenced to RAS)(12)
t
Read Command Hold Time
0
—
0
—
0
—
0
—
ns
(referenced to CAS)(12, 17, 21)
t
WCH
WCR
Write Command Hold Time(17, 27)
5
—
—
5
—
—
8
—
—
10
50
—
—
ns
ns
t
Write Command Hold Time
19
30
ꢁ0
(referenced to RAS)(17)
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25
-35
-50
-60
Min. Max. Units
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
t
WP
WPZ
RWL
CWL
Write Command Pulse Width(17)
5
10
7
—
—
—
—
—
5
10
8
—
—
—
—
—
8
—
—
—
—
—
10
10
15
15
0
—
—
—
—
—
ns
ns
ns
ns
ns
t
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(1ꢁ, 17, 20)
10
1ꢁ
1ꢁ
0
t
t
5
8
tWCS
0
0
t
DHR
Data-in Hold Time (referenced to RAS)
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
19
15
—
—
30
15
—
—
ꢁ0
15
—
—
ꢁ0
15
—
—
ns
ns
tACH
tOEH
OE Hold Time from WE during
5
—
8
—
8
—
15
—
ns
READ-MODIFY-WRITE cycle(18)
t
DS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
5
—
—
—
—
0
ꢂ
—
—
—
—
0
ꢂ
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
t
t
t
DH
10
RWC
RWD
READ-MODIFY-WRITE Cycle Time
ꢂ5
35
80
ꢁ5
100
50
1ꢁ0
80
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(1ꢁ)
t
CWD
AWD
CAS to WE Delay Time(1ꢁ, 20)
Column-Address to WE Delay Time(1ꢁ)
17
21
10
—
—
—
25
30
12
—
—
—
30
30
15
—
—
—
3ꢂ
ꢁ9
25
—
—
—
ns
ns
ns
t
tPC
EDO Page Mode READ or WRITE
Cycle Time(2ꢁ)
t
RASP
CPA
PRWC
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
25 100K
35 100K
ꢁ0 100K
ꢂ0 100K
ns
ns
ns
t
—
1ꢁ
—
—
21
—
—
27
—
—
3ꢁ
—
t
EDO Page Mode READ-WRITE
Cycle Time(2ꢁ)
32
ꢁ0
ꢁ5
5ꢂ
t
COH /tDOH Data Output Hold after CAS LOW
5
3
—
5
3
—
5
3
—
5
3
—
ns
ns
tOFF
Output Buffer Turn-Off Delay from
15
15
15
15
CAS or RAS(13,15,19, 29)
t
t
WHZ
Output Disable Delay from WE
3
15
—
3
15
—
3
15
—
3
15
—
ns
ns
CLCH
Last CAS going LOW to First CAS
10
10
10
10
returning HIGH(23)
t
CSR
CHR
ORD
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
5
7
0
—
—
—
8
8
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
t
t
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
t
REF
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
1
8
—
1
8
—
1
8
—
1
8
ms
ns
tT
50
50
50
50
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in
amonotonicmanner.
ꢁ. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
ꢂ. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCD exceeds the value shown.
8. Assumes that tRCD • tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
1ꢁ. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS •
tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD •
tRWD (MIN), tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled)
cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
1ꢂ. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to
ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS
remains LOW and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or
READ-MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
2ꢁ. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
2ꢂ. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
READCYCLE
tRC
t
RAS
t
RP
RAS
tCSH
tRSH
tRRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
tRAL
t
t
RAH
tCAH
tASC
ADDRESS
WE
Row
Column
Row
tRCS
tRCH
tAA
tRAC
(1)
tOFF
tCAC
t
CLC
Open
Open
Valid Data
I/O
OE
tOE
tOD
tOES
Don't Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
tASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
tWCS
tWCH
tWP
WE
I/O
t
t
DHR
tDH
DS
Valid Data
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
t
RAL
ACH
t
t
RAH
tCAH
t
ASC
t
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Don't Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
(1)
tPC
tCSH
tRSH
tCRP
tRCD
t
CAS,
tCP
t
CAS,
tCP
t
CAS,
tCP
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
tAR
tRAD
tRAL
tASR
tASC
tCAH
tASC
tCAH
tASC
tCAH
ADDRESS
WE
Row
Column
Column
Column
Row
t
RAH
tRRH
tRCS
tRCH
tAA
tAA
tAA
t
RAC
CAC
CLZ
tCPA
tCPA
t
t
t
CAC
t
t
CAC
tCOH
CLZ
tOFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
OE
t
OE
t
OEHC
tOE
t
OD
tOES
tOD
tOES
tOEP
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PC
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
tACH
t
ACH
t
ACH
CAH
t
RAD
t
RAL
t
ASR
t
ASC
t
CAH
t
ASC
t
t
ASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
t
RAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
t
WCS
t
t
WCH
tWCH
t
WP
t
WP
t
WP
WE
t
WCR
DHR
tRWL
t
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
Valid Data
Valid Data
Valid Data
OE
Don't Care
1ꢁ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
(1)
tPC / tPRWC
tCSH
tRSH
tCRP
tRCD
tCAS,
tCLCH
tCP
tCAS,
tCLCH
tCP
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tASR
tRAD
tRAL
tASC
tCAH
tASC
tCAH
tASC
tCAH
tRAH
ADDRESS
Row
Column
Column
Column
Row
t
RWD
t
RWL
CWL
WP
tRCS
t
CWL
t
CWL
t
tWP
tWP
t
tAWD
tAWD
tAWD
tCWD
tCWD
tCWD
WE
tAA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
tDS
t
t
t
CAC
CLZ
t
t
CAC
CLZ
t
t
CAC
CLZ
t
Open
Open
I/O
OE
D
OUT
D
t
IN
D
OUT
D
IN
D
OUT
D
IN
OD
tOD
t
OD
tOE
tOE
tOE
tOEH
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
t
RASP
t
RP
RAS
t
CSH
t
PC
tPC
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
UCAS/LCAS
t
AR
t
ACH
RAL
CAH
t
ASR
t
t
RAD
t
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
RAH
ADDRESS
WE
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
CAC
t
t
t
t
DS
tDH
Open
Open
I/O
OE
Valid Data (A)
Valid Data (B)
DIN
t
OE
Don't Care
1ꢂ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
t
CRP
ASR
t
RCD
tCP
tCAS
UCAS/LCAS
tAR
t
RAD
t
t
RAH
tCAH
tASC
tASC
ADDRESS
WE
Row
Column
Column
tRCS
tRCH
tRCS
tAA
tRAC
tCAC
tCLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
OE
tOE
tOD
Don't Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
I/O
Open
HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)(1)
tRAS
tRAS
tRP
RAS
tCRP
tRCD
t
RSH
tCHR
UCAS/LCAS
tAR
tRAD
t
RAL
tASR
tRAH
tCAH
tASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
tOFF
tCAC
tCLZ
Open
Open
Valid Data
I/O
OE
tOE
tOD
tORD
Don't Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
IS41C16256
IS41LV16256
®
ISSI
ORDERING INFORMATION : 5V
Commercial Range: 0oC to 70oC
Speed (ns) Order Part No.
Package
25
35
ꢂ0
ISꢁ1C1ꢂ25ꢂ-25K
ISꢁ1C1ꢂ25ꢂ-25T
ꢁ00-mil SOJ
ꢁ00-mil TSOP (Type II)
ISꢁ1C1ꢂ25ꢂ-35K
ISꢁ1C1ꢂ25ꢂ-35T
ꢁ00-mil SOJ
ꢁ00-mil TSOP (Type II)
ISꢁ1C1ꢂ25ꢂ-ꢂ0K
ISꢁ1C1ꢂ25ꢂ-ꢂ0T
ꢁ00-mil SOJ
ꢁ00-mil TSOP (Type II)
ORDERING INFORMATION : 3.3V
Commercial Range: 0oC to 70oC
Speed (ns) Order Part No.
Package
35
ISꢁ1LV1ꢂ25ꢂ-35K
ISꢁ1LV1ꢂ25ꢂ-35T
ꢁ00-mil SOJ
ꢁ00-mil TSOP (Type II)
ꢂ0
ISꢁ1LV1ꢂ25ꢂ-ꢂ0K
ISꢁ1LV1ꢂ25ꢂ-ꢂ0T
ꢁ00-milSOJ
ꢁ00-mil TSOP (Type II)
ORDERING INFORMATION : 5V
Industrial Range: -40oC to 85oC
Speed (ns) Order Part No.
Package
50
ISꢁ1C1ꢂ25ꢂ-50KI
ISꢁ1C1ꢂ25ꢂ-50TI
ꢁ00-milSOJ
ꢁ00-mil TSOP (Type II)
ꢂ0
ISꢁ1C1ꢂ25ꢂ-ꢂ0KI
ISꢁ1C1ꢂ25ꢂ-ꢂ0TI
ꢁ00-milSOJ
ꢁ00-mil TSOP (Type II)
ORDERING INFORMATION : 3.3V
Industrial Range: -40oC to 85oC
Speed (ns) Order Part No.
Package
ꢂ0
ISꢁ1LV1ꢂ25ꢂ-ꢂ0KI
ISꢁ1LV1ꢂ25ꢂ-ꢂ0TI
ꢁ00-milSOJ
ꢁ00-mil TSOP (Type II)
Integrated Silicon Solution, Inc. — 1-800-379-4774
19
Rev. K
10/28/05
®
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
ISSI
Notes:
1. Controlling dimension:
millimeters.
N
N/2+1
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
E1
E
1
N/2
SEATING PLANE
D
A
b
C
A2
e
B
A1
E2
Millimeters
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
No. Leads (N)
28
32
36
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
18.29 18.54
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.720 0.730
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
®
PACKAGING INFORMATION
ISSI
Millimeters
Symbol Min Max
No. Leads (N)
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Min Max
Inches
Min Max
Min
Max
40
42
44
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
25.91 26.16
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.020 1.030
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and should be measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
L
α
e
b
c
A1
Plastic TSOP (T - Type II) (MS 25)
Plastic TSOP (T - Type II) (MS 24)
Millimeters Inches
Min Max
Plastic TSOP (T - Type II) (MS 24)
Millimeters Inches
Min Max
Millimeters
Inches
Min Max
Symbol Min
Max
Symbol Min
Max
Symbol Min
Max
Ref. Std.
Ref. Std.
Ref. Std.
N
A
A1
b
c
D
24/26
N
A
A1
b
c
D
40/44
N
A
A1
b
c
D
44/50
1.20
0.05 0.15
0.30 0.51
0.12 0.21
0.0472
1.20
0.05 0.15
0.30 0.45
0.12 0.21
0.0472
1.20
0.05 0.15
0.30 0.45
0.12 0.21
0.0472
0.002 0.0059
0.012 0.0201
0.005 0.0083
0.670 0.6899
0.295 0.3051
0.050 BSC
0.002 0.0059
0.012 0.0157
0.005 0.0083
0.721 0.7287
0.396 0.4040
0.031 BSC
0.002 0.0059
0.012 0.0157
0.005 0.0083
0.821 0.8287
0.396 0.4040
0.031 BSC
17.01 17.27
7.49 7.75
1.27 BSC
18.31 18.51
10.06 10.26
0.80 BSC
20.85 21.05
10.06 10.26
0.80 BSC
E
E
E
1
e
1
1
e
e
E
L
α
9.02 9.42
0.40 0.60
0.462 0.4701
0.016 0.0236
E
L
α
11.56 11.96
0.40 0.60
0.455 0.4709
0.016 0.0236
E
L
α
11.56 11.96
0.40 0.60
0.455 0.4709
0.016 0.0236
0°
5°
0°
5°
0°
8°
0°
8°
0°
8°
0°
8°
Integrated Silicon Solution, Inc.
PK13197T40 Rev. C 08/013/99
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明