IS41C16256C_技术文档

IS41C16256C

IS41LV16256C

ADVANCED INFORMATION

APRIL 2010

256Kx16

4Mb DRAM WITH EDO PAGE MODE

DESCRIPTION

FEATURES

Theꢀ ISSI'sꢀ IS41C/LV16256Cꢀ isꢀ 262,144ꢀ xꢀ 16-bitꢀ high-per-

formanceꢀ CMOSꢀ Dynamicꢀ Randomꢀ Accessꢀ Memory.ꢀ Bothꢀ

productsꢀ offerꢀ acceleratedꢀ cycleꢀ accessꢀ EDOꢀ Pageꢀ Mode.ꢀ

EDOꢀPageꢀModeꢀallowsꢀ512ꢀrandomꢀaccessesꢀwithinꢀaꢀsingleꢀ

rowꢀwithꢀaccessꢀcycleꢀtimeꢀasꢀshortꢀasꢀ10nsꢀperꢀ16-bitꢀword.ꢀ

TheꢀByteꢀWriteꢀcontrol,ꢀofꢀupperꢀandꢀlowerꢀbyte,ꢀmakesꢀtheꢀ

IS41C/LV16256Cꢀidealꢀforꢀuseꢀinꢀ16ꢀandꢀ32-bitꢀwideꢀdataꢀbusꢀ

systems.

•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs

•ꢀ RefreshꢀInterval:ꢀꢀ512ꢀcycles/8ꢀms

•ꢀ RefreshꢀModeꢀ:ꢀꢀRAS-Only, CAS-before-RASꢀ(CBR),ꢀ

and Hidden

•ꢀ JEDECꢀstandardꢀpinout

•ꢀ Singleꢀpowerꢀsupply:ꢀꢀ

5Vꢀ±ꢀ10%ꢀ(IS41C16256C)

ꢀ

3.3Vꢀ±ꢀ10%ꢀ(IS41LV16256C)

Theseꢀ featuresꢀ makeꢀ theꢀ IS41C/LV16256Cꢀ ideally suited

for high band-width graphics, digital signal processing, high-

performance computing systems, and peripheral applications.

•ꢀ ByteꢀWriteꢀandꢀByteꢀReadꢀoperationꢀviaꢀꢀtwoꢀCAS

•ꢀ Lead-freeꢀavailable

TheꢀIS41C/LV16256Cꢀisꢀpackagedꢀinꢀ40-pinꢀ400-milꢀSOJꢀ

andꢀTSOPꢀ(TypeꢀII).

•ꢀ IndustrialꢀTemperatureꢀRangeꢀ-40°Cꢀtoꢀ+85°C

KEY TIMING PARAMETERS

Parameter

-35

-60

60ꢀ

15ꢀ

30ꢀ

25ꢀ

110

Unit

ns

Max.ꢀRASꢀAccessꢀTimeꢀ(tr a c )ꢀ

Max.ꢀCASꢀAccessꢀTimeꢀ(tc a c )ꢀ

Max.ꢀColumnꢀAddressꢀAccessꢀTimeꢀ(ta a )ꢀ

Min.ꢀEDOꢀPageꢀModeꢀCycleꢀTimeꢀ(tp c )ꢀ

Min.ꢀRead/WriteꢀCycleꢀTimeꢀ(tr c )ꢀ

35ꢀ

11ꢀ

18ꢀ

14ꢀ

60ꢀ

ns

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

1

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

PIN CONFIGURATIONS

40-Pin TSOP (Type II)

40-Pin SOJ

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

1

40

39

38

37

36

35

34

33

32

31

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

VDD

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

2

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

NC

2

3

4

5

6

7

8

9

10

I/O8

10

11

12

13

14

15

16

17

18

19

20

NC

WE

RAS

NC

A0

11

12

13

14

15

16

17

18

19

20

30

29

28

27

26

25

24

23

22

21

NC

LCAS

UCAS

OE

LCAS

UCAS

OE

WE

RAS

NC

A8

A0

A7

A1

A6

A1

A6

A2

A5

A2

A5

A3

A4

A3

A4

VDD

GND

VDD

GND

PIN DESCRIPTIONS

A0-A8ꢀ AddressꢀInputs

I/O0-15ꢀ DataꢀInputs/Outputs

WEꢀꢀ

WriteꢀEnable

OEꢀꢀ

OutputꢀEnable

RASꢀꢀ RowꢀAddressꢀStrobe

UCAS Upper Column Address Strobe

LCAS

Vd d

LowerꢀColumnꢀAddressꢀStrobe

Power

GNDꢀ

NC

Ground

No Connection

2

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

FUNCTIONAL BLOCK DIAGRAM

OE

WE

CONTROL

LOGICS

OE

CONTROL

LOGIC

CAS

CLOCK

GENERATOR

LCAS

UCAS

CAS

WE

DATA I/O BUS

RAS

CLOCK

RAS

GENERATOR

COLUMN DECODERS

SENSE AMPLIFIERS

REFRESH

COUNTER

I/O0-I/O15

MEMORY ARRAY

262,144 x 16

ADDRESS

BUFFERS

A0-A8

Integrated Silicon Solution, Inc.

3

Rev. 00A

04/09/2010

HiddenꢀRefresh²⁾ꢀ

Readꢀ

Writeꢀ

L→H→Lꢀ

Lꢀ

Hꢀ

Lꢀ

Xꢀ

ROW/COLꢀ

Do u t

IS41C16256C

IS41LV16256C

TRUTH TABLE

Function

RAS

H

LCAS UCAS

WE

X

OE

X

Address tR/tC I/O

Standby

H

X

High-Z

Read:ꢀWordꢀ

Read:ꢀLowerꢀByteꢀ

Lꢀ

Hꢀ

Lꢀ

ROW/COLꢀ

Do u t

Lꢀ

LowerꢀByte,ꢀDo u t

Upper Byte, High-Z

Read:ꢀUpperꢀByteꢀ

ꢀ

Lꢀ

ꢀ

Hꢀ

ꢀ

Lꢀ

ꢀ

Hꢀ

ꢀ

Lꢀ

ꢀ

ROW/COLꢀ

ꢀ

LowerꢀByte,ꢀHigh-Zꢀ

UpperꢀByte,ꢀDo u t

Write:ꢀWordꢀ(EarlyꢀWrite)ꢀ

Lꢀ

Xꢀ

ROW/COLꢀ

Din

Write:ꢀLowerꢀByteꢀ(EarlyꢀWrite)ꢀ

Hꢀ

LowerꢀByte,ꢀDin

Upper Byte, High-Z

Write:ꢀUpperꢀByteꢀ(EarlyꢀWrite)ꢀ

ꢀ

Lꢀ

ꢀ

Hꢀ

ꢀ

Lꢀ

ꢀ

Lꢀ

ꢀ

Xꢀ

ꢀ

ROW/COLꢀ

ꢀ

LowerꢀByte,ꢀHigh-Zꢀ

UpperꢀByte,ꢀDin

Read-Write^(1,2)

ꢀ

Lꢀ

H→Lꢀ L→Hꢀ

ROW/COLꢀ

Do u t ,ꢀDin

EDOꢀPage-ModeꢀRead⁽²⁾ꢀ 1stꢀCycle:ꢀ Lꢀ

H→Lꢀ H→Lꢀ

L→Hꢀ L→Hꢀ

Hꢀ

Lꢀ

ROW/COLꢀ

NA/COLꢀ

NA/NAꢀ

Do u t

2ndꢀCycle:ꢀ Lꢀ

AnyꢀCycle:ꢀ Lꢀ

EDOꢀPage-ModeꢀWrite⁽¹⁾

EDOꢀPage-Modeꢀꢀ

1stꢀCycle:ꢀ Lꢀ

2ndꢀCycle:ꢀ Lꢀ

H→Lꢀ H→Lꢀ

Lꢀ

Xꢀ

ROW/COLꢀ

NA/COLꢀ

Din

1stꢀCycle:ꢀ Lꢀ

2ndꢀCycle:ꢀ Lꢀ

H→Lꢀ H→Lꢀ H→Lꢀ L→Hꢀ

ROW/COLꢀ

NA/COLꢀ

Do u t ,ꢀDin

Read-Write^(1,2)

ꢀ

RAS-OnlyꢀRefreshꢀ

CBRꢀRefresh⁽³⁾

Lꢀ

Hꢀ

Lꢀ

Hꢀ

Lꢀ

Xꢀ

ROW/NAꢀ

Xꢀ

High-Z

H→Lꢀ

Notes:

1.ꢀ TheseꢀWRITEꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀWRITEꢀcyclesꢀ(eitherꢀLCAS or UCAS active).

2.ꢀ TheseꢀREADꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀREADꢀcyclesꢀ(eitherꢀLCAS or UCAS active).

3. At least one of the two CAS signals must be active (LCAS or UCAS).

4

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

Functional Description

Refresh Cycle

TheꢀIS41C/LV16256CꢀisꢀaꢀCMOSꢀDRAMꢀoptimizedꢀforꢀ

high-speedꢀ bandwidth,ꢀ lowꢀ powerꢀ applications.ꢀ Duringꢀ

READꢀorꢀWRITEꢀcycles,ꢀeachꢀbitꢀisꢀuniquelyꢀaddressedꢀ

throughꢀtheꢀ18ꢀaddressꢀbits.ꢀTheseꢀareꢀenteredꢀnineꢀbitsꢀ

(A0-A8)ꢀatꢀaꢀtime.ꢀꢀTheꢀrowꢀaddressꢀisꢀlatchedꢀbyꢀtheꢀRowꢀ

Address Strobe (RAS).ꢀTheꢀcolumnꢀaddressꢀisꢀlatchedꢀbyꢀ

the Column Address Strobe (CAS). RAS is used to latch

the ﬁrst nine bits and CAS is used the latter nine bits.

Toꢀretainꢀdata,ꢀ512ꢀrefreshꢀcyclesꢀareꢀrequiredꢀinꢀeachꢀ

8ꢀmsꢀperiod.ꢀThereꢀareꢀtwoꢀwaysꢀtoꢀrefreshꢀtheꢀmemory.

1.ꢀByꢀclockingꢀeachꢀofꢀtheꢀ512ꢀrowꢀaddressesꢀ(A0ꢀthroughꢀ

A8)ꢀwithꢀRASꢀatꢀleastꢀonceꢀeveryꢀ8ꢀms.ꢀAnyꢀread,ꢀwrite,ꢀ

read-modify-write or RAS-only cycle refreshes the ad-

dressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-

RAS refresh is activated by the falling edge of RAS,

while holding CASꢀLOW.ꢀInꢀCAS-before-RAS refresh

cycle, an internal 9-bit counter provides the row ad-

dresses and the external address inputs are ignored.

TheꢀIS41C/LV16256CꢀhasꢀtwoꢀCAS controls, LCAS and

UCAS.ꢀTheꢀLCAS and UCAS inputs internally generates

a CAS signal functioning in an identical manner to the

single CASꢀinputꢀonꢀtheꢀotherꢀ256Kꢀxꢀ16ꢀDRAMs.ꢀTheꢀkeyꢀ

difference is that each CAS controls its corresponding I/O

tristate logic (in conjunction with OE and WE and RAS).

LCAS controls I/O0 through I/O7 and UCAS controls I/

O8ꢀthroughꢀI/O15.ꢀ

CAS-before-RAS is a refresh-only mode and no data

accessꢀorꢀdeviceꢀselectionꢀisꢀallowed.ꢀThus,ꢀtheꢀoutputꢀ

remains in the High-Z state during the cycle.

TheꢀIS41C/LV16256CꢀCAS function is determined by the

ﬁrst CAS (LCAS or UCAS)ꢀtransitioningꢀLOWꢀandꢀtheꢀlastꢀ

transitioningꢀbackꢀHIGH.ꢀTheꢀtwoꢀCAS controls give the

IS41C/LV16256CꢀbothꢀBYTEꢀREADꢀandꢀBYTEꢀWRITEꢀ

cycle capabilities.

Extended Data Out Page Mode

EDOꢀpageꢀmodeꢀoperationꢀpermitsꢀallꢀ512ꢀcolumnsꢀwithinꢀ

a selected row to be randomly accessed at a high data

rate.

InꢀEDOꢀpageꢀmodeꢀreadꢀcycle,ꢀtheꢀdata-outꢀisꢀheldꢀtoꢀtheꢀ

next CAS cycle’s falling edge, instead of the rising edge.

Forꢀthisꢀreason,ꢀtheꢀvalidꢀdataꢀoutputꢀtimeꢀinꢀEDOꢀpageꢀ

mode is extended compared with the fast page mode. In

the fast page mode, the valid data output time becomes

shorter as the CASꢀcycleꢀtimeꢀbecomesꢀshorter.ꢀThere-

fore,ꢀinꢀEDOꢀpageꢀmode,ꢀtheꢀtimingꢀmarginꢀinꢀreadꢀcycleꢀ

is larger than that of the fast page mode even if the CAS

cycle time becomes shorter.

Memory Cycle

A memory cycle is initiated by bring RASꢀLOWꢀandꢀitꢀ

is terminated by returning both RAS and CAS HIGH.

Toꢀensuresꢀproperꢀdeviceꢀoperationꢀandꢀdataꢀintegrityꢀ

any memory cycle, once initiated, must not be ended or

aborted before the minimum tr a s time has expired.A new

cycle must not be initiated until the minimum precharge

time tr p , tc p has elapsed.

InꢀEDOꢀpageꢀmode,ꢀdueꢀtoꢀtheꢀextendedꢀdataꢀfunction,ꢀ

the CAS cycle time can be shorter than in the fast page

mode if the timing margin is the same.

Read Cycle

TheꢀEDOꢀpageꢀmodeꢀallowsꢀbothꢀreadꢀandꢀwriteꢀoperationsꢀ

during one RAS cycle, but the performance is equivalent

to that of the fast page mode in that case.

A read cycle is initiated by the falling edge of CAS or

OE, whichever occurs last, while holding WEꢀHIGH.ꢀTheꢀ

column address must be held for a minimum time speci-

ﬁed by ta r .ꢀDataꢀOutꢀbecomesꢀvalidꢀonlyꢀwhenꢀtr a c , ta a ,

tc a c and to e a are all satisﬁed.As a result, the access time

is dependent on the timing relationships between these

parameters.

Power-On

AfterꢀapplicationꢀofꢀtheꢀVd d supply, an initial pause of

200 µs is required followed by a minimum of eight initial-

ization cycles (any combination of cycles containing a

RAS signal).

Write Cycle

Duringꢀpower-on,ꢀitꢀisꢀrecommendedꢀthatꢀRAS track with

V^{d d}ꢀorꢀbeꢀheldꢀatꢀaꢀvalidꢀVih to avoid current surges.

A write cycle is initiated by the falling edge of CAS and

WE,ꢀwhicheverꢀoccursꢀlast.ꢀTheꢀinputꢀdataꢀmustꢀbeꢀvalidꢀ

at or before the falling edge of CAS or WE, whichever

occurs last.

Integrated Silicon Solution, Inc.ꢀ

5

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Symbol Parameters

Rating

5Vꢀ -1.0ꢀtoꢀ+7.0ꢀ ꢀ Vꢀ

3.3Vꢀ -1.0ꢀtoꢀ+7.0ꢀ ꢀ

5Vꢀ -0.5ꢀtoꢀ+4.6ꢀ ꢀ Vꢀ

Unit

ꢀ

Vtꢀ

ꢀ

VoltageꢀonꢀAnyꢀPinꢀRelativeꢀtoꢀGNDꢀꢀ

ꢀ

V

Vd d ꢀ

ꢀ

SupplyꢀVoltageꢀ

ꢀ

3.3Vꢀ -0.5ꢀtoꢀ+4.6ꢀ ꢀ

V

Io u t ꢀ

Pdꢀ

OutputꢀCurrentꢀ

PowerꢀDissipationꢀ

CommercialꢀTemperatureꢀ

IndustrialꢀTemperatureꢀ

StorageꢀTemperatureꢀ

ꢀ

50ꢀ

1ꢀ

0ꢀtoꢀ+70ꢀ

-40ꢀtoꢀ+85ꢀ ꢀꢀꢀꢀ°C

–55ꢀtoꢀ+125ꢀ ꢀ °C

ꢀ

mA

W

ꢀ

Taꢀ

ꢀꢀꢀꢀ°C

Taꢀ

Ts t g ꢀ

Note:

1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀ

damageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀ

or any other conditions above those indicated in the operational sections of this speciﬁcation is

notꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀ

reliability.

RECOMMENDED OPERATING CONDITIONS (VoltagesꢀareꢀreferencedꢀtoꢀGND.)

Symbol Parameter

Test Conditions

Min. Typ.

Max. Unit

ꢀ

Vd d ꢀ

Vihꢀ

Vilꢀ

SupplyꢀVoltageꢀ

ꢀ

5Vꢀ

3.3V

5V

3.3V

5V

3.3V

4.5ꢀ 5.0ꢀ

3.0ꢀ 3.3ꢀ

5.5ꢀ

3.6ꢀ

Vꢀ

V

InputꢀHighꢀVoltageꢀ

InputꢀLowꢀVoltageꢀ

ꢀ

2.0

—

Vd d +ꢀ1.0ꢀ Vꢀ

Vd d +ꢀ0.3ꢀ V

–1.0ꢀ —ꢀ

–0.3ꢀ —ꢀ

0.8ꢀ

Vꢀ

V

iil

ꢀ

InputꢀLeakageꢀCurrentꢀ

ꢀ

Anyꢀinputꢀ0Vꢀ≤ꢀVin ≤ꢀVd d

Otherꢀinputsꢀnotꢀunderꢀtestꢀ=ꢀ0V

-5

-5ꢀ

2.4ꢀ

—

5

µA

µAꢀ

Vꢀ

ꢀ

iio

ꢀ

OutputꢀLeakageꢀCurrentꢀ

ꢀ

Outputꢀisꢀdisabledꢀ(Hi-Z)ꢀ

0Vꢀ≤ Vo u t ≤ꢀVd d

ꢀ

—ꢀ

5ꢀ

Vo h

Vo l

OutputꢀHighꢀVoltageꢀLevelꢀ

io h ꢀ=ꢀ–5.0ꢀmAꢀ

io h ꢀ=ꢀ–2.0ꢀmAꢀꢀ

5Vꢀ

3.3V

—ꢀ

0.4ꢀ

OutputꢀLowꢀVoltageꢀLevelꢀ

io l ꢀ=ꢀ+4.2ꢀmAꢀ

io l ꢀ=ꢀ+2.0ꢀmAꢀ

5Vꢀ

3.3V

Vꢀ

ꢀ

Taꢀ

ꢀ

Com.ꢀAmbientꢀTemp.ꢀ

Ind.ꢀAmbientꢀTemp.ꢀ

ꢀ

0ꢀ

-40ꢀ

—ꢀ

+70ꢀ °Cꢀ

+85ꢀ °C

CAPACITANCE^(1,2)

Symbol

Cin1ꢀ

Cin2

Parameter

Max.

Unit

InputꢀCapacitance:ꢀA0-A8ꢀ

5ꢀ

7

pF

Input Capacitance: RAS, UCAS, LCAS, WE, OE

DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ

Cioꢀ

7ꢀ

Notes:

1.ꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.

2.ꢀꢀTestꢀconditions:ꢀꢀT^aꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz,ꢀ

6ꢀ

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

ELECTRICAL CHARACTERISTICS⁽¹⁾

(RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)

Symbol Parameter

Test Condition

VD D /Speed Min.

Max. Unit

id d 1ꢀꢀ

ꢀ

Stand-byꢀCurrent:ꢀTTLꢀ

ꢀ

RAS, LCAS, UCAS ≥ Vihꢀ

ꢀ

5Vꢀ

3.3Vꢀ

—ꢀ

5ꢀ

4ꢀ

mAꢀ

mA

ꢀ

id d 2ꢀꢀ

ꢀ

Stand-byꢀCurrent:ꢀCMOSꢀ

ꢀ

RAS, LCAS, UCAS ≥ Vd d ꢀ–ꢀ0.2Vꢀꢀ

ꢀ

5Vꢀ

3.3Vꢀ

—ꢀ

2ꢀ

1ꢀ

mAꢀ

mA

id d 3

ꢀ

Operating Current:

RAS, LCAS, UCAS,ꢀ

Address Cycling, tr c = tr c (min.)ꢀ

-35ꢀ

-60ꢀ

—ꢀ

230ꢀ

170

mA

RandomꢀRead/Write^(2,3,4)

Average Power Supply Current

id d 4

ꢀ

Operating Current:

RASꢀ=ꢀVil, LCAS, UCAS,ꢀ

Cycling tp c = tp c (min.)ꢀ

-35ꢀ

-60ꢀ

—ꢀ

220ꢀ

160ꢀ

ꢀ

EDOꢀPageꢀMode^(2,3,4)

Average Power Supply Current

id d 5ꢀꢀ

RefreshꢀCurrent:ꢀ

RAS Cycling, LCAS, UCAS ≥ Vihꢀ

tr c = tr c (min.)ꢀ

-35ꢀ

-60ꢀ

—ꢀ

230ꢀ

170

RAS-Only^(2,3)

Average Power Supply Current

id d 6ꢀꢀ

ꢀ

RefreshꢀCurrent:ꢀꢀ

CBR^(2,3,5)

RAS, LCAS, UCASꢀCyclingꢀ

tr c = tr c (min.)ꢀ

-35ꢀ

-60ꢀ

—ꢀ

230ꢀ

170ꢀ

ꢀ

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ

operationꢀisꢀassured.ꢀꢀꢀTheꢀeightꢀRAS cycles wake-up should be repeated any time the t^{r e f}refresh requirement is exceeded.

2.ꢀꢀDependentꢀonꢀcycleꢀrates.

3. Speciﬁed values are obtained with minimum cycle time and the output open.

4.ꢀꢀColumn-addressꢀisꢀchangedꢀonceꢀeachꢀEDOꢀpageꢀcycle.

5.ꢀꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.

Integrated Silicon Solution, Inc.

7

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

AC CHARACTERISTICS^{(1,2,3,4,5,6)}

(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)

-35

-60

Symbol

tr c ꢀ

Parameter

Min. Max.

Units

ns

RandomꢀREADꢀorꢀWRITEꢀCycleꢀTimeꢀ

70ꢀ

35ꢀ

—ꢀ

11ꢀ

18ꢀ

110ꢀ

60ꢀ

—ꢀ

15ꢀ

30ꢀ

ꢀ

tr a c ꢀ

tc a c ꢀ

ta a ꢀ

AccessꢀTimeꢀfromꢀRAS^(6,ꢀ7)

AccessꢀTimeꢀfromꢀCAS^{(6,ꢀ8,ꢀ15)}

AccessꢀTimeꢀfromꢀColumn-Address⁽⁶⁾ꢀ

ꢀ

—ꢀ

tr a s

tr p

RASꢀPulseꢀWidthꢀ

35ꢀ 10Kꢀ

60ꢀ 10Kꢀ

40ꢀ —ꢀ

10ꢀ 10Kꢀ

RASꢀPrechargeꢀTimeꢀ

25ꢀ

6ꢀ

—ꢀ

10Kꢀ

—ꢀ

24ꢀ

—ꢀ

—

tc a s

tc p

CASꢀPulseꢀWidth⁽²⁶⁾

CASꢀPrechargeꢀTime^(9,ꢀ25)

CASꢀHoldꢀTimeꢀ⁽²¹⁾

RAS to CASꢀDelayꢀTime^{(10, 20)}

Row-AddressꢀSetupꢀTimeꢀ

Row-AddressꢀHoldꢀTimeꢀ

ꢀ

6ꢀ

10ꢀ

60ꢀ

20ꢀ

0ꢀ

—ꢀ

45ꢀ

—ꢀ

—

tc s h

t^{r c d}

ta s r ꢀ

tr a h ꢀ

ta s c ꢀ

tc a h ꢀ

ta r ꢀ

ꢀ

35ꢀ

13ꢀ

0ꢀ

ꢀ

6ꢀ

10ꢀ

0

Column-AddressꢀSetupꢀTime⁽²⁰⁾

Column-AddressꢀHoldꢀTime⁽²⁰⁾

0

ꢀ

6ꢀ

—ꢀ

10ꢀ

45ꢀ

—ꢀ

ꢀ

Column-AddressꢀHoldꢀTimeꢀ

30ꢀ

(referenced to RAS)

tr a d

tr a l

tr p c

tr s h

tc l z

tc r p

to d ꢀ

RASꢀtoꢀColumn-AddressꢀDelayꢀTime⁽¹¹⁾

Column-Address to RASꢀLeadꢀTimeꢀ

RAS to CASꢀPrechargeꢀTimeꢀ

ꢀ

10ꢀ

18ꢀ

0ꢀ

20ꢀ

—ꢀ

—

15ꢀ

30ꢀ

0ꢀ

30ꢀ

—ꢀ

—

ꢀ

ns

RASꢀHoldꢀTime⁽²⁷⁾

ꢀ

10ꢀ

3

15ꢀ

3

CASꢀtoꢀOutputꢀinꢀLow-Z^(15,ꢀ29)

CAS to RASꢀPrechargeꢀTime⁽²¹⁾

ꢀ

5ꢀ

—ꢀ

15ꢀ

11ꢀ

—ꢀ

—

5ꢀ

—ꢀ

15ꢀ

—ꢀ

—

ꢀ

OutputꢀDisableꢀTime^{(19,ꢀ28,ꢀ29)}

ꢀ

3ꢀ

to e / to e a ꢀ OutputꢀEnableꢀTime^(15,ꢀ16)

ꢀ

0ꢀ

—ꢀ

8ꢀ

to e h c

to e p

OEꢀHIGHꢀHoldꢀTimeꢀfromꢀCASꢀHIGHꢀ

OEꢀHIGHꢀPulseꢀWidthꢀ

8ꢀ

to e s

OEꢀLOWꢀtoꢀCASꢀHIGHꢀSetupꢀTimeꢀ

ReadꢀCommandꢀSetupꢀTime^{(17, 20)}

5ꢀ

7ꢀ

tr c s ꢀ

tr r h ꢀ

0

ReadꢀCommandꢀHoldꢀTimeꢀ

0ꢀ

—ꢀ

0ꢀ

—ꢀ

ꢀ

(referenced to RAS)⁽¹²⁾

tr c h ꢀ

ReadꢀCommandꢀHoldꢀTimeꢀ

0ꢀ

—ꢀ

0ꢀ

—ꢀ

ns

(referenced to CAS)^{(12, 17, 21)}

tw c h ꢀ

tw c r ꢀ

WriteꢀCommandꢀHoldꢀTime^{(17, 27)}

ꢀ

5ꢀ

—ꢀ

10ꢀ

50ꢀ

—ꢀ

ꢀ

ns

WriteꢀCommandꢀHoldꢀTimeꢀ

30ꢀ

(referenced to RAS)⁽¹⁷⁾

8ꢀ

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}

(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)

-35

-60

Symbol

tw p ꢀ

Parameter

WriteꢀCommandꢀPulseꢀWidth⁽¹⁷⁾

Min. Max.

Units

ns

ꢀ

5ꢀ

10ꢀ

8ꢀ

—ꢀ

—

10ꢀ

15ꢀ

0

—ꢀ

—

ꢀ

tw p z

WEꢀPulseꢀWidthsꢀtoꢀDisableꢀOutputsꢀ

WriteꢀCommandꢀtoꢀRASꢀLeadꢀTime⁽¹⁷⁾

WriteꢀCommandꢀtoꢀCASꢀLeadꢀTime^{(17, 21)}

WriteꢀCommandꢀSetupꢀTime^{(14, 17, 20)}

Data-inꢀHoldꢀTimeꢀ(referencedꢀtoꢀRAS)ꢀ

ns

tr w l ꢀ

tc w l ꢀ

tw c s ꢀ

td h r ꢀ

ꢀ

ns

ꢀ

ns

0

ns

30ꢀ

15ꢀ

—ꢀ

46ꢀ

15ꢀ

—ꢀ

ꢀ

ns

ta c h ꢀ

Column-AddressꢀSetupꢀTimeꢀtoꢀCASꢀ

ns

ꢀ

PrechargeꢀduringꢀWRITEꢀCycleꢀ

to e h

ꢀ

OEꢀHoldꢀTimeꢀfromꢀWEꢀduringꢀ

8ꢀ

—ꢀ

15ꢀ

—ꢀ

ꢀ

ns

READ-MODIFY-WRITEꢀcycle⁽¹⁸⁾

t^{d s}ꢀ

Data-InꢀSetupꢀTime^(15,ꢀ22)

0

—

0

—

ns

td h ꢀ

Data-InꢀHoldꢀTime^(15,ꢀ22)

ꢀ

6ꢀ

—ꢀ

10ꢀ

140ꢀ

80ꢀ

—ꢀ

ꢀ

tr w c ꢀ

READ-MODIFY-WRITEꢀCycleꢀTimeꢀ

80ꢀ

46ꢀ

tr w d

ꢀ

RAS to WEꢀDelayꢀTimeꢀduringꢀ

ꢀ

READ-MODIFY-WRITEꢀCycle⁽¹⁴⁾

tc w d

ta w d

CAS to WEꢀDelayꢀTime^{(14, 20)}

Column-Address to WEꢀDelayꢀTime⁽¹⁴⁾

ꢀ

25ꢀ

30

—ꢀ

—

36ꢀ

49

—ꢀ

—

ꢀ

ns

tp c ꢀ

ꢀ

EDOꢀPageꢀModeꢀREADꢀorꢀWRITEꢀ

CycleꢀTime⁽²⁴⁾

14ꢀ

—ꢀ

25ꢀ

—ꢀ

tr a s p

tc p a ꢀ

RASꢀPulseꢀWidthꢀinꢀEDOꢀPageꢀModeꢀ

AccessꢀTimeꢀfromꢀCAS Precharge⁽¹⁵⁾

35ꢀ 100Kꢀ

60ꢀ 100Kꢀ

ꢀ

ns

ꢀ

—ꢀ

45ꢀ

20ꢀ

—ꢀ

60ꢀ

35ꢀ

—ꢀ

tp r w c ꢀ

ꢀ

EDOꢀPageꢀModeꢀREAD-WRITEꢀ

CycleꢀTime⁽²⁴⁾

tc o h / td o h ꢀ DataꢀOutputꢀHoldꢀafterꢀCASꢀLOWꢀ

5ꢀ

3ꢀ

—ꢀ

10ꢀ

5ꢀ

3ꢀ

—ꢀ

15ꢀ

ꢀ

ns

to f f ꢀ

OutputꢀBufferꢀTurn-OffꢀDelayꢀfromꢀ

CAS or RAS^{(13,15,19,ꢀ29)}

tw h z ꢀ

OutputꢀDisableꢀDelayꢀfromꢀWEꢀ

3ꢀ

10ꢀ

3ꢀ

15ꢀ

ꢀ

ns

tc l c h ꢀ

LastꢀCASꢀgoingꢀLOWꢀtoꢀFirstꢀCAS

10

—

10

—

ns

returning HIGH⁽²³⁾

tc s r

tc h r

CASꢀSetupꢀTimeꢀ(CBRꢀREFRESH)^{(30, 20)}

ꢀ

8ꢀ

0

—ꢀ

—

10ꢀ

0

—ꢀ

—

ꢀ

ns

CASꢀHoldꢀTimeꢀ(CBRꢀREFRESH)^{(30, 21)}

ꢀ

to r d

OEꢀSetupꢀTimeꢀpriorꢀtoꢀRAS during

ꢀ

HIDDENꢀREFRESHꢀCycleꢀ

tr e f ꢀ

tt

RefreshꢀPeriodꢀ(512ꢀCycles)ꢀ

TransitionꢀTimeꢀ(RiseꢀorꢀFall)^{(2, 3)}

—ꢀ

2ꢀ

8ꢀ

—ꢀ

2ꢀ

8ꢀ

ꢀ

ms

ns

ꢀ

50ꢀ

Integrated Silicon Solution, Inc.

9

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

AC TEST CONDITIONS

Output load: Two TTL Loads and 50 pF (Vd d = 5.0V ±10%)

One TTL Load and 50 pF (Vd d = 3.3V ±10%)

Input timing reference levels: Vih = 2.0V, Vil = 0.8V (Vd d = 5.0V ±10%);

Vih = 2.0V, Vil = 0.8V (Vd d = 3.3V ±10%)

Output timing reference levels: Vo h = 2.4V, Vo l = 0.4V (Vd d = 5V ±10%, 3.3V ±10%)

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ

operationꢀisꢀassured.ꢀTheꢀeightꢀRAS cycles wake-up should be repeated any time the t^{r e f}refresh requirement is exceeded.

2. V^ihꢀ(MIN)ꢀandꢀVilꢀ(MAX)ꢀareꢀreferenceꢀlevelsꢀforꢀmeasuringꢀtimingꢀofꢀinputꢀsignals.ꢀTransitionꢀtimes,ꢀareꢀmeasuredꢀbetweenꢀVih

and V^il(or between Vil and Vih) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate speciﬁcation, all input signals must transit between V^ihand Vil (or between Vil and Vih)

in a monotonic manner.

4. If CAS and RAS = V^ih, data output is High-Z.

5.ꢀ IfꢀCAS = V^il,ꢀdataꢀoutputꢀmayꢀcontainꢀdataꢀfromꢀtheꢀlastꢀvalidꢀREADꢀcycle.

6.ꢀ MeasuredꢀwithꢀaꢀloadꢀequivalentꢀtoꢀoneꢀTTLꢀgateꢀandꢀ50ꢀpF.

7. Assumes that t^{r c d}< tr c d ꢀ(MAX).ꢀIfꢀtr c d is greater than the maximum recommended value shown in this table, tr a c will increase

by the amount that t^{r c d}exceeds the value shown.

8.ꢀ Assumesꢀthatꢀt^{r c d}≥ tr c d ꢀ(MAX).

9. If CASꢀisꢀLOWꢀatꢀtheꢀfallingꢀedgeꢀofꢀRAS,ꢀdataꢀoutꢀwillꢀbeꢀmaintainedꢀfromꢀtheꢀpreviousꢀcycle.ꢀToꢀinitiateꢀaꢀnewꢀcycleꢀandꢀclearꢀtheꢀ

data output buffer, CAS and RAS must be pulsed for t^{c p}.

10. Operation with the t^{r c d}ꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtr a c ꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtr c d ꢀ(MAX)ꢀisꢀspeciﬁedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtr c d

is greater than the speciﬁed t^{r c d}ꢀ(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtc a c .

11. Operation within the t^{r a d}ꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtr c d ꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtr a d ꢀ(MAX)ꢀisꢀspeciﬁedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtr a d

is greater than the speciﬁed t^{r a d}(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀta a .

12.ꢀEitherꢀt^{r c h}or tr r h ꢀmustꢀbeꢀsatisﬁedꢀforꢀaꢀREADꢀcycle.

13. t^{o f f}ꢀ(MAX)ꢀdeﬁnesꢀtheꢀtimeꢀatꢀwhichꢀtheꢀoutputꢀachievesꢀtheꢀopenꢀcircuitꢀcondition;ꢀitꢀisꢀnotꢀaꢀreferenceꢀtoꢀVo h or Vo l .

14. t^{w c s}, tr w d , ta w d and tc w d ꢀareꢀrestrictiveꢀoperatingꢀparametersꢀinꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcycleꢀonly.ꢀIfꢀtw c s ≥

t^{w c s}ꢀ(MIN),ꢀtheꢀcycleꢀisꢀanꢀEARLYꢀWRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀremainꢀopenꢀcircuitꢀthroughoutꢀtheꢀentireꢀcycle.ꢀIfꢀtr w d ≥

t^{r w d}ꢀ(MIN),ꢀta w d ≥ ta w d ꢀ(MIN)ꢀandꢀtc w d ≥ tc w d ꢀ(MIN),ꢀtheꢀcycleꢀisꢀaꢀREAD-WRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀcontainꢀdataꢀreadꢀ

from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go

back to V^ih) is indeterminate. OE held HIGH and WEꢀtakenꢀLOWꢀafterꢀCASꢀgoesꢀLOWꢀresultꢀinꢀaꢀLATEꢀWRITEꢀ(OE-controlled)

cycle.

15.ꢀOutputꢀparameterꢀ(I/O)ꢀisꢀreferencedꢀtoꢀcorrespondingꢀCAS input, I/O0-I/O7 by LCASꢀandꢀI/O8-I/O15ꢀbyꢀUCAS.

16.ꢀDuringꢀaꢀREADꢀcycle,ꢀifꢀOEꢀisꢀLOWꢀthenꢀtakenꢀHIGHꢀbeforeꢀCAS goes HIGH, I/O goes open. If OEꢀisꢀtiedꢀpermanentlyꢀLOW,ꢀaꢀ

LATEꢀWRITEꢀorꢀREAD-MODIFY-WRITEꢀisꢀnotꢀpossible.

17.ꢀWriteꢀcommandꢀisꢀdeﬁnedꢀasꢀWE going low.

18.ꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcyclesꢀmustꢀhaveꢀbothꢀt^{o d}and to e h met (OEꢀHIGHꢀduringꢀWRITEꢀcycle)ꢀinꢀorderꢀtoꢀ

ensureꢀthatꢀtheꢀoutputꢀbuffersꢀwillꢀbeꢀopenꢀduringꢀtheꢀWRITEꢀcycle.ꢀTheꢀI/OsꢀwillꢀprovideꢀtheꢀpreviouslyꢀwrittenꢀdataꢀifꢀCAS remains

LOWꢀandꢀOEꢀisꢀtakenꢀbackꢀtoꢀLOWꢀafterꢀt^{o e h}is met.

19.ꢀTheꢀI/OsꢀareꢀinꢀopenꢀduringꢀREADꢀcyclesꢀonceꢀt^{o d}or to f f occur.

20.ꢀTheꢀﬁrstꢀχCASꢀedgeꢀtoꢀtransitionꢀLOW.

21.ꢀTheꢀlastꢀχCAS edge to transition HIGH.

22.ꢀTheseꢀparametersꢀareꢀreferencedꢀtoꢀCASꢀleadingꢀedgeꢀinꢀEARLYꢀWRITEꢀcyclesꢀandꢀWEꢀleadingꢀedgeꢀinꢀLATEꢀWRITEꢀorꢀREAD-

MODIFY-WRITEꢀcycles.

23.ꢀLastꢀfallingꢀχCAS edge to ﬁrst rising χCAS edge.

24.ꢀLastꢀrisingꢀχCAS edge to next cycle’s last rising χCAS edge.

25.ꢀLastꢀrisingꢀχCAS edge to ﬁrst falling χCAS edge.

26.ꢀEachꢀχCAS must meet minimum pulse width.

27.ꢀLastꢀχCASꢀtoꢀgoꢀLOW.

28.ꢀI/Osꢀcontrolled,ꢀregardlessꢀUCAS and LCAS.

29.ꢀTheꢀ3ꢀnsꢀminimumꢀisꢀaꢀparameterꢀguaranteedꢀbyꢀdesign.ꢀ

30.ꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.

10

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

READ CYCLE

t

RC

t

RAS

tRP

RAS

tCSH

t

RSH

t

RRH

t

CRP

ASR

t

CAS CLCH

t

RCD

UCAS/LCAS

t

AR

t

RAD

tRAL

t

RAH

tCAH

t

ASC

ADDRESS

Row

Column

Row

tRCS

t

RCH

WE

tAA

tRAC

(1)

OFF

t

CAC

CLC

t

Open

Valid Data

I/O

t

OE

tOD

OE

tOES

Don't Care

Note:

1. t^{o f f}is referenced from rising edge of RAS or CAS, whichever occurs last.

Integrated Silicon Solution, Inc.

11

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

EARLY WRITE CYCLE (OE = DON'T CARE)

tRC

t

RAS

tRP

RAS

tCSH

t

RSH

t

CRP

ASR

t

CAS CLCH

t

RCD

UCAS/LCAS

tAR

t

RAD

t

RAL

CAH

ACH

t

RAH

t

ASC

ADDRESS

Row

Column

Row

t

CWL

RWL

t

WCR

t

WCS

tWCH

tWP

WE

t

DHR

t

DH

t

DS

I/O

Valid Data

Don't Care

12

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)

t

RWC

RAS

t

RP

RAS

tCSH

t

RSH

t

CRP

ASR

t

CAS CLCH

t

RCD

UCAS/LCAS

tAR

t

RAD

t

RAL

ACH

t

RAH

tCAH

tASC

t

ADDRESS

Row

Column

Row

t

RWD

tCWL

tRCS

t

CWD

tRWL

tAWD

t

WP

WE

t

AA

tRAC

tCAC

tCLZ

tDS

tDH

Open

Valid DOUT

Valid DIN

I/O

t

OD

tOEH

tOE

OE

Don't Care

Integrated Silicon Solution, Inc.

13

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

EDO-PAGE-MODE READ CYCLE

t

RASP

t

RP

RAS

(1)

t

CSH

t

PC

tRSH

tCRP

t

RCD

t

CAS,

t

CP

t

CAS,

t

CP

t

CAS,

tCP

t

CLCH

t

CLCH

tCLCH

UCAS/LCAS

t

AR

tRAD

tRAL

t

ASR

tASC

t

CAH

tASC

t

CAH

tASC

t

CAH

ADDRESS

Row

Column

Row

tRAH

t

RRH

t

RCS

t

RCH

WE

tAA

t

RAC

CAC

CLZ

tCPA

t

CPA

t

CAC

t

CAC

CLZ

t

COH

t

OFF

Open

Valid Data

I/O

tOE

t

OEHC

tOE

t

OD

tOES

t

OD

tOES

OE

t

OEP

Don't Care

Note:

1. t^{p c}can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both

measurements must meet the t^{p c}speciﬁcations.

14

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

EDO-PAGE-MODE EARLY-WRITE CYCLE

t

RASP

tRP

RAS

t

CSH

t

PC

tRSH

t

CRP

t

CAS,

t

CP

t

CAS,

t

CP

t

CAS,

tCP

tRCD

t

CLCH

t

CLCH

tCLCH

UCAS/LCAS

t

AR

tACH

t

ACH

tACH

t

RAD

tRAL

tASR

t

ASC

t

CAH

tASC

tCAH

tASC

t

CAH

ADDRESS

Row

Column

Row

tRAH

t

CWL

WCS

WCH

t

CWL

tCWL

t

WCS

t

WCS

t

tWCH

tWP

WE

t

WCR

DHR

tRWL

t

tDS

t

DH

tDH

I/O

Valid Data

OE

Don't Care

Integrated Silicon Solution, Inc.ꢀ

15

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)

t

RASP

t

RP

RAS

(1)

tPC / tPRWC

t

CSH

tRSH

t

CRP

t

RCD

t

CAS,

t

CLCH

t

CP

t

CAS,

t

CLCH

t

CP

t

CAS,

t

CLCH

tCP

UCAS/LCAS

t

AR

t

ASR

t

RAD

t

RAL

t

ASC

t

CAH

t

ASC

t

CAH

tASC

tCAH

RAH

ADDRESS

Row

Column

Row

t

RWD

t

RWL

CWL

t

RCS

t

CWL

WP

t

CWL

t

WP

t

WP

tAWD

t

CWD

t

CWD

tCWD

WE

t

AA

t

AA

CPA

t

AA

tCPA

t

RAC

t

DH

DS

t

DH

DS

t

DH

DS

t

CAC

CLZ

t

CAC

CLZ

t

CAC

CLZ

t

Open

I/O

D

OUT

D

t

IN

DOUT

D

IN

DOUT

D

IN

OD

t

OD

t

OD

tOE

t

OE

tOE

tOEH

OE

Don't Care

Note:

1. t^{p c}can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both

measurements must meet the t^{p c}speciﬁcations.

16

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)

t

RASP

t

RP

RAS

t

CSH

tPC

tRSH

tCRP

t

RCD

t

CAS

t

CP

t

CAS

tCP

t

CAS

tCP

UCAS/LCAS

t

AR

t

ACH

RAL

CAH

t

ASR

t

RAD

t

ASC

t

CAH

t

ASC

t

CAH

tASC

t

RAH

ADDRESS

Row

Column (A)

Column (B)

Column (N)

Row

t

RCS

t

RCH

t

WCS

tWCH

WE

t

WHZ

t

AA

t

AA

t

CPA

CAC

COH

t

RAC

tCAC

t

tDS

tDH

Open

I/O

Valid Data (A)

Valid Data (B)

DIN

tOE

OE

Don't Care

Integrated Silicon Solution, Inc.

17

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

AC WAVEFORMS

READ CYCLE (With WE-Controlled Disable)

RAS

tCSH

t

CRP

ASR

t

RCD

tCP

t

CAS

UCAS/LCAS

tAR

t

RAD

t

RAH

t

CAH

tASC

t

ASC

ADDRESS

Row

Column

tRCS

t

RCH

tRCS

WE

tAA

tRAC

tCAC

t

CLZ

tWHZ

tCLZ

Open

Valid Data

I/O

t

OE

tOD

OE

Don't Care

RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)

tRC

t

RAS

tRP

RAS

tCRP

t

RPC

UCAS/LCAS

tASR

tRAH

ADDRESS

I/O

Row

Open

Don't Care

18

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)

tRP

tRAS

tRP

tRAS

RAS

tCHR

t

RPC

tRPC

tCP

tCSR

UCAS/LCAS

I/O

Open

HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)⁽¹⁾

tRAS

t

RAS

t

RP

RAS

tCRP

tRCD

tRSH

tCHR

UCAS/LCAS

t

AR

tRAD

t

RAL

t

ASR

t

RAH

tCAH

tASC

ADDRESS

Row

Column

t

AA

t

RAC

(2)

OFF

t

CAC

tCLZ

Open

Valid Data

I/O

t

OE

tOD

t

ORD

OE

Don't Care

Notes:

1.ꢀ AꢀHiddenꢀRefreshꢀmayꢀalsoꢀbeꢀperformedꢀafterꢀaꢀWriteꢀCycle.ꢀInꢀthisꢀcase,ꢀWEꢀ=ꢀLOWꢀandꢀOE = HIGH.

2. t^{o f f}is referenced from rising edge of RAS or CAS, whichever occurs last.

Integrated Silicon Solution, Inc.

19

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

ORDERING INFORMATION : 3.3V

Industrial Range: -40^oC to +85^oC

Speed (ns) Order Part No.

Package

ꢀ

35ꢀ

IS41LV16256C-35KIꢀ

IS41LV16256C-35KLIꢀ

IS41LV16256C-35TIꢀ

IS41LV16256C-35TLIꢀ

400-milꢀSOJꢀ ꢀ

400-milꢀSOJ,ꢀLead-freeꢀ

400-milꢀTSOPꢀ(TypeꢀII)ꢀ

ꢀ

400-milꢀTSOPꢀ(TypeꢀII),ꢀLead-free

ORDERING INFORMATION : 5V

Industrial Range: -40^oC to +85^oC

Speed (ns) Order Part No.

Package

ꢀ

35ꢀ

IS41C16256C-35KIꢀ

IS41C16256C-35KLIꢀ

IS41C16256C-35TIꢀ

IS41C16256C-35TLIꢀ

400-milꢀSOJꢀ ꢀ

400-milꢀSOJ,ꢀLead-freeꢀ

400-milꢀTSOPꢀ(TypeꢀII)ꢀ

ꢀ

400-milꢀTSOPꢀ(TypeꢀII),ꢀLead-free

Note:

Theꢀ-35ꢀspeedꢀoptionꢀsupportsꢀ35nsꢀandꢀ60nsꢀtimingꢀspeciﬁcations.

20

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

Integrated Silicon Solution, Inc.

21

Rev. 00A

04/09/2010

IS41C16256C

IS41LV16256C

22

Integrated Silicon Solution, Inc.

Rev. 00A

04/09/2010


型号：	IS41C16256C
厂家：	INTEGRATED SILICON SOLUTION, INC
描述：	4Mb DRAM WITH EDO PAGE MODE 与EDO页模式DRAM 4MB 动态存储器
文件：	总22页 (文件大小：475K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IS41C16256C [ISSI]

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