IS41LV16100B-60TL [ISSI]
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE; 1M ×16 （ 16兆位）动态RAM与EDO页模式
| 型号： | IS41LV16100B-60TL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 文件： | 总22页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS41LV16100B
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI
APRIL2005
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs; tristate I/O
TheISSIIS41LV16100Bis1,048,576x16-bithigh-perfor-
manceCMOS DynamicRandomAccessMemories. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1,024 random ac-
cesses within a single row with access cycle time as short
as 20 ns per 16-bit word.
• Refresh Interval:
— Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
ThesefeaturesmaketheIS41LV16100Bideallysuited for
high-bandwidthgraphics, digitalsignalprocessing, high-
performance computing systems, and peripheral
applications.
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range: -40oC to +85oC
• Lead-free available
The IS41LV16100B is packaged in a 42-pin 400-mil SOJ
and 400-mil 50- (44-) pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
-50
50
-60
60
Unit
ns
PIN CONFIGURATIONS
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
50(44)-Pin TSOP (Type II)
42-PinSOJ
14
15
ns
Max. Column Address Access Time (tAA) 25
30
ns
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
44
43
42
41
40
39
38
37
36
35
34
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
30
85
40
ns
2
2
3
3
110
ns
4
4
5
5
6
6
7
PIN DESCRIPTIONS
7
8
8
9
A0-A9
I/O0-15
WE
Address Inputs
DataInputs/Outputs
WriteEnable
9
10
11
I/O8
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
LCAS
UCAS
OE
WE
RAS
NC
OE
OutputEnable
A9
RAS
UCAS
LCAS
VDD
RowAddressStrobe
A9
NC
A8
A8
UpperColumnAddressStrobe
LowerColumnAddressStrobe
Power
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
VDD
GND
VDD
GND
GND
NC
Ground
NoConnection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
1
04/14/05
®
ISSI
IS41LV16100B
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
TRUTH TABLE
Function
RAS LCAS UCAS WE
OE
X
Addresst
R
/t
C
I/O
High-Z
Standby
H
L
L
H
L
L
H
L
X
H
H
X
Read:Word
Read: Lower Byte
L
ROW/COL
ROW/COL
DOUT
H
L
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write:Word(EarlyWrite)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
D
IN
Write:LowerByte(EarlyWrite)
H
Lower Byte, DIN
Upper Byte, High-Z
Write:UpperByte(EarlyWrite)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
H→L
L→H
D
OUT, DIN
EDOPage-ModeRead(2) 1stCycle:
2nd Cycle:
L
L
L
H→L
H→L
L→H
H→L
H→L
L→H
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
DOUT
DOUT
DOUT
AnyCycle:
EDOPage-ModeWrite(1) 1stCycle:
2nd Cycle:
L
L
H→L
H→L
H→L
H→L
L
L
X
X
ROW/COL
NA/COL
D
D
IN
IN
EDOPage-Mode(1,2)
Read-Write
1stCycle:
2nd Cycle:
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L→H
L→H
ROW/COL
NA/COL
D
D
OUT, DIN
OUT, DIN
Hidden Refresh
Read(2)
L→H→L
L→H→L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
D
D
OUT
OUT
Write(1,3)
RAS-OnlyRefresh
CBRRefresh(4)
Notes:
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H→L
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
3
04/13/05
®
ISSI
IS41LV16100B
Functional Description
Auto Refresh Cycle
The IS41LV16100B is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16addressbits.Theseareenteredtenbits(A0-A9)at time.
The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS). RAS is used to latch the first nine bits
and CAS is used to latch the latter nine bits.
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. Byclockingeachofthe1,024rowaddresses(A0throughA9)
with RAS at least once every 128 ms. Any read, write, read-
modify-writeorRAS-onlycyclerefreshestheaddressedrow.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
TheIS41LV16100BhastwoCAScontrols, LCAS andUCAS.
The LCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single CAS input on
theother1Mx16DRAMs.ThekeydifferenceisthateachCAS
controlsitscorrespondingI/Otristatelogic(inconjunctionwith
OE and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
TheIS41LV16100B CASfunctionisdeterminedbythefirst
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16100BbothBYTEREADandBYTEWRITE cycle
capabilities.
EDOpagemodeoperationpermitsall1,024columnswithin
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
Read Cycle
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Power-On
After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.
During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.
4
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Rev. B
04/13/05
®
ISSI
IS41LV16100B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VT
Parameters
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
Voltage on Any Pin Relative to GND
SupplyVoltage
3.3V
3.3V
VDD
IOUT
PD
V
OutputCurrent
mA
W
PowerDissipation
1
TA
CommercialOperationTemperature
IndustrialOperationTemperature
0 to +70
-40 to +85
°C
°C
TSTG
StorageTemperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
VDD
Parameter
Min.
3.0
Typ.
3.3
—
Max.
3.6
Unit
V
SupplyVoltage
Input High Voltage
Input Low Voltage
3.3V
3.3V
3.3V
VIH
2.0
VDD + 0.3
0.8
V
VIL
–0.3
—
V
TA
CommercialAmbientTemperature
IndustrialAmbientTemperature
0
–40
—
—
70
85
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Input Capacitance: A0-A9
Max.
Unit
pF
CIN1
CIN2
5
7
7
Input Capacitance: RAS, UCAS, LCAS, WE, OE
pF
CIO
Data Input/Output Capacitance: I/O0-I/O15
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
5
04/13/05
®
ISSI
IS41LV16100B
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed Min. Max.
Unit
IIL
InputLeakageCurrent
Any input 0V ≤ VIN ≤ VDD
–10
10
µA
Other inputs not under test = 0V
IIO
OutputLeakageCurrent
Output is disabled (Hi-Z)
–10
10
µA
0V ≤ VOUT ≤ VDD
VOH
VOL
ICC1
Output High Voltage Level
Output Low Voltage Level
StandbyCurrent:TTL
IOH = –2.0 mA (3.3V)
IOL = 2.0 mA (3.3V)
2.4
—
—
V
V
0.4
RAS, LCAS, UCAS ≥ VIH Commercial 3.3V
—
—
3
4
mA
mA
Industrial 3.3V
ICC2
ICC3
StandbyCurrent:CMOS
RAS, LCAS, UCAS ≥ VDD – 0.2V
3.3V
—
2
mA
mA
OperatingCurrent:
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
180
170
RandomRead/Write(2,3,4)
AveragePowerSupplyCurrent
ICC4
ICC5
OperatingCurrent:
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
—
—
180
170
mA
mA
mA
EDOPageMode(2,3,4)
AveragePowerSupplyCurrent
RefreshCurrent:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
180
170
RAS-Only(2,3)
AveragePowerSupplyCurrent
ICC6
RefreshCurrent:
CBR(2,3,5)
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
—
—
180
170
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
ACCHARACTERISTICS(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50
-60
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
85
—
—
—
50
30
8
—
50
14
25
10K
—
110
—
—
—
60
40
10
10
60
20
0
—
60
15
30
10K
—
tRAC
tCAC
tAA
tRAS
tRP
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-AddressSetupTime
Row-AddressHoldTime
Column-AddressSetupTime(20)
Column-AddressHoldTime(20)
tCAS
tCP
10K
—
10K
—
9
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
50
12
0
—
—
37
—
45
—
8
—
10
0
—
0
—
—
8
—
10
40
—
Column-AddressHoldTime
30
—
—
(referencedtoRAS)
tRAD
tRAL
tRPC
tRSH
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
14
25
5
25
—
—
—
—
—
12
14
—
—
—
—
—
15
30
5
30
—
—
—
—
—
12
15
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
0
15
0
5
5
3
3
tOE/tOEA Output Enable Time(15, 16)
—
15
10
5
—
15
10
5
tOEHC
tOEP
tOES
tRCS
tRRH
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
ReadCommandSetupTime(17, 20)
0
0
ReadCommandHoldTime
0
0
(referencedtoRAS)(12)
tRCH
ReadCommandHoldTime
0
—
0
—
ns
(referencedtoCAS)(12, 17, 21)
tWCH
tWCR
Write Command Hold Time(17, 27)
8
—
—
10
50
—
—
ns
ns
WriteCommandHoldTime
40
(referencedtoRAS)(17)
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Rev. B
7
04/13/05
®
ISSI
IS41LV16100B
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50
-60
Symbol
tWP
Parameter
Min. Max.
Min. Max.
Units
ns
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
8
10
13
8
—
—
—
—
—
—
—
10
10
15
15
0
—
—
—
—
—
—
—
tWPZ
tRWL
tCWL
ns
ns
ns
tWCS
tDHR
0
ns
39
14
40
15
ns
tOEH
OE Hold Time from WE during
ns
READ-MODIFY-WRITEcycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
—
—
—
—
0
15
—
—
—
—
ns
ns
ns
ns
tDH
tRWC
tRWD
READ-MODIFY-WRITECycleTime
110
65
155
85
RAS to WE Delay Time during
READ-MODIFY-WRITECycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
40
30
—
—
—
40
55
40
—
—
—
ns
ns
ns
EDO Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
50
—
56
100K
30
60
—
56
100K
35
ns
ns
ns
tPRWC
EDOPageModeREAD-WRITE
Cycle Time(24)
—
—
tCOH
tOFF
Data Output Hold after CAS LOW
5
3
—
12
5
3
—
15
ns
ns
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 29)
tWHZ
Output Disable Delay from WE
3
10
—
3
15
—
ns
ns
tCLCH
Last CAS going LOW to First CAS
10
10
returningHIGH(23)
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
5
8
0
—
—
—
5
10
0
—
—
—
ns
ns
ns
OE Setup Time prior to RAS during
HIDDENREFRESHCycle
tREF
tT
Auto Refresh Period (1,024 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
3
16
50
—
3
16
50
ms
ns
8
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Rev. B
04/13/05
®
ISSI
IS41LV16100B
AC TEST CONDITIONS
Outputload: One TTL Load and 50 pF (VDD = 3.3V ±10%)
Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VDD = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonicmanner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≤ tRCD (MAX).
9. IfCASisLOWatthefallingedgeof RAS, dataoutwillbemaintainedfromthepreviouscycle. Toinitiateanewcycleandclearthedata
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≤ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≤ tRWD
(MIN), tAWD ≤ tAWD (MIN) and tCWD ≤ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. IfOE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtOD andtOEH met(OEHIGHduringWRITEcycle)inordertoensure
thattheoutputbufferswillbeopenduringtheWRITEcycle. TheI/OswillprovidethepreviouslywrittendataifCASremainsLOWand
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
9
04/13/05
®
ISSI
IS41LV16100B
READCYCLE
t
RC
t
RAS
t
RP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
ASR
t
RAH
t
CAH
t
ASC
ADDRESS
Row
Column
Row
t
RCS
t
RCH
WE
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLC
t
Open
Open
Valid Data
I/O
t
OE
tOD
OE
t
OES
Undefined
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
t
DHR
t
DH
t
DS
I/O
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11
04/13/05
®
ISSI
IS41LV16100B
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
WE
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
t
OD
tOEH
t
OE
OE
Undefined
Don’t Care
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
RCD
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
t
RAD
t
RAL
CAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
ADDRESS
Row
Column
Column
Column
Row
t
RAH
t
RRH
t
RCS
t
RCH
WE
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
t
CPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
t
OE
t
OEHC
tOE
t
OD
t
OES
t
OD
t
OES
OE
t
OEP
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
13
04/13/05
®
ISSI
IS41LV16100B
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
t
RHCP
RAS
t
CSH
t
PC
t
RSH
t
CRP
t
RCD
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
tACH
t
ACH
t
ACH
CAH
t
RAD
t
RAL
t
ASR
t
ASC
t
CAH
t
ASC
t
t
ASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
t
RAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
t
WCS
t
t
WCH
tWCH
t
WP
t
WP
t
WP
WE
t
WCR
DHR
tRWL
t
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
Valid Data
Valid Data
Valid Data
OE
Don’t Care
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
t
RASP
t
RP
RAS
(1)
tPC / tPRWC
t
CSH
t
RSH
CLCH
t
CRP
t
RCD
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
tCP
UCAS/LCAS
t
AR
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
tRWD
tRCS
t
t
t
RWL
CWL
WP
t
t
CWL
WP
t
t
CWL
WP
t
AWD
t
AWD
t
AWD
t
CWD
t
CWD
t
CWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
tDS
t
t
t
CAC
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
Open
Open
I/O
DOUT
DIN
DOUT
DIN
DOUT
DIN
t
OD
t
OD
t
OD
t
OE
t
OE
tOE
t
OEH
OE
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
15
04/13/05
®
ISSI
IS41LV16100B
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tRSH
tCAS
tCRP
tASR
tRCD
tCAS
tCP
tCAS
tCP
tCP
UCAS/LCAS
tAR
tACH
tRAL
tRAD
tASC
tCAH
tASC
tCAH
tASC
tCAH
tRAH
ADDRESS
Row
Column (A)
Column (B)
Column (N)
Row
tRCS
tRCH
tWCS
tWCH
WE
tWHZ
tAA
tAA
tCPA
tCAC
tCOH
tRAC
tCAC
tDS
tDH
Open
Open
I/O
Valid Data (A)
Valid Data (B)
DIN
tOE
OE
Don’t Care
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tASR
tRAH
tCAH
tRCH
tASC
tRCS
tASC
ADDRESS
Row
Column
Column
tRCS
WE
tAA
tRAC
tCAC
tCLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
tOE
tOD
OE
Undefined
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
17
04/13/05
®
ISSI
IS41LV16100B
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
Open
I/O
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
t
CRP
t
RCD
t
RSH
tCHR
UCAS/LCAS
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
t
OE
tOD
t
ORD
OE
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
®
ISSI
IS41LV16100B
ORDERING INFORMATION : 3.3V
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
50
IS41LV16100B-50K
IS41LV16100B-50KL
IS41LV16100B-50T
IS41LV16100B-50TL
400-mil SOJ
400-milSOJ,Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
60
IS41LV16100B-60K
IS41LV16100B-60KL
IS41LV16100B-60T
IS41LV16100B-60TL
400-mil SOJ
400-milSOJ,Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
Industrial Range: -40°C to +85°C
Speed(ns)
Order Part No.
Package
50
IS41LV16100B-50KI
IS41LV16100B-50KLI
IS41LV16100B-50TI
IS41LV16100B-50TLI
400-mil SOJ
400-milSOJ,Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
60
IS41LV16100B-60KI
IS41LV16100B-60KLI
IS41LV16100B-60TI
IS41LV16100B-60TLI
400-mil SOJ
400-milSOJ,Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
19
04/13/05
®
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
ISSI
Notes:
1. Controlling dimension:
millimeters.
N
N/2+1
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
E1
E
1
N/2
SEATING PLANE
D
A
b
C
A2
e
B
A1
E2
Millimeters
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
No. Leads (N)
28
32
36
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
18.29 18.54
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.720 0.730
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
®
PACKAGING INFORMATION
ISSI
Millimeters
Symbol Min Max
No. Leads (N)
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Min Max
Inches
Min Max
Min
Max
40
42
44
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
25.91 26.16
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.020 1.030
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and should be measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
L
α
e
b
c
A1
Plastic TSOP (T - Type II) (MS 25)
Plastic TSOP (T - Type II) (MS 24)
Millimeters Inches
Min Max
Plastic TSOP (T - Type II) (MS 24)
Millimeters Inches
Min Max
Millimeters
Inches
Min Max
Symbol Min
Max
Symbol Min
Max
Symbol Min
Max
Ref. Std.
Ref. Std.
Ref. Std.
N
A
A1
b
c
D
24/26
N
A
A1
b
c
D
40/44
N
A
A1
b
c
D
44/50
1.20
0.05 0.15
0.30 0.51
0.12 0.21
0.0472
1.20
0.05 0.15
0.30 0.45
0.12 0.21
0.0472
1.20
0.05 0.15
0.30 0.45
0.12 0.21
0.0472
0.002 0.0059
0.012 0.0201
0.005 0.0083
0.670 0.6899
0.295 0.3051
0.050 BSC
0.002 0.0059
0.012 0.0157
0.005 0.0083
0.721 0.7287
0.396 0.4040
0.031 BSC
0.002 0.0059
0.012 0.0157
0.005 0.0083
0.821 0.8287
0.396 0.4040
0.031 BSC
17.01 17.27
7.49 7.75
1.27 BSC
18.31 18.51
10.06 10.26
0.80 BSC
20.85 21.05
10.06 10.26
0.80 BSC
E
E
E
1
e
1
1
e
e
E
L
α
9.02 9.42
0.40 0.60
0.462 0.4701
0.016 0.0236
E
L
α
11.56 11.96
0.40 0.60
0.455 0.4709
0.016 0.0236
E
L
α
11.56 11.96
0.40 0.60
0.455 0.4709
0.016 0.0236
0°
5°
0°
5°
0°
8°
0°
8°
0°
8°
0°
8°
Integrated Silicon Solution, Inc.
PK13197T40 Rev. C 08/013/99
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