IS41LV8200A-50J [ISSI]
EDO DRAM, 2MX8, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28;型号: | IS41LV8200A-50J |
厂家: | INTEGRATED SILICON SOLUTION, INC |
描述: | EDO DRAM, 2MX8, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28 动态存储器 光电二极管 内存集成电路 |
文件: | 总20页 (文件大小:121K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
IS41LV8200A
ISSI
2M x 8 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
APRIL2005
FEATURES
DESCRIPTION
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs
• RefreshInterval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
The ISSI IS41LV8200A is 2,097,152 x 8-bit high-perfor-
mance CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 random ac-
cesses within a single row with access cycle time as short
as 20 ns per 4-bit word.
These features make the IS41LV8200A ideally suited for
high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral
applications.
• Lead-freeavailable
The IS41LV8200A is packaged in 28-pin 300-mil SOJ with
JEDEC standard pinouts.
PRODUCT SERIES OVERVIEW
KEY TIMING PARAMETERS
Part No.
Refresh
Voltage
IS41LV8200A
2K
3.3V ± 10%
Parameter
-50
50
14
25
20
85
-60
60
Unit
ns
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA
15
ns
)
30
ns
EDO Page Mode Cycle Time (tPC
)
25
ns
PIN CONFIGURATION
28 Pin SOJ
Read/WriteCycleTime(tRC)
104
ns
VDD
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
2
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
3
PIN DESCRIPTIONS
4
5
A0-A10
I/O0-7
WE
Address Inputs
6
Data Inputs/Outputs
Write Enable
7
8
OE
Output Enable
Row Address Strobe
Column Address Strobe
Power
A10
A0
9
A8
10
11
12
13
14
A7
RAS
CAS
VDD
A1
A6
A2
A5
A3
A4
GND
NC
Ground
VDD
GND
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
1
04/13/05
®
IS41LV8200A
ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGIC
OE
CONTROL
LOGIC
CAS
CONTROL
LOGIC
CAS
RAS
CAS
WE
OE
RAS
DATA I/O BUS
RAS
CLOCK
GENERATOR
COLUMN DECODER
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O7
MEMORY ARRAY
2,097,152 x 8
ADDRESS
BUFFERS
A0-A10
TRUTHTABLE
Function
Standby
Read
RAS
CAS
WE
X
OE
X
Address tR/tC
X
I/O
H
L
L
L
H
L
L
L
High-Z
DOUT
H
L
ROW/COL
ROW/COL
ROW/COL
Write: Word (Early Write)
Read-Write
L
X
DIN
H→L
L→H
DOUT, DIN
EDO Page-Mode Read
1st Cycle:
2nd Cycle:
L
L
H→L
H→L
H
H
L
L
ROW/COL
NA/COL
DOUT
DOUT
EDO Page-Mode Write
1st Cycle:
2nd Cycle:
L
L
H→L
H→L
L
L
X
X
ROW/COL
NA/COL
DIN
DIN
EDO Page-Mode
Read-Write
1st Cycle:
2nd Cycle:
L
L
H→L
H→L
H→L
H→L
L→H
L→H
ROW/COL
NA/COL
DOUT, DIN
DOUT, DIN
Hidden Refresh
Read
L→H→L
L→H→L
L
L
H
L
L
X
ROW/COL
ROW/COL
DOUT
DOUT
Write(1)
RAS-Only Refresh
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
CBR Refresh
H→L
Note:
1. EARLY WRITE only.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
Functional Description
Auto Refresh Cycle
The IS41LV8200A is CMOS DRAMs optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressedthroughthe
11 address bits. These are entered 11 bits (A0-A10) at a
time. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read,write,read-modify-writeorRAS-onlycyclerefreshes
the addressed row.
2. UsingaCAS-before-RAS refreshcycle.CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
columnaddressmustbeheldforaminimumtimespecified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
3
04/13/05
®
IS41LV8200A
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VT
Parameters
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
Voltage on Any Pin Relative to GND
Supply Voltage
3.3V
3.3V
VDD
V
IOUT
PD
Output Current
mA
W
Power Dissipation
Storage Temperature
1
TSTG
–55 to +125
°C
Note:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
intheoperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periodsmayaffectreliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
VIH
VIL
Supply Voltage
3.3V
3.3V
3.3V
3.0
2.0
3.3
—
3.6
VDD + 0.3
0.8
V
V
V
Input High Voltage
Input Low Voltage
–0.3
—
CAPACITANCE(1,2)
Symbol
Parameter
Max.
Unit
CIN1
CIN2
CIO
Input Capacitance: A0-A10(A11)
5
7
7
pF
pF
pF
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
VDD
Speed Min.
Max. Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ VDD
Other inputs not under test = 0V
–5
5
µA
µA
V
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ VDD
–5
2.4
—
5
VOH
VOL
IOH = –5.0 mA, VDD = 5V
IOH = –2.0 mA, VDD = 3.3V
—
0.4
IOL = 4.2 mA, VDD = 5V
IOL = 2 mA, VDD = 3.3V
V
ICC1
ICC2
ICC3
Standby Current: TTL
RAS, CAS ≥ VIH
3.3V
3.3V
—
—
1
1
mA
mA
mA
Standby Current: CMOS
RAS, CAS ≥ VDD – 0.2V
Operating Current:
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
150
140
Random Read/Write(2,3,4)
Average Power Supply Current
ICC4
ICC5
Operating Current:
RAS= VIL, CAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
150
140
mA
mA
mA
EDO Page Mode(2,3,4)
AveragePowerSupplyCurrent
RefreshCurrent:
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
150
140
RAS-Only(2,3)
AveragePowerSupplyCurrent
ICC6
RefreshCurrent:
CBR(2,3,5)
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
—
—
150
140
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
5
04/13/05
®
IS41LV8200A
ISSI
ACCHARACTERISTICS(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
tRC
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
85
—
—
—
50
30
8
—
50
14
25
10K
—
104
—
—
—
60
40
10
15
45
18
0
—
60
15
30
10K
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAC
tCAC
tAA
tRAS
tRP
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-AddressSetupTime
Row-AddressHoldTime
Column-AddressSetupTime(20)
Column-AddressHoldTime(20)
tCAS
tCP
10K
—
10K
—
8
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
45
19
0
—
—
37
—
45
—
9
—
10
0
—
0
—
—
7
—
10
55
—
Column-AddressHoldTime
44
—
—
(referencedtoRAS)
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
14
25
5
25
—
—
—
—
—
—
15
12
—
—
—
—
—
—
13
30
5
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
30
0
13
35
0
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
tCRP
tOD
5
5
5
5
tOE
Output Enable Time(15, 16)
—
8
—
13
7
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
7
8
8
OE LOW to CAS HIGH Setup Time
ReadCommandSetupTime(17, 20)
5
5
0
0
ReadCommandHoldTime
0
0
(referencedtoRAS)(12)
tRCH
ReadCommandHoldTime
0
—
0
—
ns
(referencedtoCAS)(12, 17, 21)
tWCH
tWCR
WriteCommandHoldTime(17)
8
—
—
10
50
—
—
ns
ns
WriteCommandHoldTime
40
(referencedtoRAS)(17)
tWP
Write Command Pulse Width(17)
8
7
—
—
10
7
—
—
ns
ns
tWPZ
WE Pulse Widths to Disable Outputs
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50
-60
Symbol
tRWL
Parameter
Min.
13
8
Max.
—
Min.
15
10
0
Max.
—
Units
ns
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
tCWL
—
—
ns
tWCS
tDHR
0
—
—
ns
46
15
—
55
15
—
ns
tACH
Column-Address Setup Time to CAS
—
—
ns
PrechargeduringWRITECycle
tOEH
OE Hold Time from WE during
8
—
10
—
ns
READ-MODIFY-WRITEcycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
—
—
—
—
0
10
—
—
—
—
ns
ns
ns
ns
tDH
tRWC
tRWD
READ-MODIFY-WRITECycleTime
108
64
133
79
RAS to WE Delay Time during
READ-MODIFY-WRITECycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
25
37
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
EDO Page Mode READ or WRITE
Cycle Time
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
READ-WRITE Cycle Time(24)
50
—
59
5
100K
30
60
—
63
5
100K
32
ns
ns
ns
ns
ns
tPRWC
tCOH
tOFF
—
—
Data Output Hold after CAS LOW
—
—
Output Buffer Turn-Off Delay from
0
12
0
15
CAS or RAS(13,15,19, 24)
tWHZ
tCSR
tCHR
tORD
Output Disable Delay from WE
3
10
10
0
10
—
—
—
3
10
10
0
10
—
—
—
ns
ns
ns
ns
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDENREFRESHCycle
tREF
tT
AutoRefreshPeriod
Transition Time (Rise or Fall)(2, 3)
2,048 Cycles
—
2
32
50
—
2
32
50
ms
ns
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF (VDD = 3.3V ±10%)
Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VDD = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VDD = 3.3V ±10%)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
7
04/13/05
®
IS41LV8200A
ISSI
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonicmanner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. IfCAS isLOWatthefallingedgeofRAS, dataoutwillbemaintainedfromthepreviouscycle. Toinitiateanewcycleandclearthedata
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtOD andtOEH met(OE HIGHduringWRITEcycle)inordertoensure
thattheoutputbufferswillbeopenduringtheWRITEcycle. TheI/OswillprovidethepreviouslywrittendataifCAS remainsLOWand
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or
READ-MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
READCYCLE
tRC
tRAS
tRP
RAS
CAS
tCSH
tRSH
tCAS tCLCH
tRRH
tCRP
tASR
tRCD
tAR
tRAD
tRAH
tRAL
tCAH
tASC
ADDRESS
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
(1)
tCAC
tCLC
tOFF
tOD
Open
Open
Valid Data
I/O
tOE
OE
tOES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
9
04/13/05
®
IS41LV8200A
ISSI
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
t
RWC
RAS
t
RP
RAS
CAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
t
AR
t
RAD
t
RAL
ACH
t
t
RAH
tCAH
t
ASC
t
ADDRESS
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
WE
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
t
OD
tOEH
t
OE
OE
Don’t Care
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
t
DHR
t
DH
t
DS
I/O
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
11
04/13/05
®
IS41LV8200A
ISSI
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
CAS
t
AR
t
RAD
t
RAL
CAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
ADDRESS
Row
Column
Column
Column
Row
t
RAH
t
RRH
t
RCS
t
RCH
WE
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
t
CPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
t
OE
t
OEHC
tOE
t
OD
t
OES
t
OD
t
OES
OE
t
OEP
Don’t Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RASP
t
RP
RAS
CAS
(1)
tPC / tPRWC
t
CSH
t
RSH
CLCH
t
CRP
t
RCD
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
tCP
t
AR
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
tRWD
tRCS
t
t
t
RWL
CWL
WP
t
t
CWL
WP
t
t
CWL
WP
t
AWD
t
AWD
t
AWD
t
CWD
t
CWD
t
CWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
tDS
t
t
t
CAC
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
Open
Open
I/O
DOUT
DIN
DOUT
DIN
DOUT
DIN
t
OD
t
OD
t
OD
t
OE
t
OE
tOE
t
OEH
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
13
04/13/05
®
IS41LV8200A
ISSI
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PC
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
CAS
t
AR
tACH
t
ACH
t
ACH
CAH
t
RAD
t
RAL
t
ASR
t
ASC
t
CAH
t
ASC
t
t
ASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
t
RAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
t
WCS
t
t
WCH
tWCH
t
WP
t
WP
t
WP
WE
t
WCR
DHR
tRWL
t
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
Valid Data
Valid Data
Valid Data
OE
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
t
RASP
t
RP
RAS
CAS
t
CSH
t
PC
tPC
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
t
AR
t
ACH
RAL
CAH
t
ASR
t
t
RAD
t
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
RAH
ADDRESS
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
WE
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
CAC
t
t
t
t
DS
tDH
Open
Open
I/O
Valid Data (A)
Valid Data (B)
DIN
t
OE
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
15
04/13/05
®
IS41LV8200A
ISSI
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tASR
tRCD
tCP
tCAS
CAS
tAR
tRAD
tRAH
tCAH
tRCH
tASC
tRCS
tASC
ADDRESS
Row
Column
Column
tRCS
WE
tAA
tRAC
tCAC
tCLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
tOE
tOD
OE
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
CAS
t
CRP
t
RPC
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
IS41LV8200A
ISSI
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
tRAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
CAS
Open
I/O
Don’t Care
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
tRAS
t
RP
RAS
CAS
t
CRP
t
RCD
t
RSH
tCHR
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
t
CAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
t
OE
tOD
t
ORD
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
17
04/13/05
®
IS41LV8200A
ISSI
ORDERING INFORMATION
Voltage: 3.3V
Speed(ns)
Order Part No.
Package
50
50
60
60
IS41LV8200A-50J
IS41LV8200A-50JL
IS41LV8200A-60J
IS41LV8200A-60JL
300-mil SOJ
300-milSOJ,Lead-free
300-mil SOJ
300-milSOJ,Lead-free
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
04/13/05
®
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
ISSI
N
E1
E
1
SEATING PLANE
D
A
A2
B
C
e
b
A1
E2
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusionsandshouldbemeasuredfromthebottomof
MILLIMETERS
INCHES
Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
thepackage
.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
Leads
24/26
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
17.02
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.670
0.325
0.295
0.247
2.67
0.51
0.81
0.25
17.27
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.680
0.345
0.305
0.287
B
C
D
E
E1
E2
e
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
®
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
ISSI
MILLIMETERS
INCHES
MILLIMETERS
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
28
Leads
32
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
18.29
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.720
0.325
0.295
0.247
A1
A2
b
0.64
2.41
0.41
0.66
0.20
20.83
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.820
0.325
0.295
0.247
2.67
0.51
0.81
0.25
18.54
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.730
0.345
0.305
0.287
2.67
0.51
0.81
0.25
21.08
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.830
0.345
0.305
0.287
B
B
C
C
D
D
E
E
E1
E2
e
E1
E2
e
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.D
02/25/03
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