IS42S16320F-7TLI-TR [ISSI]
IC DRAM 512M PARALLEL 54TSOP;
| 型号： | IS42S16320F-7TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC DRAM 512M PARALLEL 54TSOP 动态存储器 |
| 文件： | 总63页 (文件大小：1265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42R86400F/16320F, IS45R86400F/16320F
IS42S86400F/16320F, IS45S86400F/16320F
32Mx16, 64Mx8
512Mb SDRAM
JULY 2017
DEvIcE OvERvIEW
ISSI's 512Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
Theꢀ512MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ
FEATURES
•ꢀ Clock frequency: 200, 166, 143 MHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
PAcKAGE INFORMATION
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Powerꢀsupply:ꢀVdd/Vddq = 2.3V-3.6V
ꢀ IS42/45SxxxxxFꢀ-ꢀVdd/Vddq = 3.3Vꢀ
ꢀ IS42/45RxxxxxFꢀ-ꢀVdd/Vddq = 2.5
•ꢀ LVTTLꢀinterface
IS42/45S16320F
IS42/45S86400F
IS42/45R16320F
IS42/45R86400F
8M x 16 x 4 banks
54-pinꢀTSOP-II
54-ballꢀTF-BGA
16M x 8 x 4 banks
54-pinꢀTSOP-II
•ꢀ Programmableꢀburstꢀlengthꢀ
– (1, 2, 4, 8, full page)
KEY TIMING PARAMETERS
•ꢀ Programmableꢀburstꢀsequence:ꢀ
Sequential/Interleave
Parameter
-5
-6
-7
Unit
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ SelfꢀRefresh
•ꢀ 8Kꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCAS latency (2, 3 clocks)
ClkꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
5ꢀ
10ꢀ
ꢀ
6ꢀ
10ꢀ
ꢀ
7ꢀ
7.5ꢀ
ꢀ
nsꢀ
ns
ClkꢀFrequencyꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
200ꢀ
100ꢀ
ꢀ
ꢀ
ꢀ
167ꢀ
100ꢀ
143ꢀ
133ꢀ
Mhzꢀ
Mhz
AccessꢀTimeꢀꢀfromꢀClockꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
5ꢀ
6ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
5.4ꢀ
6ꢀ
5.4ꢀ
5.4
nsꢀ
ns
operations capability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
ADDRESS TABLE
•ꢀ Packages:ꢀ
x8/x16:ꢀ54-pinꢀTSOP-II,ꢀ54-ballꢀTF-BGAꢀ(x16ꢀonly)
Parameter
32M x 16
64M x 8
Configuration 8M x 16 x 4
banks
16M x 8 x 4
banks
•ꢀ TemperatureꢀRange:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive, A1 (-40oC to +85oC)
Bank Address BA0, BA1
Pins/Balls
BA0, BA1
Automotive, A2 (-40oC to +105oC)
Autoprecharge A10/AP
Pins/Ball
A10/AP
Row Address 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
Column
1K(A0ꢀ–ꢀA9)
2K(A0ꢀ–ꢀA9,ꢀ
Address
A11)
Refresh Count
Com./Ind./A1 8Kꢀ/ꢀ64ms
A2 8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
DEvIcE OvERvIEW
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ
Theꢀ 512Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ
random-accessꢀmemoryꢀdesignedꢀtoꢀoperateꢀinꢀeitherꢀ3.3Vꢀ
Vdd/Vddq orꢀ2.5VꢀVdd/Vddq memory systems, depending
ontheDRAMoption. Internallyconfiguredasaquad-bank
DRAM with a synchronous interface.
enabled. Precharge one bank while accessing one of the
otherthreebankswillhidetheprechargecyclesandprovide
seamless, high-speed, random-access operation.
SDRAMreadandwriteaccessesareburstorientedstarting
at a selected location and continuing for a programmed
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1ꢀselectꢀtheꢀbank;ꢀA0-A12ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ
registered are used to select the starting column location
for the burst access.
Theꢀ512MbꢀSDRAMꢀ(536,870,912ꢀbits)ꢀincludesꢀanꢀAUTOꢀ
REFRESHꢀ MODE,ꢀ andꢀ aꢀ power-saving,ꢀ power-downꢀ
mode. All signals are registered on the positive edge of
theꢀclockꢀsignal,ꢀCLK.ꢀꢀAllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀ
compatible.
Theꢀ512MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ
data at a high data rate with automatic column-address
generation, theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
A self-timed row precharge initiated at the end of the burst
FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
13
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
A10
A12
A11
A9
V
Q
CONTROLLER
16
16
A8
A7
REFRESH
COUNTER
A6
A5
8192
A4
A3
A2
A1
A0
BA0
BA1
8192
MEMORY CELL
ARRAY
8192
8192
13
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
13
13
SENSE AMP I/O GATE
1024
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
10
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
10
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
VSS
NC
DQM
CLK
CKE
A12
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DEScRIPTIONS
A0-A12
Row Address Input
WE
Write Enable
A0-A9,ꢀA11ꢀ
BA0, BA1
DQ0ꢀtoꢀDQ7ꢀ
ColumnꢀAddressꢀInput
Bank Select Address
DataꢀI/O
DQMꢀ
Vdd
DataꢀInput/OutputꢀMask
Power
Vssꢀ
Vddqꢀ
Vssqꢀ
NC
Ground
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
No Connection
Chip Select
RAS
CAS
Row Address Strobe Command
Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
VDD
VSS
DQML
WE
CAS
RAS
CS
NC
DQMH
CLK
CKE
A12
A11
A9
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DEScRIPTIONS
WE
Write Enable
A0-A12
Row Address Input
DQMLꢀ x16ꢀLowerꢀByte,ꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByte,ꢀInput/OutputꢀMask
A0-A9ꢀ
ꢀ
ColumnꢀAddressꢀInput
Bank Select Address
DataꢀI/O
BA0, BA1
Vdd
Power
DQ0ꢀtoꢀDQ15ꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NC
Ground
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
No Connection
Chip Select
RAS
CAS
Row Address Strobe Command
Column Address Strobe Command
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
PIN cONFIGURATION
54-ball TF-BGA for x16 (TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ13.00ꢀmmꢀBody,ꢀ0.8ꢀmmꢀBallꢀPitch)
package code: B
1 2 3 4 5 6 7 8 9
A
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8 NC VSS
DQMH CLK CKE
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
B
C
D
E
F
G
H
J
A12 A11
A9
A6
A4
A8
A7
A5
A0
A3
A1
A10
VSS
A2 VDD
PIN DEScRIPTIONS
A0-A12
A0-A9ꢀ
BA0, BA1
DQ0ꢀtoꢀDQ15ꢀꢀꢀꢀ DataꢀI/O
Row Address Input
ColumnꢀAddressꢀInput
Bank Select Address
WE
Write Enable
DQMLꢀ
DQMHꢀꢀꢀ
Vdd
x16ꢀLowerꢀByteꢀInput/OutputꢀMask
x16ꢀUpperꢀByteꢀInput/OutputꢀMask
Power
CLKꢀ
CKEꢀ
CS
SystemꢀClockꢀInput
ClockꢀEnable
Chip Select
Row Address Strobe Command
Vssꢀ
Ground
Vddqꢀ
Vssqꢀ
NC
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
No Connection
RAS
CAS
Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
PIN FUNcTIONS
Symbol
Type
Funꢀtion (In Detail)
A0-A12
Input Pin/Ball
ꢀ
AddressꢀInputs:ꢀA0-A12ꢀareꢀsampledꢀduringꢀtheꢀACTIVEꢀcommandꢀ(row-addressꢀ
A0-A12)ꢀandꢀREAD/WRITEꢀcommandꢀ(columnꢀaddressꢀA0-A9,ꢀA11ꢀ(x8);ꢀA0-A9ꢀ
(x16), with A10 defining auto precharge) to select one location out of the memory
arrayꢀinꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀcommandꢀtoꢀ
determineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀselectedꢀbyꢀBA0,ꢀ
BA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀLOADꢀMODEꢀ
REGISTERꢀcommand.
BA0, BA1
CAS
Input Pin/Ball
Input Pin/Ball
Input Pin/Ball
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
CKEꢀ
ꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refresh mode. CKEꢀisꢀan asynchronous input.
CLKꢀ
Input Pin/Ball
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin/Ball
TheꢀCS input determines whether command input is enabled within the device.
Command input is enabled when CSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
device remains in the previous state when CSꢀisꢀHIGH.
DQM: x8
Input Pin/Ball
ꢀ
DQxꢀpinsꢀcontrolꢀtheꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀForꢀexampleꢀwithꢀx16,ꢀinꢀreadꢀmode,
DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀLOW,ꢀthe
ꢀDQML,ꢀDQMH:ꢀx16ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀtoꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenꢀDQML/DQMHꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀ
to OEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀDQMLꢀandꢀDQMHꢀcontrolꢀtheꢀinputꢀ
buffer.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀ
andꢀdataꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀ
masked and cannot be written to the device.
DQ0-DQ7:ꢀx8ꢀ
ꢀInput/OutputꢀPin/Ballꢀ
DataꢀonꢀtheꢀDataꢀBusꢀisꢀlatchedꢀonꢀDQꢀpinsꢀduringꢀWriteꢀcommands,ꢀandꢀbufferedꢀfor
DQ0-DQ15: x16
output after Read commands.
RAS
WE
Input Pin/Ball
Input Pin/Ball
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddq
Vdd
Power Supply Pin/Ball
Power Supply Pin/Ball
Power Supply Pin/Ball
Power Supply Pin/Ball
ꢀ
ꢀ
ꢀ
ꢀ
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
Vssq is the output buffer ground.
Vssq
Vss
Vss is the device internal ground.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
GENERAL DEScRIPTION
READ
requiringꢀanꢀexplicitꢀcommand.ꢀA10ꢀtoꢀenableꢀtheꢀAUTOꢀ
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
and starts a burst read access to an active row. Inputs
A0-Anꢀ(Forꢀcolumnꢀaddresses,ꢀn=A9ꢀforꢀx16,ꢀn=A11ꢀforꢀ
x8), provides the starting column location. When A10 is
HIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀPRECHARGEꢀ
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ
whenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀselected.ꢀꢀDQ’sꢀreadꢀ
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ
later.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ
wasꢀregisteredꢀLOW.
PRECHARGEꢀfunctionꢀinꢀconjunctionꢀwithꢀaꢀspecificꢀREADꢀ
orꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀ
command, auto precharge is either enabled or disabled.
AUTOꢀPRECHARGEꢀdoesꢀnotꢀapplyꢀexceptꢀinꢀfull-pageꢀ
burstꢀ mode.ꢀ Uponꢀ completionꢀ ofꢀ theꢀ READꢀ orꢀWRITEꢀ
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH cOMMAND
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomati-
callyꢀgeneratedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ
(trc) is required for a single refresh operation, and no
otherꢀcommandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀ
commandꢀisꢀexecutedꢀatꢀleastꢀ8192ꢀtimesꢀforꢀeveryꢀTref
period.ꢀDuringꢀanꢀAUTOꢀREFRESHꢀcommand,ꢀaddressꢀ
bitsꢀareꢀ“Don’tꢀCare”.ꢀꢀThisꢀcommandꢀcorrespondsꢀtoꢀCBRꢀ
Auto-refresh.
WRITE
A burst write access to an active row is initiated with the
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀ
and the starting column location is provided by inputs A0-
Anꢀ(Forꢀcolumnꢀaddresses,ꢀn=A9ꢀforꢀx16,ꢀn=A11ꢀforꢀx8).ꢀ
AUTO-PRECHARGEꢀisꢀdeterminedꢀbyꢀA10.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ
TERMINATE.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
open for subsequent accesses.
A memory array is written with corresponding input data
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time. Data will be written to memory when DQM signal is
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/column location.
cOMMAND INHIBIT
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled
NO OPERATION
When CSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ
commands from being registered during idle or wait
states.
PREcHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bank(s) is executed after passage of the period tRP, which
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ
has been precharged, it is in the idle state and must be
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ
issued to that bank.
LOAD MODE REGISTER
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ
registerꢀisꢀloadedꢀfromꢀA0-A12.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ
be issued when all banks are idle.
AcTIvE cOMMAND
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ
inputs selects a bank to be accessed, and the address
inputsꢀonꢀA0-A12ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ
command is issued to the bank, the row remains open
for accesses.
AUTO PREcHARGE
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-
charge is initiated at the earliest valid stage within a burst.
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
cOMMAND TRUTH TABLE
cKE
A12, A11
Funꢀtion
n – 1
Hꢀꢀ
n
CS
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
RAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
CAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
WE
×ꢀꢀ
Hꢀ
BA1
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
BA0
×ꢀꢀ
×ꢀ
A10 A9 - A0
Deviceꢀdeselectꢀ(DESL)ꢀꢀ
Noꢀoperationꢀ(NOP)ꢀ ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀ
×
Hꢀꢀ
×
Burstꢀstopꢀ(BST)ꢀꢀ
Readꢀꢀ
ꢀ
ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
×ꢀꢀ
Lꢀꢀ
Hꢀ
Lꢀ
×
ꢀ
Hꢀꢀ
Vꢀ
Vꢀ
V
V
V
×
Readꢀwithꢀautoꢀprechargeꢀꢀ Hꢀꢀ
Writeꢀꢀ ꢀꢀ Hꢀꢀ
Writeꢀwithꢀautoꢀprechargeꢀꢀ Hꢀ
Bankꢀactivateꢀ(ACT)ꢀꢀꢀ Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀꢀ
Lꢀ
Hꢀ
Vꢀ
Hꢀꢀ
Vꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀ
×ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀ
ꢀVꢀꢀ
Vꢀ
Prechargeꢀselectꢀbankꢀ(PRE)ꢀ Hꢀꢀ
Prechargeꢀallꢀbanksꢀ(PALL)ꢀ Hꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Vꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀ
×
CBRꢀAuto-Refreshꢀ(REF)ꢀ
Self-Refreshꢀ(SELF)ꢀ ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×ꢀ
×
Modeꢀregisterꢀsetꢀ(MRS)ꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Vꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
DQM TRUTH TABLE
cKE
Funꢀtion
n-1
Hꢀꢀ
H
n
DQMH
Lꢀꢀ
DQML
Dataꢀwriteꢀ/ꢀoutputꢀenableꢀꢀꢀ
ꢀ
ꢀ
ꢀ
×ꢀꢀ
×
ꢀ
ꢀ
L
Data mask / output disable
H
H
×
L
Upperꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Lowerꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Upperꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
Lowerꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
ꢀ×ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
×
H
Note:
1.ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
2. x16 options shown.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
cKE TRUTH TABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CKE
CurrentꢀStateꢀ/Functionꢀꢀ
ActivatingꢀClockꢀsuspendꢀmodeꢀentryꢀꢀ
AnyꢀClockꢀsuspendꢀmodeꢀꢀ
Clockꢀsuspendꢀmodeꢀexitꢀꢀ
AutoꢀrefreshꢀcommandꢀIdleꢀ(REF)ꢀꢀ
SelfꢀrefreshꢀentryꢀIdleꢀ(SELF)ꢀꢀ
PowerꢀdownꢀentryꢀIdleꢀꢀ
nꢀ–ꢀ1ꢀꢀ nꢀꢀ
CS
×ꢀ
RAS
×ꢀꢀ
×ꢀꢀ
×ꢀ
CAS WE
Address
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀ
×
×
×
×
×
×ꢀꢀ
×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀ
ꢀ
Selfꢀrefreshꢀexitꢀꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×
ꢀ
ꢀ
Powerꢀdownꢀexitꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
FUNcTIONAL TRUTH TABLE
current State
CS
RAS CAS WE
Address
Xꢀ
command
DESLꢀꢀ
Aꢀtion
Idleꢀ
Hꢀꢀ Xꢀ
Xꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown
ILLEGALꢀ(3)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
Xꢀ
NOPꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Xꢀ
BSTꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
A,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGAL(3)
Rowꢀactivating
Nop
AutoꢀrefreshꢀorꢀSelf-refresh(4)
Modeꢀregisterꢀset
Nop
Lꢀꢀ
Lꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
OC,ꢀBA1=Lꢀꢀ
Xꢀ
RowꢀActiveꢀ
Hꢀꢀ Xꢀ
Xꢀ
DESLꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Xꢀ
NOPꢀꢀ
Nop
Hꢀꢀ
Hꢀ
Xꢀ
BSTꢀ
Nop
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀreadꢀ(5)
Beginꢀwriteꢀ(5)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Lꢀ
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
Precharge
Precharge all banks(6)
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Xꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
ꢀ
OC,ꢀBAꢀꢀ
Xꢀ
Readꢀ
Hꢀꢀ Xꢀ
DESLꢀꢀ
Continueꢀburstꢀtoꢀendꢀtoꢀꢀ ꢀ
Row active
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Xꢀ
NOPꢀꢀ
ꢀ
ContinueꢀburstꢀtoꢀendꢀꢀRowꢀꢀ
Row active
ꢀ
ꢀ
Lꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
H
Hꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
Terminateꢀburst,ꢀꢀ ꢀ
ꢀ
ꢀ
begin new read (7)
ꢀ
Lꢀ
Hꢀꢀ
Lꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
WRIT/WRITAꢀꢀ
ꢀ
Terminateꢀꢀburst,ꢀꢀꢀ
begin write (7,8)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
BA,ꢀRAꢀꢀ
ACTꢀꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
Lꢀꢀ
BA,ꢀA10ꢀꢀ
PRE/PALLꢀꢀ
Terminateꢀburstꢀꢀꢀ ꢀ
ꢀ
Precharging
ꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
ꢀ
OC,ꢀBAꢀꢀ
Xꢀ
Writeꢀ
Xꢀ
Xꢀ
DESLꢀꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
ꢀ
ꢀ
Write recovering
ꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Xꢀ
NOPꢀꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Write recovering
ꢀ
ꢀ
Lꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
Hꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
Terminateꢀburst,ꢀstartꢀreadꢀ:ꢀꢀ
Determine AP (7,8)
ꢀ
Lꢀ
Hꢀꢀ
Lꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
WRIT/WRITAꢀꢀ
ꢀ
Terminateꢀburst,ꢀnewꢀwriteꢀ:ꢀꢀ
Determine AP (7)
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
BA,ꢀRAꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
RAꢀACTꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
TerminateꢀburstꢀPrechargingꢀ(9)
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
ILLEGAL
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
10
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Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
FUNcTIONAL TRUTH TABLE continued:
current State
CS
RAS CAS
WE
Address
command
Aꢀtion
Readꢀwithꢀautoꢀ
Hꢀ
ꢀ×ꢀꢀ
×ꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
DESLꢀ
Continueꢀburstꢀtoꢀend,ꢀPrechargeꢀꢀ
Precharging
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
H
Hꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
xꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀPrecharge
ILLEGAL
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(11)
ꢀ
ꢀ
ꢀ
ꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3)
ILLEGALꢀ(11)
ILLEGAL
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Write with Auto
Precharge
ꢀ×ꢀꢀ
DESLꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
recovering with auto precharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
×ꢀꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
recovering with auto precharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(11)
ꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Prechargingꢀ
Hꢀꢀ ×ꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop, Enter idle after tRP
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
×ꢀꢀ
NOPꢀꢀ
×ꢀꢀ
BSTꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA, A10
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
ꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGAL(3)
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
NopꢀꢀEnterꢀidleꢀafterꢀtRP
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
×
ꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Row Activating
H
×
DESLꢀꢀ
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀ
H
H
×ꢀꢀ
NOPꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
BSTꢀꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
Lꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGALꢀ(3,9)
ILLEGALꢀ(3)
ILLEGAL
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
FUNcTIONAL TRUTH TABLE continued:
current State
CS
H
RAS CAS
WE
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Address
×ꢀꢀ
command
DESLꢀꢀ
NOPꢀꢀ
Aꢀtion
Write Recovering
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
ꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
ꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀCA,ꢀA10ꢀ
BA, RA
BA, A10
×ꢀꢀ
READ/READAꢀꢀ Beginꢀread (8)
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀnewꢀwrite
ILLEGALꢀ(3)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
WriteꢀRecoveringꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
withꢀAutoꢀ
×ꢀꢀ
NOPꢀꢀ
Prechargeꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
ꢀ×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(3,8,11)
ꢀ
Lꢀꢀ
Hꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Refresh
Hꢀꢀ ×ꢀꢀ
×ꢀ
DESLꢀꢀꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRC
Nop,ꢀEnterꢀidleꢀafterꢀtRC
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
NOP/BSTꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL
ꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ILLEGAL
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
ꢀ×ꢀꢀ
ILLEGAL
ModeꢀRegisterꢀ
Accessingꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
ILLEGAL
Hꢀꢀ
Lꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
NOPꢀ
Lꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/WRITEꢀꢀ ILLEGAL
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
×ꢀꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
BA,ꢀRAꢀꢀ
ꢀ
ACT/PRE/PALLꢀꢀ ILLEGALꢀ
REF/MRSꢀ
ꢀ
ꢀ
ꢀ
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Notes:
1.ꢀAllꢀentriesꢀassumeꢀthatꢀCKEꢀisꢀactiveꢀ(CKEn-1=CKEn=H).
2.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀPowerꢀDownꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
3.ꢀIllegalꢀtoꢀbankꢀinꢀspecifiedꢀstates;ꢀFunctionꢀmayꢀbeꢀlegalꢀinꢀtheꢀbankꢀindicatedꢀbyꢀBankꢀAddressꢀ(BA),ꢀdependingꢀonꢀtheꢀstateꢀofꢀ
that bank.
4.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀSelf-Refreshꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9.ꢀMustꢀmaskꢀprecedingꢀdataꢀwhichꢀdon’tꢀsatisfyꢀtDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
cKE RELATED cOMMAND TRUTH TABLE(1)
cKE
current State
Operation
n-1
Hꢀ
Lꢀ
n
CS
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
H
RAS
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
CAS
Xꢀ
Xꢀ
Hꢀ
Lꢀ
WE
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
Address
Self-Refreshꢀ(S.R.)ꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀS.R.ꢀ
Self-Refresh Recovery(2)
Self-Refresh Recovery(2)
Illegalꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
—
—
—
X
Lꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
X
MaintainꢀS.R.ꢀ
Lꢀ
Xꢀ
X
Self-Refresh Recovery Idle After trc
Idle After trc
H
ꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
ꢀ
ꢀ
Illegalꢀ
Illegalꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Begin clock suspend next cycle(5)
Begin clock suspend next cycle(5)
Illegalꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
Illegalꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Exit clock suspend next cycle(2)
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Maintainꢀclockꢀsuspendꢀ
Lꢀ
Power-Downꢀ(P.D.)ꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀP.D.ꢀ
EXITꢀP.D.ꢀ-->ꢀIdle(2)
Hꢀ
Lꢀ
ꢀ
ꢀ
Maintainꢀpowerꢀdownꢀmodeꢀ
Lꢀ
AllꢀBanksꢀIdleꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Auto-Refreshꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Self-Refresh(3)
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
—
—
—
X
Lꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Power-Down(3)
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
Anyꢀstateꢀ
other than
listedꢀaboveꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Begin clock suspend next cycle(4)
Exitꢀclockꢀsuspendꢀnextꢀcycleꢀ
Hꢀ
Hꢀ
Lꢀ
Maintainꢀclockꢀsuspendꢀ
Lꢀ
Notes:
1.ꢀHꢀ:ꢀHighꢀlevel,ꢀLꢀ:ꢀlowꢀlevel,ꢀXꢀ:ꢀHighꢀorꢀlowꢀlevelꢀ(Don’tꢀcare).
2.ꢀCKEꢀLowꢀtoꢀHighꢀtransitionꢀwillꢀre-enableꢀCLKꢀandꢀotherꢀinputsꢀasynchronously.ꢀAꢀminimumꢀsetupꢀ
timeꢀmustꢀbeꢀsatisfiedꢀbeforeꢀanyꢀcommandꢀotherꢀthanꢀEXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4.ꢀMustꢀbeꢀlegalꢀcommandꢀasꢀdefinedꢀinꢀOperativeꢀCommandꢀTable.
5. Illegal if txsr is not satisfied.
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
STATE DIAGRAM
Self
Refresh
SELF
SELF exit
REF
Mode
Register
Set
MRS
CBR (Auto)
Refresh
IDLE
CKE
CKE
ACT
Power
Down
CKE
Active
Power
Down
Row
Active
CKE
BST
Write
BST
Read
Auto Prech
Write
Read
arge
Read
CKE
CKE
CKE
WRITE
SUSPEND
READ
SUSPEND
READ
WRITE
Write
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
CKE
Precharge
POWER
ON
Precharge
Automatic sequence
Manual Input
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vdd maxꢀ
Vddq max
Vinꢀ
Parameters
Rating
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–1.0ꢀtoꢀVddqꢀ+ꢀ0.5ꢀ
1
Unit
V
V
V
V
W
mA
°C
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
Allowable Power Dissipation
output Shorted Current
operatingꢀTemperatureꢀ
ꢀ
ꢀ
ꢀ
Voutꢀ
Pd max
Ics
50
ꢀ
Topr
Com.
Ind.
A1
0 to +70
-40 to +85
-40 to +85
-40 to +105
A2
ꢀ
Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–65ꢀtoꢀ+150ꢀ
°C
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
Dc REcOMMENDED OPERATING cONDITIONS
IS42/45S86400F, IS42/45S16320F - 3.3v Operation
Symbol Parameters
Min.
3.0
3.0
2.0
-0.3
-5
-5
2.4
–
Typ.
3.3
3.3
–
–
–
–
–
–
Max.
3.6
3.6
Unit
V
V
V
V
µA
µA
V
Vdd
SupplyꢀVoltage
Vddq
I/OꢀSupplyꢀVoltage
InputꢀHighꢀVoltage
InputꢀLowꢀVoltage
(1)
Vih
Vddq+0.3
0.8
(2)
Vil
Iil
InputꢀLeakageꢀCurrentꢀ(0Vꢀ≤ Vin ≤ꢀVdd)
OutputꢀLeakageꢀCurrentꢀ(Outputꢀdisabled,ꢀ0Vꢀ≤ Vout ≤ Vdd)
OutputꢀHighꢀVoltageꢀCurrentꢀ(Iohꢀ=ꢀ-2mA)
OutputꢀLowꢀVoltageꢀCurrentꢀ(Iolꢀ=ꢀ2mA)
+5
+5
–
0.4
Iol
Voh
Vol
V
IS42/45R86400F, IS42/45S16320F - 2.5v Operation
Symbol
Vdd
Vddq
Parameters
SupplyꢀVoltage
I/OꢀSupplyꢀVoltage
InputꢀHighꢀVoltage
Min.
2.3
2.3
2.0
-0.3
-5
-5
Typ.
Max.
2.7
2.7
Unit
V
V
V
V
µA
µA
V
2.5
2.5
-
-
–
–
–
–
(1)
Vih
Vil
Vddq+0.3
0.55
+5
(2)
InputꢀLowꢀVoltage
Iil
InputꢀLeakageꢀCurrentꢀ(0Vꢀ≤ Vin ≤ꢀVdd)
OutputꢀLeakageꢀCurrentꢀ(Outputꢀdisabled,ꢀ0Vꢀ≤ Vout ≤ Vdd)
OutputꢀHighꢀVoltageꢀCurrentꢀ(Iohꢀ=ꢀ-2mA)
OutputꢀLowꢀVoltageꢀCurrentꢀ(Iolꢀ=ꢀ2mA)
Iol
Voh
Vol
+5
-
0.2
Vddq-0.2
-
V
Notes:
1. Vih (overshoot): Vih (max) = Vddq +1.2V (pulse width < 3ns).
2. Vil (undershoot): Vil (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
cAPAcITANcE cHARAcTERISTIcS(1) (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVddꢀ=ꢀVddq =ꢀ3.3ꢀ±ꢀ0.3V,ꢀfꢀ=ꢀ1MHz)
Symbol
Cin1ꢀ
Parameter
Min.
2.5ꢀ
2.5ꢀ
4.0ꢀ
Max.
Unit
pF
pF
InputꢀCapacitance:ꢀCLKꢀ
InputꢀCapacitance:Allꢀotherꢀinputꢀpinsꢀ
DataꢀInput/OutputꢀCapacitance:ꢀDQSꢀ
3.5ꢀ ꢀ
3.8ꢀ ꢀ
6.0ꢀ ꢀ
ꢀ
ꢀ
ꢀ
Cin2ꢀ
Ci/oꢀ
pF
Note:ꢀ1.ꢀ Theꢀparameterꢀisꢀcharacterized.
THERMAL RESISTANcE
Package
Substrate
Theta-ja
Theta-ja
Theta-ja
Theta-jc
Units
(Airflow = 0m/s) (Airflow = 1m/s) (Airflow = 2m/s)
Alloy42 TSOP2(54)
Copper TSOP2(54)
BGA(54)
4-layer
4-layer
4-layer
56.1
37.1
38.5
49.6
32.1
32.8
46.2
29.9
31.2
8.1
7.1
4.9
C/W
C/W
C/W
Dc ELEcTRIcAL cHARAcTERISTIcS
(RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test condition
-5
-6
-7
Unit
i
dd1 (1)
ꢀ
OperatingꢀCurrentꢀ
Oneꢀbankꢀactive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
140ꢀ ꢀꢀꢀꢀꢀꢀ120ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ110ꢀꢀ
ꢀ
ꢀ
mA
tclkꢀ=ꢀtclk (min), trcꢀ=ꢀtrc (min)
i
i
i
dd2p
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil
(In Power-Down Mode)
(max), tckꢀ=ꢀ15nsꢀ
ꢀ
4ꢀ
4
ꢀꢀꢀꢀꢀꢀ4ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ4ꢀ ꢀ
mA
mA
mA
dd2ps
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil
(In Power-Down Mode)
(max),ꢀCLKꢀ≤ Vil
(
max
)
4
4
(2)
dd2n
Precharge Standby Current
(In Non Power-Down Mode)
Precharge Standby Current
CS ≥ Vccꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
ckꢀ=ꢀ15ns
CS ≥ Vccꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
(
min
)
25
25
25
t
I
I
I
i
I
i
dd2ns
(min) or
15
8ꢀ
15
15
mA
mA
mA
mA
mA
mA
(In Non Power-Down Mode) CKEꢀ≤ Vil
(max), All inputs stable
dd3p
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
(Power-Down Mode)
CKEꢀ≤ Vil
CKEꢀ≤ Vil
(
max), tckꢀ=ꢀ15nsꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀ8ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ8ꢀ ꢀ
ꢀ
dd3ps
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
(Power-Down Mode)
(max),ꢀCLKꢀ≤ Vil
(
max
)
8
8
8
(2)
dd3n
Active Standby Current
(In Non Power-Down Mode)
Active Standby Current
CS ≥ Vccꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
ckꢀ=ꢀ15ns
CS ≥ Vccꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
(
min
)
35
20
35
20
35
20
t
dd3ns
(min) or
(In Non Power-Down Mode) CKEꢀ≤ Vil
(max), All inputs stable
dd4
ꢀ
OperatingꢀCurrentꢀ
Allꢀꢀbanksꢀactive,ꢀBLꢀ=ꢀ4,ꢀCLꢀ=ꢀ3,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
200ꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀ180ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ150ꢀ
ꢀ
tckꢀ=ꢀtck (min)
i
i
dd5
dd6
Auto-Refresh Current
t
rcꢀ=ꢀtrc (min), tclkꢀ=ꢀtclk (min)
160
6
145
6
140
6
mA
mA
ꢀ
Self-RefreshꢀCurrentꢀ
CKEꢀ≤ 0.2V
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3.ꢀꢀAllꢀvaluesꢀapplicableꢀforꢀoperationꢀwithꢀTa ≤ 85°C.
4.ꢀForꢀA2ꢀtemperatureꢀgradeꢀwithꢀTa > 85°C: IDD2P and IDD2PS are derated to 50% above the values; IDD3P and IDD3PS are
derated to 30% above the values.
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
Ac ELEcTRIcAL cHARAcTERISTIcS (1,2,3)
-5
-6
Min.
-7
Symbol Parameter
Min.
Max.
Max.
Min. Max. Units
tck3ꢀ
tck2
ClockꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
5ꢀ
10ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
6ꢀꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
10ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ꢀꢀ 7ꢀꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ns
ns
ꢀ
ꢀ7.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀ
tac3ꢀ
tac2
AccessꢀTimeꢀFromꢀCLKꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.0ꢀ
6ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀ5.4ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀꢀ6ꢀ
ꢀ
ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀ5.4ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀ5.4ꢀ
ns
ns
tchꢀ
tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
ꢀ
2ꢀꢀꢀꢀꢀꢀꢀ —ꢀ
2.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ꢀ2.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ꢀꢀꢀꢀꢀ2ꢀ .5ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ns
ns
2ꢀ
ꢀ
—ꢀ
ꢀ
2.5ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
toh3ꢀ
toh2
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ2.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀ
2.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ꢀ
ꢀ
2.5ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
2.5ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
ns
ns
tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
5ꢀ
0ꢀꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
—ꢀꢀꢀꢀꢀꢀꢀ5.4ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀꢀ6ꢀꢀ
ꢀ1.5ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
1.5ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
1.5ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
1.5ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀ—ꢀꢀ
60ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
42ꢀꢀꢀꢀꢀ100Kꢀ
18ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
18ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
12ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
12ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
ꢀ
ꢀ
ꢀ
0ꢀꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀ5.4ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀ5.4ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
thz3ꢀ
thz2ꢀ
tdsꢀ
OutputꢀHIGHꢀImpedanceꢀTimeꢀ
ꢀ
—ꢀ
—ꢀ
6ꢀ
InputꢀDataꢀSetupꢀTime(2)
InputꢀDataꢀHoldꢀTime(2)
AddressꢀSetupꢀTime(2)
AddressꢀHoldꢀTime(2)
CKEꢀSetupꢀTime(2)
CKEꢀHoldꢀTime(2)
ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
55ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
1.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
1.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
1.5ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
0.8ꢀꢀꢀꢀꢀꢀꢀ—ꢀꢀ
60ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
tdhꢀ
ꢀ
tasꢀ
ꢀ
tahꢀ
ꢀ
tcksꢀ
tckhꢀ
tcmsꢀ
tcmhꢀ
trcꢀ
ꢀ
ꢀ
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE, DQM)(2)
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE, DQM)(2)
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
trasꢀ
trpꢀ
40ꢀ ꢀ 100Kꢀ
37
100K
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
15ꢀ
15ꢀ
10ꢀ
10ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
15ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
14ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
14ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
trcdꢀ
trrdꢀ
tdplꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ ꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
ꢀ
ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
Command Delay time
tdalꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
ꢀ
25ꢀ
ꢀ
—ꢀ
30
—ꢀꢀ
30
—
ns
Command Delay time (During Auto-Precharge)
tmrd
tdde
txsr
ttꢀ
ModeꢀRegisterꢀProgramꢀTimeꢀ
PowerꢀDownꢀExitꢀSetupꢀTimeꢀ
Self-RefreshꢀExitꢀTimeꢀ
TransitionꢀTimeꢀ
RefreshꢀCycleꢀTimeꢀ(8192)ꢀ Ta ≤ 70oCꢀCom,ꢀInd,ꢀA1,ꢀA2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
12ꢀꢀꢀꢀꢀꢀ—ꢀ ꢀ
6ꢀ ꢀꢀꢀꢀꢀ—ꢀ ꢀ
70ꢀꢀꢀꢀꢀꢀ—ꢀ ꢀ
0.3ꢀꢀꢀꢀꢀ1.2ꢀꢀ
14ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
7ꢀꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
67ꢀꢀꢀꢀꢀꢀꢀꢀ—ꢀ
0.3ꢀꢀꢀꢀꢀꢀꢀ1.2ꢀ
ns
ns
ns
ns
60ꢀ
0.3ꢀ
—ꢀ
1.2ꢀ
trefꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
64ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
64ꢀ
64ꢀ
—ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀꢀ 64ꢀ
ꢀ—ꢀꢀꢀꢀꢀꢀꢀ ꢀ64ꢀ
—ꢀꢀꢀꢀꢀꢀꢀꢀꢀ 16ꢀ
msꢀ
msꢀ
ms
Ta ≤ 85oCꢀInd,ꢀA1,ꢀA2ꢀ
Ta > 85oCꢀA2ꢀ
Notes:
1.ꢀ Theꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2. measured with tt =ꢀ1ꢀns.ꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(tt /2 - 0.5) ns should be added to the parameter.
3. ꢀTheꢀreferenceꢀlevelꢀisꢀ1.4Vꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih(min.)ꢀandꢀVil
(max).
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
OPERATING FREQUENcY / LATENcY RELATIONSHIPS
SYMBOL PARAMETER
-5
5ꢀ
-6
6ꢀ
-7
7ꢀ
-7
UNITS
ns
—ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
ꢀ
7.5ꢀ
133ꢀ
ꢀ—ꢀ
OperatingꢀFrequencyꢀ
200ꢀ
167ꢀ
143ꢀ
MHz
tcac
trcdꢀ
trac
CASꢀꢀLatencyꢀ
ꢀ
3ꢀ
3ꢀ
3ꢀ
3ꢀ
3ꢀ
3ꢀ
2ꢀ
2ꢀ
cycle
cycle
cycleꢀ
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(trcd + tcac)
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
6ꢀ
—ꢀ
6ꢀ
—ꢀ
6ꢀ
—ꢀ
—ꢀ
4
trc
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
11ꢀ
8ꢀ
10ꢀ
7ꢀ
9ꢀ
6ꢀ
3ꢀ
2ꢀ
1ꢀ
8ꢀ
5ꢀ
2ꢀ
2ꢀ
1ꢀ
cycle
cycle
cycle
cycle
cycle
trasꢀ
trpꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
3ꢀ
3ꢀ
trrdꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
2ꢀ
2ꢀ
tccdꢀ
ꢀꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
1ꢀ
1ꢀ
tdplꢀ
tdalꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
2ꢀ
4ꢀ
cycle
cycle
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(During Auto-Precharge)
trbd
twbdꢀ
trql
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime CASꢀꢀLatencyꢀ=ꢀ3ꢀ
3ꢀ
ꢀ—ꢀ
3ꢀ
—ꢀ
3ꢀ
—ꢀ
—ꢀ
2ꢀ
cycle
cycle
cycle
cycle
cycleꢀ
(Read)
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀꢀ
(Write)
0ꢀ
0ꢀ
0ꢀ
0ꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime CASꢀꢀLatencyꢀ=ꢀ3ꢀ
3ꢀ
—ꢀ
3ꢀ
—ꢀ
3ꢀ
—ꢀ
—ꢀ
2ꢀ
(Read)
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
twdlꢀ
tpql
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀꢀ
(Write)
0ꢀ
0ꢀ
0ꢀ
0ꢀ
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read) CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
-2ꢀ
—ꢀ
-2ꢀ
—ꢀ
–2ꢀ
—ꢀ
—ꢀ
-1ꢀ
tqmdꢀ
tdmdꢀ
tmrdꢀ
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
cycle
cycle
cycle
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
Note: Settings follow AC Electrical Characteristics on previous page.
18
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Rev. B1
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IS42/45R86400F/16320F IS42/45S86400F/16320F
Ac TEST cONDITIONS: 3.3v
Input Load
Output Load
tCK
t
CH
tCL
3.0V
1.4V
CLK
0V
1.4V
t
CMS
tCMH
3.0V
1.4V
50Ω
Z = 50Ω
INPUT
Output
0V
50 pF
t
AC
t
OH
OUTPUT
1.4V
1.4V
Ac TEST cONDITIONS
IS42/45Sxxxxx
Rating
IS42/45Rxxxxx
Rating
Parameter
ACꢀInputꢀLevelsꢀꢀ
0Vꢀtoꢀ3.0Vꢀ
1ꢀnsꢀ
0Vꢀtoꢀ2.5V
1ꢀns
ꢀ
ꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
InputꢀTimingꢀReferenceꢀLevelꢀ
OutputꢀTimingꢀMeasurementꢀReferenceꢀLevelꢀ
1.4Vꢀ
1.4Vꢀ
1.25V
1.25V
Ac TEST cONDITIONS: 2.5v
Input Load
Output Load
t
CK
tCL
t
CH
2.5V
1.25V
1.25V
CLK
0.0V
50Ω
Z = 50Ω
t
CMS
t
CMH
Output
2.5V
1.25V
0.0V
50 pF
INPUT
t
AC
t
OH
1.25V
1.25V
OUTPUT
Integrated Silicon Solution, Inc. — www.issi.comꢀ
19
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
Initialization
FUNcTIONAL DEScRIPTION
SDRAMs must be powered up and initialized in a
predefined manner.
Theꢀ512MbꢀSDRAMsꢀareꢀquad-bankꢀDRAMsꢀwhichꢀoper-
ateꢀatꢀ3.3Vꢀorꢀ2.5Vꢀandꢀincludeꢀaꢀsynchronousꢀinterfaceꢀ
(all signals are registered on the positive edge of the clock
signal,ꢀCLK).ꢀ
Theꢀ512MbꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ
toꢀVddꢀandꢀVddq (simultaneously) and the clock is stable
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorꢀWRITEꢀ
command.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀ
ACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀ
be accessed (BA0 and BA1 select the bank, A0-A12 select the
row).ꢀTheꢀaddressꢀbitsꢀA0-An; registered coincident with the
READꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀ
column location for the burst access.
A 100µs delay is required prior to issuing any command
other than a COMMANDꢀINHIBIT or a NOP.ꢀTheꢀCOMMANDꢀ
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100usꢀperiodꢀandꢀ
should continue at least through the end of the period.
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ
be applied once the 100µs delay has been satisfied. All
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀanꢀ
idle state after which at least two AUTOꢀREFRESH cycles
must be performed. After the AUTOꢀREFRESH cycles are
complete, the SDRAM is then ready for mode register
programming.
Prior to normal operation, the SDRAM must be initial-
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ
covering device initialization, register definition, command
descriptions and device operation.
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ
any operational command because it will power up in an
unknown state.
20
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Rev. B1
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IS42/45R86400F/16320F IS42/45S86400F/16320F
INITIALIꢁE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
To+1
t
CL
Tp+1
Tp+2
Tp+3
tCK
t
CH
CLK
CKE
tCKS t
CKH
tCMS
tCMH
t
CMS
tCMH
tCMS tCMH
AUTO
REFRESH
AUTO
Load MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
REFRESH
DQM/
DQML, DQMH
t
t
AS
tAH
A0-A9, A11, A12
A10
ROW
ROW
BANK
CODE
AS
tAH
ALL BANKS
CODE
SINGLE BANK
ALL BANKS
t
AS
tAH
BA0, BA1
DQ
CODE
t
RP
t
RC
t
RC
tMRD
T
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
and CLK stable all banks
At least 2 Auto-Refresh Commands
DON'T CARE
T = 100µs Min.
Notes:
1. If CSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.
3. JEDEC and PC100 specify three clocks.
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.
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21
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
AUTO-REFRESH cYcLE
T0
T1
T2
Tn+1
To+1
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11, A12
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
t
AS
tAH
High-Z
t
RP
t
RC
t
RC
DON'T CARE
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
22
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Rev. B1
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IS42/45R86400F/16320F IS42/45S86400F/16320F
SELF-REFRESH cYcLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
t
CH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
≥ tRAS
t
CKS
t
CMS
tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11, A12
A10
ALL BANKS
SINGLE BANK
tAS
tAH
BA0, BA1
DQ
BANK
High-Z
tRP
tXSR
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
Notes:
1.ꢀꢀSelf-RefreshꢀmodeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ+85oC.
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23
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀ
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst(sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10,ꢀM11,ꢀ
and M12 are reserved for future use.
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
until it is programmed again or the device loses power.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle, and the controller must wait the specified time before
initiatingꢀtheꢀsubsequentꢀoperation.ꢀViolatingꢀeitherꢀofꢀtheseꢀ
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
All Other States Reserved
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A12, A11, A10 = "0"
1
24
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Rev. B1
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IS42/45R86400F/16320F IS42/45S86400F/16320F
BURST LENGTH
reached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-Anꢀwhenꢀtheꢀ
ReadandwriteaccessestotheSDRAMareburstoriented,
with the burst length being programmable, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-
mines the maximum number of column locations that can
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ
command to generate arbitrary burst lengths.
burst length is set to two; by A2-An when the burst length
is set to four; and by A3-An when the burst length is set
toꢀeight,ꢀwhereꢀAnꢀ=ꢀA9ꢀforꢀx16,ꢀandꢀAnꢀ=ꢀA11ꢀforꢀx8.ꢀTheꢀ
remaining (least significant) address bit(s) is (are) used
toꢀselectꢀtheꢀstartingꢀlocationꢀwithinꢀtheꢀblock.ꢀFull-pageꢀ
bursts wrap within the page if the boundary is reached.
BurstꢀType
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
Reservedstatesshouldnotbeused,asunknownoperation
or incompatibility with future versions may result.
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ
the burst length, the burst type and the starting column
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ
columnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
BURST DEFINITION
Burst
Starting column
Address
Order of Aꢀꢀesses Within a Burst
Length
Type = Sequential
Type = Interleaꢂed
A 0
2
4
0
1
0-1
1-0
0-1
1-0
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A 2
0
A 1
0
A 0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ꢀ
ꢀ
Fullꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...
…Cn - 1,
ꢀ
ꢀ
ꢀ
Pageꢀ nꢀ=ꢀA0-A9ꢀ(x16)ꢀ ꢀ
(y) nꢀ=ꢀA0-A9,ꢀA11ꢀ(x8)
(location 0-y)
Cn…
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Rev. B1
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IS42/45R86400F/16320F IS42/45S86400F/16320F
cAS Latenꢀy
Operating Mode
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ
the registration of a READ command and the availability of
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ
three clocks.
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ
to zero; the other combinations of values for M7 and M8 are
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycle time is such that all relevant access times are met,
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
is programmed to two clocks, the DQs will start driving
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀTheꢀAllowableꢀOperatingꢀFrequencyꢀ
table indicates the operating frequencies at which each
CAS latency setting can be used.
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
cAS Latenꢀy
Allowable Operating Frequenꢀy (MHz)
Speed
cAS Latenꢀy = 2
cAS Latenꢀy = 3
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
-5
100
100
133
200
167
143
-6
-7
cAS LATENcY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
DOUT
t
LZ
tOH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
DOUT
t
LZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
26
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AcTIvATING SPEcIFIc ROW WITHIN SPE-
cIFIc BANK
cHIP OPERATION
BANK/ROW AcTIvATION
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ
to a bank within the SDRAM, a row in that bank must be
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
CLK
HIGH
CKE
CS
After opening a row (issuingꢀanꢀACTIVEꢀcommand), a READ
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ
entered.ꢀForꢀexample,ꢀaꢀtrcd specification of 15ns with a
143MHzclock(7nsperiod)resultsin2.14clocks, rounded
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[trcd (MIN)/tck] ≤ꢀ3.ꢀ(Theꢀsameꢀ
procedure is used to convert other specification limits from
time units to clock cycles).
RAS
CAS
WE
A0-A12
BA0, BA1
ROW ADDRESS
BANK ADDRESS
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ
same bank can only be issued after the previous active
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ
same bank is defined by trc.
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ
issuedwhilethefirstbankisbeingaccessed, whichresults
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ
different banks is defined by trrd.
EXAMPLE: MEETING TRcD (MIN) WHEN 2 < [TRcD (MIN)/TcK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
t
RCD
DON'T CARE
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READS
READ cOMMAND
READ bursts are initiated with a READ command, as
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.
CLK
CKE
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theREADcommand,andautoprechargeiseitherenabledor
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-
lowing illustrations, auto precharge is disabled.
HIGH
CS
RAS
During READ bursts, the valid data-out element from the
starting column address will be available following the
CAS latency after the READ command.Each subsequent
data-out element will be valid by the next positive clock
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtiming
for each possible CAS latency setting.
CAS
WE
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9, A11
A12
Data from any READ burst may be truncated with a sub-
sequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note:
x16: A11 is "Don't Care"
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesbefore
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shown in Consecutive READ Bursts for CAS latencies of
two and three; data element n + 3 is either the last of a
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀTheꢀ512Mbꢀ
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architec-
ture.A READ command can be initiated on any clock cycle
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ
read accesses can be performed to the same bank, as
shown in Random READ Accesses, or each subsequent
READ may be performed to a different bank.
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ
command (DQM latency is two clocks for output buffers)
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ
command that truncated the READ command. If not, the
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ
be invalid.
Data from any READ burst may be truncated with a sub-
sequentꢀ WRITEꢀ command,ꢀ andꢀ dataꢀ fromꢀ aꢀ fixed-lengthꢀ
READ burst may be immediately followed by data from a
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-
mediately following the last (or last desired) data element
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ
avoided. In a given system design, there may be a pos-
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ
a single-cycle delay should occur between the last read
dataꢀandꢀtheꢀWRITEꢀcommand.
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked.
Afixed-lengthREADburstmaybefollowedby,ortruncated
with, aPRECHARGE commandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
sameꢀbank.ꢀTheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ
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diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequent command to the same bank cannot be issued
until trp is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
and address buses be available at the appropriate time to
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.ꢀTheꢀBURSTꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cycles before
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleCASlatency;dataelementn+3isthelastdesired
data element of a longer burst.
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RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
D
OUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
DON'T CARE
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cONSEcUTIvE READ BURSTS
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 3
DON'T CARE
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RANDOM READ AccESSES
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
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READ BURST TERMINATION
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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ALTERNATING BANK READ AccESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11, A12
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
tLZ
tOH
tOH
tOH
tOH
t
OH
DQ
D
OUT
m
D
OUT m+
1
DOUT m+
2
DOUT m+
3
DOUT
b
t
AC
t
AC
t
AC
t
AC
tAC
t
AC
t
t
t
t
RCD - BANK 0
RRD
CAS Latency - BANK 0
t
RP - BANK 0
tRCD - BANK 0
t
RCD - BANK 3
CAS Latency - BANK 3
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
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READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
READ
CMS CMH
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
tAC
tAC
t
AC
t
AC
t
AC
t
AC
tHZ
DQ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+
1
t
LZ
t
OH
t
OH
t
OH
tOH
tOH
tOH
t
RCD
CAS Latency
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1) CAS latency = 2, Burst Length = Full Page
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
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READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
tOH
t
OH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
tLZ
tLZ
tHZ
tAC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1) CAS latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
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READ to PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
RQL
High-Z
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
t
RQL
High-Z
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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WRITES
AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ
shownꢀinꢀWRITEꢀCommandꢀdiagram.
n + 1 is either the last of a burst of two or the last desired
ofꢀaꢀlongerꢀburst.ꢀTheꢀ512MbꢀSDRAMꢀusesꢀaꢀpipelinedꢀ
architecture and therefore does not require the 2n rule as-
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ
can be initiated on any clock cycle following a previous
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ
a page can be performed to the same bank, as shown in
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ
be performed to a different bank.
WRITE cOMMAND
CLK
HIGH
CKE
CS
RAS
CAS
WE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstmaybeimmediatelyfollowedbyasubsequentREAD
command.ꢀOnceꢀtheꢀREADꢀcomꢀmandꢀisꢀregistered,ꢀtheꢀ
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
same bank (provided that auto precharge was not acti-
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtdpl after the
clock edge at which the last desired input data element
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtdpl of
at least one clock plus time, regardless of frequency. In
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ
must be used to mask input data for the clock edge prior
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-
CHARGEꢀdiagram.ꢀDataꢀn+1 is either the last of a burst
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ
same bank cannot be issued until trp is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9, A11
A12
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note:
x16: A11 is "Don't Care"
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ
following illustrations, auto precharge is disabled.
Inthecaseofafixed-lengthburstbeingexecutedtocomple-
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRECHARGEcommand
is that it requires that the command and address buses be
availableattheappropriatetimetoissuethecommand;the
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ
used to truncate fixed-length or full-page bursts.
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-in element will be
registeredcoincidentwiththeWRITEꢀcommand.Subsequent
data elements will be registered on each successive posi-
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ
assuming no other commands have been initiated, the
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-
tinue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ
will be the input data applied one clock previous to the
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ
BurstꢀTermination,ꢀwhereꢀdataꢀn is the last desired data
element of a longer burst.
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ
data provided coincident with the new command applies to
the new command.
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WRITE BURST
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE TO WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
RANDOM WRITE cYcLES
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
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WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PREcHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
D
IN n+1
DIN n+2
DON'T CARE
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WP2 - WRITE to PREcHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
ADDRESS
DQ
PRECHARGE
WRITE
NOP
NOP
NOP
NOP
ACTIVE
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
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WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
tDS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
t
DS
t
DH
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
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WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
DIN
m
DIN m+
2
D
IN m+3
DQ
tRCD
DON'T CARE
Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
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ALTERNATING BANK WRITE AccESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12
A10
ROW
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
DQ
DIN m
DIN m+1
DIN m+2
DIN m+3
DIN b
DIN b+1
DIN b+2
DIN b+3
tRCD - BANK 0
tRRD
tDPL - BANK 0
tRCD - BANK 1
tRP - BANK 0
t
RCD - BANK 0
tDPL - BANK 1
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
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cLOcK SUSPEND
of a suspended internal clock edge is ignored; any data
Clock suspend mode occurs when a column access/burst
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ
the synchronous logic.
present on the DQ pins remains driven;and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ
the internal clock and related operation will resume on the
subsequent positive clock edge.
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ
Any command or data present on the input pins at the time
clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
D
IN
n
DIN n+1
DIN n+2
DON'T CARE
clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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cLOcK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCKS tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN n(2)
A0-A9, A11, A12
A10
COLUMN m(2)
tAS tAH
tAS tAH
BA0, BA1
BANK
BANK
tDS tDH
tAC
tAC
tHZ
DQ
DOUT
m
D
OUT m+1
DIN e
DIN e+1
t
LZ
tOH
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled.
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
46
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IS42/45R86400F/16320F IS42/45S86400F/16320F
PREcHARGE
PREcHARGE command
TheꢀPRECHARGEꢀcommandꢀ(seeꢀfigure)ꢀisꢀusedꢀtoꢀdeac-
tivate the open row in a particular bank or the open row in
allꢀbanks.ꢀTheꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀ
access some specified time (trp)ꢀafterꢀtheꢀPRECHARGEꢀ
command is issued.Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare.”ꢀOnceꢀaꢀbankꢀhasꢀbeenꢀ
precharged, it is in the idle state and must be activated
priorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀ
that bank.
CLK
HIGH
CKE
CS
RAS
CAS
WE
POWER-DOWN
Power-downꢀoccursꢀifꢀCKEꢀisꢀregisteredꢀLOWꢀcoincidentꢀ
withꢀaꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀwhenꢀnoꢀaccessesꢀ
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers,ꢀexcludingꢀCKE,ꢀforꢀmaximumꢀpowerꢀsavingsꢀwhileꢀ
inꢀstandby.ꢀTheꢀdeviceꢀmayꢀnotꢀremainꢀinꢀtheꢀpower-downꢀ
stateꢀlongerꢀthanꢀtheꢀrefreshꢀperiodꢀ(TREF)ꢀsinceꢀnoꢀrefreshꢀ
operations are performed in this mode.
A0-A9, A11, A12
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
Theꢀpower-downꢀstateꢀisꢀexitedꢀbyꢀregisteringꢀaꢀNOPꢀorꢀ
COMMANDꢀINHIBITꢀandꢀCKEꢀHIGHꢀatꢀtheꢀdesiredꢀclockꢀ
edge (meeting tcks). See figure "Power-Down".
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
tRCD
tRAS
t
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than 64ms
DON'T CARE
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POWER-DOWN MODE cYcLE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS
t
CKH
t
CKS
tCKS
t
CMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/DQML
DQMH
A0-A9, A11, A12
A10
ROW
ROW
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
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BURST READ/SINGLE WRITE
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occurs are defined below.
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ
=ꢀ0).
READ with Auto Preꢀharge
1.Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n,
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
begin when the READ to bank m is registered.
cONcURRENT AUTO PREcHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
whenregistered.DQMshouldbeusedthreeclocksprior
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bank m is registered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSI
READ With Auto Preꢀharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK n,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Preꢀharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tDPL - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
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WRITE with Auto Preꢀharge
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
WRITE tobankmwillinterruptaWRITE onbanknwhen
3.Interrupted by a READ (with or without auto precharge):
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀwhenꢀ
registered, with the data-out appearing (CAS latency)
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtdpl
is met, where tdpl begins when the READ to bank m is
registered.ꢀTheꢀlastꢀvalidꢀWRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ
tdpl is met, where tdplꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ
bank m.
WRITE With Auto Preꢀharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Preꢀharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
t
RP - BANK n
Internal States
tDPL - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
SINGLE READ WITH AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tOH
tAC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
t
RP
Notes:
1) CAS latency = 2, Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
51
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
SINGLE READ WITHOUT AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
tCMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
ROW
A0-A9, A11, A12
A10
ROW
AS
tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
AS
tAH
BA0, BA1
BANK
BANK
BANK
BANK
tDS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
DPL(3)
t
RP
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
52
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
READ WITH AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tOH
t
OH
tOH
tOH
t
t
t
RCD
RAS
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
53
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
READ WITHOUT AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11, A12
A10
ROW
ROW
ROW
BANK
AS
tAH
ROW
AS
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
DOUT m+1
DOUT m+2
DOUT m+3
t
LZ
tOH
tOH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
SINGLE WRITE WITH AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS tCMH
NOP(3)
NOP(3)
NOP(3)
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
tWR
tRP
DON'T CARE
Notes:
1) Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
55
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
SINGLE WRITE - WITHOUT AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN m(2)
ROW
A0-A9, A11, A12
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
tAS tAH
BA0, BA1
BANK
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tDPL(3)
tRP
tRAS
tRC
DON'T CARE
Notes:
1) Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
3) tras must not be violated.
56
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
WRITE - WITH AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11, A12
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tDS
t
DH
tDS
t
DH
t
DS
tDH
tDS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
DPL
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
57
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
WRITE - WITHOUT AUTO PREcHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
tCMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
tCMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
ROW
A0-A9, A11, A12
A10
ROW
AS
tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
AS
tAH
BA0, BA1
BANK
BANK
BANK
BANK
tDS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
DPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
3) tras must not be violated.
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
ORDERING INFORMATION - vDD = 2.5v for x16
commerꢀial Range: 0oc to +70oc
Frequenꢀy
Speed (ns)
Order Part No.
Paꢀkage
167 MHz
6
IS42R16320F-6TL
IS42R16320F-6BL
IS42R16320F-7TL
IS42R16320F-7BL
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
143 MHz
7
Industrial Range: -40oc to +85oc
Frequenꢀy
Speed (ns)
Order Part No.
Paꢀkage
143 MHz
7
IS42R16320F-7TLI
IS42R16320F-7BLI
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
Note:ꢀForꢀ2.5Vꢀproductꢀsupport,ꢀpleaseꢀcontactꢀISSI.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
59
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
ORDERING INFORMATION - vDD = 3.3v for x8
commerꢀial Range: 0oc to +70oc
Frequenꢀy
167 MHz
143 MHz
Speed (ns)
Order Part No.
Paꢀkage
6
7
IS42S86400F-6TL
IS42S86400F-7TL
54-pinꢀTSOPII,ꢀLead-free
54-pinꢀTSOPII,ꢀLead-free
Industrial Range: -40oc to +85oc
Frequenꢀy
167 MHz
143 MHz
Speed (ns)
Order Part No.
Paꢀkage
6
7
IS42S86400F-6TLI
IS42S86400F-7TLI
54-pinꢀTSOPII,ꢀLead-free
54-pinꢀTSOPII,ꢀLead-free
ORDERING INFORMATION - vDD = 3.3v for x16
commerꢀial Range: 0oc to +70oc
Frequenꢀy
Speed (ns)
Order Part No.
Paꢀkage
IS42S16320F-5TL
IS42S16320F-5BL
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
200 MHz
5
IS42S16320F-6TL
IS42S16320F-6BL
IS42S16320F-7TL
IS42S16320F-7BL
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
167 MHz
143 MHz
6
7
Industrial Range: -40oc to +85oc
Frequenꢀy
Speed (ns)
Order Part No.
Paꢀkage
167 MHz
IS42S16320F-6TLI
IS42S16320F-6BLI
IS42S16320F-7TLI
IS42S16320F-7BLI
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
6
143 MHz
7
60
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
ORDERING INFORMATION - vDD = 3.3v for x16
Automotiꢁe Range, A1: -40°c to +85°c
Frequenꢀy
Speed (ns)
Order Part No.
Paꢀkage
IS45S16320F-6TLA1
IS45S16320F-6BLA1
IS45S16320F-7TLA1
IS45S16320F-7CTLA1
IS45S16320F-7BLA1
54-pinꢀTSOPII,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
54-pinꢀTSOPII,ꢀLead-free
54-pinꢀTSOPII,ꢀCopperꢀLeadꢀframe,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
167 MHz
6
143 MHz
7
Automotiꢁe Range, A2: -40°c to +105°c
Frequenꢀy
Speed (ns)
Order Part No.
Paꢀkage
IS45S16320F-7TLA2
IS45S16320F-7CTLA2
IS45S16320F-7BLA2
54-pinꢀTSOPII,ꢀLead-free
54-pinꢀTSOPII,ꢀCopperꢀLeadꢀframe,ꢀLead-free
54-ballꢀBGA,ꢀLead-free
143 MHz
7
*Note:ꢀForꢀcopperꢀleadframeꢀsupport,ꢀpleaseꢀcontactꢀISSI.
Integrated Silicon Solution, Inc. — www.issi.com
61
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
62
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
07/17/2017
IS42/45R86400F/16320F IS42/45S86400F/16320F
Integrated Silicon Solution, Inc. — www.issi.com
63
Rev. B1
07/17/2017
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