IS43LR16800D-5BLI [ISSI]
DDR DRAM, 8MX16, 5ns, CMOS, PBGA60, 8 X 9 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-60;
| 型号： | IS43LR16800D-5BLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | DDR DRAM, 8MX16, 5ns, CMOS, PBGA60, 8 X 9 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-60 动态存储器 双倍数据速率 |
| 文件： | 总52页 (文件大小：1011K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS43LR16800D, IS43LR32400D
4Mx32, 8Mx16
128Mb Mobile DDR SDRAM
ADVANCED INFORMATION
MARCH 2009
FEATURES:
DESCRIPTION
ISSI’sꢀ128-MbitꢀMobileꢀDDRꢀSDRAMꢀachievesꢀhigh-
speed data transfer using pipeline architecture and two
dataꢀwordꢀaccessesꢀperꢀclockꢀcycle.ꢀTheꢀ134,217,728-
bit memory array is internally organized as four banks
ofꢀ32Mbꢀtoꢀallowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀ
allowsꢀReadꢀandꢀWriteꢀburstꢀaccessesꢀtoꢀbeꢀvirtuallyꢀ
continuous, with the option to concatenate or truncate
theꢀbursts.ꢀTheꢀprogrammableꢀfeaturesꢀofꢀburstꢀlength,ꢀ
burstꢀsequenceꢀandꢀCASꢀlatencyꢀenableꢀfurtherꢀ
advantages.ꢀTheꢀdeviceꢀisꢀavailableꢀinꢀ16-bitꢀandꢀ32-bitꢀ
dataꢀwordꢀsizeꢀꢀInputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀ
onꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀ
dataꢀisꢀreferencedꢀtoꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀ
bothꢀedgesꢀofꢀCLK.ꢀCommandsꢀareꢀregisteredꢀonꢀtheꢀ
positiveꢀedgesꢀofꢀCLK.ꢀ
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
per clock cycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
received with data, to be used in capturing data
at the receiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀ
data and data mask referenced to both edges of
DQS
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
at both rising and falling edges of data strobe
•ꢀ BurstꢀLength:ꢀ2,ꢀ4,ꢀ8ꢀꢀandꢀ16
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrechargeꢀ
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀpowerꢀ
savingꢀPower-downꢀmode.ꢀSelfꢀRefreshꢀmodesꢀincludeꢀ
TemperatureꢀCompensatedꢀSelfꢀRefreshꢀ(TCSR)ꢀandꢀ
PartialꢀArrayꢀSelfꢀRefreshꢀ(PASR)ꢀoptions,ꢀwhichꢀallowꢀ
usersꢀtoꢀachieveꢀadditionalꢀpowerꢀsaving.ꢀTheꢀTCSRꢀ
andꢀPASRꢀoptionsꢀcanꢀbeꢀprogrammedꢀviaꢀtheꢀextendedꢀ
modeꢀregister.ꢀAllꢀinputsꢀareꢀLVCMOSꢀcompatible.ꢀ
ADDRESS TABLE
MOBILE FEATURES:
Parameter
4M x 32
8M x 16
•ꢀ Vd d ꢀandꢀVd d q :ꢀ1.8Vꢀ+ꢀ0.1V
Configuration
1Mꢀxꢀ32ꢀxꢀ4ꢀ
2Mꢀxꢀ16ꢀxꢀ4ꢀ
banks
•ꢀ 1.8VꢀLVCMOSꢀcompatibleꢀinputs
banks
•ꢀ TemperatureꢀCompensatedꢀSelfꢀRefreshꢀ(TCSR)ꢀ
controlled by on-chip temperature sensor
•ꢀ PartialꢀArrayꢀSelfꢀRefreshꢀ(PASR)
BankꢀAddressꢀ
Pins
BA0,ꢀBA1
A10/AP
BA0,ꢀBA1
A10/AP
Autoprecharge
•ꢀ SelectableꢀOutputꢀDriveꢀStrengthꢀ(DS)
Pins
•ꢀ ClockꢀStop,ꢀPowerꢀDownꢀandꢀDeepꢀPowerꢀDownꢀ
(DPD)ꢀmodes
RowꢀAddresses
4K(A0ꢀ–ꢀA11)
256(A0ꢀ–ꢀA7)
4K(A0ꢀ–ꢀA11)
512(A0ꢀ–ꢀA8)
Column
Addresses
RefreshꢀCount
4Kꢀ/ꢀ64ms
4Kꢀ/ꢀ64ms
OPTIONS:
•ꢀ Dieꢀrevision:ꢀD
•ꢀ Configuration(s):ꢀ4Mꢀx32,ꢀ8Mꢀx16
•ꢀ Package(s):ꢀ90ꢀBallꢀBGAꢀ(x32),ꢀ
60ꢀBallꢀBGAꢀ(x16)ꢀ
•ꢀ Lead-freeꢀpackageꢀavailable
•ꢀ TemperatureꢀRange:ꢀCommercialꢀ(0°Cꢀtoꢀ+70°C)ꢀ
andꢀIndustrialꢀ(-40°Cꢀtoꢀ+85°C)
KEY TIMING PARAMETERS
SpeedꢀGradeꢀ
Fc k ꢀMAXꢀCL=3
Fc k ꢀMAXꢀCL=2
-5
-6
-75
133
83.3
Units
200
83.3
166
83.3
MHz
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
FUNCTIONAL BLOCK DIAGRAM (8Mx16)
CLK
CLK
CKE
CS
RAS
CAS
COMMAND
DECODER
LDM, UDM
2
DATA IN
BUFFER
&
CLOCK
GENERATOR
16
16
UDQS, LDQS
REFRESH
CONTROLLER
I/O 0-15
2
MODE REGISTER
AND EXTENDED
MODE REGISTER
WE
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A11
A10
A9
CONTROLLER
14
16
16
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
12
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
14
SENSE AMP I/O GATE
512
(x16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
PIN CONFIGURATION:
Package Code B: 60-ball FBGA (top view)
(8mmꢀxꢀ9mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
Top View
(Balls seen through the package)
1
2
3
4
5
6
7
8
9
60-Ball
2
A
B
C
D
E
F
1
3
7
8
9
A
B
C
D
E
F
VSS DQ15 VSSQ VDDQ DQ0 VDD
VDDQ DQ13 DQ14 DQ1 DQ2 VSSQ
VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ
VDDQ DQ9 DQ10 DQ5 DQ6 VSSQ
VSSQ UDQS DQ8 DQ7 LDQS VDDQ
VSS UDM
NC
NC
LDM VDD
CAS RAS
G
H
J
G
H
J
CKE
A9
CK
A11
A7
CK
NC
WE
CS
BA0
BA1
A1
A6
A8 A10/AP A0
A5 A2 A3
K
K
VSS
A4
VDD
PIN DESCRIPTION: for x16
A0-A11
A0-A8
BA0,ꢀBA1
DQ0ꢀ–ꢀDQ15
CK,ꢀCK
CKE
RowꢀAddressꢀInput
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
System Clock Input
ClockꢀEnable
CS
Chip Select
CAS
Column Address Strobe Command
RowꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
RAS
WE
LDM,ꢀUDM
LDQS,ꢀUDQS
VDD
DataꢀWriteꢀMask
DataꢀStrobeꢀ
Power
VDDQ
VSS
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
VSSQ
NC
GroundꢀforꢀI/OꢀPins
No Connection
Integrated Silicon Solution, Inc.
3
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
PIN CONFIGURATION:
Package Code B: 90-ball FBGA (top view)
(8mmꢀxꢀ13mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
Top View
(Balls seen through the package)
90-Ball
2
1
2
3
4
5
6
7
8
9
1
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
VSS DQ31 VSSQ VDDQ DQ16 VDD
VDDQ DQ29 DQ30 DQ17 DQ18 VSSQ
VSSQ DQ27 DQ28 DQ19 DQ20 VDDQ
VDDQ DQ25 DQ26 DQ21 DQ22 VSSQ
VSSQ DQS3 DQ24 DQ23 DQS2 VDDQ
VDD
CKE
A9
DM3
CK
NC
CK
NC
NC
WE
CS
DM2
CAS
BA0
VSS
RAS
BA1
A1
G
H
J
G
H
J
A11
A6
A7
A8 A10/AP A0
A5 A2 DM0
K
L
A4
DM1
A3
K
L
VSSQ DQS1 DQ8
DQ7 DQS0 VDDQ
M
N
P
R
M
N
P
R
VDDQ DQ9 DQ10 DQ5
VSSQ DQ11 DQ12 DQ3
VDDQ DQ13 DQ14 DQ1
DQ6 VSSQ
DQ4 VDDQ
DQ2 VSSQ
VSS DQ15 VSSQ VDDQ DQ0
VDD
PIN DESCRIPTION: for x32
A0-A11
A0-A7
BA0,ꢀBA1
DQ0ꢀ–ꢀDQ31
CK,ꢀCK
CKE
RowꢀAddressꢀInput
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
System Clock Input
ClockꢀEnable
CS
Chip Select
CAS
Column Address Strobe Command
RowꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
RAS
WE
DM0ꢀ–ꢀDM3
DQS0ꢀ–ꢀDQS3
VDD
DataꢀWriteꢀMask
DataꢀStrobeꢀ
Power
VDDQ
VSS
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
VSSQ
NC
GroundꢀforꢀI/OꢀPins
No Connection
4ꢀ
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Symbol
Type
Description
CK,ꢀCK
Input
Clock:ꢀCKꢀandꢀCK are differential clock inputs. All address and control input signals
areꢀsampledꢀonꢀtheꢀcrossingꢀofꢀtheꢀpositiveꢀedgeꢀofꢀCKꢀandꢀnegativeꢀedgeꢀofꢀCK.ꢀ
InputꢀandꢀoutputꢀdataꢀisꢀreferencedꢀtoꢀtheꢀcrossingꢀofꢀCKꢀandꢀCKꢀ(bothꢀdirectionsꢀofꢀ
crossing).ꢀInternalꢀclockꢀsignalsꢀareꢀderivedꢀfromꢀCK/ꢀCK.
CKE
Input
Input
ClockꢀEnable:ꢀCKEꢀHIGHꢀactivates,ꢀandꢀCKEꢀLOWꢀdeactivatesꢀinternalꢀclockꢀsignals,ꢀ
andꢀdeviceꢀinputꢀbuffersꢀandꢀoutputꢀdrivers.ꢀTakingꢀCKEꢀLOWꢀprovidesꢀPRECHARGEꢀ
POWER-DOWNꢀandꢀSELFꢀREFRESHꢀoperationꢀ(allꢀbanksꢀidle),ꢀorꢀACTIVEꢀ
POWERDOWNꢀ(rowꢀACTIVEꢀinꢀanyꢀbank).ꢀCKEꢀisꢀsynchronousꢀforꢀallꢀfunctionsꢀexceptꢀ
forꢀSELFꢀREFRESHꢀEXIT,ꢀwhichꢀisꢀachievedꢀasynchronously.ꢀInputꢀbuffers,ꢀexcludingꢀ
CK,ꢀCKꢀandꢀCKE,ꢀareꢀdisabledꢀduringꢀpower-downꢀandꢀselfꢀrefreshꢀmodeꢀwhichꢀareꢀ
contrived for low standby power consumption.
CS
ChipꢀSelect:ꢀCSꢀenablesꢀ(registeredꢀLOW)ꢀandꢀdisablesꢀ(registeredꢀHIGH)ꢀtheꢀ
command decoder. All commands are masked when CSꢀisꢀregisteredꢀHIGH.ꢀCS
providesꢀforꢀexternalꢀbankꢀselectionꢀonꢀsystemsꢀwithꢀmultipleꢀbanks.ꢀCS is considered
part of the command code.
RAS, CAS,
Input
Input
WEꢀInputꢀCommandꢀInputs:ꢀRAS, CAS and WEꢀ(alongꢀwithꢀCS)ꢀdefineꢀtheꢀcommandꢀ
being entered.
WE
DMꢀforꢀx16;ꢀ
LDM,ꢀUDMꢀforꢀ
x32;ꢀDM0-DM3
InputꢀDataꢀMask:ꢀDMꢀisꢀanꢀinputꢀmaskꢀsignalꢀforꢀwriteꢀdata.ꢀInputꢀdataꢀisꢀmaskedꢀ
whenꢀDMꢀisꢀsampledꢀHIGHꢀalongꢀwithꢀthatꢀinputꢀdataꢀduringꢀaꢀWRITEꢀaccess.ꢀDMꢀ
isꢀsampledꢀonꢀbothꢀedgesꢀofꢀDQS.ꢀAlthoughꢀDMꢀpinsꢀareꢀinput-only,ꢀtheꢀDMꢀloadingꢀ
matchesꢀtheꢀDQꢀandꢀDQSꢀloading.
Forꢀx16ꢀdevices,ꢀLDMꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀUDMꢀcorrespondsꢀtoꢀtheꢀ
dataꢀonꢀDQ8-DQ15.
Forꢀx32ꢀdevices,ꢀDM0ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀDM1ꢀcorrespondsꢀtoꢀ
theꢀdataꢀonꢀDQ8-DQ15,ꢀDM2ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ16-DQ23,ꢀandꢀDM3ꢀ
correspondsꢀtoꢀtheꢀdataꢀonꢀDQ24-DQ31.
BA0,ꢀBA1
Aꢀ[n:0]
Input
Input
InputꢀBankꢀAddressꢀInputs:ꢀBA0ꢀandꢀBA1ꢀdefineꢀtoꢀwhichꢀbankꢀanꢀACTIVE,ꢀREAD,ꢀ
WRITEꢀorꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
AddressꢀInputs:ꢀprovideꢀtheꢀrowꢀaddressꢀforꢀACTIVEꢀcommands,ꢀandꢀtheꢀcolumnꢀ
addressꢀandꢀAUTOꢀPRECHARGEꢀbitꢀforꢀREADꢀ/ꢀWRITEꢀcommands,ꢀtoꢀselectꢀoneꢀ
locationꢀoutꢀofꢀtheꢀmemoryꢀarrayꢀinꢀtheꢀrespectiveꢀbank.ꢀTheꢀaddressꢀinputsꢀalsoꢀ
provideꢀtheꢀopcodeꢀduringꢀaꢀMODEꢀREGISTERꢀSETꢀcommand.
DQꢀforꢀx16;ꢀ
DQ0-DQ15ꢀforꢀ
x32;ꢀ
I/O
I/O
DataꢀBus:ꢀInputꢀ/ꢀOutput
DQ0-DQ31
DQSꢀforꢀx16:ꢀ
LDQS,UDDSꢀ
forꢀx32:
DataꢀStrobe:ꢀOutputꢀwithꢀreadꢀdata,ꢀinputꢀwithꢀwriteꢀdata.ꢀEdge-alignedꢀwithꢀreadꢀdata,ꢀ
centered with write data. Used to capture write data.
Forꢀx16ꢀdevice,ꢀLDQSꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀUDQSꢀcorrespondsꢀtoꢀ
theꢀdataꢀonꢀDQ8-DQ15.
DQS0-DQS3
Forꢀx32ꢀdevice,ꢀDQS0ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀDQS1ꢀcorrespondsꢀtoꢀ
theꢀdataꢀonꢀDQ8-DQ15,ꢀDQS2ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ16-DQ23,ꢀandꢀDQS3ꢀ
correspondsꢀtoꢀtheꢀdataꢀonꢀDQ24-DQ31.
NC
—
NoꢀConnect:ꢀShouldꢀbeꢀleftꢀunconnected.
VDDQ
VSSQ
VDD
Supply
Supply
Supply
Supply
I/OꢀPowerꢀSupply
I/OꢀGround
PowerꢀSupply
Ground
VSS
Integrated Silicon Solution, Inc. ꢀ
5
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
SIMPLIFIED STATE DIAGRAM
Power
On
Po wer
applied
Self
Refresh
DPDSX
Deep
Power
Down
REFSX
Precharge
All Banks
REFS
DPDS
Idle
MRS
EMRS
MRS
Auto
Refresh
All banks
precharged
REFA
CKEL
CKEH
Precharge
Power
Down
Active
Power
Down
ACT
CKEH
CKEL
Row
Active
Burst
Stop
WRITE
READ
BST
WRITE
READ
WRITEA
READA
READ
WRITE
READ
WRITEA
READ A
READA
PRE
PRE
PRE
WRITE A
READ A
Precharge
PREALL
PRE
Automatic Sequence
Command Sequence
ACTꢀ=ꢀActive
EMRSꢀ=ꢀExt.ꢀModeꢀReg.ꢀSet
MRSꢀ=ꢀModeꢀRegisterꢀSet
PREꢀ=ꢀPrecharge
REFSXꢀ=ꢀExitꢀSelfꢀRefresh
BSTꢀ=ꢀBurstꢀTerminate
READꢀ=ꢀReadꢀw/oꢀAutoꢀPrecharge
READAꢀ=ꢀReadꢀwithꢀAutoꢀPrecharge
WRITEꢀ=ꢀWriteꢀw/oꢀAutoꢀPrecharge
WRITEAꢀ=ꢀWriteꢀwithꢀAutoꢀPrecharge
CKELꢀ=ꢀEnterꢀPower-Down
CKEHꢀ=ꢀExitꢀPower-Down
PREALLꢀ=ꢀPrechargeꢀAllꢀBanks
REFAꢀ=ꢀAutoꢀRefresh
DPDSꢀ=ꢀEnterꢀDeepꢀPower-Down
DPDSXꢀ=ꢀExitꢀDeepꢀPower-Down
REFSꢀ=ꢀEnterꢀSelfꢀRefresh
Note:ꢀUseꢀcautionꢀwithꢀthisꢀdiagram.ꢀItꢀisꢀindentedꢀtoꢀprovideꢀaꢀfloorꢀplanꢀofꢀtheꢀpossibleꢀstateꢀtransitionsꢀandꢀcommandsꢀtoꢀcontrolꢀ
them, not all details. In particular situations involving more than one bank are not captured in full detail.
6
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Electrical Specifications
Absolute Maximum DC Ratings(3)
Parameter
Symbol
Min
-1.0
-1.0
-0.5
-55
Max
2.4
Units
V
Notes
VDDꢀsupplyꢀvoltageꢀrelativeꢀtoꢀVSS
VDDꢀsupplyꢀvoltageꢀrelativeꢀtoꢀVSSQ
VoltageꢀonꢀanyꢀballꢀrelativeꢀtoꢀVSS
StorageꢀTemperature
VDD
VDDQ
Vin,ꢀVo u t
ts t g
1
1
2
2.4
V
2.4
V
oC
+150
Notes:ꢀ
1.ꢀVDD,ꢀVDDQꢀmustꢀbeꢀwithinꢀ300mVꢀofꢀeachꢀotherꢀatꢀallꢀtꢀimes.
2.ꢀVoltageꢀonꢀanyꢀI/OꢀmayꢀnotꢀexceedꢀvoltageꢀonꢀVDDQ
3.ꢀStressesꢀgreaterꢀthanꢀthoseꢀlistedꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonly,ꢀandꢀfunctionalꢀ
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
isꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.
AC/DC Electrical Characteristics and Operating Conditions
VDDꢀ=ꢀ+1.8Vꢀ±0.1V,ꢀVDDQꢀ=ꢀ+1.8Vꢀ±0.1V
Parameter/Condition
Symbol
Vd d ꢀ
Min
1.7ꢀ
1.7ꢀ
Max
1.9ꢀ
1.9ꢀ
Units Notes
Supplyꢀvoltageꢀ
Vꢀ
Vꢀ
1
1
I/Oꢀsupplyꢀvoltageꢀ
Vd d q ꢀ
Address and Command Inputs
Inputꢀvoltageꢀhighꢀ
Vihꢀ
0.8ꢀ×ꢀVDDQꢀ
–0.3ꢀ
VDDQꢀ+ꢀ0.3ꢀ
0.2ꢀ×ꢀVDDQꢀ
Vꢀ
Vꢀ
2,3
2,3
Inputꢀvoltageꢀlowꢀꢀ
Vilꢀ
Clock Inputs (CK, CK)
DCꢀinputꢀvoltageꢀꢀ
Vinꢀ
Vid(d c )ꢀ
Vid(a c )ꢀ
Vixꢀ
–0.3ꢀ
VDDQꢀ+ꢀ0.3ꢀ
VDDQꢀ+ꢀ0.36ꢀ
VDDQꢀ+ꢀ0.6ꢀ
0.6ꢀ×ꢀVDDQꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
4
DCꢀinputꢀdifferentialꢀvoltageꢀꢀ
ACꢀinputꢀdifferentialꢀvoltageꢀꢀ
ACꢀdifferentialꢀcrossingꢀvoltageꢀꢀ
Data Inputs
0.4ꢀ×ꢀVDDQꢀ
0.6ꢀ×ꢀVDDQꢀ
0.4ꢀ×ꢀVDDQꢀ
4,5
4,5
4,6
DCꢀinputꢀhighꢀvoltageꢀꢀ
DCꢀinputꢀlowꢀvoltageꢀꢀ
Vih(d c )ꢀ
Vil(d c )ꢀ
Vih(a c )ꢀ
Vil(a c )ꢀ
0.7ꢀ×ꢀVDDQꢀ
–0.3ꢀ
VDDQꢀ+ꢀ0.3ꢀ
0.3ꢀ×ꢀVDDQꢀ
VDDQꢀ+ꢀ0.3ꢀ
0.2ꢀ×ꢀVDDQꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
2,7,3
2,7,3
2,7,3
2,7,3
ACꢀinputꢀhighꢀvoltageꢀꢀ
0.8ꢀ×ꢀVDDQꢀ
–0.3ꢀ
ACꢀinputꢀlowꢀvoltageꢀꢀ
Data Outputs
DCꢀoutputꢀhighꢀvoltage:ꢀLogicꢀ1ꢀ(Io h ꢀ=ꢀ-0.1mA)ꢀꢀ
DCꢀoutputꢀlowꢀvoltage:ꢀLogicꢀ0ꢀ(Io l ꢀ=ꢀ0.1mA)ꢀꢀ
Leakage Current
Vo h ꢀ
Vo l ꢀ
0.9ꢀ×ꢀVDDQꢀ
–ꢀ
–ꢀ
V
V
0.1ꢀ×ꢀVDDQꢀ
Inputꢀleakageꢀcurrent.ꢀAnyꢀinputꢀ0Vꢀ<ꢀVINꢀ<ꢀVDDꢀ
(Allꢀotherꢀballsꢀnotꢀunderꢀtestꢀ=ꢀ0V)
Output leakage current
(DQsꢀareꢀdisabled;ꢀ0Vꢀ≤ꢀVo u t ≤ Vd d q )ꢀ
Operating Temperature
Commercialꢀ
Ii
-1
1
mA
Io z ꢀ
–5ꢀ
5ꢀ
μA
Taꢀ
0ꢀ
+70ꢀ
+85ꢀ
oC
oC
Industrial
Taꢀ
-40ꢀ
Integrated Silicon Solution, Inc. ꢀ
7
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Notes:
1.ꢀAnyꢀpositiveꢀglitchꢀmustꢀbeꢀlessꢀthanꢀ1/3ꢀofꢀtheꢀclockꢀcycleꢀandꢀnotꢀmoreꢀthanꢀ+200mVꢀorꢀ2.0V,ꢀwhicheverꢀisꢀless.ꢀAnyꢀnega-
tiveꢀglitchꢀmustꢀbeꢀlessꢀthanꢀ1/3ꢀofꢀtheꢀclockꢀcycleꢀandꢀnotꢀexceedꢀeitherꢀ-150mVꢀorꢀ1.6V,ꢀwhicheverꢀisꢀmoreꢀpositive.
2.ꢀToꢀmaintainꢀaꢀvalidꢀlevel,ꢀtheꢀtransitioningꢀedgeꢀofꢀtheꢀinputꢀmust:ꢀ
a.ꢀSustainꢀaꢀconstantꢀslewꢀrateꢀfromꢀtheꢀcurrentꢀACꢀlevelꢀthroughꢀtoꢀtheꢀtargetꢀACꢀlevel,ꢀVil(AC),ꢀorꢀVih(AC).ꢀ
b.ꢀReachꢀatꢀleastꢀtheꢀtargetꢀACꢀlevel.ꢀ
c.ꢀAfterꢀtheꢀACꢀtargetꢀlevelꢀisꢀreached,ꢀcontinueꢀtoꢀmaintainꢀatꢀleastꢀtheꢀtargetꢀDCꢀlevel,ꢀVil(DC)ꢀorꢀVih(DC).
3.ꢀVihꢀovershoot:ꢀVihꢀ(MAX)ꢀ=ꢀVDDQꢀ+ꢀ0.5Vꢀforꢀaꢀpulseꢀwidthꢀ=ꢀ3nsꢀandꢀtheꢀpulseꢀwidthꢀcanꢀnotꢀbeꢀgreaterꢀthanꢀ1/3ꢀofꢀtheꢀcycleꢀ
rate.ꢀVilꢀundershoot:ꢀVilꢀ(MIN)ꢀ=ꢀ-0.5Vꢀforꢀaꢀpulseꢀwidthꢀ=ꢀ3nsꢀandꢀtheꢀpulseꢀwidthꢀcanꢀnotꢀbeꢀgreaterꢀthanꢀ1/3ꢀofꢀtheꢀcycleꢀ
rate.
4.ꢀCKꢀandꢀCKꢀinputꢀslewꢀrateꢀmustꢀbeꢀ=ꢀ1V/nsꢀ(2V/nsꢀifꢀmeasuredꢀdifferentially).
5.ꢀVIDꢀisꢀtheꢀmagnitudeꢀofꢀtheꢀdifferenceꢀbetweenꢀtheꢀinputꢀlevelꢀonꢀCKꢀandꢀtheꢀinputꢀlevelꢀonꢀCK.
6.ꢀTheꢀvalueꢀofꢀVixꢀisꢀexpectedꢀtoꢀequalꢀVd d q /2ꢀofꢀtheꢀtransmittingꢀdeviceꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀtheꢀsame.
7.ꢀDQꢀandꢀDMꢀinputꢀslewꢀratesꢀmustꢀnotꢀdeviateꢀfromꢀDQSꢀbyꢀmoreꢀthanꢀ10ꢀpercent.ꢀIfꢀtheꢀDQ/DM/DQSꢀslewꢀrateꢀisꢀlessꢀthanꢀ
0.5V/ns,ꢀtimingꢀmustꢀbeꢀderated:ꢀ50psꢀmustꢀbeꢀaddedꢀtoꢀtDSꢀandꢀtDHꢀforꢀeachꢀ100mv/nsꢀreductionꢀinꢀslewꢀrate.ꢀIfꢀslewꢀrate-
exceedsꢀ4V/ns,ꢀfunctionalityꢀisꢀuncertain.
8ꢀ
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
CAPACITANCE CHARACTERISTICS
Parameter
Symbol
CCK
CDCK
CI
Min
1.5
–
Max
3.0
Units
pF
Notes
Inputꢀcapacitance:ꢀCK,ꢀCK
Deltaꢀinputꢀcapacitance:ꢀCK,ꢀCK
Inputꢀcapacitance:ꢀCommandꢀAddress
Deltaꢀinputꢀcapacitance:ꢀCommandꢀandꢀaddress
Input/outputꢀcapacitance:ꢀDQs,ꢀDQS,ꢀDM
Deltaꢀinput/outputꢀcapacitance:ꢀDQs,ꢀDQS,ꢀDM
0.25
3.0
pF
2
2
1
1.5
–
pF
CDI
0.5
pF
CIO
2.0
–
4.5
pF
CDIO
0.5
pF
Notes:
1.ꢀTheꢀI/OꢀcapacitanceꢀperꢀDQSꢀandꢀDQꢀbyte/groupꢀwillꢀnotꢀdifferꢀbyꢀmoreꢀthanꢀthisꢀmaximumꢀamountꢀforꢀanyꢀgivenꢀdevice.
2.ꢀTheꢀinputꢀcapacitanceꢀperꢀballꢀgroupꢀwillꢀnotꢀdifferꢀbyꢀmoreꢀthanꢀthisꢀmaximumꢀamountꢀforꢀanyꢀgivenꢀdevice.
Integrated Silicon Solution, Inc.
9
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
IDD Specification Parameters and Test Conditions
Symbol Parameter/ Test Condition
8Mx16
Unit
-5
-6
-75
IDD0
Operatingꢀoneꢀbankꢀactive-prechargeꢀcurrent:ꢀtRCꢀ=ꢀtRCꢀ(MIN);ꢀtCKꢀ=ꢀtCKꢀ
(MIN);ꢀCKEꢀisꢀHIGH;ꢀCSꢀisꢀHIGHꢀbetweenꢀvalidꢀcommands;ꢀAddressꢀinputsꢀ
areꢀswitchingꢀeveryꢀtwoꢀclockꢀcycles;ꢀDataꢀbusꢀinputsꢀareꢀstable
TBD 75 TBD mA
TBD 500 TBD mA
TBD 500 TBD mA
IDD2P
Prechargeꢀpower-downꢀstandbyꢀcurrent:ꢀAllꢀbanksꢀidle;ꢀCKEꢀ=ꢀLOW;ꢀCSꢀ=ꢀ
HIGH,ꢀtCKꢀ=ꢀtCK(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀ
inputs are stable
IDD2PS Prechargeꢀpower-downꢀstandbyꢀcurrentꢀwithꢀclockꢀstopped:ꢀAllꢀbanksꢀidle;ꢀ
CKEꢀ=ꢀLOW;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW,ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀ
areꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀstable
IDD2N
Prechargeꢀnon-power-downꢀstandbyꢀcurrent:ꢀAllꢀbanksꢀidle;ꢀCKEꢀ=ꢀHIGH;ꢀCSꢀ TBD 25 TBD mA
=ꢀHIGH;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀ
inputs are stable
IDD2NS Prechargeꢀnon-power-downꢀstandbyꢀcurrent:ꢀClockꢀstopped;ꢀAllꢀbanksꢀidle;ꢀ
CKEꢀ=ꢀHIGH;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW;ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀ
areꢀswitchingꢀeveryꢀtwoꢀclockꢀcycles;ꢀDataꢀbusꢀinputsꢀareꢀstable
TBD 15 TBD mA
IDD3P
Activeꢀpower-downꢀstandbyꢀcurrent:ꢀOneꢀbankꢀactive;ꢀCKEꢀ=ꢀLOW;ꢀCS=HIGH;ꢀ TBD
tCK=tCKꢀ(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀ
stable
3
3
TBD mA
TBD mA
IDD3PS Activeꢀpower-downꢀstandbyꢀcurrentꢀwithꢀclockꢀstopped:ꢀOneꢀbankꢀactive;ꢀCKEꢀ TBD
=ꢀLOW;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW;ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀ
switching;ꢀDataꢀbusꢀinputsꢀareꢀstable
IDD3N
Activeꢀnon-power-downꢀstandby:ꢀOneꢀbankꢀactive;ꢀCKEꢀ=ꢀHIGH;ꢀCSꢀ=ꢀHIGH;ꢀ TBD 25 TBD mA
tCKꢀ=ꢀtCKꢀ(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀ
are stable
IDD3NS Activeꢀnon-power-downꢀstandbyꢀwithꢀclockꢀstopped:ꢀOneꢀbankꢀactive;ꢀCKEꢀ=ꢀ
HIGH;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW;ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀ
switching;ꢀDataꢀbusꢀinputsꢀareꢀstable
TBD 20 TBD mA
TBD 155 TBD mA
TBD 155 TBD mA
IDD4R
Operatingꢀburstꢀread:ꢀOneꢀbankꢀactive;ꢀBLꢀ=ꢀ4;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀContinuousꢀ
READꢀbursts;ꢀIOUTꢀ=ꢀ0mA;ꢀAddressꢀinputsꢀareꢀswitchingꢀeveryꢀtwoꢀclockꢀ
cycles;ꢀ50ꢀpercentꢀdataꢀchangingꢀeachꢀburst
IDD4W
Operatingꢀburstꢀwrite:ꢀOneꢀbankꢀactive;ꢀBLꢀ=ꢀ4;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀContinuousꢀ
WRITEꢀbursts;ꢀAddressꢀinputsꢀareꢀswitching;ꢀ50ꢀpercentꢀdataꢀchangingꢀeachꢀ
burst
IDD5
IDD5a
IDD8
Autoꢀrefresh:ꢀBurstꢀrefresh;ꢀCKEꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀ tRFCꢀ=ꢀtRFCꢀ TBD 105 TBD mA
inputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀstable (MIN)
Autoꢀrefresh:ꢀBurstꢀrefresh;ꢀCKEꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀ tRFCꢀ=ꢀtREFI TBD TBD TBD mA
inputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀstable
Deepꢀpower-downꢀcurrent:ꢀAddressꢀandꢀcontrolꢀballsꢀareꢀstable;ꢀDataꢀbusꢀ
inputsꢀareꢀstable;ꢀTypicalꢀvaluesꢀatꢀ25oC,ꢀnotꢀaꢀmaximumꢀvalue.
TBD TBD TBD mA
IDD6a
IDD6c
IDD6a
IDD6c
IDD6a
IDD6c
Selfꢀrefresh:ꢀCKEꢀ=ꢀLOW;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀAddressꢀandꢀ
controlꢀinputsꢀareꢀstable;ꢀDataꢀbusꢀinputsꢀareꢀstable
Fullꢀarray,ꢀ85o TBD 800 TBD mA
Fullꢀarray,ꢀ45o TBD 700 TBD mA
Halfꢀarray,ꢀ85o TBD TBD TBD mA
Halfꢀarray,ꢀ45o TBD TBD TBD mA
1/4ꢀarray,ꢀ85o TBD TBD TBD mA
1/4ꢀarray,ꢀ45o TBD TBD TBD mA
10
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
IDD Specification Parameters and Test Conditions
Symbol Parameter/ Test Condition
4Mx32
Unit
-5
-6
-75
IDD0
Operatingꢀoneꢀbankꢀactive-prechargeꢀcurrent:ꢀtRCꢀ=ꢀtRCꢀ(MIN);ꢀtCKꢀ=ꢀtCKꢀ
(MIN);ꢀCKEꢀisꢀHIGH;ꢀCSꢀisꢀHIGHꢀbetweenꢀvalidꢀcommands;ꢀAddressꢀinputsꢀ
areꢀswitchingꢀeveryꢀtwoꢀclockꢀcycles;ꢀDataꢀbusꢀinputsꢀareꢀstable
TBD 75 TBD mA
TBD 500 TBD mA
TBD 500 TBD mA
IDD2P
Prechargeꢀpower-downꢀstandbyꢀcurrent:ꢀAllꢀbanksꢀidle;ꢀCKEꢀ=ꢀLOW;ꢀCSꢀ=ꢀ
HIGH,ꢀtCKꢀ=ꢀtCK(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀ
inputs are stable
IDD2PS Prechargeꢀpower-downꢀstandbyꢀcurrentꢀwithꢀclockꢀstopped:ꢀAllꢀbanksꢀidle;ꢀ
CKEꢀ=ꢀLOW;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW,ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀ
areꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀstable
IDD2N
Prechargeꢀnon-power-downꢀstandbyꢀcurrent:ꢀAllꢀbanksꢀidle;ꢀCKEꢀ=ꢀHIGH;ꢀCSꢀ TBD 25 TBD mA
=ꢀHIGH;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀ
inputs are stable
IDD2NS Prechargeꢀnon-power-downꢀstandbyꢀcurrent:ꢀClockꢀstopped;ꢀAllꢀbanksꢀidle;ꢀ
CKEꢀ=ꢀHIGH;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW;ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀ
areꢀswitchingꢀeveryꢀtwoꢀclockꢀcycles;ꢀDataꢀbusꢀinputsꢀareꢀstable
TBD 15 TBD mA
IDD3P
Activeꢀpower-downꢀstandbyꢀcurrent:ꢀOneꢀbankꢀactive;ꢀCKEꢀ=ꢀLOW;ꢀCS=HIGH;ꢀ TBD
tCK=tCKꢀ(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀ
stable
3
3
TBD mA
TBD mA
IDD3PS Activeꢀpower-downꢀstandbyꢀcurrentꢀwithꢀclockꢀstopped:ꢀOneꢀbankꢀactive;ꢀCKEꢀ TBD
=ꢀLOW;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW;ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀ
switching;ꢀDataꢀbusꢀinputsꢀareꢀstable
IDD3N
Activeꢀnon-power-downꢀstandby:ꢀOneꢀbankꢀactive;ꢀCKEꢀ=ꢀHIGH;ꢀCSꢀ=ꢀHIGH;ꢀ TBD 25 TBD mA
tCKꢀ=ꢀtCKꢀ(MIN);ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀ
are stable
IDD3NS Activeꢀnon-power-downꢀstandbyꢀwithꢀclockꢀstopped:ꢀOneꢀbankꢀactive;ꢀCKEꢀ=ꢀ
HIGH;ꢀCSꢀ=ꢀHIGH;ꢀCKꢀ=ꢀLOW;ꢀ/CKꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀinputsꢀareꢀ
switching;ꢀDataꢀbusꢀinputsꢀareꢀstable
TBD 20 TBD mA
TBD 155 TBD mA
TBD 155 TBD mA
IDD4R
Operatingꢀburstꢀread:ꢀOneꢀbankꢀactive;ꢀBLꢀ=ꢀ4;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀContinuousꢀ
READꢀbursts;ꢀIOUTꢀ=ꢀ0mA;ꢀAddressꢀinputsꢀareꢀswitchingꢀeveryꢀtwoꢀclockꢀ
cycles;ꢀ50ꢀpercentꢀdataꢀchangingꢀeachꢀburst
IDD4W
Operatingꢀburstꢀwrite:ꢀOneꢀbankꢀactive;ꢀBLꢀ=ꢀ4;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀContinuousꢀ
WRITEꢀbursts;ꢀAddressꢀinputsꢀareꢀswitching;ꢀ50ꢀpercentꢀdataꢀchangingꢀeachꢀ
burst
IDD5
IDD5a
IDD8
Autoꢀrefresh:ꢀBurstꢀrefresh;ꢀCKEꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀ tRFCꢀ=ꢀtRFCꢀ TBD 105 TBD mA
inputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀstable (MIN)
Autoꢀrefresh:ꢀBurstꢀrefresh;ꢀCKEꢀ=ꢀHIGH;ꢀAddressꢀandꢀcontrolꢀ tRFCꢀ=ꢀtREFI TBD TBD TBD mA
inputsꢀareꢀswitching;ꢀDataꢀbusꢀinputsꢀareꢀstable
Deepꢀpower-downꢀcurrent:ꢀAddressꢀandꢀcontrolꢀballsꢀareꢀstable;ꢀDataꢀbusꢀ
inputsꢀareꢀstable;ꢀTypicalꢀvaluesꢀatꢀ25oC,ꢀnotꢀaꢀmaximumꢀvalue.
TBD TBD TBD mA
IDD6a
IDD6c
IDD6a
IDD6c
IDD6a
IDD6c
Selfꢀrefresh:ꢀCKEꢀ=ꢀLOW;ꢀtCKꢀ=ꢀtCKꢀ(MIN);ꢀAddressꢀandꢀ
controlꢀinputsꢀareꢀstable;ꢀDataꢀbusꢀinputsꢀareꢀstable
Fullꢀarray,ꢀ85o TBD 800 TBD mA
Fullꢀarray,ꢀ45o TBD 700 TBD mA
Halfꢀarray,ꢀ85o TBD TBD TBD mA
Halfꢀarray,ꢀ45o TBD TBD TBD mA
1/4ꢀarray,ꢀ85o TBD TBD TBD mA
1/4ꢀarray,ꢀ45o TBD TBD TBD mA
Integrated Silicon Solution, Inc.
11
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
AC CHARACTERISTICS (ACꢀoperatingꢀconditionsꢀunlessꢀotherwiseꢀnoted)ꢀ(Sheetꢀ1ꢀofꢀ2)
Parameter
Symbol
-5
-6
-75
Unit Note
Min
Max
Min
Max
Min
Max
DQꢀOutputꢀAccessꢀTimeꢀ(fromꢀCK,ꢀ/
CK)ꢀCL=3
tAC3
tAC2
2
5
2
5.5
2
6
ns
ns
ns
ns
DQꢀOutputꢀAccessꢀTimeꢀ(fromꢀCK,ꢀ/
CK)ꢀCL=2
2
2
2
6.5
5
2
2
2
6.5
5
2
2
2
6.5
6
DQSꢀOutputꢀAccessꢀTimeꢀ(fromꢀ
CK,ꢀꢀꢀꢀꢀꢀ/CK)ꢀCL=3
tDQSCK3
tDQSCK2
DQSꢀOutputꢀAccessꢀTimeꢀ(fromꢀ
CK,ꢀꢀꢀꢀꢀꢀ/CK)ꢀCL=2
6.5
6.5
6.5
ClockꢀHigh-levelꢀWidth
ClockꢀLow-levelꢀWidth
ClockꢀHalfꢀPeriod
tCH
tCL
tHP
0.45
0.45
Minꢀ
0.55
0.55
–
0.45
0.45
Minꢀ
0.55
0.55
–
0.45
0.45
Minꢀ
0.55 tCK
0.55 tCK
–
ns
1
(tCL,tCH)
(tCL,tCH)
(tCL,tCH)
SystemꢀClockꢀCycleꢀTimeꢀCLꢀ=ꢀ3
SystemꢀClockꢀCycleꢀTimeꢀCLꢀ=ꢀ2
tCK3
tCK2
tDS
5
–
–
–
6
–
–
–
7.5
–
–
–
ns
ns
ns
12
12
12
DQꢀandꢀDMꢀInputꢀSetupꢀTimeꢀ
(slow/fastꢀslewꢀrate)
0.58/ꢀ
0.48
0.7/ꢀ0.6
0.9/ꢀ0.8
2,3
2,3
DQꢀandꢀDMꢀInputꢀHoldꢀTimeꢀ(slow/
fastꢀslewꢀrateꢀ)
tDH
0.58/ꢀ
0.48
–
0.7/ꢀ0.6
–
0.9/ꢀ0.8
–
ns
DQꢀandꢀDMꢀInputꢀPulseꢀWidth
tDIPW
1.8
–
–
2.1
–
–
1.6/ꢀ1.8
1.5/ꢀ1.3
–
–
ns
ns
Address and Control Input Setup
tIS
1.1/ 0.9
1.3/ 1.1
4
4
Timeꢀ(slow/fastꢀslewꢀrate)
AddressꢀandꢀControlꢀInputꢀHoldꢀ
Timeꢀ(slow/fastꢀslewꢀrate)
tIH
1.1/ 0.9
–
–
1.3/ 1.1
–
–
1.5/1.3
–
–
ns
ns
ns
ns
ns
AddressꢀandꢀControlꢀInputꢀPulseꢀ
Width
tIPW
tLZ
2.3
1.0
–
2.3
1.0
–
2.6
1.0
–
DQꢀ&ꢀDQSꢀLow-impedanceꢀtimeꢀ
fromꢀCK,ꢀ/CK
–
–
–
5
DQꢀ&ꢀDQSꢀHigh-impedanceꢀtimeꢀ
fromꢀCK,/CK;ꢀCL=3
tHZ3
tHZ2
5.0
6.5
5.0
6.5
6.0
6.5
5,6
5,6
DQꢀ&ꢀDQSꢀHigh-impedanceꢀtimeꢀ
fromꢀCK,ꢀ/CK;ꢀCL=2
–
–
–
DQSꢀ-ꢀDQꢀSkew
tDQSQ
tQH
–
0.4
–
–
0.5
–
–
0.6
ns
ns
DQꢀ/ꢀDQSꢀoutputꢀholdꢀtimeꢀfromꢀ
DQS
tHP-
tQHS
tHP-
tQHS
tHP-
tQHS
–
DataꢀHoldꢀSkewꢀFactor
tQHS
–
0.5
–
0.65
1.25
–
0.75
ns
WriteꢀCommandꢀtoꢀ1stꢀDQSꢀ
LatchingꢀTransition
tDQSS
0.75
1.25
0.75
0.75
1.25 tCK
DQSꢀInputꢀHigh-LevelꢀWidth
DQSꢀInputꢀLow-LevelꢀWidth
tDQSH
tDQSL
tDSS
0.4
0.4
0.2
0.6
0.6
–
0.4
0.4
0.2
0.6
0.6
–
0.4
0.4
0.2
0.6
0.6
–
tCK
tCK
tCK
DQSꢀFallingꢀEdgeꢀofꢀCKꢀSetupꢀ
Time
DQSꢀFallingꢀEdgeꢀHoldꢀTimeꢀfromꢀ
CK
tDSH
0.2
–
0.2
–
0.2
–
tCK
12
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
AC CHARACTERISTICS (ACꢀoperatingꢀconditionsꢀunlessꢀotherwiseꢀnoted)ꢀ(Sheetꢀ2ꢀofꢀ2)
Parameter
Symbol
-5
-6
-75
Unit Note
Min
Max
–
Min
Max
–
Min
Max
–
MODEꢀREGISTERꢀSETꢀCommandꢀ
Period
tMRD
2
2
2
tCK
WriteꢀPreambleꢀSetupꢀTime
WriteꢀPostamble
tWPRES
tWPST
tWPRE
tRPRE
tRPRE
tRPST
tRAS
0
–
–
0
–
–
0
–
–
ns
0.4
0.25
0.9
0.5
0.4
40
0.4
0.25
0.9
0.5
0.4
42
0.4
0.25
0.9
0.5
0.4
45
tCK
WriteꢀPreamble
–
–
–
tCK
tCK
tCK
tCK
6
6
ReadꢀPreambleꢀCL=3
ReadꢀPreambleꢀCL=2
DQSꢀreadꢀpostamble
1.1
1.1
0.6
70,000
1.1
1.1
0.6
70,000
1.1
1.1
0.6
ACTIVEꢀtoꢀPRECHARGEꢀ
CommandꢀPeriod
70,000 ns
ACTIVEꢀtoꢀACTIVEꢀCommandꢀ
Period
tRC
55
70
–
–
60
–
–
75
70
–
–
ns
ns
AUTOꢀREFRESHꢀtoꢀACTIVE/AUTOꢀ
REFRESHꢀCommandꢀPeriod
tRFC
70
ACTIVEꢀtoꢀREADꢀorꢀWRITEꢀDelay
PRECHARGEꢀCommandꢀPeriod
tRCD
tRP
15
15
10
–
–
–
18
15
12
–
–
–
22.5
22.5
15
–
–
–
ns
ns
ns
ACTIVEꢀBankꢀAꢀtoꢀACTIVEꢀBankꢀBꢀ
Delay
tRRD
WRITEꢀRecoveryꢀTime
tWR
15
–
15
–
15
–
ns
AutoꢀPrechargeꢀWriteꢀRecoveryꢀ+ꢀ
PrechargeꢀTime
tDAL
(tWR/tCK)+(tRP/tCK)
tCK
9
InternalꢀWriteꢀtoꢀReadꢀCommandꢀ
Delay
tWTR
tXSR
tXP
2
120
2
–
–
–
–
1
120
1
–
–
–
–
1
120
1
–
–
–
–
tCK
ns
SelfꢀRefreshꢀExitꢀtoꢀnextꢀvalidꢀ
CommandꢀDelay
7
8
ExitꢀPowerꢀDownꢀtoꢀnextꢀvalidꢀ
CommandꢀDelay
tCK
tCK
CKEꢀmin.ꢀPulseꢀWidthꢀ(Highꢀandꢀ
Low)
tCKE
1
1
1
AverageꢀPeriodicꢀRefreshꢀInterval
RefreshꢀPeriod
tREFI
tREF
15.6
–
15.6
–
15.6
–
–
us
64
64
64
ms
Integrated Silicon Solution, Inc.
13
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Notes:
1.ꢀtHP(min)ꢀisꢀtheꢀlesserꢀofꢀmin(tCL,tCH)ꢀactuallyꢀappliedꢀtoꢀtheꢀdeviceꢀCKꢀandꢀCK inputs, collectively
2.ꢀDQꢀandꢀDMꢀinputꢀslewꢀratesꢀmustꢀnotꢀdeviateꢀfromꢀDQSꢀbyꢀmoreꢀthanꢀ10ꢀpercent.
3.ꢀIfꢀtheꢀDQ/DM/DQSꢀslewꢀrateꢀisꢀlessꢀthanꢀ0.5V/ns,ꢀtimingꢀmustꢀbeꢀderated:ꢀ50psꢀmstꢀbeꢀaddedꢀtoꢀtDSꢀandꢀtDHꢀforꢀeachꢀ
100mV/nsꢀreductionꢀinꢀslewꢀrate.ꢀIfꢀslewꢀrateꢀexceedsꢀ4V/ns,ꢀfunctionalityꢀisꢀuncertain.
4.ꢀFastꢀcommand/addressꢀinputꢀslewꢀrateꢀ1V/nS.ꢀSlowꢀcommand/addressꢀinputꢀslewꢀrateꢀ0.5ꢀV/ns.
5.ꢀtHZꢀandꢀtLZꢀtransitionsꢀoccurꢀinꢀtheꢀsameꢀaccessꢀtimeꢀwindowsꢀasꢀdataꢀvalidꢀtransitions.
6.ꢀtHZꢀ(MAX)ꢀwillꢀprevailꢀoverꢀtDQSCKꢀ(MAX)ꢀ+ꢀtRPSTꢀ(MAX)ꢀcondition.
7.ꢀClockꢀmustꢀbeꢀtoggledꢀaꢀminimumꢀofꢀtwoꢀtimesꢀduringꢀthisꢀperiod.
8.ꢀClockꢀmustꢀbeꢀtoggledꢀaꢀminimumꢀofꢀoneꢀtimeꢀduringꢀthisꢀperiod.
9.ꢀtDAL=(tWR/tCK)+(tRP/tCK):ꢀforꢀeachꢀterm,ꢀifꢀnotꢀalreadyꢀanꢀinteger,ꢀroundꢀtoꢀtheꢀnextꢀhigherꢀinteger.
10.ꢀOutputsꢀmeasuredꢀwithꢀequivalentꢀload:
50
I/O
20 pF
Full-drive strength
50
I/O
10 pF
Ha lf-drive strength
50
I/O
5 pF
Quarter-drive strength
14
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
OUTPUT SLEW RATE CHARACTERISTICS
PARAMETER
MIN
0.7ꢀ
0.3ꢀ
0.7ꢀ
MAX
2.5ꢀ
1.0ꢀ
1.4ꢀ
UNIT
V/nsꢀ
V/nsꢀ
—ꢀ
NOTES
1,2
Pull-upꢀandꢀPull-DownꢀSlewꢀRateꢀforꢀFullꢀStrengthꢀDriverꢀ
Pull-upꢀandꢀPull-DownꢀSlewꢀRateꢀforꢀHalfꢀStrengthꢀDriverꢀꢀ
OutputꢀSlewꢀrateꢀMatchingꢀratioꢀ(Pull-upꢀtoꢀPull-down)ꢀꢀ
1,2
3
NOTES:
1.ꢀꢀMeasuredꢀwithꢀaꢀtestꢀloadꢀofꢀ20ꢀpFꢀconnectedꢀtoꢀVSSQ.
2.ꢀꢀOutputꢀslewꢀrateꢀforꢀrisingꢀedgeꢀisꢀmeasuredꢀbetweenꢀVILD(DC)ꢀtoꢀVIHD(AC)ꢀandꢀforꢀfallingꢀedgeꢀbetweenꢀVIHD(DC)ꢀtoꢀ
VILD(AC).
3.ꢀꢀTheꢀratioꢀofꢀpull-upꢀslewꢀrateꢀtoꢀpull-downꢀslewꢀrateꢀisꢀspecifiedꢀforꢀtheꢀsameꢀtemperatureꢀandꢀvoltage,ꢀoverꢀtheꢀentireꢀtem-
peratureꢀandꢀvoltageꢀrange.ꢀForꢀaꢀgivenꢀoutput,ꢀitꢀrepresentsꢀtheꢀmaximumꢀdifferenceꢀbetweenꢀpull-upꢀandꢀpull-downꢀdriversꢀ
due to process variation.
AC OVERSHOOT/UNDERSHOOT SPECIFICATION
PARAMETER
SPECIFICATION
0.5ꢀV
Maximumꢀpeakꢀamplitudeꢀallowedꢀforꢀovershootꢀꢀ
Maximumꢀpeakꢀamplitudeꢀallowedꢀforꢀundershootꢀꢀ
ꢀ
ꢀ
0.5ꢀV
TheꢀareaꢀbetweenꢀovershootꢀsignalꢀandꢀVDDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀꢀ
TheꢀareaꢀbetweenꢀundershootꢀsignalꢀandꢀGNDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀꢀ
3ꢀV-ns
3ꢀV-ns
NOTES:
1.ꢀThisꢀspecificationꢀisꢀintendedꢀforꢀdevicesꢀwithꢀnoꢀclampꢀprotectionꢀandꢀisꢀguaranteedꢀbyꢀdesign.
2.5
Overshoot Area
2.0
VDD
1.5
1.0
Max. Amplitude = 0.5 V
Max. Area = 3 V-ns
0.5
0
VSS
-0.5
Undershoot Area
Time (ns)
AC Overshoot and Undershoot Definition
Integrated Silicon Solution, Inc. ꢀ
15
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
DRIVER CHARACTERISTICS
MobileꢀDDRꢀSDRAMꢀoutputꢀdriverꢀcharacteristicsꢀareꢀdefinedꢀforꢀfullꢀandꢀhalfꢀdriveꢀstrengthꢀoperationꢀasꢀselectedꢀinꢀ
theꢀExtendedꢀModeꢀRegister.ꢀTheꢀtableꢀbelowꢀshowsꢀtheꢀdataꢀinꢀaꢀtabularꢀformatꢀsuitableꢀforꢀinputꢀintoꢀsimulationꢀtools.ꢀ
Theꢀfollowingꢀfiguresꢀshowꢀtheꢀdriverꢀstrengthꢀcharacteristicsꢀgraphically.
I-V CURVES FOR FULL DRIVE STRENGTH AND HALF DRIVE STRENGTH(1,2)
Voltage
[V]
FULL DRIVE STRENGTH
Pull-Down Current Pull-Up Current
[mA] [mA]
HALF DRIVE STRENGTH
Pull-Down Current Pull-Up Current
[mA] [mA]
Min
0.00
Max.
0.00
Min.
0.00
Max.
0.00
Min.
0.00
Max
0.00
Min.
0.00
Max.
0.00
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.85
0.9
2.80
18.53
26.80
32.80
37.05
40.00
42.50
44.57
46.50
47.48
48.50
49.40
50.05
51.35
52.65
53.95
55.25
56.55
57.85
59.15
60.45
61.75
-2.80
-18.53
-26.80
-32.80
-37.05
-40.00
-42.50
-44.57
-46.50
-47.48
-48.50
-49.40
-50.05
-51.35
-52.65
-53.95
-55.25
-56.55
-57.85
-59.15
-60.45
-61.75
1.27
8.42
-1.27
-2.55
-3.82
-5.09
-6.36
-7.64
-8.91
-10.16
-10.80
-10.80
-10.80
-10.80
-10.80
-10.80
-10.80
-10.80
-10.80
-10.80
-10.80
—
-8.42
5.60
-5.60
2.55
12.30
14.95
16.84
18.20
19.30
20.30
21.20
21.60
22.00
22.45
22.73
23.21
23.67
24.14
24.61
25.08
25.54
26.01
26.48
26.95
-12.30
-14.95
-16.84
-18.20
-19.30
-20.30
-21.20
-21.60
-22.00
-22.45
-22.73
-23.21
-23.67
-24.14
-24.61
-25.08
-25.54
-26.01
-26.48
-26.95
8.40
-8.40
3.82
11.20
14.00
16.80
19.60
22.40
23.80
ꢀ23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
—
-11.20
-14.00
-16.80
-19.60
-22.40
-23.80
-23.80
-23.80
-23.80
-23.80
-23.80
-23.80
-23.80
-23.80
-23.80
-23.80
—
5.09
6.36
7.64
8.91
10.16
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
—
0.95
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
—
—
—
—
NOTES:
1.ꢀBasedꢀonꢀnominalꢀimpedanceꢀofꢀ25ꢀOhmsꢀ(FullꢀDrive)ꢀandꢀ55ꢀOhmsꢀ(HalfꢀDrive)ꢀatꢀVDDQ/2
2.ꢀTheꢀfullꢀvariationꢀinꢀdriverꢀcurrentꢀfromꢀminimumꢀtoꢀmaximumꢀdueꢀtoꢀprocess,ꢀtemperatureꢀandꢀvoltageꢀwillꢀlieꢀwithinꢀtheꢀouterꢀ
boundingꢀlinesꢀofꢀtheꢀI-Vꢀcurve.
16
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Full Drive Strength I-V Curves
75.0
50.0
25.0
0.0
PD Max
PD Min
PU Min
PU Max
0.0
0.5
1.0
1.5
-25.0
-50.0
-75.0
I-V Curves For Full Drive Strength
Half Drive Strength I-V Curves
30.0
20.0
10.0
0.0
PD Max
PD Min
PU Min
PU Max
0.0
0.5
1.0
1.5
-10.0
-20.0
-30.0
I-V Curves For Half Drive Strength
Integrated Silicon Solution, Inc. ꢀ
17
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
FUNCTIONAL DESCRIPTION
TheꢀMobileꢀDDRꢀSDRAMꢀisꢀaꢀhighꢀspeedꢀCMOS,ꢀdynamicꢀrandom-accessꢀmemoryꢀinternallyꢀconfiguredꢀasꢀaꢀquad-
bankꢀDRAM.ꢀTheꢀ128ꢀMbꢀdevicesꢀcontains:ꢀ134,217,728ꢀbits.ꢀ
TheꢀMobileꢀDDRꢀSDRAMꢀusesꢀdoubleꢀdataꢀrateꢀarchitectureꢀtoꢀachieveꢀhighꢀspeedꢀoperation.ꢀTheꢀdoubleꢀdataꢀrateꢀ
architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycleꢀatꢀtheꢀI/Oꢀpins.ꢀAꢀsingleꢀreadꢀorꢀwriteꢀaccessꢀforꢀtheꢀMobileꢀDDRꢀSDRAMꢀeffectivelyꢀconsistsꢀofꢀaꢀsingleꢀ2n-bitꢀ
wide,ꢀoneꢀclockꢀcycleꢀdataꢀtransferꢀatꢀtheꢀinternalꢀDRAMꢀcoreꢀandꢀtwoꢀcorrespondingꢀn-bitꢀwide,ꢀone-half-clock-cycleꢀ
dataꢀtransfersꢀatꢀtheꢀI/Oꢀpins.ꢀ
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀMobileꢀDDRꢀSDRAMꢀareꢀburstꢀoriented;ꢀaccessesꢀstartꢀatꢀaꢀselectedꢀlocationꢀandꢀ
continueꢀforꢀaꢀprogrammedꢀnumberꢀofꢀlocationsꢀinꢀaꢀprogrammedꢀsequence.ꢀAccessesꢀbeginꢀwithꢀtheꢀregistrationꢀofꢀ
anꢀACTIVEꢀcommand,ꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀ
withꢀtheꢀACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀtheꢀrowꢀtoꢀbeꢀaccessed.ꢀTheꢀaddressꢀbitsꢀregisteredꢀ
coincidentꢀwithꢀtheꢀREADꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀtheꢀstartingꢀcolumnꢀlocationꢀforꢀtheꢀ
burst access.
Priorꢀtoꢀnormalꢀoperation,ꢀtheꢀMobileꢀDDRꢀSDRAMꢀmustꢀbeꢀinitialized.ꢀTheꢀfollowingꢀsectionꢀprovidesꢀdetailedꢀ
information covering device initialization, register definition, command description and device operation.
INITIALIZATION
MobileꢀDDRꢀSDRAMsꢀmustꢀbeꢀpoweredꢀupꢀandꢀinitializedꢀinꢀaꢀpredefinedꢀmanner.ꢀOperationsꢀproceduresꢀotherꢀthanꢀ
those specified may result in undefined operation. If there is any interruption to the device power, the initialization
routineꢀshouldꢀbeꢀfollowed.ꢀTheꢀstepsꢀtoꢀbeꢀfollowedꢀforꢀdeviceꢀinitializationꢀareꢀlistedꢀbelow.ꢀTheꢀInitializationꢀFlowꢀ
diagramꢀandꢀtheꢀInitializationꢀFlowꢀsequenceꢀareꢀshownꢀinꢀtheꢀfollowingꢀfigures.ꢀ
TheꢀModeꢀRegisterꢀandꢀExtendedꢀModeꢀRegisterꢀdoꢀnotꢀhaveꢀdefaultꢀvalues.ꢀIfꢀtheyꢀareꢀnotꢀprogrammedꢀduringꢀtheꢀ
initializationꢀsequence,ꢀitꢀmayꢀleadꢀtoꢀunspecifiedꢀoperation.ꢀTheꢀclockꢀstopꢀfeatureꢀisꢀnotꢀavailableꢀuntilꢀtheꢀdeviceꢀhasꢀ
been properly initialized from Step 1 through 11.
18
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
•ꢀꢀStep1:ꢀProvideꢀpower,ꢀtheꢀdeviceꢀcoreꢀpowerꢀ(VDD)ꢀandꢀtheꢀdeviceꢀI/Oꢀpowerꢀ(VDDQ)ꢀmustꢀbeꢀbroughtꢀ
upꢀsimultaneouslyꢀtoꢀpreventꢀdeviceꢀlatch-up.ꢀAlthoughꢀnotꢀrequired,ꢀitꢀisꢀrecommendedꢀthatꢀVDDꢀandꢀ
VDDQꢀareꢀfromꢀtheꢀsameꢀpowerꢀsource.ꢀAlsoꢀassertꢀandꢀholdꢀClockꢀEnableꢀ(CKE)ꢀtoꢀaꢀLVCMOSꢀlogicꢀ
high level
•ꢀꢀStepꢀ2:ꢀOnceꢀtheꢀsystemꢀhasꢀestablishedꢀconsistentꢀdeviceꢀpowerꢀandꢀCKEꢀisꢀdrivenꢀhigh,ꢀitꢀisꢀsafeꢀtoꢀ
apply stable clock
•ꢀꢀStepꢀ3:ꢀThereꢀmustꢀbeꢀatꢀleastꢀ200ꢀμsꢀofꢀvalidꢀclocksꢀbeforeꢀanyꢀcommandꢀmayꢀbeꢀgivenꢀtoꢀtheꢀDRAM.ꢀ
DuringꢀthisꢀtimeꢀNOPꢀorꢀDESELECTꢀcommandsꢀmustꢀbeꢀissuedꢀonꢀtheꢀcommandꢀbus.
•ꢀꢀStepꢀ4:ꢀIssueꢀaꢀPRECHARGEꢀALLꢀcommand.
•ꢀꢀStepꢀ5:ꢀProvideꢀNOPsꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtRPꢀtime.
•ꢀꢀStepꢀ6:ꢀIssueꢀanꢀAUTOꢀREFRESHꢀcommandꢀfollowedꢀbyꢀNOPsꢀorꢀDESELECTꢀcommandꢀforꢀatꢀleastꢀ
tRFCꢀtime.ꢀIssueꢀtheꢀsecondꢀAUTOꢀREFRESHꢀcommandꢀfollowedꢀbyꢀNOPsꢀorꢀDESELECTꢀcommandꢀforꢀ
atꢀleastꢀtRFCꢀtime.ꢀNoteꢀasꢀpartꢀofꢀtheꢀinitializationꢀsequenceꢀthereꢀmustꢀbeꢀtwoꢀautoꢀrefreshꢀcommandsꢀ
issued.ꢀTheꢀtypicalꢀflowꢀisꢀtoꢀissueꢀthemꢀatꢀStepꢀ6,ꢀbutꢀtheyꢀmayꢀalsoꢀbeꢀissuedꢀbetweenꢀstepsꢀ10ꢀandꢀ11.
•ꢀꢀStepꢀ7:ꢀUsingꢀtheꢀMRSꢀcommand,ꢀloadꢀtheꢀbaseꢀmodeꢀregister.ꢀSetꢀtheꢀdesiredꢀoperatingꢀmodes.
•ꢀꢀStepꢀ8:ꢀProvideꢀNOPsꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtMRDꢀtime.
•ꢀꢀStepꢀ9:ꢀUsingꢀtheꢀMRSꢀcommand,ꢀprogramꢀtheꢀextendedꢀmodeꢀregisterꢀforꢀtheꢀdesiredꢀoperatingꢀmodes.ꢀ
Noteꢀtheꢀorderꢀofꢀtheꢀbaseꢀandꢀextendedꢀmodeꢀregisterꢀprogrammingꢀisꢀnotꢀimportant.
•ꢀꢀStepꢀ10:ꢀProvideꢀNOPꢀorꢀDESELCTꢀcommandsꢀforꢀatꢀleastꢀtMRDꢀtime.
•ꢀꢀStepꢀ11:ꢀTheꢀDRAMꢀhasꢀbeenꢀproperlyꢀinitializedꢀandꢀisꢀreadyꢀforꢀanyꢀvalidꢀcommand.
Initialization Flow Diagram
1
2
3
4
5
6
7
8
9
VDD and VDDQ Ramp: CKE must be held high
Apply stable clocks
Wait at least 200 µs with NOP or DESELECT on command
bus
PRECHARGE ALL
Assert NOP or DESELCT for t time
RP
Issue two AUTOREFRESH commands each followed by
NOP or DESELECT commands for t
time
RFC
Configure Mode Register
Assert NOP or DESELECT for t
time
MRD
Configure Extended Mode Register
10 Assert NOP or DESELECT for t
time
MRD
11 LPDDR SDRAM is ready for any valid command
Integrated Silicon Solution, Inc.
19
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Initialization Waveform Sequence
VDD
VDDQ
200µs
tCK
tRP
tRFC
tRFC
tMRD
tMRD
CK
CK
CKE
NOP
PRE
ARF
ARF
MRS
CODE
CODE
MRS
CODE
CODE
ACT
RA
Command
Address
A10
All
RA
Banks
BA
BA0,BA1
BA0=L
BA1=L
BA0=L
BA1=H
DM
(High-Z)
DQ, DQS
VDD / VDDQ powered up
Clock stable
Load
Load
Mode Reg. Ext. Mode Reg.
= Don't Care
20
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
MODE REGISTER (MR) DEFINITION
TheꢀModeꢀRegisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀofꢀoperationꢀofꢀtheꢀMobileꢀDDRꢀSDRAM.ꢀThisꢀdefinitionꢀ
includesꢀtheꢀdefinitionꢀofꢀaꢀburstꢀlength,ꢀaꢀburstꢀtype,ꢀandꢀaꢀCASꢀlatency.ꢀTheꢀModeꢀRegisterꢀisꢀprogrammedꢀviaꢀ
theꢀMODEꢀREGISTERꢀSETꢀcommandꢀ(withꢀBA0=0ꢀandꢀBA1=0)ꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀ
reprogrammed,ꢀtheꢀdeviceꢀgoesꢀintoꢀDeepꢀPower-Downꢀmode,ꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀꢀModeꢀRegisterꢀbitsꢀA0-A2ꢀ
specifyꢀtheꢀburstꢀlength,ꢀA3ꢀtheꢀtypeꢀofꢀburstꢀ(sequentialꢀorꢀinterleave),ꢀA4-A6ꢀtheꢀCASꢀlatency.ꢀAꢀlogicꢀ0ꢀshouldꢀbeꢀ
programmed to all the undefined addresses bits to ensure future compatibility.
TheꢀModeꢀRegisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀprogress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀ
theꢀspecifiedꢀtimeꢀtMRDꢀbeforeꢀinitiatingꢀanyꢀsubsequentꢀoperation.ꢀViolatingꢀeitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀ
unspecified operation.
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
MODE REGISTER DEFINITION
AddressꢀBusꢀ(Ax)
ModeꢀReg.ꢀ(Ex)
BA1 BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Reserved(2)
A2 A1 A0 Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
16
Reserved
Reserved
Reserved
A3 Burst Type
0
1
Sequential
Interleave
A6 A5 A4 CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Reserved
Program Extended mode Register
Reserved
Notes:
1.ꢀ MSBꢀdependsꢀonꢀMobileꢀDDRꢀSDRAMꢀdensity.
2. A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.
Integrated Silicon Solution, Inc.
21
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Burst Length
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀMobileꢀDDRꢀSDRAMꢀareꢀburstꢀoriented,ꢀwithꢀtheꢀburstꢀlengthꢀbeingꢀsetꢀandꢀtheꢀ
burstꢀorderꢀasꢀinꢀBurstꢀDefinition.ꢀTheꢀburstꢀlengthꢀdeterminesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀbeꢀ
accessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀlengthsꢀofꢀ2,ꢀ4,ꢀ8,ꢀorꢀ16ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀ
sequentialꢀandꢀtheꢀinterleavedꢀburstꢀtypes.ꢀ
Burst Definition
Burst
Length
Starting Column
Address
ORDER OF ACCESSES WITHIN A BURST
(HEXADECIMAL NOTATION)
A3 A2 A1 A0
Sequential
Interleaved
0
1
0-1
0-1
2
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 - 1 - 2 - 3
0 - 1 - 2 - 3
1 - 2 - 3 - 0
1 - 0 - 3 - 2
4
2 - 3 - 0 - 1
2 - 3 - 0 - 1
3 - 0 - 1 - 2
3 - 2 - 1 - 0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7
1ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ0
2ꢀ-ꢀ3ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ0ꢀ-ꢀ1
3ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ2
4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3
5ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ4
6ꢀ-ꢀ7ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ4ꢀ-ꢀ5
7ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ6
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7
1ꢀ-ꢀ0ꢀ-ꢀ3ꢀ-ꢀ2ꢀ-ꢀ5ꢀ-ꢀ4ꢀ-ꢀ7ꢀ-ꢀ6
2ꢀ-ꢀ3ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ4ꢀ-ꢀ5
3ꢀ-ꢀ2ꢀ-ꢀ1ꢀ-ꢀ0ꢀ-ꢀ7ꢀ-ꢀ6ꢀ-ꢀ5ꢀ-ꢀ4
4ꢀ-ꢀ5ꢀ-ꢀ6ꢀ-ꢀ7ꢀ-ꢀ0ꢀ-ꢀ1ꢀ-ꢀ2ꢀ-ꢀ3
5ꢀ-ꢀ4ꢀ-ꢀ7ꢀ-ꢀ6ꢀ-ꢀ1ꢀ-ꢀ0ꢀ-ꢀ3ꢀ-ꢀ2
6ꢀ-ꢀ7ꢀ-ꢀ4ꢀ-ꢀ5ꢀ-ꢀ2ꢀ-ꢀ3ꢀ-ꢀ0ꢀ-ꢀ1
7ꢀ-ꢀ6ꢀ-ꢀ5ꢀ-ꢀ4ꢀ-ꢀ3ꢀ-ꢀ2ꢀ-ꢀ1ꢀ-ꢀ0
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
16
Notes:
1.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀtwo,ꢀA1-Anꢀselectsꢀtheꢀtwoꢀdataꢀelementꢀblock;ꢀA0ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
2.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀfour,ꢀA2-Anꢀselectsꢀtheꢀfourꢀdataꢀelementꢀblock;ꢀA0-A1ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
3.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀeight,ꢀA3-Anꢀselectsꢀtheꢀeightꢀdataꢀelementꢀblock;ꢀA0-A2ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
4.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀsixteen,ꢀA4-Anꢀselectsꢀtheꢀsixteenꢀdataꢀelementꢀblock;ꢀA0-A3ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
5.ꢀ Wheneverꢀaꢀboundaryꢀofꢀtheꢀblockꢀisꢀreachedꢀwithinꢀaꢀgivenꢀsequence,ꢀtheꢀfollowingꢀaccessꢀwrapsꢀwithinꢀtheꢀblock.
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀcolumnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo,ꢀbyꢀA2-Anꢀwhenꢀtheꢀburstꢀlengthꢀ
isꢀsetꢀtoꢀ4,ꢀbyꢀA3-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀ8ꢀandꢀA4-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀ16ꢀ(whereꢀAnꢀisꢀtheꢀ
mostꢀsignificantꢀcolumnꢀaddressꢀbitꢀforꢀaꢀgivenꢀconfiguration).ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀaddressꢀbit(s)ꢀisꢀ(are)ꢀ
usedꢀtoꢀselectꢀtheꢀstartingꢀlocationꢀwithinꢀtheꢀblock.ꢀTheꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀbothꢀreadꢀandꢀwriteꢀ
bursts.
Burst Type
Accessesꢀwithinꢀaꢀgivenꢀburstꢀmayꢀbeꢀprogrammedꢀtoꢀbeꢀeitherꢀsequentialꢀorꢀinterleaved;ꢀthisꢀisꢀreferredꢀtoꢀasꢀtheꢀ
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀA3.ꢀTheꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀtheꢀburstꢀlength,ꢀtheꢀ
burst type and the starting column address.
Read Latency
TheꢀREADꢀlatency,ꢀorꢀCASꢀlatency,ꢀisꢀtheꢀdelayꢀbetweenꢀtheꢀregistrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀIfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀaꢀclockꢀedgeꢀnꢀandꢀtheꢀlatencyꢀisꢀ3ꢀclocks,ꢀtheꢀfirstꢀ
dataꢀelementꢀwillꢀbeꢀvalidꢀatꢀnꢀ+ꢀ2tCKꢀ+ꢀtAC.ꢀIfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀaꢀclockꢀedgeꢀnꢀandꢀtheꢀlatencyꢀisꢀ2ꢀ
clocks,ꢀtheꢀfirstꢀdataꢀelementꢀwillꢀbeꢀvalidꢀatꢀnꢀ+ꢀtCKꢀ+ꢀtAC.
EXTENDED MODE REGISTER (EMR) DEFINITION
TheꢀExtendedꢀModeꢀRegisterꢀcontrolsꢀfunctionsꢀbeyondꢀthoseꢀcontrolledꢀbyꢀtheꢀModeꢀRegister;ꢀtheseꢀadditionalꢀ
functionsꢀincludeꢀoutputꢀdriveꢀstrengthꢀselection,ꢀTemperatureꢀCompensatedꢀSelfꢀRefreshꢀ(TCSR)ꢀandꢀPartialꢀArrayꢀ
SelfꢀRefreshꢀ(PASR),ꢀasꢀshownꢀinꢀExtendedꢀModeꢀRegisterꢀDefinition.ꢀBothꢀTCSRꢀandꢀPASRꢀareꢀeffectiveꢀisꢀinꢀSelfꢀ
Refreshꢀmodeꢀonly.ꢀTheꢀExtendedꢀModeꢀRegisterꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀ(withꢀ
BA1=1ꢀandꢀBA0=0)ꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀreprogrammed,ꢀtheꢀdeviceꢀisꢀputꢀinꢀDeepꢀPower-
Downꢀmode,ꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀTheꢀExtendedꢀModeꢀRegisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀidleꢀandꢀ
noꢀburstsꢀareꢀinꢀprogress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀtMRDꢀbeforeꢀinitiatingꢀanyꢀsubsequentꢀ
operation.ꢀViolatingꢀeitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.ꢀAddressꢀbitsꢀA0-A2ꢀspecifyꢀPASR,ꢀ
A3-A4ꢀtheꢀTCSR,ꢀA5-A6ꢀtheꢀDriveꢀStrength.ꢀAꢀlogicꢀ0ꢀshouldꢀbeꢀprogrammedꢀtoꢀallꢀtheꢀundefinedꢀaddressesꢀbitsꢀtoꢀ
ensureꢀfutureꢀcompatibility.ꢀReservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀ
versions may result.
Partial Array Self Refresh (PASR)
WithꢀPASR,ꢀtheꢀselfꢀrefreshꢀmayꢀbeꢀrestrictedꢀtoꢀaꢀvariableꢀportionꢀofꢀtheꢀtotalꢀarray.ꢀTheꢀwholeꢀarrayꢀ(default),ꢀ1/2ꢀ
array,ꢀ1/4ꢀarray,ꢀ1/8ꢀarray,ꢀorꢀ1/16ꢀarrayꢀcouldꢀbeꢀselected.ꢀDataꢀoutsideꢀtheꢀdefinedꢀareaꢀwillꢀbeꢀlost.ꢀAddressꢀbitsꢀA0ꢀ
toꢀA2ꢀareꢀusedꢀtoꢀsetꢀPASR.
Temperature Compensated Self Refresh (TCSR)
ThisꢀfunctionꢀisꢀusedꢀinꢀtheꢀMobileꢀDDRꢀSDRAMꢀtoꢀsetꢀrefreshꢀratesꢀbasedꢀonꢀcaseꢀtemperature.ꢀTheꢀdeviceꢀhasꢀ
InternalꢀTemperatureꢀCompensatedꢀSelfꢀRefreshꢀfeature,ꢀwhichꢀautomaticallyꢀadjustsꢀtheꢀrefreshꢀrateꢀbasedꢀonꢀtheꢀ
deviceꢀtemperatureꢀwithoutꢀanyꢀregisterꢀupdateꢀneeded.ꢀItꢀignoresꢀ(don’tꢀcare)ꢀtheꢀinputsꢀtoꢀaddressꢀbitsꢀA3ꢀandꢀA4ꢀ
duringꢀEMRSꢀprogramming.
Output Driver Strength (DS)
Theꢀdriveꢀstrengthꢀcanꢀbeꢀsetꢀtoꢀfullꢀ(default),ꢀ1/2,ꢀ1/4,ꢀorꢀ1/8ꢀstrengthꢀviaꢀaddressꢀbitsꢀA5ꢀandꢀA6.ꢀTheꢀpartialꢀdriveꢀ
strength options are intended for lighter loads or point-to-point environments.
Integrated Silicon Solution, Inc.
23
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Extended Mode Register Definition
AddressꢀBusꢀ(Ax)
BA1 BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Ext.ꢀModeꢀReg.ꢀ(Ex)
Reserved(2)
A2 A1 A0 PASR
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
All banks
Half array (BA1 = 0)
Quarter array (BA1 = BA0 = 0)
Reserved
Reserved
1/8 array
(BA1 = BA0 = Row Addr MSB = 0)
1
1
1
1
0
1
1/16 array
(BA1 = BA0 = Row Addr 2 MSB = 0)
Reserved
Internal TCSR
On-chipꢀtemperatureꢀsensorꢀisꢀusedꢀinꢀplaceꢀofꢀ
TSCR.ꢀSettingꢀtheseꢀbitsꢀwillꢀhaveꢀnoꢀeffect.
A6 A5 Drive Strength
0
0
1
1
0
1
0
1
Full Drive
Half Drive
Quarter Strength Driver
1/8 Strength Driver
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Reserved
Program Extended mode Register
Reserved
NOTES:
1.ꢀMSBꢀdependsꢀonꢀMobileꢀDDRꢀSDRAMꢀdensity.
2. A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.
24
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
11.CKEꢀisꢀHIGHꢀforꢀallꢀcommandsꢀshownꢀexceptꢀSELFꢀREFRESHꢀandꢀDEEPꢀPOWER-DOWN.
10.
BA0ꢀandꢀBA1ꢀvalueꢀselectꢀbetweenꢀMRSꢀandꢀEMRS.
IS43LR16800D, IS43LR32400D
COMMANDS TRUTH TABLES
Allꢀcommandsꢀ(addressꢀandꢀcontrolꢀsignals)ꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀclockꢀ(crossingꢀofꢀCKꢀgoingꢀhighꢀ
andꢀCKꢀgoingꢀlow).ꢀTruthꢀTableꢀshowsꢀbasicꢀtimingꢀparametersꢀforꢀallꢀcommands.ꢀ
TruthꢀTablesꢀforꢀCommandsꢀprovideꢀaꢀquickꢀreferenceꢀofꢀavailableꢀcommands.ꢀTableꢀ"CurrentꢀState"ꢀprovidesꢀtheꢀ
currentꢀstateꢀ/ꢀnextꢀstateꢀinformation.ꢀThisꢀisꢀfollowedꢀbyꢀaꢀdetailedꢀdescriptionꢀofꢀeachꢀcommand.
TRUTH TABLES - COMMANDS
NAME (FUNCTION)
CS
H
L
RAS CAS WE
BA
X
A10/AP Address Notes
DESELECTꢀ(NOP)ꢀ
X
H
L
X
H
H
L
X
H
H
H
X
X
X
X
2
2
NOꢀOPERATIONꢀ(NOP)ꢀ
ACTIVEꢀ(selectꢀbankꢀandꢀactivateꢀrow)ꢀ
X
L
Valid
Valid
Row
L
Row
Col
READꢀ(selectꢀbankꢀandꢀcolumnꢀandꢀstartꢀreadꢀ
burst)ꢀ
L
H
READꢀwithꢀAPꢀ(readꢀburstꢀwithꢀAutoꢀPrecharge)ꢀ
L
L
H
H
L
L
H
L
Valid
Valid
H
L
Col
Col
3
WRITEꢀ(selectꢀbankꢀandꢀcolumnꢀandꢀstartꢀwriteꢀ
burst)ꢀ
WRITEꢀwithꢀAPꢀ(writeꢀburstꢀwithꢀAutoꢀ
Precharge)ꢀ
L
L
L
L
H
H
L
L
H
H
H
L
L
L
L
Valid
X
H
X
L
Col
X
3
4,ꢀ5
6
BURSTꢀTERMINATEꢀorꢀenterꢀDEEPꢀPOWERꢀ
DOWNꢀ
PRECHARGEꢀ(deactivateꢀrowꢀinꢀselectedꢀ
bank)ꢀ
Valid
X
X
PRECHARGEꢀALLꢀ(deactivateꢀrowsꢀinꢀallꢀ
banks)ꢀ
L
H
X
X
6
AUTOꢀREFRESHꢀorꢀenterꢀSELFꢀREFRESHꢀ
MODEꢀREGISTERꢀSETꢀ
L
L
L
L
L
L
H
L
X
X
7,8,9
Valid
Op-code
10
Notes:
1.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
2.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
3.ꢀ Autoprechargeꢀisꢀnon-persistent.ꢀA10ꢀHighꢀenablesꢀAutoꢀPrecharge,ꢀwhileꢀA10ꢀLowꢀdisablesꢀAutoprecharge.
4.ꢀ BurstꢀTerminateꢀappliesꢀtoꢀonlyꢀReadꢀburstsꢀwithꢀAutoꢀPrechargeꢀdisabled.ꢀThisꢀcommandꢀisꢀundefinedꢀandꢀshouldꢀnotꢀbeꢀ
usedꢀforꢀReadꢀwithꢀAutoꢀPrechargeꢀenabled,ꢀandꢀforꢀWriteꢀbursts.
5.ꢀ ThisꢀcommandꢀisꢀBURSTꢀTERMINATEꢀifꢀCKEꢀisꢀHighꢀandꢀDEEPꢀPOWERꢀDOWNꢀentryꢀifꢀCKEꢀisꢀLow.
6.ꢀ IfꢀA10ꢀisꢀLow,ꢀbankꢀaddressꢀdeterminesꢀwhichꢀbankꢀisꢀtoꢀbeꢀprecharged.ꢀIfꢀA10ꢀisꢀHigh,ꢀallꢀbanksꢀareꢀprechargedꢀandꢀBA0-
BA1areꢀdon’tꢀcare.
7.ꢀ ThisꢀcommandꢀisꢀAUTOꢀREFRESHꢀifꢀCKEꢀisꢀHigh,ꢀandꢀSELFꢀREFRESHꢀifꢀCKEꢀisꢀlow.
8.ꢀ AllꢀaddressꢀinputsꢀandꢀI/Oꢀareꢀ‘don'tꢀcare’ꢀexceptꢀforꢀCKE.ꢀInternalꢀrefreshꢀcountersꢀcontrolꢀbankꢀandꢀrowꢀaddressing.
9.ꢀ AllꢀbanksꢀmustꢀbeꢀprechargedꢀbeforeꢀissuingꢀanꢀAUTO-REFRESHꢀorꢀSELFꢀREFRESHꢀcommand.
TRUTH TABLE - DM Operations
FUNCTION
WriteꢀEnableꢀ
Write Inhibit
DM
Lꢀ
DQ
Valid
X
NOTES
1
1
H
Note:ꢀUsedꢀtoꢀmaskꢀwriteꢀdata,ꢀprovidedꢀcoincidentꢀwithꢀtheꢀcorrespondingꢀdata.
Integrated Silicon Solution, Inc. ꢀ
25
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
TRUTH TABLE - CKE
CKE n-1 CKE n Current State
COMMAND n
ACTION n
NOTES
L
L
L
L
PowerꢀDown
X
MaintainꢀPowerꢀDown
MaintainꢀSelfꢀRefresh
MaintainꢀDeepꢀPowerꢀDown
ExitꢀPowerꢀDown
SelfꢀRefresh
X
L
L
DeepꢀPowerꢀDown
PowerꢀDown
X
L
H
H
H
L
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
AUTOꢀREFRESH
BURSTꢀTERMINATE
5,ꢀ6,ꢀ9
5,ꢀ7,ꢀ10
5,ꢀ8
5
L
SelfꢀRefresh
ExitꢀSelfꢀRefresh
L
DeepꢀPowerꢀDown
AllꢀBanksꢀIdle
Bank(s)ꢀActive
AllꢀBanksꢀIdle
AllꢀBanksꢀIdle
ExitꢀDeepꢀPowerꢀDown
PrechargeꢀPowerꢀDownꢀEntry
ActiveꢀPowerꢀDownꢀEntry
SelfꢀRefreshꢀentry
H
H
H
H
H
L
5
L
L
EnterꢀDeepꢀPowerꢀDown
H
SeeꢀtheꢀotherꢀTruthꢀTables
Notes:
1.ꢀ CKEnꢀisꢀtheꢀlogicꢀstateꢀofꢀCKEꢀatꢀclockꢀedgeꢀn;ꢀCKEn-1ꢀwasꢀtheꢀstateꢀofꢀCKEꢀatꢀtheꢀpreviousꢀclockꢀedge.
2.ꢀ CurrentꢀstateꢀisꢀtheꢀstateꢀofꢀMobileꢀDDRꢀimmediatelyꢀpriorꢀtoꢀclockꢀedgeꢀn.
3.ꢀ COMMANDnꢀisꢀtheꢀcommandꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀACTIONnꢀisꢀtheꢀresultꢀofꢀCOMMANDn.
4.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
5.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
6.ꢀ PowerꢀDownꢀexitꢀtimeꢀ(tXP)ꢀshouldꢀelapseꢀbeforeꢀaꢀcommandꢀotherꢀthanꢀNOPꢀorꢀDESELECTꢀisꢀissued.
7.ꢀ SELFꢀREFRESHꢀexitꢀtimeꢀ(tXSR)ꢀshouldꢀelapseꢀbeforeꢀaꢀcommandꢀotherꢀthanꢀNOPꢀorꢀDESELECTꢀisꢀissued.
8.ꢀ TheꢀDeepꢀPower-DownꢀexitꢀprocedureꢀmustꢀbeꢀfollowedꢀasꢀdiscussedꢀinꢀtheꢀDeepꢀPower-DownꢀsectionꢀofꢀtheꢀFunctionalꢀ
Description.
9.ꢀ TheꢀclockꢀmustꢀtoggleꢀatꢀleastꢀonceꢀduringꢀtheꢀtXPꢀperiod.
10.TheꢀclockꢀmustꢀtoggleꢀatꢀleastꢀonceꢀduringꢀtheꢀtXSRꢀtime.
Basic Timing Parameters for Commands
tCK
tCH
tCL
CK
CK
tIS tIH
Valid
Input
Valid
Valid
= Don't Care
NOTE: Input = A0 - An, BA0, BA1, CKE, CS, RAS, CAS, WE;
An = Address bus MSB
26
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK n
CURRENT
STATE
CS RAS CAS WE COMMAND / ACTION
NOTES
Any
Idle
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
DESELECTꢀ(NOPꢀ/ꢀcontinueꢀpreviousꢀoperation)
NoꢀOperationꢀ(NOPꢀ/ꢀcontinueꢀpreviousꢀoperation)
ACTIVEꢀ(selectꢀandꢀactivateꢀrow)
L
AUTOꢀREFRESH
10
10
L
L
MODEꢀREGISTERꢀSET
H
H
L
L
H
L
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀwriteꢀburst)
PRECHARGEꢀ(deactivateꢀrowꢀinꢀbankꢀorꢀbanks)
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀnewꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀwriteꢀburst)
PRECHARGEꢀ(truncateꢀreadꢀburst,ꢀstartꢀprecharge)
BURSTꢀTERMINATE
RowꢀActive
L
H
L
L
4
Read
H
H
L
H
L
5,ꢀ6
5,ꢀ6,13
L
(AutoꢀPrecharge
Disabled)
H
H
L
L
H
H
H
L
L
11
Write
H
L
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀnewꢀwriteꢀburst)
PRECHARGEꢀ(truncateꢀwriteꢀburst,ꢀstartꢀprecharge)
5,ꢀ6,12
5,ꢀ6
12
L
(AutoꢀPrecharge
Disabled)
H
L
Notes:
1.ꢀ TheꢀtableꢀappliesꢀwhenꢀbothꢀCKEn-1ꢀandꢀCKEnꢀareꢀHIGH,ꢀandꢀafterꢀtXSRꢀorꢀtXPꢀhasꢀbeenꢀmetꢀifꢀtheꢀpreviousꢀstateꢀwasꢀSelfꢀ
RefreshꢀorꢀPowerꢀDown.
2.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
3.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
4.ꢀ Thisꢀcommandꢀmayꢀorꢀmayꢀnotꢀbeꢀbankꢀspecific.ꢀIfꢀallꢀbanksꢀareꢀbeingꢀprecharged,ꢀtheyꢀmustꢀbeꢀinꢀaꢀvalidꢀstateꢀforꢀprecharg-
ing.
5.ꢀ AꢀcommandꢀotherꢀthanꢀNOPꢀshouldꢀnotꢀbeꢀissuedꢀtoꢀtheꢀsameꢀbankꢀwhileꢀaꢀREADꢀorꢀWRITEꢀburstꢀwithꢀAutoꢀPrechargeꢀisꢀ
enabled.
6.ꢀ TheꢀnewꢀReadꢀorꢀWriteꢀcommandꢀcouldꢀbeꢀAutoꢀPrechargeꢀenabledꢀorꢀAutoꢀPrechargeꢀdisabled.
7.ꢀ CurrentꢀStateꢀDefinitions:
a.ꢀ Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtRPꢀhasꢀbeenꢀmet.
b.ꢀ RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtRCDꢀhasꢀbeenꢀmet.ꢀNoꢀdataꢀburstsꢀ/ꢀaccessesꢀandꢀnoꢀregisterꢀ
accesses are in progress.
c.ꢀ Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀAutoꢀPrechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀterminated.
d.ꢀ Write:ꢀaꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀAutoꢀPrechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀterminated.
8.ꢀ Theꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀaꢀcommandꢀissuedꢀtoꢀtheꢀsameꢀbank.ꢀDESELECTꢀorꢀNOPꢀcommandsꢀorꢀ
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mandsꢀtoꢀtheꢀotherꢀbankꢀareꢀdeterminedꢀbyꢀitsꢀcurrentꢀstateꢀandꢀTableꢀ8,ꢀandꢀaccordingꢀtoꢀTableꢀ9.
a.ꢀ Precharging:ꢀstartsꢀwithꢀtheꢀregistrationꢀofꢀaꢀPRECHARGEꢀcommandꢀandꢀendsꢀwhenꢀtRPꢀisꢀmet.ꢀOnceꢀtRPꢀisꢀmet,ꢀtheꢀꢀ
bank will be in the idle state.
b.ꢀ RowꢀActivating:ꢀstartsꢀwithꢀregistrationꢀofꢀanꢀACTIVEꢀcommandꢀandꢀendsꢀwhenꢀtRCDꢀisꢀmet.ꢀOnceꢀtRCDꢀisꢀmet,ꢀtheꢀbankꢀꢀ
ꢀ
willꢀbeꢀinꢀtheꢀ‘rowꢀactive’ꢀstate.
c.ꢀ ReadꢀwithꢀAPꢀEnabled:ꢀstartsꢀwithꢀtheꢀregistrationꢀofꢀtheꢀREADꢀcommandꢀwithꢀAutoꢀPrechargeꢀenabledꢀandꢀendsꢀwhenꢀꢀ
tRPꢀhasꢀbeenꢀmet.ꢀOnceꢀtRPꢀhasꢀbeenꢀmet,ꢀtheꢀbankꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
d.ꢀ WriteꢀwithꢀAPꢀEnabled:ꢀstartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀAutoꢀPrechargeꢀenabledꢀandꢀendsꢀwhenꢀtRPꢀꢀ
hasꢀbeenꢀmet.ꢀOnceꢀtRPꢀisꢀmet,ꢀtheꢀbankꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ
ꢀ
Integrated Silicon Solution, Inc. ꢀ
27
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
9.ꢀ Theꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀanyꢀexecutableꢀcommand;ꢀDESELECTꢀorꢀNOPꢀcommandsꢀmustꢀbeꢀappliedꢀtoꢀ
each positive clock edge during these states.
a.ꢀ Refreshing:ꢀstartsꢀwithꢀregistrationꢀofꢀanꢀAUTOꢀREFRESHꢀcommandꢀandꢀendsꢀwhenꢀtRFCꢀisꢀmet.ꢀOnceꢀtRFCꢀisꢀmet,ꢀtheꢀꢀ
ꢀ
deviceꢀwillꢀbeꢀinꢀanꢀ‘allꢀbanksꢀidle’ꢀstate.
b.ꢀ AccessingꢀModeꢀRegister:ꢀstartsꢀwithꢀregistrationꢀofꢀaꢀMODEꢀREGISTERꢀSETꢀcommandꢀandꢀendsꢀwhenꢀtMRDꢀhasꢀbeenꢀꢀ
met.ꢀOnceꢀtMRDꢀisꢀmet,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀanꢀ‘allꢀbanksꢀidle’ꢀstate.
ꢀ
c.ꢀ PrechargingꢀAll:ꢀstartsꢀwithꢀtheꢀregistrationꢀofꢀaꢀPRECHARGEꢀALLꢀcommandꢀandꢀendsꢀwhenꢀtRPꢀisꢀmet.ꢀOnceꢀtRPꢀisꢀmet,ꢀꢀ
the bank will be in the idle state.
10.ꢀNotꢀbank-specific;ꢀrequiresꢀthatꢀallꢀbanksꢀareꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀprogress.
11.ꢀNotꢀbank-specific.ꢀBURSTꢀTERMINATEꢀaffectsꢀtheꢀmostꢀrecentꢀreadꢀburst,ꢀregardlessꢀofꢀbank.
12.ꢀRequiresꢀappropriateꢀDMꢀmasking.
13.ꢀAꢀWRITEꢀcommandꢀmayꢀbeꢀappliedꢀafterꢀtheꢀcompletionꢀofꢀtheꢀREADꢀburst;ꢀotherwise,ꢀaꢀBURSTꢀTERMINATEꢀmustꢀbeꢀusedꢀ
toꢀendꢀtheꢀREADꢀpriorꢀtoꢀassertingꢀaꢀWRITEꢀcommand.
28
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m
CURRENT STATE CS RAS CAS WE COMMAND / ACTION
NOTES
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
DESELECTꢀ(NOPꢀ/ꢀcontinueꢀpreviousꢀoperation)
NoꢀOperationꢀ(NOPꢀ/ꢀcontinueꢀpreviousꢀoperation)
Any command allowed to bank m
ACTIVEꢀ(selectꢀandꢀactivateꢀrow)
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀwriteꢀburst)
PRECHARGE
Idle
RowꢀActivating,
Active, or
H
H
L
8
8
L
Precharging
H
H
L
L
Read
L
H
H
L
ACTIVEꢀ(selectꢀandꢀactivateꢀrow)
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀnewꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀwriteꢀburst)
PRECHARGE
H
H
L
8
(AutoꢀPrecharge
disabled)
L
8,10
H
H
L
L
Write
L
H
H
L
ACTIVEꢀ(selectꢀandꢀactivateꢀrow)
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀnewꢀwriteꢀburst)
PRECHARGE
H
H
L
8,9
8
(AutoꢀPrecharge
disabled)
L
H
H
L
L
L
H
H
L
ACTIVEꢀ(selectꢀandꢀactivateꢀrow)
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀnewꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀwriteꢀburst)
PRECHARGE
Readꢀwith
H
H
L
5,ꢀ8
AutoꢀPrecharge
L
5,ꢀ8,ꢀ10
H
H
L
L
L
H
H
L
ACTIVEꢀ(selectꢀandꢀactivateꢀrow)
READꢀ(selectꢀcolumnꢀ&ꢀstartꢀreadꢀburst)
WRITEꢀ(selectꢀcolumnꢀ&ꢀstartꢀnewꢀwriteꢀburst)
PRECHARGE
Write with
H
H
L
5,ꢀ8
5,ꢀ8
AutoꢀPrecharge
L
H
L
Notes:
1.ꢀ TheꢀtableꢀappliesꢀwhenꢀbothꢀCKEn-1ꢀandꢀCKEnꢀareꢀHIGH,ꢀandꢀafterꢀtXSRꢀorꢀtXPꢀhasꢀbeenꢀmetꢀifꢀtheꢀpreviousꢀstateꢀwasꢀSelfꢀ
RefreshꢀorꢀPowerꢀDown.
2.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
3.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
4.ꢀ CurrentꢀStateꢀDefinitions:
a.ꢀ Idle:ꢀtheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtRPꢀhasꢀbeenꢀmet.
b.ꢀ RowꢀActive:ꢀaꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtRCDꢀhasꢀbeenꢀmet.ꢀNoꢀdataꢀbursts/accessesꢀandꢀnoꢀregisterꢀac-
cesses are in progress.
c.ꢀ Read:ꢀaꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀAutoꢀPrechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀterminated.
d.ꢀ Write:ꢀaꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀAutoꢀPrechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀterminated.
5.ꢀ ReadꢀwithꢀAPꢀenabledꢀandꢀWriteꢀwithꢀAPꢀenabled:ꢀtheꢀReadꢀwithꢀAutoꢀPrechargeꢀenabledꢀorꢀWriteꢀwithꢀAutoꢀPrechargeꢀ
enabledꢀstatesꢀcanꢀbeꢀbrokenꢀintoꢀtwoꢀparts:ꢀtheꢀaccessꢀperiodꢀandꢀtheꢀprechargeꢀperiod.ꢀForꢀReadꢀwithꢀAP,ꢀtheꢀprechargeꢀ
periodꢀisꢀdefinedꢀasꢀifꢀtheꢀsameꢀburstꢀwasꢀexecutedꢀwithꢀAutoꢀPrechargeꢀdisabledꢀandꢀthenꢀfollowedꢀwithꢀtheꢀearliestꢀpossibleꢀ
PRECHARGEꢀcommandꢀthatꢀstillꢀaccessesꢀallꢀtheꢀdataꢀinꢀtheꢀburst.ꢀForꢀWriteꢀwithꢀAP,ꢀtheꢀprechargeꢀperiodꢀbeginsꢀwhenꢀtWRꢀ
ends,ꢀwithꢀtWRꢀmeasuredꢀasꢀifꢀAutoꢀPrechargeꢀwasꢀdisabled.ꢀTheꢀaccessꢀperiodꢀstartsꢀwithꢀregistrationꢀofꢀtheꢀcommandꢀandꢀ
endsꢀwhereꢀtheꢀprechargeꢀperiodꢀ(orꢀtRP)ꢀbegins.ꢀDuringꢀtheꢀprechargeꢀperiodꢀofꢀtheꢀReadꢀwithꢀAPꢀenabledꢀorꢀWriteꢀwithꢀAPꢀ
enabledꢀstates,ꢀACTIVE,ꢀPRECHARGE,ꢀREAD,ꢀandꢀWRITEꢀcommandsꢀtoꢀtheꢀotherꢀbankꢀmayꢀbeꢀapplied;ꢀduringꢀtheꢀaccessꢀ
period,ꢀonlyꢀACTIVEꢀandꢀPRECHARGEꢀcommandsꢀtoꢀtheꢀotherꢀbanksꢀmayꢀbeꢀapplied.ꢀInꢀeitherꢀcase,ꢀallꢀotherꢀrelatedꢀlimita-
tionsꢀapplyꢀ(e.g.ꢀcontentionꢀbetweenꢀREADꢀdataꢀandꢀWRITEꢀdataꢀmustꢀbeꢀavoided).
6.ꢀAUTOꢀREFRESH,ꢀSELFꢀREFRESH,ꢀandꢀMODEꢀREGISTERꢀSETꢀcommandsꢀmayꢀonlyꢀbeꢀissuedꢀwhenꢀallꢀbankꢀareꢀidle.
7.ꢀAꢀBURSTꢀTERMINATEꢀcommandꢀcannotꢀbeꢀissuedꢀtoꢀanotherꢀbank;ꢀitꢀappliesꢀtoꢀtheꢀbankꢀrepresentedꢀbyꢀtheꢀcurrentꢀstateꢀonly.
8.ꢀREADsꢀorꢀWRITEsꢀlistedꢀinꢀtheꢀCommandꢀcolumnꢀincludeꢀREADsꢀandꢀWRITEsꢀwithꢀAutoꢀPrechargeꢀenabledꢀandꢀREADsꢀandꢀ
WRITEsꢀwithꢀAutoꢀPrechargeꢀdisabled.
9.ꢀRequiresꢀappropriateꢀDMꢀmasking.
10.ꢀAꢀWRITEꢀcommandꢀmayꢀbeꢀappliedꢀafterꢀtheꢀcompletionꢀofꢀdataꢀoutput,ꢀotherwiseꢀaꢀBURSTꢀTERMINATEꢀcommandꢀmustꢀbeꢀ
issuedꢀtoꢀendꢀtheꢀREADꢀpriorꢀtoꢀassertingꢀaꢀWRITEꢀcommand.
Integrated Silicon Solution, Inc.
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IS43LR16800D, IS43LR32400D
OPERATION
DESELECT
TheꢀDESELECTꢀfunctionꢀ(CSꢀ=ꢀHigh)ꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀexecutedꢀbyꢀtheꢀMobileꢀDDRꢀSDRAM.ꢀꢀTheꢀ
MobileꢀDDRꢀSDRAMꢀisꢀeffectivelyꢀdeselected.ꢀOperationsꢀalreadyꢀinꢀprogressꢀareꢀnotꢀaffected.
NO OPERATION
TheꢀNOꢀOPERATIONꢀ(NOP)ꢀcommandꢀisꢀusedꢀtoꢀperformꢀaꢀNOPꢀtoꢀaꢀMobileꢀDDRꢀSDRAMꢀthatꢀisꢀselectedꢀ(CS
=ꢀLow).ꢀThisꢀpreventsꢀunwantedꢀcommandsꢀfromꢀbeingꢀregisteredꢀduringꢀidleꢀorꢀwaitꢀstates.ꢀOperationsꢀalreadyꢀinꢀ
progress are not affected.
NOP Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-An
BA0,BA1
= Don't Care
MODE REGISTER SET
TheꢀModeꢀRegisterꢀandꢀtheꢀExtendedꢀModeꢀRegisterꢀareꢀloadedꢀviaꢀtheꢀaddressꢀinputs.ꢀSeeꢀ"ModeꢀRegister"ꢀandꢀtheꢀ
"ExtendedꢀModeꢀRegister"ꢀdescriptionsꢀforꢀfurtherꢀdetails.ꢀ
TheꢀMODEꢀREGISTERꢀSETꢀcommandꢀcanꢀonlyꢀbeꢀissuedꢀwhenꢀallꢀbanksꢀareꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀprogress,ꢀandꢀ
aꢀsubsequentꢀexecutableꢀcommandꢀcannotꢀbeꢀissuedꢀuntilꢀtMRDꢀ(seeꢀ"ModeꢀRegisterꢀSetꢀCommandꢀTiming")ꢀisꢀmet.ꢀ
Mode Register Set command
CK
CK
Mode Register Set Command Timing
CKE
(High)
CK
CK
CS
Command
MRS
Code
NOP
tMRD
Valid
RAS
CAS
Address
Valid
WE
= Don't Care
A0-An
BA0,BA1
Code
NOTE: Code = Mode Register / Extended Mode Register selection
Code
(BA0, BA1) and op-code (A0 - An)
= Don't Care
30
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
ACTIVE
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀtoꢀaꢀbankꢀinꢀtheꢀMobileꢀDDRꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀ
beꢀopened.ꢀThisꢀisꢀaccomplishedꢀbyꢀtheꢀACTIVEꢀcommand:ꢀBA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀandꢀtheꢀaddressꢀinputsꢀ
selectꢀtheꢀrowꢀtoꢀbeꢀactivated.ꢀMoreꢀthanꢀoneꢀbankꢀcanꢀbeꢀactiveꢀatꢀanytime.ꢀ
Onceꢀaꢀrowꢀisꢀopen,ꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcouldꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀtheꢀtRCDꢀspecification.ꢀ
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀrowꢀinꢀtheꢀsameꢀbankꢀcanꢀonlyꢀbeꢀissuedꢀafterꢀtheꢀpreviousꢀrowꢀhasꢀbeenꢀ
closed.ꢀTheꢀminimumꢀtimeꢀintervalꢀbetweenꢀtwoꢀsuccessiveꢀACTIVEꢀcommandsꢀonꢀtheꢀsameꢀbankꢀisꢀdefinedꢀbyꢀtRC.ꢀ
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀissuedꢀwhileꢀtheꢀfirstꢀbankꢀisꢀbeingꢀaccessed,ꢀwhichꢀresultsꢀ
inꢀaꢀreductionꢀofꢀtotalꢀrowꢀaccessꢀoverhead.ꢀTheꢀminimumꢀtimeꢀintervalꢀbetweenꢀtwoꢀsuccessiveꢀACTIVEꢀcommandsꢀ
onꢀdifferentꢀbanksꢀisꢀdefinedꢀbyꢀtRRD.ꢀBankꢀActivationꢀCommandꢀCycleꢀshowsꢀtheꢀtRCDꢀandꢀtRRDꢀdefinition.ꢀ
TheꢀrowꢀremainsꢀactiveꢀuntilꢀaꢀPRECHARGEꢀcommandꢀ(orꢀREADꢀorꢀWRITEꢀcommandꢀwithꢀAutoꢀPrecharge)ꢀisꢀissuedꢀ
to the bank.
AꢀPRECHARGEꢀcommandꢀ(orꢀREADꢀorꢀWRITEꢀcommandꢀwithꢀAutoꢀPrecharge)ꢀmustꢀbeꢀissuedꢀbeforeꢀopeningꢀaꢀ
different row in the same bank.
ACTIVE command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-An
BA0,BA1
RA
BA
= Don't Care
BA = Bank Address
RA = Row Address
Bank Activation Command Cycle
CK
CK
Command
A0-An
ACT
Row
BA x
NOP
ACT
Row
BA y
NOP
NOP
RD/WR
Col
NOP
BA0, BA1
BA y
tRRD
tRCD
= Don't Care
Integrated Silicon Solution, Inc.
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Rev. 00D
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IS43LR16800D, IS43LR32400D
READ
READ Command
TheꢀREADꢀcommandꢀisꢀusedꢀtoꢀinitiateꢀaꢀburstꢀreadꢀaccessꢀtoꢀ
anꢀactiveꢀrow,ꢀwithꢀaꢀburstꢀlengthꢀasꢀsetꢀinꢀtheꢀModeꢀRegister.ꢀ
BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀandꢀtheꢀaddressꢀinputsꢀselectꢀ
theꢀstartingꢀcolumnꢀlocation.ꢀTheꢀvalueꢀofꢀA10ꢀdeterminesꢀ
whetherꢀorꢀnotꢀAutoꢀPrechargeꢀisꢀused.ꢀIfꢀAutoꢀPrechargeꢀisꢀ
selected, the row being accessed will be precharged at the
endꢀofꢀtheꢀreadꢀburst;ꢀifꢀAutoꢀPrechargeꢀisꢀnotꢀselected,ꢀtheꢀ
rowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccesses.
CK
CK
CKE
(High)
CS
RAS
CAS
WE
TheꢀbasicꢀReadꢀtimingꢀparametersꢀforꢀDQsꢀareꢀshownꢀinꢀ
FigureꢀBasicꢀReadꢀTimingꢀParametersꢀtheyꢀapplyꢀtoꢀallꢀReadꢀ
operations.
A0-An
CA
DuringꢀReadꢀbursts,ꢀDQSꢀisꢀdrivenꢀbyꢀtheꢀMobileꢀDDRꢀ
SDRAMꢀalongꢀwithꢀtheꢀoutputꢀdata.ꢀTheꢀinitialꢀLowꢀstateꢀ
ofꢀtheꢀDQSꢀisꢀknownꢀasꢀtheꢀreadꢀpreamble;ꢀtheꢀLowꢀstateꢀ
coincident with last data-out element is known as the read
postamble.ꢀTheꢀfirstꢀdata-outꢀelementꢀisꢀedgeꢀalignedꢀwithꢀ
theꢀfirstꢀrisingꢀedgeꢀofꢀDQSꢀandꢀtheꢀsuccessiveꢀdata-outꢀ
elementsꢀareꢀedgeꢀalignedꢀtoꢀsuccessiveꢀedgesꢀofꢀDQS.ꢀThisꢀ
isꢀshownꢀinꢀFigureꢀReadꢀBurstꢀShowingꢀCASꢀLatencyꢀwithꢀaꢀ
CAS latency of 2 and 3.
Enable AP
AP
Disable AP
A10
BA0,BA1
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Uponꢀcompletionꢀofꢀaꢀreadꢀburst,ꢀassumingꢀnoꢀotherꢀREADꢀ
commandꢀhasꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀtoꢀHigh-Z.
Basic Read Timing Parameters
tCK
tCK
tCH
tCL
CK
CK
tDQSCK
tDQSCK
tACmax
tRPST
tRPRE
DQS
DQ
tDQSQmax
tAC
tLZ
tHZ
DO n DO n+1 DO n+2 DO n+3
tQH tQH
tDQSCK
tDQSCK
tACmin
tRPST
tRPRE
DQS
DQ
tDQSQmax
tAC
tLZ
tHZ
DO n
tQH
DO n+1 DO n+2 DO n+3
tQH
= Don't Care
Notes:
1.ꢀ DOꢀnꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn
2.ꢀ AllꢀDQꢀareꢀvalidꢀtACꢀafterꢀtheꢀCKꢀedge.
AllꢀDQꢀareꢀvalidꢀtDQSQꢀafterꢀtheꢀDQSꢀedge,ꢀregardlessꢀofꢀtAC
32
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Read Burst Showing CAS Latency
CK
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
Address
BA,Col n
CL=2
DQS
DQ
DO n
CL=3
DQS
DQ
DO n
= Don't Care
Notes:
1.ꢀ DOꢀnꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn
2.ꢀ BA,ꢀColꢀnꢀ=ꢀBankꢀA,ꢀColumnꢀn
3.ꢀ BurstꢀLengthꢀ=ꢀ4;ꢀ3ꢀsubsequentꢀelementsꢀofꢀDataꢀOutꢀappearꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDOꢀn
4.ꢀ ShownꢀwithꢀnominalꢀtAC,ꢀtDQSCKꢀandꢀtDQSQ
READ to READ
DataꢀfromꢀaꢀreadꢀburstꢀmayꢀbeꢀconcatenatedꢀorꢀtruncatedꢀbyꢀaꢀsubsequentꢀREADꢀcommand.ꢀTheꢀfirstꢀdataꢀfromꢀtheꢀ
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is
beingꢀtruncated.ꢀTheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀXꢀcyclesꢀafterꢀtheꢀfirstꢀREADꢀcommand,ꢀwhereꢀXꢀequalsꢀ
theꢀnumberꢀofꢀdesiredꢀdata-outꢀelementꢀpairsꢀ(pairsꢀareꢀrequiredꢀbyꢀtheꢀ2nꢀprefetchꢀarchitecture).ꢀ
AꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀfollowingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀreadꢀ
accessesꢀwithinꢀaꢀpageꢀorꢀpagesꢀcanꢀbeꢀperformedꢀasꢀshownꢀinꢀFigureꢀRandomꢀReadꢀBursts.
READ BURST TERMINATE
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand.ꢀTheꢀBURSTꢀTERMINATEꢀlatencyꢀ
isꢀequalꢀtoꢀtheꢀreadꢀ(CAS)ꢀlatency,ꢀi.e.,ꢀtheꢀBURSTꢀTERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀXꢀcyclesꢀafterꢀtheꢀREADꢀ
commandꢀwhereꢀXꢀequalsꢀtheꢀdesiredꢀdata-outꢀelementꢀpairs.
READ to WRITE
DataꢀfromꢀREADꢀburstꢀmustꢀbeꢀcompletedꢀorꢀtruncatedꢀbeforeꢀaꢀsubsequentꢀWRITEꢀcommandꢀcanꢀbeꢀissued.ꢀIfꢀ
truncationꢀisꢀnecessary,ꢀtheꢀBURSTꢀTERMINATEꢀcommandꢀmustꢀbeꢀused,ꢀasꢀshownꢀinꢀFigureꢀReadꢀtoꢀWriteꢀforꢀtheꢀ
caseꢀofꢀnominalꢀtDQSS.
READ to PRECHARGE
AꢀReadꢀburstꢀmayꢀbeꢀfollowedꢀbyꢀorꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbankꢀ(providedꢀAutoꢀ
Prechargeꢀwasꢀnotꢀactivated).ꢀTheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀXꢀcyclesꢀafterꢀtheꢀREADꢀcommand,ꢀ
whereꢀXꢀequalꢀtheꢀnumberꢀofꢀdesiredꢀdata-outꢀelementꢀpairs.
FollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀsameꢀbankꢀcannotꢀbeꢀissuedꢀuntilꢀtRPꢀisꢀmet.ꢀ
Note that part of the row precharge time is hidden during the access of the last data-out elements.
InꢀtheꢀcaseꢀofꢀaꢀReadꢀbeingꢀexecutedꢀtoꢀcompletion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀtimeꢀ(asꢀ
describedꢀabove)ꢀprovidesꢀtheꢀsameꢀoperationꢀthatꢀwouldꢀresultꢀfromꢀReadꢀburstꢀwithꢀAutoꢀPrechargeꢀenabled.ꢀTheꢀ
disadvantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀandꢀaddressꢀbusesꢀbeꢀavailableꢀatꢀ
theꢀappropriateꢀtimeꢀtoꢀissueꢀtheꢀcommand.ꢀTheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀusedꢀtoꢀ
truncate bursts.
Integrated Silicon Solution, Inc.
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Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Consecutive Read Bursts
CK
CK
Command
READ
NOP
READ
NOP
NOP
NOP
Address
BA,Col n
BA,Col b
CL=2
DQS
DQ
DO n
DO b
CL=3
DQS
DQ
DO n
DO b
= Don't Care
Notes:
1.ꢀ DOꢀnꢀ(orꢀb)ꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀnꢀ(orꢀcolumnꢀb).
2.ꢀ BurstꢀLengthꢀ=ꢀ4,ꢀ8ꢀorꢀ16ꢀ(ifꢀ4,ꢀtheꢀburstsꢀaꢀreꢀconcatenated;ꢀifꢀ8ꢀorꢀ16,ꢀtheꢀsecondꢀburstꢀinterruptsꢀtheꢀfirst).
3.ꢀ Readꢀburstsꢀareꢀtoꢀanꢀactiveꢀrowꢀinꢀanyꢀbank.
4.ꢀ ShownꢀwithꢀnominalꢀtAC,ꢀtDQSCKꢀandꢀtDQSQ.
Non-Consecutive Read Bursts
CK
CK
Command
READ
NOP
NOP
READ
NOP
NOP
Address
BA,Col n
BA,Col b
CL=2
DQS
DQ
DO n
CL=3
DO b
DQS
DQ
DO n
= Don't Care
Notes:
1.ꢀ DOꢀnꢀ(orꢀb)ꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀnꢀ(orꢀcolumnꢀb).
2.ꢀ BAꢀColꢀnꢀ(b)ꢀ=ꢀBankꢀA,ꢀColumnꢀnꢀ(b).
3.ꢀ BurstꢀLengthꢀ=ꢀ4;ꢀ3ꢀsubsequentꢀelementsꢀofꢀDataꢀOutꢀappearꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDOꢀnꢀ(b).
4.ꢀ ShownꢀwithꢀnominalꢀtAC,ꢀtDQSCKꢀandꢀtDQSQ.
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Random Read Bursts
CK
CK
Command
READ
READ
READ
READ
BA,Col g
NOP
NOP
Address
BA,Col n
BA,Col x
BA,Col b
CL=2
DQS
DQ
DO n
CL=3
DO n' DO x DO x' DO b DO b' DO g DO g'
DQS
DQ
DO n
DO n' DO x DO x' DO b DO b'
= Don't Care
Notes:
1.ꢀ DOꢀn,ꢀeꢀtc.ꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn,ꢀetc.
n',ꢀx',ꢀeꢀtc.ꢀ=ꢀDataꢀOutꢀelements,ꢀaccordingꢀtoꢀtheꢀprogrammedꢀburstꢀorder.
2.ꢀ BA,ꢀColꢀnꢀ=ꢀBankꢀA,ꢀColumnꢀn.
3.ꢀ BurstꢀLengthꢀ=ꢀ2,ꢀ4,ꢀ8ꢀorꢀ16ꢀinꢀcasesꢀshownꢀ(ifꢀburstꢀofꢀ4,ꢀ8ꢀorꢀ16,ꢀtheꢀburstꢀisꢀinterrupted).
4.ꢀ Readsꢀareꢀtoꢀactiveꢀrowsꢀinꢀanyꢀbanks.
Terminating a Read Burst
CK
CK
Command
READ
BST
NOP
NOP
NOP
NOP
Address
BA,Col n
CL=2
DQS
CL=3
DQS
DQ
= Don't Care
Notes:
1.ꢀ DOꢀnꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn.
2.ꢀ BA,ꢀColꢀnꢀ=ꢀBankꢀA,ꢀColumnꢀn.
3.ꢀ Casesꢀshownꢀareꢀburstsꢀofꢀ4,ꢀ8ꢀorꢀ16ꢀterminatedꢀafterꢀ2ꢀdataꢀelements.
4.ꢀ ShownꢀwithꢀnominalꢀtAC,ꢀtDQSCKꢀandꢀtDQSQ.
Integrated Silicon Solution, Inc. ꢀ
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IS43LR16800D, IS43LR32400D
Read To Write
CK
CK
Command
READ
BST
NOP
WRITE
NOP
NOP
Address
BA,Col n
BA,Col b
CL=2
tDQSS
DQS
DQ
DO n
DM
Command
Address
READ
BST
NOP
NOP
WRITE
NOP
BA,Col n
BA,Col b
CL=3
DQS
DQ
DO n
DM
= Don't Care
Notes:
1.ꢀ DOnꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn;ꢀDIbꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀb.
2.ꢀ Burstꢀlengthꢀ=ꢀ4,ꢀ8ꢀorꢀ16ꢀinꢀtheꢀcasesꢀshown;ꢀifꢀtheꢀburstꢀlengthꢀisꢀ2,ꢀtheꢀBSTꢀcommandꢀcanꢀbeꢀomitted.
3.ꢀ ShownꢀwithꢀnominalꢀtAC,ꢀtDQSCKꢀandꢀtDQSQ.
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Integrated Silicon Solution, Inc.
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IS43LR16800D, IS43LR32400D
Read To Precharge
CK
CK
Command
READ
NOP
PRE
NOP
NOP
ACT
Bank
Address
BA,Col n
BA, Row
(a or all)
tRP
CL=2
DQS
DQ
DO n
CL=3
DQS
DQ
DO n
= Don't Care
Notes:
1.ꢀ DOꢀnꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn.
2.ꢀ Casesꢀshownꢀareꢀeitherꢀuninterruptedꢀburstꢀofꢀ4,ꢀorꢀinterruptedꢀburstsꢀofꢀ8ꢀorꢀ16.
3.ꢀ ShownꢀwithꢀnominalꢀtAC,ꢀtDQSCKꢀandꢀtDQSQ.
4.ꢀ Prechargeꢀmayꢀbeꢀappliedꢀatꢀ(BLꢀ/ꢀ2)ꢀtCKꢀafterꢀtheꢀREADꢀcommand.
5.ꢀ NoteꢀthatꢀPrechargeꢀmayꢀnotꢀbeꢀissuedꢀbeforeꢀtRASꢀnsꢀafterꢀtheꢀACTIVEꢀcommandꢀforꢀapplicableꢀbanks.
6.ꢀ TheꢀACTIVEꢀcommandꢀmayꢀbeꢀappliedꢀifꢀtRCꢀhasꢀbeenꢀmet.
Burst Terminate
TheꢀBURSTꢀTERMINATEꢀcommandꢀisꢀusedꢀtoꢀtruncateꢀreadꢀburstsꢀ(withꢀAutoꢀPrechargeꢀdisabled).ꢀTheꢀmostꢀrecentlyꢀ
registeredꢀREADꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀtruncated.ꢀNoteꢀthatꢀtheꢀBURSTꢀ
TERMINATEꢀcommandꢀisꢀnotꢀbankꢀspecific.
Thisꢀcommandꢀshouldꢀnotꢀbeꢀusedꢀtoꢀterminateꢀwriteꢀbursts.
Burst Terminate Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-An
BA0,BA1
= Don't Care
Integrated Silicon Solution, Inc. ꢀ
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Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
WRITE
WRITE command
TheꢀWRITEꢀcommandꢀisꢀusedꢀtoꢀinitiateꢀaꢀburstꢀwriteꢀaccessꢀ
toꢀanꢀactiveꢀrow,ꢀwithꢀaꢀburstꢀlengthꢀasꢀsetꢀinꢀtheꢀModeꢀ
Register.ꢀBA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀandꢀtheꢀaddressꢀ
inputsꢀselectꢀtheꢀstartingꢀcolumnꢀlocation.ꢀTheꢀvalueꢀofꢀ
A10ꢀdeterminesꢀwhetherꢀorꢀnotꢀAutoꢀPrechargeꢀisꢀused.ꢀIfꢀ
AutoꢀPrechargeꢀisꢀselected,ꢀtheꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀ
prechargedꢀatꢀtheꢀendꢀofꢀtheꢀwriteꢀburst;ꢀifꢀAutoꢀPrechargeꢀ
isꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀ
accesses.
CK
CK
CKE
(High)
CS
RAS
CAS
WE
BasicꢀWriteꢀtimingꢀparametersꢀforꢀDQsꢀareꢀshownꢀinꢀFigureꢀ
BasicꢀWriteꢀTimingꢀParameters;ꢀtheyꢀapplyꢀtoꢀallꢀWriteꢀ
operations.
A0-An
CA
Input data appearing on the data bus, is written to the
memoryꢀarrayꢀsubjectꢀtoꢀtheꢀDMꢀinputꢀlogicꢀlevelꢀappearingꢀ
coincidentꢀwithꢀtheꢀdata.ꢀIfꢀaꢀgivenꢀDMꢀsignalꢀisꢀregisteredꢀ
Low,ꢀtheꢀcorrespondingꢀdataꢀwillꢀbeꢀwrittenꢀtoꢀtheꢀmemory;ꢀ
ifꢀtheꢀDMꢀsignalꢀisꢀregisteredꢀHigh,ꢀtheꢀcorrespondingꢀdataꢀ
inputsꢀwillꢀbeꢀignored,ꢀandꢀaꢀwriteꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte / column location.
Enable AP
AP
Disable AP
A10
BA0,BA1
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Basic Write Timing Parameters
tCK
tCH
tCL
CK
CK
Case 1:
tDQSS = min
tDSH
tDSH
tDQSS
tDQSH
tWPST
DQS
tWPRES
tDQSL
tWPRE
tDS
tDH
DQ, DM
DI n
Case 2:
tDQSS = max
DQS
tDSS
tDSS
tDQSS
tDQSH
tWPST
tWPRES
tDQSL
tWPRE
tDH
tDS
DQ, DM
DI n
= Don't Care
Notes:
1.ꢀ DIꢀnꢀ=ꢀDataꢀInꢀforꢀcolumnꢀn.
2.ꢀ 3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀn.
3.ꢀ tDQSS:ꢀeachꢀrisingꢀedgeꢀofꢀDQSꢀmustꢀfallꢀwithinꢀtheꢀ±ꢀ25%ꢀwindowꢀofꢀtheꢀcorrespondingꢀpositiveꢀclockꢀedge.
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Integrated Silicon Solution, Inc.
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IS43LR16800D, IS43LR32400D
DuringꢀWriteꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-inꢀelementꢀwillꢀbeꢀregisteredꢀonꢀtheꢀfirstꢀrisingꢀedgeꢀofꢀDQSꢀfollowingꢀtheꢀ
WRITEꢀcommand,ꢀandꢀtheꢀsubsequentꢀdataꢀelementsꢀwillꢀbeꢀregisteredꢀonꢀsuccessiveꢀedgesꢀofꢀDQS.ꢀTheꢀLowꢀstateꢀ
ofꢀDQSꢀbetweenꢀtheꢀWRITEꢀcommandꢀandꢀtheꢀfirstꢀrisingꢀedgeꢀisꢀcalledꢀtheꢀwriteꢀpreamble,ꢀandꢀtheꢀLowꢀstateꢀonꢀ
DQSꢀfollowingꢀtheꢀlastꢀdata-inꢀelementꢀisꢀcalledꢀtheꢀwriteꢀpostamble.ꢀTheꢀtimeꢀbetweenꢀtheꢀWRITEꢀcommandꢀandꢀtheꢀ
firstꢀcorrespondingꢀrisingꢀedgeꢀofꢀDQSꢀ(tDQSS)ꢀisꢀspecifiedꢀwithꢀaꢀrelativelyꢀwideꢀrangeꢀ-ꢀfromꢀ75%ꢀtoꢀ125%ꢀofꢀaꢀclockꢀ
cycle.ꢀTheꢀfigureꢀbelowꢀshowsꢀtheꢀtwoꢀextremesꢀofꢀtDQSSꢀforꢀaꢀburstꢀofꢀ4.ꢀUponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀ
otherꢀcommandsꢀhaveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀremainꢀhigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀbeꢀignored.
Write Burst (min. and max. tDQSS)
CK
CK
Command
WRITE
NOP
NOP
NOP
NOP
NOP
Address
BA,Col b
tDQSSmin
DQS
DQ
DM
tDQSSmax
DQS
DQ
DM
= Don't Care
Notes:ꢀ
1.ꢀ DIꢀbꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀb.
2.ꢀ 3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀaꢀreꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀb.
3.ꢀ Aꢀnon-interruptedꢀburstꢀofꢀ4ꢀisꢀshown.
4.ꢀ A10ꢀisꢀLOWꢀwithꢀtheꢀWRITEꢀcommandꢀ(AutoꢀPrechargeꢀisꢀdisabled).
WRITE to WRITE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀconcatenatedꢀwithꢀorꢀtruncatedꢀwithꢀaꢀsubsequentꢀWRITEꢀcommand.ꢀInꢀeitherꢀcase,ꢀ
aꢀcontinuousꢀflowꢀofꢀinputꢀdata,ꢀcanꢀbeꢀmaintained.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀanyꢀpositiveꢀedgeꢀofꢀ
theꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand.
Theꢀfirstꢀdata-inꢀelementꢀfromꢀtheꢀnewꢀburstꢀisꢀappliedꢀafterꢀeitherꢀtheꢀlastꢀelementꢀofꢀaꢀcompletedꢀburstꢀorꢀtheꢀlastꢀ
desiredꢀdataꢀelementꢀofꢀaꢀlongerꢀburstꢀwhichꢀisꢀbeingꢀtruncated.ꢀTheꢀnewꢀWRITEꢀcommandꢀshouldꢀbeꢀissuedꢀXꢀcyclesꢀ
afterꢀtheꢀfirstꢀWRITEꢀcommand,ꢀwhereꢀXꢀequalsꢀtheꢀnumberꢀofꢀdesiredꢀdata-inꢀelementꢀpairs.ꢀ
Full-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀaꢀpageꢀorꢀpagesꢀcanꢀbeꢀperformedꢀasꢀshownꢀinꢀFigureꢀ29.
WRITE to READ
DataꢀforꢀanyꢀWriteꢀburstꢀmayꢀbeꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀcommand.ꢀToꢀfollowꢀaꢀWriteꢀwithoutꢀtruncatingꢀtheꢀ
writeꢀburst,ꢀtWTRꢀshouldꢀbeꢀmetꢀasꢀshownꢀinꢀNon-interruptingꢀWriteꢀtoꢀRead.ꢀ
DataꢀforꢀanyꢀWriteꢀburstꢀmayꢀbeꢀtruncatedꢀbyꢀaꢀsubsequentꢀREADꢀcommandꢀasꢀshownꢀinꢀFigureꢀInterruptingꢀWriteꢀtoꢀ
Read.ꢀNoteꢀthatꢀtheꢀonlyꢀdata-inꢀpairsꢀthatꢀareꢀregisteredꢀpriorꢀtoꢀtheꢀtWTRꢀperiodꢀareꢀwrittenꢀtoꢀtheꢀinternalꢀarray,ꢀandꢀ
anyꢀsubsequentꢀdata-inꢀmustꢀbeꢀmaskedꢀwithꢀDM.
Integrated Silicon Solution, Inc.
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Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
WRITE to PRECHARGE:
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀfollowedꢀbyꢀaꢀsubsequentꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbankꢀ(providedꢀ
AutoꢀPrechargeꢀwasꢀnotꢀactivated).ꢀToꢀfollowꢀaꢀWRITEꢀwithoutꢀtruncatingꢀtheꢀWRITEꢀburst,ꢀtWRꢀshouldꢀbeꢀmet.ꢀDataꢀ
forꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀbyꢀaꢀsubsequentꢀPRECHARGEꢀcommand.
Noteꢀthatꢀonlyꢀdata-inꢀpairsꢀthatꢀareꢀregisteredꢀpriorꢀtoꢀtheꢀtWRꢀperiodꢀareꢀwrittenꢀtoꢀtheꢀinternalꢀarray,ꢀandꢀanyꢀ
subsequentꢀdata-inꢀshouldꢀbeꢀmaskedꢀwithꢀDM.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀ
theꢀsameꢀbankꢀcannotꢀbeꢀissuedꢀuntilꢀtRPꢀisꢀmet.
Concatenated Write Bursts
CK
CK
Command
WRITE
NOP
WRITE
NOP
NOP
NOP
Address
BA,Col b
BA,Col n
tDQSSmin
DQS
DQ
Di b
Di n
DM
tDQSSmax
DQS
DQ
Di b
Di n
DM
= Don't Care
Notes:
1.ꢀ DIꢀbꢀ(n)ꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀbꢀ(columnꢀn).
2.ꢀ 3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀb.
3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀn.
3.ꢀ Non-interruptedꢀburstsꢀofꢀ4ꢀareꢀshown.
4.ꢀ EachꢀWRITEꢀcommandꢀmayꢀbeꢀtoꢀanyꢀactiveꢀbank.
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Non-Consecutive Write Bursts
CK
CK
Command
WRITE
NOP
NOP
WRITE
NOP
NOP
Address
BA,Col b
BA,Col n
tDQSSmax
DQS
DQ
DM
= Don't Care
Notes:
1.ꢀ DIꢀbꢀ(n)ꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀbꢀ(orꢀcolumnꢀn).
2.ꢀ 3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀaꢀreꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀb.
3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀn.
3.ꢀ Non-interruptedꢀburstsꢀofꢀ4ꢀareꢀshown.
4.ꢀ EachꢀWRITEꢀcommandꢀmayꢀbeꢀtoꢀanyꢀactiveꢀbankꢀandꢀmayꢀbeꢀtoꢀtheꢀsameꢀorꢀdifferentꢀdevices.
Random Write Cycles
CK
CK
Command
WRITE
WRITE
WRITE
WRITE
WRITE
NOP
Address
BA,Col b
BA,Col x
BA,Col n
BA,Col a
BA,Col g
tDQSSmax
DQS
DQ
Di b
Di b'
Di x
Di x'
Di n
Di n'
Di a
Di a'
DM
= Don't Care
Notes:
1.ꢀ DIꢀbꢀetc.ꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀb,ꢀetc.ꢀ;
b',ꢀetc.ꢀ=ꢀtheꢀnextꢀDataꢀInꢀfollowingꢀDIꢀb,ꢀetc.ꢀaccordingꢀtoꢀtheꢀprogrammedꢀburstꢀorder.
2.ꢀ Programmedꢀbursꢀtꢀlengthꢀ=ꢀ2,ꢀ4,ꢀ8ꢀorꢀ16ꢀinꢀcasesꢀshown.ꢀIfꢀburstꢀofꢀ4,ꢀ8ꢀorꢀ16,ꢀburstꢀwouldꢀbeꢀtruncated.
3.ꢀ EachꢀWRITEꢀcommandꢀmayꢀbeꢀtoꢀanyꢀactiveꢀbankꢀandꢀmayꢀbeꢀtoꢀtheꢀsameꢀorꢀdifferentꢀdevices.
Integrated Silicon Solution, Inc. ꢀ
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Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Non-Interrupting Write to Read
CK
CK
Command
WRITE
NOP
NOP
NOP
READ
NOP
NOP
Address
BA,Col b
BA,Col n
tDQSSmax
tWTR
CL=3
DQS
DQ
Di b
DM
= Don't Care
Notes:
1.ꢀ DIꢀbꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀbꢀ.
3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀb.
2.ꢀ Aꢀnon-interruptedꢀburstꢀofꢀ4ꢀisꢀshown.
3.ꢀ tWTRꢀisꢀreferencedꢀfromꢀtheꢀpositiveꢀclockꢀedgeꢀafterꢀtheꢀlastꢀDataꢀInꢀpair.
4.ꢀ A10ꢀisꢀLOWꢀwithꢀtheꢀWRITEꢀcommandꢀ(AutoꢀPrechargeꢀisꢀdisabled).
5.ꢀ TheꢀREADꢀandꢀWRITEꢀcommandsꢀaꢀreꢀtoꢀtheꢀsameꢀdeviceꢀbutꢀnotꢀnecessarilyꢀtoꢀtheꢀsameꢀbank.
Interrupting Write to Read
CK
CK
Command
WRITE
NOP
NOP
READ
NOP
NOP
NOP
Address
BA,Col b
BA,Col n
tDQSSmax
tWTR
CL=3
DQS
DQ
Di b
DO n
DM
= Don't Care
Notes:
1.ꢀ DIꢀbꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀb.ꢀDOꢀnꢀ=ꢀDataꢀOutꢀfromꢀcolumnꢀn.
2.ꢀ Anꢀinterruptedꢀburstꢀofꢀ4ꢀisꢀshown,ꢀ2ꢀdataꢀelementsꢀaꢀreꢀwritten.
3ꢀsubsequentꢀelementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀb.
3.ꢀ tWTRꢀisꢀreferencedꢀfromꢀtheꢀpositiveꢀclockꢀedgeꢀafterꢀtheꢀlastꢀDataꢀInꢀpair.
4.ꢀ A10ꢀisꢀLOWꢀwithꢀtheꢀWRITEꢀcommandꢀ(AutoꢀPrechargeꢀisꢀdisabled).
5.ꢀ TheꢀREADꢀandꢀWRITEꢀcommandsꢀareꢀtoꢀtheꢀsameꢀdeviceꢀbutꢀnotꢀnecessarilyꢀtoꢀtheꢀsameꢀbank.
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Non-Interrupting Write to Precharge
CK
CK
Command
WRITE
NOP
NOP
NOP
NOP
tWR
PRE
BA a
Address
BA,Col b
(or all)
tDQSSmax
DQS
DQ
Di b
DM
= Don't Care
Notes:
1.ꢀ DIꢀbꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀb.
3ꢀsubsequentꢀeꢀlementsꢀofꢀDataꢀInꢀareꢀappliedꢀinꢀtheꢀprogrammedꢀorderꢀfollowingꢀDIꢀb.
2.ꢀ Aꢀnon-interruptedꢀburstꢀofꢀ4ꢀisꢀshown.
3.ꢀ tWRꢀisꢀreferencedꢀfromꢀtheꢀpositiveꢀclockꢀedgeꢀafterꢀtheꢀlastꢀDataꢀInꢀpair.
4.ꢀ A10ꢀisꢀLOWꢀwithꢀtheꢀWRITEꢀcommandꢀ(AutoꢀPꢀrechargeꢀisꢀdisabled).
Interrupting Write to Precharge
CK
CK
Command
WRITE
NOP
NOP
NOP
PRE
NOP
BA a
Address
BA,Col b
(or all)
tDQSSmax
tWR
*2
DQS
DQ
Di b
DM
*1
*1
*1
*1
= Don't Care
Notes:
1.ꢀ DIꢀbꢀ=ꢀDataꢀInꢀtoꢀcolumnꢀbꢀ.
2.ꢀ Anꢀinterruptedꢀburstꢀofꢀ4,ꢀ8ꢀorꢀ16ꢀisꢀshown,ꢀ2ꢀdataꢀelementsꢀareꢀwritten.
3.ꢀ tWRꢀisꢀreferencedꢀfromꢀtheꢀpositiveꢀclockꢀedgeꢀafterꢀtheꢀlastꢀdesiredꢀDataꢀInꢀpair.
4.ꢀ A10ꢀisꢀLOWꢀwithꢀtheꢀWRITEꢀcommandꢀ(AutoꢀPrechargeꢀisꢀdisabled).
5.ꢀ *1ꢀ=ꢀcanꢀbeꢀDon'tꢀCareꢀforꢀprogrammedꢀburstꢀlengthꢀofꢀ4.
6.ꢀ *2ꢀ=ꢀforꢀprogrammedꢀburstꢀlengthꢀofꢀ4,ꢀDQSꢀbecomesꢀDon'tꢀCareꢀatꢀthisꢀpoint.
Integrated Silicon Solution, Inc. ꢀ
43
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IS43LR16800D, IS43LR32400D
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀopenꢀrowꢀinꢀaꢀparticularꢀbankꢀorꢀtheꢀopenꢀrowꢀinꢀallꢀbanks.ꢀ
Theꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀaccessꢀaꢀspecifiedꢀtimeꢀ(tRP)ꢀafterꢀtheꢀPRECHARGEꢀcommandꢀisꢀ
issued.
Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be
precharged,ꢀinputsꢀBA0,ꢀBA1ꢀselectꢀtheꢀbank.ꢀOtherwiseꢀBA0,ꢀBA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare”.
Onceꢀaꢀbankꢀhasꢀbeenꢀprecharged,ꢀitꢀisꢀinꢀtheꢀidleꢀstateꢀandꢀmustꢀbeꢀactivatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandꢀ
beingꢀissued.ꢀAꢀPRECHARGEꢀcommandꢀwillꢀbeꢀtreatedꢀasꢀaꢀNOPꢀifꢀthereꢀisꢀnoꢀopenꢀrowꢀinꢀthatꢀbank,ꢀorꢀifꢀtheꢀ
previously open row is already in the process of precharging.
AUTO PRECHARGE
AutoꢀPrechargeꢀisꢀaꢀfeatureꢀwhichꢀperformsꢀtheꢀsameꢀindividualꢀbankꢀprechargeꢀfunctionꢀasꢀdescribedꢀabove,ꢀbutꢀ
withoutꢀrequiringꢀanꢀexplicitꢀcommand.ꢀThisꢀisꢀaccomplishedꢀbyꢀusingꢀA10ꢀ(A10ꢀ=ꢀHigh),ꢀtoꢀenableꢀAutoꢀPrechargeꢀinꢀ
conjunctionꢀwithꢀaꢀspecificꢀREADꢀorꢀWRITEꢀcommand.ꢀAꢀprechargeꢀofꢀtheꢀbankꢀ/ꢀrowꢀthatꢀisꢀaddressedꢀwithꢀtheꢀREADꢀ
orꢀWRITEꢀcommandꢀisꢀautomaticallyꢀperformedꢀuponꢀcompletionꢀofꢀtheꢀreadꢀorꢀwriteꢀburst.ꢀAutoꢀPrechargeꢀisꢀnonꢀ
persistentꢀinꢀthatꢀitꢀisꢀeitherꢀenabledꢀorꢀdisabledꢀforꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀcommand.
AutoꢀPrechargeꢀensuresꢀthatꢀaꢀprechargeꢀisꢀinitiatedꢀatꢀtheꢀearliestꢀvalidꢀstageꢀwithinꢀaꢀburst.ꢀTheꢀuserꢀmustꢀnotꢀissueꢀ
anotherꢀcommandꢀtoꢀtheꢀsameꢀbankꢀuntilꢀtheꢀprechargingꢀtimeꢀ(tRP)ꢀisꢀcompleted.ꢀThisꢀisꢀdeterminedꢀasꢀifꢀanꢀexplicitꢀ
PRECHARGEꢀcommandꢀwasꢀissuedꢀatꢀtheꢀearliestꢀpossibleꢀtime,ꢀasꢀdescribedꢀforꢀeachꢀburstꢀtypeꢀinꢀtheꢀOperationꢀ
section of this specification.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀisꢀusedꢀtoꢀtruncateꢀreadꢀburstsꢀ(withꢀAutoꢀPrechargeꢀdisabled).
TheꢀmostꢀrecentlyꢀregisteredꢀREADꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀtruncated.ꢀNoteꢀthatꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀisꢀnotꢀbankꢀspecific.ꢀThisꢀcommandꢀshouldꢀnotꢀbeꢀusedꢀtoꢀterminateꢀwriteꢀbursts.ꢀ
Burst Terminate Command
PRECHARGE command
CK
CK
CK
CK
CKE
(High)
CKE
(High)
CS
CS
RAS
CAS
WE
RAS
CAS
WE
A0-An
BA0,BA1
A0-A9, An
All Banks
= Don't Care
A10
One Bank
BA
BA0,BA1
= Don't Care
BA = Bank Address
(if A10 = L, otherwise Don't Care)
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
REFRESH REQUIREMENTS
MobileꢀDDRꢀSDRAMꢀdevicesꢀrequireꢀaꢀrefreshꢀofꢀallꢀrowsꢀinꢀanyꢀrollingꢀ64msꢀinterval.ꢀEachꢀrefreshꢀisꢀgeneratedꢀinꢀ
oneꢀofꢀtwoꢀways:ꢀbyꢀanꢀexplicitꢀAUTOꢀREFRESHꢀcommand,ꢀorꢀbyꢀanꢀinternallyꢀtimedꢀeventꢀinꢀSELFꢀREFRESHꢀmode.ꢀ
Dividingꢀtheꢀnumberꢀofꢀdeviceꢀrowsꢀintoꢀtheꢀrollingꢀ64msꢀintervalꢀdefinesꢀtheꢀaverageꢀrefreshꢀintervalꢀ(tREFI),ꢀwhichꢀisꢀ
a guideline to controllers for distributed refresh timing.
AUTO REFRESH
AUTOꢀREFRESHꢀcommandꢀisꢀusedꢀduringꢀnormalꢀoperationꢀofꢀtheꢀMobileꢀDDRꢀSDRAM.ꢀThisꢀcommandꢀisꢀnonꢀ
persistent,ꢀsoꢀitꢀmustꢀbeꢀissuedꢀeachꢀtimeꢀaꢀrefreshꢀisꢀrequired.ꢀ
Theꢀrefreshꢀaddressingꢀisꢀgeneratedꢀbyꢀtheꢀinternalꢀrefreshꢀcontroller.ꢀTheꢀMobileꢀDDRꢀSDRAMꢀrequiresꢀAUTOꢀ
REFRESHꢀcommandsꢀatꢀanꢀaverageꢀperiodicꢀintervalꢀofꢀtREFI.ꢀ
SELF REFRESH
TheꢀSELFꢀREFRESHꢀcommandꢀcanꢀbeꢀusedꢀtoꢀretainꢀdataꢀinꢀtheꢀMobileꢀDDRꢀSDRAM,ꢀevenꢀifꢀtheꢀrestꢀofꢀtheꢀsystemꢀ
isꢀpoweredꢀdown.ꢀWhenꢀinꢀtheꢀSelfꢀRefreshꢀmode,ꢀtheꢀMobileꢀDDRꢀSDRAMꢀretainsꢀdataꢀwithoutꢀexternalꢀclocking.ꢀ
TheꢀMobileꢀDDRꢀSDRAMꢀdeviceꢀhasꢀaꢀbuilt-inꢀtimerꢀtoꢀaccommodateꢀSelfꢀRefreshꢀoperation.ꢀTheꢀSELFꢀREFRESHꢀ
commandꢀisꢀinitiatedꢀlikeꢀanꢀAUTOꢀREFRESHꢀcommandꢀexceptꢀCKEꢀisꢀLOW.ꢀInputꢀsignalsꢀexceptꢀCKEꢀareꢀ“Don’tꢀ
Care”ꢀduringꢀSelfꢀRefresh.ꢀTheꢀuserꢀmayꢀhaltꢀtheꢀexternalꢀclockꢀoneꢀclockꢀafterꢀtheꢀSELFꢀREFRESHꢀcommandꢀisꢀ
registered.
Onceꢀtheꢀcommandꢀisꢀregistered,ꢀCKEꢀmustꢀbeꢀheldꢀlowꢀtoꢀkeepꢀtheꢀdeviceꢀinꢀSelfꢀRefreshꢀmode.ꢀTheꢀclockꢀisꢀ
internallyꢀdisabledꢀduringꢀSelfꢀRefreshꢀoperationꢀtoꢀsaveꢀpower.ꢀTheꢀminimumꢀtimeꢀthatꢀtheꢀdeviceꢀmustꢀremainꢀinꢀ
SelfꢀRefreshꢀmodeꢀisꢀtRFC.ꢀꢀTheꢀprocedureꢀforꢀexitingꢀSelfꢀRefreshꢀrequiresꢀaꢀsequenceꢀofꢀcommands.ꢀFirst,ꢀtheꢀ
clockꢀmustꢀbeꢀstableꢀpriorꢀtoꢀCKEꢀgoingꢀbackꢀHigh.ꢀOnceꢀSelfꢀRefreshꢀExitꢀisꢀregistered,ꢀaꢀdelayꢀofꢀatꢀleastꢀtXSꢀmustꢀ
be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in
progress.
TheꢀuseꢀofꢀSelfꢀRefreshꢀmodeꢀintroducesꢀtheꢀpossibilityꢀthatꢀanꢀinternallyꢀtimedꢀrefreshꢀeventꢀcanꢀbeꢀmissedꢀwhenꢀ
CKEꢀisꢀraisedꢀforꢀexitꢀfromꢀSelfꢀRefreshꢀmode.ꢀUponꢀexitꢀfromꢀSelfꢀRefreshꢀanꢀextraꢀAUTOꢀREFRESHꢀcommandꢀisꢀ
recommended.ꢀInꢀtheꢀSelfꢀRefreshꢀmode,ꢀtwoꢀadditionalꢀpower-savingꢀoptionsꢀexist:ꢀTemperatureꢀCompensatedꢀSelfꢀ
Refreshꢀ(TCSR)ꢀandꢀPartialꢀArrayꢀSelfꢀRefreshꢀ(PASR);ꢀtheyꢀareꢀdescribedꢀinꢀtheꢀExtendedꢀModeꢀRegisterꢀsection.
AUTO REFRESH command
SELF REFRESH command
CK
CK
CK
CK
CKE
CKE
(High)
CS
CS
RAS
CAS
WE
RAS
CAS
WE
A0-An
BA0,BA1
A0-An
BA0,BA1
= Don't Care
= Don't Care
Integrated Silicon Solution, Inc. ꢀ
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Rev. 00D
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IS43LR16800D, IS43LR32400D
Auto Refresh Cycles Back-to-Back
CK
CK
tRP
NOP
tRFC
NOP
tRFC
NOP
Command
Address
PRE
ARF
NOP
ARF
NOP
ACT
Ba A,
Row n
Row n
A10 (AP)
DQ
Pre All
High-Z
= Don't Care
Ba A, Row n = Bank A, Row n
Note:ꢀBaꢀA,ꢀRowꢀnꢀ=ꢀBankꢀA,ꢀRowꢀn.
Self Refresh Entry and Exit
CK
CK
tRP
> tRFC
tXSR
tRFC
CKE
Command
Address
PRE
NOP
ARF
NOP
NOP
NOP
ARF
NOP
ACT
Ba A,
R
ow n
A10 (AP)
DQ
Row n
Pre All
High-Z
Enter
Self Refresh
Mode
Exit from
Self Refresh
Mode
Any Command
(Auto Refresh
Recommended)
= Don't Care
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
POWER-DOWN
Power-downꢀisꢀenteredꢀwhenꢀCKEꢀisꢀregisteredꢀLowꢀ(noꢀaccessesꢀcanꢀbeꢀinꢀprogress).ꢀIfꢀpower-downꢀoccursꢀwhenꢀallꢀ
banksꢀareꢀidle,ꢀthisꢀmodeꢀisꢀreferredꢀtoꢀasꢀprechargeꢀpower-down;ꢀifꢀpower-downꢀoccursꢀwhenꢀthereꢀisꢀaꢀrowꢀactiveꢀinꢀ
any bank, this mode is referred to as active power-down.
Enteringꢀpower-downꢀdeactivatesꢀtheꢀinputꢀandꢀoutputꢀbuffers,ꢀexcludingꢀCK,ꢀCKꢀandꢀCKE.ꢀInꢀpower-downꢀmode,ꢀCKEꢀ
Lowꢀmustꢀbeꢀmaintained,ꢀandꢀallꢀotherꢀinputꢀsignalsꢀareꢀ“Don’tꢀCare”.ꢀTheꢀminimumꢀpower-downꢀdurationꢀisꢀspecifiedꢀ
byꢀtCKE.ꢀHowever,ꢀpower-downꢀdurationꢀisꢀlimitedꢀbyꢀtheꢀrefreshꢀrequirementsꢀofꢀtheꢀdevice.ꢀ
Theꢀpower-downꢀstateꢀisꢀsynchronouslyꢀexitedꢀwhenꢀCKEꢀisꢀregisteredꢀHighꢀ(alongꢀwithꢀaꢀNOPꢀorꢀDESELECTꢀ
command).ꢀAꢀvalidꢀcommandꢀmayꢀbeꢀappliedꢀtXPꢀafterꢀexitꢀfromꢀpower-down.
Power-Down Entry and Exit
CK
CK
tRP
tCKE
tXP
CKE
Command
Address
PRE
NOP
NOP
NOP
NOP
NOP
Valid
Valid
Valid
A10 (AP)
DQ
Pre All
High-Z
Power Down
Entry
Exit from
Power Down
Any
Command
= Don't Care
Note:ꢀPrechargeꢀPower-Downꢀmodeꢀshown:ꢀallꢀbanksꢀareꢀidleꢀandꢀtRPꢀisꢀmetꢀwhenꢀPower-DownꢀEntryꢀcommandꢀisꢀissued.
Integrated Silicon Solution, Inc. ꢀ
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Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
DEEP POWER-DOWN
TheꢀDeepꢀPower-Downꢀ(DPD)ꢀmodeꢀenablesꢀveryꢀlowꢀstandbyꢀcurrents.ꢀAllꢀinternalꢀvoltageꢀgeneratorsꢀinsideꢀtheꢀ
MobileꢀDDRꢀSDRAMꢀareꢀstoppedꢀandꢀallꢀmemoryꢀdataꢀisꢀlostꢀinꢀthisꢀmode.ꢀAllꢀtheꢀinformationꢀinꢀtheꢀModeꢀRegisterꢀ
andꢀtheꢀExtendedꢀModeꢀRegisterꢀisꢀlost.ꢀ
DeepꢀPower-DownꢀisꢀenteredꢀusingꢀtheꢀBURSTꢀTERMINATEꢀcommandꢀexceptꢀthatꢀCKEꢀisꢀregisteredꢀLow.ꢀAllꢀbanksꢀ
mustꢀbeꢀinꢀidleꢀstateꢀwithꢀnoꢀactivityꢀonꢀtheꢀdataꢀbusꢀpriorꢀtoꢀenteringꢀtheꢀDPDꢀmode.ꢀWhileꢀinꢀthisꢀstate,ꢀCKEꢀmustꢀbeꢀ
heldꢀinꢀaꢀconstantꢀLowꢀstate.ꢀ
ToꢀexitꢀtheꢀDPDꢀmode,ꢀCKEꢀisꢀtakenꢀhighꢀafterꢀtheꢀclockꢀisꢀstableꢀandꢀNOPꢀcommandsꢀmustꢀbeꢀmaintainedꢀforꢀatꢀleastꢀ
200ꢀμs.ꢀAfterꢀ200ꢀμsꢀaꢀcompleteꢀre-initializationꢀisꢀrequiredꢀfollowingꢀstepsꢀ4ꢀthroughꢀ11ꢀasꢀdefinedꢀforꢀtheꢀinitializationꢀ
sequence.
Deep Power-Down Entry and Exit
T0
T1
Ta0
Ta1
Ta2
CK
CK
CKE
Command
Address
DQS
NOP
DPD
NOP
Valid
Valid
DQ
DM
tRP
T = 200 µs
Exit DPD Mode
Enter DPD Mode
= Don't Care
Notes:
1.ꢀ ClockꢀmustꢀbeꢀstableꢀbeforeꢀexitingꢀDeepꢀPower-Downꢀmode.ꢀThatꢀis,ꢀtheꢀclockꢀmustꢀbeꢀcyclingꢀwithinꢀspecificationsꢀbyꢀTa0.
2.ꢀ DeviceꢀmusꢀtꢀbeꢀinꢀtheꢀaꢀllꢀbanksꢀidleꢀstateꢀpriorꢀtoꢀenteringꢀDeepꢀPower-Downꢀmode.
3.ꢀ 200μsꢀisꢀrequiredꢀbeforeꢀanyꢀcommandꢀcanꢀbeꢀaꢀppliedꢀuponꢀexitingꢀDeepꢀPower-Downꢀmode.
4.ꢀ UponꢀexitingꢀDeepꢀPower-DownꢀmodeꢀaꢀPRECHARGEꢀALLꢀcommandꢀmustꢀbeꢀissued,ꢀfollowedꢀbyꢀtwoꢀAUTOꢀREFRESHꢀ
commandsꢀandꢀaꢀloadꢀmodeꢀregisterꢀsequence.
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Integrated Silicon Solution, Inc.
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IS43LR16800D, IS43LR32400D
CLOCK STOP
Stopping a clock during idle periods is an effective method of reducing power consumption.
TheꢀMobileꢀDDRꢀSDRAMꢀsupportsꢀclockꢀstopꢀunderꢀtheꢀfollowingꢀconditions:
•ꢀ Theꢀlastꢀcommandꢀ(ACTIVE,ꢀREAD,ꢀWRITE,ꢀPRECHARGE,ꢀAUTOꢀREFRESHꢀorꢀMODEꢀREGISTERꢀSET)ꢀhasꢀex-
ecutedꢀtoꢀcompletion,ꢀincludingꢀanyꢀdata-outꢀduringꢀreadꢀbursts;ꢀtheꢀnumberꢀofꢀclockꢀpulsesꢀperꢀaccessꢀcommandꢀ
dependsꢀonꢀtheꢀdevice’sꢀACꢀtimingꢀparametersꢀandꢀtheꢀclockꢀfrequency;
•ꢀ Theꢀrelatedꢀtimingꢀconditionsꢀ(tRCD,ꢀtWR,ꢀtRP,ꢀtRFC,ꢀtMRD)ꢀhasꢀbeenꢀmet;
•ꢀ CKEꢀisꢀheldꢀHigh
Whenꢀallꢀconditionsꢀhaveꢀbeenꢀmet,ꢀtheꢀdeviceꢀisꢀeitherꢀinꢀ“idleꢀstate”ꢀorꢀ“rowꢀactiveꢀstate”ꢀandꢀclockꢀstopꢀmodeꢀmayꢀ
beꢀenteredꢀwithꢀCKꢀheldꢀLowꢀandꢀCKꢀheldꢀHigh.ꢀ
Clockꢀstopꢀmodeꢀisꢀexitedꢀbyꢀrestartingꢀtheꢀclock.ꢀAtꢀleastꢀoneꢀNOPꢀcommandꢀhasꢀtoꢀbeꢀissuedꢀbeforeꢀtheꢀnextꢀaccessꢀ
commandꢀmayꢀbeꢀapplied.ꢀAdditionalꢀclockꢀpulsesꢀmightꢀbeꢀrequiredꢀdependingꢀonꢀtheꢀsystemꢀcharacteristics.
•ꢀ Initiallyꢀtheꢀdeviceꢀisꢀinꢀclockꢀstopꢀmode
•ꢀ TheꢀclockꢀisꢀrestartedꢀwithꢀtheꢀrisingꢀedgeꢀofꢀT0ꢀandꢀaꢀNOPꢀonꢀtheꢀcommandꢀinputs
•ꢀ WithꢀT1ꢀaꢀvalidꢀaccessꢀcommandꢀisꢀlatched;ꢀthisꢀcommandꢀisꢀfollowedꢀbyꢀNOPꢀcommandsꢀinꢀorderꢀtoꢀallowꢀforꢀclockꢀ
stop as soon as this access command is completed
•ꢀ TnꢀisꢀtheꢀlastꢀclockꢀpulseꢀrequiredꢀbyꢀtheꢀaccessꢀcommandꢀlatchedꢀwithꢀT1
•ꢀ TheꢀclockꢀcanꢀbeꢀstoppedꢀafterꢀTn
Clock Stop Mode Entry and Exit
T0
T1
T2
Tn
CK
CK
CKE
Timing Condition
NOP
CMD
Valid
NOP
NOP
NOP
Command
Address
(High-Z)
DQ, DQS
Clock
Stopped
Exit
Valid
Enter
Clock
Stop
= Don't Care
Clock Command
Stop
Mode
Mode
Integrated Silicon Solution, Inc. ꢀ
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IS43LR16800D, IS43LR32400D
8Mx16 ORDERING INFORMATION - Vd d = 1.8V
Commercial Range: 0°C to 70°C
Frequency
ꢀ200ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ133ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
5ꢀ
6ꢀ
IS43LR16800D-5BLꢀ
IS43LR16800D-6BLꢀ
IS43LR16800D-75BLꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
60-ballꢀFBGA,ꢀLead-free
60-ballꢀFBGA,ꢀLead-free
7.5ꢀ
Industrial Range: -40°C to +85°C
Frequency
ꢀ200ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ133ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
5ꢀ
6ꢀ
IS43LR16800D-5BLIꢀ
IS43LR16800D-6BLIꢀ
IS43LR16800D-75BLIꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
60-ballꢀFBGA,ꢀLead-free
60-ballꢀFBGA,ꢀLead-free
7.5ꢀ
PleaseꢀcontactꢀProductꢀManagerꢀforꢀleadedꢀproductꢀsupport.
4Mx32 ORDERING INFORMATION - Vd d = 1.8V
Commercial Range: 0°C to 70°C
Frequency
ꢀ200ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ133ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
5ꢀ
6ꢀ
IS43LR32400D-5BLꢀ
IS43LR32400D-6BLꢀ
IS43LR32400D-75BLꢀ
90-ballꢀFBGA,ꢀLead-freeꢀ
90-ballꢀFBGA,ꢀLead-free
90-ballꢀFBGA,ꢀLead-free
7.5ꢀ
Industrial Range: -40°C to +85°C
Frequency
ꢀ200ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ133ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
5ꢀ
6ꢀ
IS43LR32400D-5BLIꢀ
IS43LR32400D-6BLIꢀ
IS43LR32400D-75BLIꢀ
90-ballꢀFBGA,ꢀLead-freeꢀ
90-ballꢀFBGA,ꢀLead-free
90-ballꢀFBGA,ꢀLead-free
7.5ꢀ
PleaseꢀcontactꢀProductꢀManagerꢀforꢀleadedꢀproductꢀsupport.
50
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Integrated Silicon Solution, Inc. ꢀ
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Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
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Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
相关型号：
SI9130DB
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