IS43R16320A [ISSI]
32Meg x 16 512-MBIT DDR SDRAM; 32Meg ×16 512兆位的DDR SDRAM
| 型号： | IS43R16320A |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 32Meg x 16 512-MBIT DDR SDRAM |
| 文件： | 总18页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS43R16320A
ISSI
MARCH 2006
32Meg x 16
512-MBIT DDR SDRAM
FEATURES
DEVICE OVERVIEW
• Clock Frequency: 166 MHz
ISSI’s 512-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 536,870,912-bit memory
array is internally organized as four banks of 128M-bit to
allowconcurrentoperations. ThepipelineallowsRead
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
• Power supply (VDD and VDDQ)
DDR 333: 2.5V + 0.2V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
and Active operations
• Commands and addresses register on positive
clock edges (CK)
• Bi-directional Data Strobe signal for data cap-
ture
• Differential clock inputs (CK and CK) for
two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
with clock inputs
• Programmable burst length for Read and Write
operations
KEY TIMING PARAMETERS
• Programmable CAS Latency (2 or 2.5 clocks)
Parameter
-6
Unit
• Programmable burst sequence: sequential or
DDR333
interleaved
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
• Burst concatenation and truncation supported
for maximum data throughput
—
6
7.5
ns
ns
ns
• Auto Pre-charge option for each Read or Write
burst
Clock Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
—
166
133
MHz
MHz
MHz
• 8192 refresh cycles every 64ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power
Down Modes
• Lead-free package
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
03/22/06
®
IS43R16320A
ISSI
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
NC
DQ8
NC
V
DDQ
LDQS
NC
VSSQ
UDQS
NC
VDD
DNU
LDM
WE
VREF
VSS
UDM
CK
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTIONS
WE
WriteEnable
x16 Input Mask
DataStrobe
Power
A0-A12
A0-A9
Row Address Input
LDM,UDM
Column Address Input
Bank Select Address
Data I/O
LDQS,UDQS
VDD
BA0, BA1
DQ0 to DQ15
CK, CK
CKE
Vss
Ground
System Clock Input
Clock Enable
VDDQ
Power Supply for I/O Pin
Ground for I/O Pin
InputReferenceVoltage
Do Not Use
VssQ
VREF
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
DNU
CAS
NC
NoConnection
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
Mode Register Operation
BA1 BA0 A12
A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
Mode Register
0*
0*
CAS Latency
Burst Length
Operating Mode
A12 - A9
0
A8
0
A7
0
A6 - A0
Valid
Operating Mode
Burst
Type
Normal operation
Do not reset DLL
A3
0
1
Sequential
Interleave
Normal operation
in DLL Reset
0
1
0
Valid
Reserved
CAS Latency
Burst Length
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A2
0
A1
0
A0
0
Burst Length
0
0
0
0
1
1
1
1
Reserved
2
0
1
0
0
1
1
0
0
1
0
4
1
1
Reserved
Reserved
Reserved
2.5
0
1
1
8
0
0
1
0
0
Reserved
Reserved
Reserved
Reserved
0
1
1
0
1
1
0
1
1
0
1
1
Reserved
1
1
1
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
03/22/06
®
IS43R16320A
ISSI
Burst Definition
Starting Column Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Burst Length
A2
A1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1
0-1
2
4
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
0
0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
1
1
1
1
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR333.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
Read Command
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
CA
A0-A9
A10
EN AP
DIS AP
BA
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
BA0, BA1
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
03/22/06
®
IS43R16320A
ISSI
Write Command
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
A0-A9
CA
EN AP
A10
DIS AP
BA
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
BA0, BA1
Don’t Care
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
Capacitance
Parameter
Symbol
CI1
Min.
2.0
Max.
3.0
Units
pF
Notes
Input Capacitance: CK, CK
1
1
Delta Input Capacitance: CK, CK
delta CI1
CI2
0.25
3.0
pF
Input Capacitance: All other input-only pins (except DM)
Delta Input Capacitance: All other input-only pins (except DM)
Input/Output Capacitance: DQ, DQS, DM
2.0
4.0
pF
1
delta CI2
CIO
0.5
pF
1
5.0
pF
1, 2
1
Delta Input/Output Capacitance: DQ, DQS, DM
delta CIO
0.5
pF
1. VDDQ = VDD = 2.5V 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is
required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0°C < TA < 70oC; V
= V = + 2.5V 0.2V (DDR333); see AC Characteristics)
DD
DDQ
Symbol
Parameter
Min
Max
Units
Notes
VDD
Supply Voltage DDR333
2.3
2.3
2.7
2.7
V
V
1
1
VDDQ
I/O Supply Voltage DDR333
Supply Voltage
I/O Supply Voltage
V
SS, VSSQ
0
0
V
VREF
VTT
I/O Reference Voltage
0.49 x VDDQ
VREF - 0.04
VREF + 0.15
-0.3
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
1.4
V
V
V
V
V
V
V
1, 2
1, 3
1
I/O Termination Voltage (System)
Input High (Logic1) Voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
VIRatio
Input Low (Logic0) Voltage
1
Input Voltage Level, CK and CK Inputs
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
V-I Matching Pullup Current to Pulldown Current Ratio
Input Leakage Current
-0.3
1
0.30
1, 4
1, 4
5
0.30
0.71
-2
-5
2
5
II
µA
1
1
Any input 0V < V
; (All other pins not under test = 0V)
IN < VDD
Output Leakage Current
(DQs are disabled; 0V < Vout < VDDQ
µ
IOZ
A
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
03/22/06
®
IS43R16320A
ISSI
DC Electrical Characteristics and Operating Conditions
(0°C < TA < 70oC; V
= V = + 2.5V 0.2V (DDR333); see AC Characteristics)
DD
DDQ
Symbol
Parameter
Min
Max
Units
Notes
IOH
IOL
IOHW
IOLW
Output Current: Nominal Strength Driver
High current (VOUT= VDDQ -0.373V, min VREF, min VTT
Low current (VOUT= 0.373V, max VREF, max VTT
− 16.8
)
)
mA
mA
1
16.8
− 9.0
9.0
)
Output Current: Half- Strength Driver
High current (VOUT= VDDQ -0.763V, min VREF, min VTT
Low current (VOUT= 0.763V, max VREF, max VTT
1
)
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2ꢀ of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
Normal Strength Driver Pulldown and Pullup Characteristics
1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the
outer bounding lines of the V-I curve.
2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve.
Normal Strength Driver Pulldown Characteristics
140
Maximum
Typical High
Typical Low
Minimum
0
0
2.7
V
(V)
OUT
3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the
outer bounding lines of the V-I curve.
4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
Normal Strength Driver Pullup Characteristics
0
Minimum
Typical Low
Typical High
Maximum
-200
0
2.7
V
(V)
OUT
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device
drain to source voltages from 0.1 to 1.0.
6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10ꢀ, for device
drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.
7. These characteristics are intended to obey the SSTL_2 class II standard.
8. This specification is intended for DDR SDRAM only.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
03/22/06
®
IS43R16320A
ISSI
Normal Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA)
Pullup Current (mA)
Typical
Low
Typical
High
Typical
Low
Typical
Min
Voltage (V)
Min
Max
Max
High
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
6.0
6.8
13.5
20.1
26.6
33.0
39.1
44.2
49.8
55.2
60.3
65.2
69.9
74.2
78.4
82.3
85.9
89.1
92.2
95.3
97.2
99.1
100.9
101.9
102.8
103.8
104.6
105.4
4.6
9.6
-6.1
-7.6
-14.5
-4.6
-10.0
-20.0
12.2
18.1
24.1
29.8
34.6
39.4
43.7
47.5
51.3
54.1
56.2
57.9
59.3
60.1
60.5
61.0
61.5
62.0
62.5
62.9
63.3
63.8
64.1
64.6
64.8
65.0
9.2
18.2
-12.2
-18.1
-24.0
-29.8
-34.3
-38.1
-41.1
-43.8
-46.0
-47.8
-49.2
-50.0
-50.5
-50.7
-51.0
-51.1
-51.3
-51.5
-51.6
-51.8
-52.0
-52.2
-52.3
-52.5
-52.7
-52.8
-9.2
13.8
18.4
23.0
27.7
32.2
36.8
39.6
42.6
44.8
46.2
47.1
47.4
47.7
48.0
48.4
48.9
49.1
49.4
49.6
49.8
49.9
50.0
50.2
50.4
50.5
26.0
-21.2
-13.8
-18.4
-23.0
-27.7
-32.2
-36.0
-38.2
-38.7
-39.0
-39.2
-39.4
-39.6
-39.9
-40.1
-40.2
-40.3
-40.4
-40.5
-40.6
-40.7
-40.8
-40.9
-41.0
-41.1
-41.2
-29.8
33.9
-27.7
-38.8
41.8
-34.1
-46.8
49.4
-40.5
-54.4
56.8
-46.9
-61.8
63.2
-53.1
-69.5
69.9
-59.4
-77.3
76.3
-65.5
-85.2
82.5
-71.6
-93.0
88.3
-77.6
-100.6
-108.1
-115.5
-123.0
-130.4
-136.7
-144.2
-150.5
-156.9
-163.2
-169.6
-176.0
-181.3
-187.6
-192.9
-198.2
93.8
-83.6
99.1
-89.7
103.8
108.4
112.1
115.9
119.6
123.3
126.5
129.5
132.4
135.0
137.3
139.2
140.8
-95.5
-101.3
-107.1
-112.4
-118.7
-124.0
-129.3
-134.6
-139.9
-145.2
-150.5
-155.3
-160.1
Normal Strength Driver Evaluation Conditions
Typical
Minimum
Maximum
25 °C
2.5V
70 °C
0 °C
Temperature (Tambient
)
2.3V
2.7V
VDDQ
typical process
slow-slow process
fast-fast process
Process conditions
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and
VIH(AC)
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT
50Ω
Output
Timing Reference Point
(VOUT
)
30pF
Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. A
03/22/06
®
IS43R16320A
ISSI
AC Input Operating Conditions
o
(0 °C < T < 70 C V = V
= 2.5V + 0.2V (DDR333); See AC Characteristics)
A
DD
DDQ
Symbol
Parameter/Condition
Min
Max
Unit
V
Notes
1, 2
VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
VIL(AC) Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
VID(AC) Input Differential Voltage, CK and CK Inputs
VIX(AC) Input Crossing Point Voltage, CK and CK Inputs
VREF + 0.31
VREF - 0.31
V
1, 2
0.62
VDDQ + 0.6
V
1, 2, 3
1, 2, 4
0.5*VDDQ
-
0.2 0.5*VDDQ + 0.2
V
1. Input slew rate = 1V/ns
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
I
Specifications and Conditions
DD
(0 °C < T <70oC V
= V = 2.5V + 0.2V (DDR333); See AC Characteristics)
DDQ
A
DD
DDR333
(6K)
tCK=6ns
Symbol
Parameter/Condition
Unit
mA
mA
Notes
Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM,
and DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
96
99
1
1
Operating Current: one bank; active / read / precharge; Burst = 2; tRC
RC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once
per clock cycle
=
IDD1
t
Precharge Power Down Standby Current: all banks idle; Power Down
mode; CKE < VIL (max)
IDD2P
IDD2N
5
mA
mA
1
1
Idle Standby Current: CS > VIH (min); all banks idle; CKE > VIH (min);
address and control inputs changing once per clock cycle
25
Active Power Down Standby Current: one bank active; Power Down
IDD3P mode;
CKE < VIL (max)
11
45
mA
mA
1
1
Active Standby Current: one bank; active / precharge; CS > VIH (min);
CKE > VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock
cycle
IDD3N
Operating Current: one bank; Burst = 2; reads; continuous burst; address
IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; IOUT = 0mA
104
117
mA
mA
1
1
Operating Current: one bank; Burst = 2; writes; continuous burst; address
IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL = 2.5
IDD5
IDD6
Auto-Refresh Current: tRC = tRFC (min)
Self-Refresh Current: CKE < 0.2V
193
5
mA
mA
1
1, 2
Operating current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every trans-
fer;
IDD7
307
mA
1
t RC = t RC (min); I OUT = 0mA.
1. IDD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
Values are averaged from high and low temp values using x16 devices.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C < T < 70 oC V = V
DDQ
= 2.5V + 0.2V (DDR333); See AC Characteristics)
A
DD
DDR333
(6K)
Symbol
Parameter
Unit
Notes
Min
Max
+0.7
+0.6
0.55
0.55
t
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
-0.7
-0.6
ns
ns
1-4
1-4
AC
t
DQSCK
t
0.45
0.45
t
t
1-4
CH
CK
CK
t
CK low-level width
1-4
CL
CL = 3.0
CL = 2.5
CL = 2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-4
t
Clock cycle time
6
12
12
1-4
CK
7.5
1-4
t
DQ and DM input hold time
0.45
1-4, 15, 16
1-4, 15, 16
2-4, 12
1-4
DH
t
DQ and DM input setup time
0.45
2.2
DS
t
Input pulse width
IPW
t
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
1.75
-0.7
-0.7
DIPW
t
+0.7
+0.7
1-4, 5
1-4, 5
1-4
HZ
t
LZ
+0.45
+0.4
TSOP Package
BGA Package
DQS-DQ skew
(DQS & associated DQ signals)
t
DQSQ
1-4
Minimum half clk period for any given cycle;
min
CL CH
t
t
1-4
HP
CK
defined by clk high (t ) or clk low (t ) time
(t , t
)
CH
CL
t
Data output hold time from DQS
t
- t
t
t
t
1-4
1-4
1-4
QH
HP QHS
CK
CK
CK
0.55
0.5
TSOP Package
BGA Package
t
Data hold Skew Factor
QHS
Write command to 1st DQS latching
transition
t
0.75
1.25
t
1-4
DQSS
CK
t
DQS input high pulse width (write cycle)
DQS input low pulse width (write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
0.35
0.35
0.2
0.2
2
t
t
t
t
t
1-4
1-4
DQSH
CK
CK
CK
CK
CK
t
DQSL
t
1-4
DSS
DSH
MRD
t
1-4
t
1-4
t
0
ns
1-4, 7
1-4, 6
1-4
WPRES
t
Write postamble
0.40
0.25
0.60
t
WPST
WPRE
CK
CK
t
Write preamble
t
2-4, 9,
11, 12
Address and control input hold time
(fast slew rate)
t
0.75
ns
ns
ns
ns
IH
2-4, 9,
11, 12
Address and control input setup time
(fast slew rate)
t
0.75
0.8
IS
IH
Address and control input hold time
(slow slew rate)
2-4, 10-12,
14
t
Address and control input setup time
(slow slew rate)
2-4, 10, 11,
12, 14
t
0.8
IS
t
Read preamble
Read postamble
0.9
1.1
t
1-4
1-4
RPRE
CK
CK
t
0.40
0.60
t
RPST
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. A
03/22/06
®
IS43R16320A
ISSI
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C < T < 70 oC V = V
DDQ
= 2.5V + 0.2V (DDR333); See AC Characteristics)
A
DD
DDR333
(6K)
Symbol
Parameter
Unit
Notes
Min
42
Max
t
Active to Precharge command
120,000 ns
1-4
1-4
1-4
1-4
RAS
t
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command period
Active to Read or Write delay
60
ns
ns
ns
RC
t
72
RFC
RCD
t
18
min
RCD RAS
t
Active to Read Command with Autoprecharge
ns
1-4
RAP
(t
, t
)
t
Precharge command period
Active bank A to Active bank B command
Write recovery time
18
12
15
ns
ns
ns
1-4
1-4
1-4
RP
t
RRD
t
WR
DAL
WTR
(t /t
)
WR CK
t
Auto precharge write recovery + precharge time
+
t
1-4, 13
CK
(t /t
)
RP CK
t
Internal write to read command delay
Power down exit time
1
6
t
1-4
1-4
CK
t
ns
ns
PDEX
XSNR
XSRD
t
t
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
75
200
1-4
t
1-4
CK
t
7.8
us
1-4, 8
REFI
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
Electrical Characteristics & AC Timing - Absolute Specifications Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the
input reference level for signals other than CK/CK is V
.
REF
3. Inputs are not recognized as valid until V
stabilizes.
REF
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics
(Note 3) is V
.
TT
5.
t
and t transitions occur in the same access time windows as valid data transitions. These parameters are
HZ LZ
not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving
(LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the
device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic
LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this
time, depending on t
.
DQSS
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between V (AC) and V (AC).
OH
OL
10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between V (AC) and
OH
V
(AC).
OL
11. CK/CK slew rates are ≥ 1.0V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may
be guaranteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t is equal
CK
to the actual system clock cycle time. For example, for DDR333 at CL = 2.5, t
(18ns/6ns) = 3 + 3 = 6.
= (15ns/6ns) +
DAL
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. A
03/22/06
®
IS43R16320A
ISSI
14. An input setup and hold time derating table is used to increase t and t in the case where the input slew
IS
IH
rate is below 0.5 V/ns.
delta (tIS
)
delta (tIH)
Input Slew Rate
0.5 V/ns
Unit
ps
Notes
1,2
0
0
0
0
+50
ps
1,2
0.4 V/ns
+100
ps
1,2
0.3 V/ns
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t and t in the case where the I/O slew rate
DS
DH
is below 0.5 V/ns.
delta (tDS
0
)
delta (tDH)
Input Slew Rate
0.5 V/ns
Unit
ps
Notes
1,2
0
+75
+75
+150
ps
1,2
0.4 V/ns
+150
ps
1,2
0.3 V/ns
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t and t in the case where DQ, DM, and DQS
DS
DH
slew rates differ.
delta (tDS
0
)
delta (tDH
0
)
Input Slew Rate
0.0 V/ns
Unit
ps
Notes
1,2,3,4
1,2,3,4
1,2,3,4
+50
+50
ps
0.25 V/ns
+100
+100
ps
0.5 V/ns
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
®
IS43R16320A
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
Speed(ns)
Order Part No.
Package
166 MHz
6
IS43R16320A-6TL
66-pinTSOP-II,Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. A
03/22/06
®
PACKAGING INFORMATION
ISSI
Plastic TSOP 66-pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Symbol Min
Max
Min
Max
Ref. Std.
No. Leads (N)
66
A
A1
A2
b
C
D
E1
E
e
—
1.20
—
0.047
0.05 0.15
—
0.002 0.006
—
—
—
0.24 0.40
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.65 BSC
0.009 0.016
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.026 BSC
L
0.40 0.60
0.016 0.024
L1
ZD
α
—
—
—
—
0.71 REF
0° 8°
0.028 REF
0°
8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
08/09/05
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