IS43R16320D-6BL-TR [ISSI]
IC DRAM 512M PARALLEL 60TFBGA;
| 型号： | IS43R16320D-6BL-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC DRAM 512M PARALLEL 60TFBGA 动态存储器 |
| 文件： | 总33页 (文件大小：1045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
16Mx32, 32Mx16, 64Mx8
512Mb DDR SDRAM
MAY 2015
FEATURES
DEVICE OVERVIEW
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-6)
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.6Vꢀ±ꢀ0.1Vꢀ(-5)
•ꢀ SSTL_2ꢀcompatibleꢀI/O
ISSI’sꢀ512-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ
transfer using pipeline architecture and two data word
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ536,870,912-bitꢀmemoryꢀ
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ128Mbꢀtoꢀ
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ
and Write burst accesses to be virtually continuous, with
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ
programmable features of burst length, burst sequence
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
per clock cycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
received with data, to be used in capturing data
at the receiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ
transitions
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀ
data and data mask referenced to both edges of
DQS
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.
ADDRESS TABLE
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
Parameter
16M x 32
32M x 16
64M x 8
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
at both rising and falling edges of data strobe
Configuration 4Mꢀxꢀ32ꢀxꢀ4ꢀ
8Mꢀxꢀ16ꢀxꢀ4ꢀ
16Mꢀxꢀ8ꢀxꢀ4ꢀ
banks
banks
banks
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8
BankꢀAddressꢀ BA0,ꢀBA1
Pins
BA0,ꢀBA1
BA0,ꢀBA1
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrecharge
Autoprecharge A8/AP
Pins
A10/AP
A10/AP
RowꢀAddress 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
•ꢀ TRASꢀLockoutꢀSupportedꢀ(tRAP = tRCD
)
Column
Address
512(A0ꢀ–ꢀA7,ꢀ 1K(A0ꢀ–ꢀA9)
A9)
2K(A0ꢀ–ꢀA9,ꢀ
A11)
OPTIONS
RefreshꢀCount
Com./Ind./A1 8Kꢀ/ꢀ64ms
A2 8Kꢀ/ꢀ16ms
•ꢀ Configuration(s):ꢀ16Mx32,ꢀ32Mx16,ꢀandꢀ64Mx8
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
•ꢀ Package(s):ꢀ144ꢀBallꢀBGAꢀ(x32),ꢀ66-pinꢀTSOP-IIꢀ
(x8,ꢀx16),ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)
•ꢀ Lead-freeꢀpackage
•ꢀꢀ TemperatureꢀRange:ꢀ
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)
KEY TIMING PARAMETERS
Speed Grade
-5
200ꢀ 167ꢀ
ckꢀMaxꢀCLꢀ=ꢀ2.5ꢀ 167ꢀ 167ꢀ
ckꢀMaxꢀCLꢀ=ꢀ2ꢀ 133ꢀ 133ꢀ
-6
Units
F
F
F
ckꢀMaxꢀCLꢀ=ꢀ3ꢀ
ꢀ
ꢀ
ꢀ
MHz
MHz
MHz
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
FUNCTIONAL BLOCK DIAGRAM (x32)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
DM0-DM3
4
DATA IN
BUFFER
&
CLOCK
GENERATOR
32
32
I/O 0-31
REFRESH
CONTROLLER
DQS0-DQS3
Mode Registers and
Ext. Mode Registers
4
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A12
A11
A10
A9
CONTROLLER
15
32
32
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
A3
A2
8192
8192
13
MEMORY CELL
ARRAY
8192
8192
13
A1
BANK 0
ROW
A0
ROW
ADDRESS
LATCH
BA0
BA1
ADDRESS
BUFFER
13
13
13
SENSE AMP I/O GATE
2
512
(x 32)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
FUNCTIONAL BLOCK DIAGRAM (x16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
LDM, UDM
2
DATA IN
BUFFER
&
CLOCK
GENERATOR
16
16
I/O 0-15
REFRESH
CONTROLLER
LDQS, UDQS
Mode Registers and
Ext. Mode Registers
2
VDD/VDDQ
Vss/VssQ
SELF
DATA OUT
BUFFER
REFRESH
A12
A11
A10
A9
CONTROLLER
15
16
16
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
A3
A2
8192
8192
13
MEMORY CELL
ARRAY
8192
8192
13
A1
BANK 0
ROW
A0
ROW
ADDRESS
LATCH
BA0
BA1
ADDRESS
BUFFER
13
13
13
SENSE AMP I/O GATE
2
1024
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
10
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
10
Integrated Silicon Solution, Inc. ꢀ
3
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN CONFIGURATIONS
66 pin TSOP - Type II for x8
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC
DQ4
V
SS
Q
VDDQ
NC
NC
DDQ
NC
NC
NC
NC
V
V
SSQ
DQS
NC
VDD
NC
VREF
VSS
DM
CK
NC
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTION: x8
A0-A12
A0-A9,ꢀA11ꢀ
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ7ꢀ
CK,ꢀCK
CKEꢀ
RowꢀAddressꢀInput
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
DMꢀꢀ
DataꢀWriteꢀMask
DQS
DataꢀStrobe
VDDꢀ
VDDQꢀ
VSSꢀ
VSSQꢀ
VREF
NC
Power
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
System Clock Input
ClockꢀEnable
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
WE
RowꢀAddressꢀStrobeꢀ
Command
WriteꢀEnable
4ꢀ
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN CONFIGURATION
Package Code B: 60-ball FBGA (top view) for x8
(8mmꢀxꢀ13mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
Top View
(BallsꢀseenꢀthroughꢀtheꢀꢀPackage)
: Ball Existing
: Depopulated Ball
1
2
3
7
8
9
Top View
(See the balls through the Package)
VSSQ DQ7
VSS
VDD
DQ0 VDDQ
A
B
C
D
1
2 3 6 7 8 9
4 5
NC
NC
VDDQ DQ6
VSSQ DQ5
DQ1 VSSQ
DQ2 VDDQ
NC
NC
NC
NC
A
B
C
D
E
F
NC
VDDQ DQ4
DQ3 VSSQ
DQS
NC
VSSQ
NC
NC
VDDQ
VDD
CAS
CS
E
F
VREF
DM
NC
VSS
CK
CKE
A9
WE
RAS
BA1
CK
A12
A11
A8
G
H
J
G
H
J
BA0
K
L
A7
A0 A10/AP
K
A6
A4
A5
A2
A1
A3
L
M
VSS
VDD
M
BGA Package Ball Pattern
Top View
x8 Device Ball Pattern
PIN DESCRIPTION: x8
A0-A12
A0-A9,ꢀA11ꢀ
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ7
CK,ꢀCK
CKEꢀ
RowꢀAddressꢀInput
DQS
DataꢀStrobe
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
VDDꢀ
VDDQꢀ
VSSꢀ
VSSQꢀ
VREF
NC
Power
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
System Clock Input
ClockꢀEnable
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
WE
RowꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
DMꢀ
DataꢀWriteꢀMask
Integrated Silicon Solution, Inc.
5
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
NC
DQ8
NC
V
DDQ
LDQS
NC
VSSQ
UDQS
NC
VDD
NC
VREF
VSS
UDM
CK
LDM
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTION: x16
A0-A12
A0-A9ꢀ
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ15ꢀ
CK,ꢀCK
CKEꢀ
RowꢀAddressꢀInput
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
LDM,ꢀUDMꢀꢀ
DataꢀWriteꢀMask
LDQS,ꢀUDQS
VDDꢀ
DataꢀStrobe
Power
VDDQꢀ
VSSꢀ
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
System Clock Input
ClockꢀEnable
VSSQꢀ
VREF
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
NC
RAS
WE
RowꢀAddressꢀStrobeꢀ
Command
WriteꢀEnable
6ꢀ
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN CONFIGURATION
Package Code B: 60-ball FBGA (top view) for x16
(8mmꢀxꢀ13mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
Top View
(BallsꢀseenꢀthroughꢀtheꢀꢀPackage)
: Ball Existing
: Depopulated Ball
1
2
3
7
8
9
Top View
(See the balls through the Package)
VSSQ DQ15
VSS
VDD
DQ0 VDDQ
A
B
C
D
1
2 3 6 7 8 9
4 5
DQ14 VDDQ DQ13
DQ12 VSSQ DQ11
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
A
B
C
D
E
F
DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
DQ8 VSSQ UDQS
VREF
E
F
NC
VSS
UDM
CK
LDM
WE
VDD
CAS
CS
CK
A12
A11
A8
G
H
J
G
H
J
RAS
BA1
CKE
A9
BA0
K
L
A7
A0 A10/AP
K
A6
A4
A5
A2
A1
A3
L
M
VSS
VDD
M
BGA Package Ball Pattern
Top View
x16 Device Ball Pattern
PIN DESCRIPTION: x16
A0-A12
A0-A9ꢀ
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ15ꢀ
CK,ꢀCK
CKEꢀ
RowꢀAddressꢀInput
LDQS,ꢀUDQSꢀ
DataꢀStrobe
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
VDDꢀ
VDDQꢀ
VSSꢀ
VSSQꢀ
VREF
NC
Power
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
System Clock Input
ClockꢀEnable
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
RowꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
WE
LDM,ꢀUDMꢀ
DataꢀWriteꢀMask
Integrated Silicon Solution, Inc. ꢀ
7
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN CONFIGURATION
Package Code B: 144-ball FBGA (top view)
(12mmꢀxꢀ12mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
Top View (Ballsꢀseenꢀthroughꢀtheꢀpackage)
1 2 3 4 5 6 7 8 9 10 11 12
A
B
C
D
E
F
DQ28 VSSQ DM3 DQS3
VDDQ NC VDDQ DQ27
VSSQ VSSQ DQ26 DQ25
VSS VDD VDDQ DQ24
VSSQ VDDQ DQ15 DQ14
VSSQ VDDQ DQ13 DQ12
DQ2 DQ0 DQ31 DQ29
DQ1 VDDQ VDDQ DQ30
VSSQ VDD VDD VSSQ
VSSQ VSS VSS VSSQ
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
A10 VDD VDD A12
DQS0 DM0 VSSQ DQ3
DQ4 VDDQ NC VDDQ
DQ6 DQ5 VSSQ VSSQ
DQ7 VDDQ VDD VSS
DQ17 DQ16 VDDQ VSSQ
DQ19 DQ18 VDDQ VSSQ
G
H
J
VSSQ NC
DM1 DQS1
DQS2 DM2
NC VSSQ
VSSQ VDDQ DQ11 DQ10
VSSQ VDDQ DQ9 DQ8
DQ21 DQ20 VDDQ VSSQ
DQ22 DQ23 VDDQ VSSQ
K
L
VSS VDD
NC
NC
NC
CAS
RAS
CS
WE VDD VSS
CK
A2
A1
A9
A4
A5
A6
NC
A7
CK
A8
NC
NC
NC
BA1
A0
A11
A3
M
CKE VREF
BA0
Note:ꢀVssꢀballsꢀinsideꢀtheꢀdottedꢀboxꢀareꢀoptionalꢀforꢀpurposesꢀofꢀthermalꢀdissipation.
PIN DESCRIPTION: for x32
A0-A12
A0-A7,ꢀA9
BA0,ꢀBA1
DQ0ꢀ–ꢀDQ31
CK,ꢀCK
CKE
RowꢀAddressꢀInput
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
WE
WriteꢀEnable
DM0-DM3
DQS0-DQS3
VDD
DataꢀWriteꢀMask
DataꢀStrobeꢀ
Power
System Clock Input
ClockꢀEnable
VDDQ
VREF
VSS
PowerꢀSupplyꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
Ground
CS
Chip Select
CAS
Column Address Strobe
Command
VSSQ
NC
GroundꢀforꢀI/OꢀPins
No Connection
RAS
RowꢀAddressꢀStrobeꢀ
Command
8
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN FUNCTIONAL DESCRIPTIONS
Symbol
Type Description
CK,ꢀCK
Input Clock:ꢀCKꢀandꢀCK are differential clock inputs. All address and control input signals are sampled
onꢀtheꢀcrossingꢀofꢀtheꢀpositiveꢀedgeꢀofꢀCKꢀandꢀnegativeꢀedgeꢀofꢀCK.ꢀInputꢀandꢀoutputꢀdataꢀisꢀ
referencedꢀtoꢀtheꢀcrossingꢀofꢀCKꢀandꢀCKꢀ(bothꢀdirectionsꢀofꢀcrossing).ꢀInternalꢀclockꢀsignalsꢀareꢀ
derivedꢀfromꢀCK/ꢀCK.
CKE
Input ClockꢀEnable:ꢀCKEꢀHIGHꢀactivates,ꢀandꢀCKEꢀLOWꢀdeactivatesꢀinternalꢀclockꢀsignals,ꢀandꢀdeviceꢀ
inputꢀbuffersꢀandꢀoutputꢀdrivers.ꢀTakingꢀCKEꢀLOWꢀprovidesꢀPRECHARGEꢀPOWER-DOWNꢀandꢀ
SELFꢀREFRESHꢀoperationꢀ(allꢀbanksꢀidle),ꢀorꢀACTIVEꢀPOWERDOWNꢀ(rowꢀACTIVEꢀinꢀanyꢀ
bank).ꢀCKEꢀisꢀsynchronousꢀforꢀallꢀfunctionsꢀexceptꢀforꢀSELFꢀREFRESHꢀEXIT,ꢀwhichꢀisꢀachievedꢀ
asynchronously.ꢀInputꢀbuffers,ꢀexcludingꢀCK,ꢀCKꢀandꢀCKE,ꢀareꢀdisabledꢀduringꢀpower-downꢀandꢀ
self refresh mode which are contrived for low standby power consumption.
CS
Input ChipꢀSelect:ꢀCSꢀenablesꢀ(registeredꢀLOW)ꢀandꢀdisablesꢀ(registeredꢀHIGH)ꢀtheꢀcommandꢀ
decoder.ꢀAllꢀcommandsꢀareꢀmaskedꢀwhenꢀCSꢀisꢀregisteredꢀHIGH.ꢀCSꢀprovidesꢀforꢀexternalꢀbankꢀ
selection on systems with multiple banks. CS is considered part of the command code.
Input Command Inputs: RAS, CAS and WEꢀ(alongꢀwithꢀCS) define the command being entered.
RAS, CAS,
WE
DM:ꢀx8;ꢀ
LDM,ꢀUDM:ꢀ
x16;ꢀ
Input InputꢀDataꢀMask:ꢀDMꢀisꢀanꢀinputꢀmaskꢀsignalꢀforꢀwriteꢀdata.ꢀInputꢀdataꢀisꢀmaskedꢀwhenꢀDMꢀisꢀ
sampledꢀHIGHꢀalongꢀwithꢀthatꢀinputꢀdataꢀduringꢀaꢀWRITEꢀaccess.ꢀDMꢀisꢀsampledꢀonꢀbothꢀedgesꢀ
ofꢀDQS.ꢀAlthoughꢀDMꢀpinsꢀareꢀinput-only,ꢀtheꢀDMꢀloadingꢀmatchesꢀtheꢀDQꢀandꢀDQSꢀloading.
DM0-DM3:ꢀ
x32
Forꢀx16ꢀdevices,ꢀLDMꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀUDMꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15.
Forꢀx32ꢀdevices,ꢀDM0ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀDM1ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15,ꢀDM2ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ16-DQ23,ꢀandꢀDM3ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ24-DQ31.
BA0,ꢀBA1
Input InputꢀBankꢀAddressꢀInputs:ꢀBA0ꢀandꢀBA1ꢀdefineꢀtoꢀwhichꢀbankꢀanꢀACTIVE,ꢀREAD,ꢀWRITEꢀorꢀ
PRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
A [12:0]
Input AddressꢀInputs:ꢀprovideꢀtheꢀrowꢀaddressꢀforꢀACTIVEꢀcommands,ꢀandꢀtheꢀcolumnꢀaddressꢀandꢀ
AUTOꢀPRECHARGEꢀbitꢀforꢀREADꢀ/ꢀWRITEꢀcommands,ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀofꢀtheꢀmemoryꢀ
arrayꢀinꢀtheꢀrespectiveꢀbank.ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀopcodeꢀduringꢀaꢀMODEꢀ
REGISTERꢀSETꢀcommand.
DQ:
DQ0-DQ7:ꢀx8;
DQ0-DQ15:ꢀ
x16
I/O
DataꢀBus:ꢀInputꢀ/ꢀOutput
DQ0-DQ31:ꢀ
x32
DQS:ꢀx8:
I/O
DataꢀStrobe:ꢀOutputꢀwithꢀreadꢀdata,ꢀinputꢀwithꢀwriteꢀdata.ꢀEdge-alignedꢀwithꢀreadꢀdata,ꢀcenteredꢀ
withꢀwriteꢀdata.ꢀUsedꢀtoꢀcaptureꢀwriteꢀdata.
LDQS,ꢀUDQS
x16:ꢀ
DQS0-DQS3:ꢀ
x32
Forꢀx16ꢀdevice,ꢀLDQSꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀUDQSꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15.
Forꢀx32ꢀdevice,ꢀDQS0ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀDQS1ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15,ꢀDQS2ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ16-DQ23,ꢀandꢀDQS3ꢀcorrespondsꢀtoꢀtheꢀdataꢀ
onꢀDQ24-DQ31.
NC
--
No Connect: Should be left unconnected.
VREF
VDDQ
VSSQ
VDD
Supply SSTL_2ꢀreferenceꢀvoltage.
Supply I/OꢀPowerꢀSupply.
Supply I/OꢀGround.
Supply Power Supply.
Supply Ground.
VSS
Integrated Silicon Solution, Inc. ꢀ
9
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
COMMANDS TRUTH TABLES
Allꢀcommandsꢀ(addressꢀandꢀcontrolꢀsignals)ꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀclockꢀ(crossingꢀofꢀCKꢀgoingꢀhighꢀ
andꢀCKꢀgoingꢀlow).ꢀTruthꢀTableꢀshowsꢀbasicꢀtimingꢀparametersꢀforꢀallꢀcommands.ꢀ
TRUTH TABLE - COMMANDS
NAME (FUNCTION)
CS
H
L
RAS CAS WE
BA
X
AP
X
Address Notes
DESELECTꢀ(NOP)ꢀ
X
H
L
X
H
H
L
X
H
H
H
X
X
2
2
NOꢀOPERATIONꢀ(NOP)ꢀ
ACTIVEꢀ(selectꢀbankꢀandꢀactivateꢀrow)ꢀ
X
X
L
Valid
Valid
X
Row
Column
READꢀ(selectꢀbankꢀandꢀcolumnꢀandꢀstartꢀreadꢀ
L
H
L
burst)
READꢀwithꢀAPꢀ(readꢀburstꢀwithꢀAutoꢀPrecharge)ꢀ
L
L
H
H
L
L
H
L
Valid
Valid
H
L
Column
Column
3
3
WRITEꢀ(selectꢀbankꢀandꢀcolumnꢀandꢀstartꢀwriteꢀ
burst)
WRITEꢀwithꢀAPꢀ(writeꢀburstꢀwithꢀAutoꢀ
L
H
L
L
Valid
H
Column
Precharge)
BURSTꢀTERMINATE
L
L
H
L
H
H
L
L
X
X
L
X
X
4
PRECHARGEꢀ(deactivateꢀrowꢀinꢀselectedꢀ
Valid
5
bank)
PRECHARGEꢀALLꢀ(deactivateꢀrowsꢀinꢀallꢀ
banks)
L
L
H
L
X
H
X
X
X
5
AUTOꢀREFRESHꢀorꢀenterꢀSELFꢀREFRESHꢀ
MODEꢀREGISTERꢀSETꢀ
L
L
L
L
L
L
H
L
X
6,7,8
9
Valid
Op-code
Notes:
1. All states and sequences not shown are illegal or reserved.
2.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
3.ꢀ Autoprechargeꢀisꢀnon-persistent.ꢀAPꢀHighꢀenablesꢀAutoꢀPrecharge,ꢀwhileꢀAPꢀLowꢀdisablesꢀAutoprecharge.
4.ꢀ BurstꢀTerminateꢀappliesꢀtoꢀonlyꢀReadꢀburstsꢀwithꢀAutoꢀPrechargeꢀdisabled.ꢀThisꢀcommandꢀisꢀundefinedꢀandꢀshouldꢀnotꢀbeꢀ
usedꢀforꢀReadꢀwithꢀAutoꢀPrechargeꢀenabled,ꢀandꢀforꢀWriteꢀbursts.
5.ꢀ IfꢀAPꢀisꢀLow,ꢀbankꢀaddressꢀdeterminesꢀwhichꢀbankꢀisꢀtoꢀbeꢀprecharged.ꢀIfꢀAPꢀisꢀHigh,ꢀallꢀbanksꢀareꢀprechargedꢀandꢀBA0-
BA1areꢀdon’tꢀcare.
6.ꢀ ThisꢀcommandꢀisꢀAUTOꢀREFRESHꢀifꢀCKEꢀisꢀHigh,ꢀandꢀSELFꢀREFRESHꢀifꢀCKEꢀisꢀlow.
7.ꢀ AllꢀaddressꢀinputsꢀandꢀI/Oꢀareꢀ‘don'tꢀcare’ꢀexceptꢀforꢀCKE.ꢀInternalꢀrefreshꢀcountersꢀcontrolꢀbankꢀandꢀrowꢀaddressing.
8.ꢀ AllꢀbanksꢀmustꢀbeꢀprechargedꢀbeforeꢀissuingꢀanꢀAUTO-REFRESHꢀorꢀSELFꢀREFRESHꢀcommand.
9.ꢀ BA0ꢀandꢀBA1ꢀvalueꢀselectꢀbetweenꢀMRSꢀandꢀEMRS.
10.ꢀCKEꢀisꢀHIGHꢀforꢀallꢀcommandsꢀshownꢀexceptꢀSELFꢀREFRESH.
ADDRESSING
TRUTH TABLE - DM Operations
x32
x16
x8
FUNCTION
WriteꢀEnableꢀ
Write Inhibit
DM
Lꢀ
DQ
Valid
X
AutoꢀPrechargeꢀ(AP)ꢀ
RowꢀAddressꢀ(RA)ꢀ
A8
A10
A10
A0-A12 A0-A12 A0-A12
H
ColumnꢀAddressꢀ(CA) A0-A7,ꢀ
A9
A0-A9
A0-A9,ꢀ
A11
Note:ꢀUsedꢀtoꢀmaskꢀwriteꢀdata,ꢀprovidedꢀcoincidentꢀwithꢀtheꢀ
corresponding data.
10
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
TRUTH TABLE - CKE
CKE n-1 CKE n Current State
COMMAND n
ACTION n
NOTES
L
L
L
L
PowerꢀDown
SelfꢀRefresh
PowerꢀDown
SelfꢀRefresh
AllꢀBanksꢀIdle
Bank(s)ꢀActive
AllꢀBanksꢀIdle
X
MaintainꢀPowerꢀDown
MaintainꢀSelfꢀRefresh
ExitꢀPowerꢀDown
X
L
H
H
L
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
AUTOꢀREFRESH
6
L
ExitꢀSelfꢀRefresh
6,ꢀ7
6
H
H
H
H
PrechargeꢀPowerꢀDownꢀEntry
ActiveꢀPowerꢀDownꢀEntry
SelfꢀRefreshꢀentry
L
6
L
H
SeeꢀTruthꢀTablesꢀ-ꢀCommands
Notes:
1.ꢀ CKEnꢀisꢀtheꢀlogicꢀstateꢀofꢀCKEꢀatꢀclockꢀedgeꢀn;ꢀCKEn-1ꢀwasꢀtheꢀstateꢀofꢀCKEꢀatꢀtheꢀpreviousꢀclockꢀedge.
2.ꢀ CurrentꢀstateꢀisꢀtheꢀstateꢀofꢀDDRꢀimmediatelyꢀpriorꢀtoꢀclockꢀedgeꢀn.
3.ꢀ COMMANDnꢀisꢀtheꢀcommandꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀACTIONnꢀisꢀtheꢀresultꢀofꢀCOMMANDn.
4.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
5.ꢀ CKEꢀmustꢀnotꢀgoꢀLOWꢀduringꢀaꢀReadꢀorꢀWrite,ꢀandꢀmustꢀstayꢀHIGHꢀuntilꢀafterꢀtrpst or twr, respectively.
6.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
7.ꢀꢀNOPsꢀorꢀDeselectsꢀmustꢀbeꢀissuedꢀforꢀatꢀleastꢀtsnrꢀafterꢀSelf-Refreshꢀexitꢀbeforeꢀanyꢀotherꢀcommand.ꢀAfterꢀDLLꢀReset,ꢀatꢀ
least txsrdꢀmustꢀelapseꢀbeforeꢀanyꢀReadꢀcommandsꢀoccur.
Basic Timing Parameters for Commands
tCK
tCH
tCL
CK
CK
tIS tIH
Valid
Input
Valid
Valid
= Don't Care
NOTE: Input = A0 - An, BA0, BA1, CKE, CS, RAS, CAS, WE;
An = Address bus MSB
Integrated Silicon Solution, Inc.
11
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
SIMPLIFIED STATE DIAGRAM
Power
Applied
Power
On
Precharge
PREALL
Self
Refresh
REFS
REFSX
MRS
MRS
REFA
Auto
Refresh
Idle
EMRS
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Read
Write
Write
Read
Write A
Read A
Read
Read
Write
Read A
Write A
Read
A
PRE
Write
A
Read
A
PRE
PRE
Precharge
PRE
PREALL
Automatic Sequence
Command Sequence
PREALLꢀ=ꢀPrechargeꢀAllꢀBanksꢀ
CKELꢀ=ꢀEnterꢀPowerꢀDown
MRSꢀ=ꢀModeꢀRegisterꢀSetꢀ
CKEHꢀ=ꢀExitꢀPowerꢀDown
REFSꢀ=ꢀEnterꢀSelfꢀRefreshꢀ
Write A = Write with Autoprecharge
REFSXꢀ=ꢀExitꢀSelfꢀRefreshꢀ
ReadꢀAꢀ=ꢀReadꢀwithꢀAutoprecharge
REFAꢀ=ꢀAutoꢀRefreshꢀ
EMRSꢀ=ꢀExtendedꢀModeꢀRegisterꢀSetꢀ
ACTꢀ=ꢀActive
PREꢀ=ꢀPrecharge
12
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
FUNCTIONAL DESCRIPTION
TheꢀDDRꢀSDRAMꢀisꢀaꢀhighꢀspeedꢀCMOS,ꢀdynamicꢀrandom-accessꢀmemoryꢀinternallyꢀconfiguredꢀasꢀaꢀquad-bankꢀ
DRAM.ꢀTheꢀ512Mbꢀdevicesꢀcontains:ꢀ536,870,912ꢀbits.ꢀ
TheꢀDDRꢀSDRAMꢀusesꢀdoubleꢀdataꢀrateꢀarchitectureꢀtoꢀachieveꢀhighꢀspeedꢀoperation.ꢀTheꢀdoubleꢀdataꢀrateꢀ
architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycleꢀatꢀtheꢀI/Oꢀpins.ꢀAꢀsingleꢀreadꢀorꢀwriteꢀaccessꢀforꢀtheꢀDDRꢀSDRAMꢀeffectivelyꢀconsistsꢀofꢀaꢀsingleꢀ2n-bitꢀwide,ꢀ
oneꢀclockꢀcycleꢀdataꢀtransferꢀatꢀtheꢀinternalꢀDRAMꢀcoreꢀandꢀtwoꢀcorrespondingꢀn-bitꢀwide,ꢀone-half-clock-cycleꢀ
dataꢀtransfersꢀatꢀtheꢀI/Oꢀpins.ꢀReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀDDRꢀSDRAMꢀareꢀburstꢀoriented;ꢀaccessesꢀstartꢀatꢀaꢀ
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin
withꢀtheꢀregistrationꢀofꢀanꢀACTIVEꢀcommand,ꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀaddressꢀ
bitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀtheꢀrowꢀtoꢀbeꢀaccessed.ꢀTheꢀ
addressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀREADꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀtheꢀstartingꢀ
column location for the burst access.
Priorꢀtoꢀnormalꢀoperation,ꢀtheꢀDDRꢀSDRAMꢀmustꢀbeꢀinitialized.ꢀTheꢀfollowingꢀsectionꢀprovidesꢀdetailedꢀinformationꢀ
covering device initialization, register definition, command description and device operation
INITIALIZATION
DDRꢀSDRAMsꢀmustꢀbeꢀpoweredꢀupꢀandꢀinitializedꢀinꢀaꢀpredefinedꢀmanner.ꢀOperationsꢀproceduresꢀotherꢀthanꢀthoseꢀ
specified may result in undefined operation. If there is any interruption to the device power, the initialization routine
shouldꢀbeꢀfollowed.ꢀTheꢀstepsꢀtoꢀbeꢀfollowedꢀforꢀdeviceꢀinitializationꢀareꢀlistedꢀbelow.ꢀTheꢀInitializationꢀFlowꢀdiagramꢀ
andꢀtheꢀInitializationꢀFlowꢀsequenceꢀareꢀshownꢀinꢀtheꢀfollowingꢀfigures.ꢀ
TheꢀModeꢀRegisterꢀandꢀExtendedꢀModeꢀRegisterꢀdoꢀnotꢀhaveꢀdefaultꢀvalues.ꢀIfꢀtheyꢀareꢀnotꢀprogrammedꢀduringꢀtheꢀ
initializationꢀsequence,ꢀitꢀmayꢀleadꢀtoꢀunspecifiedꢀoperation.ꢀTheꢀclockꢀstopꢀfeatureꢀisꢀnotꢀavailableꢀuntilꢀtheꢀdeviceꢀhasꢀ
beenꢀproperlyꢀinitializedꢀfromꢀStepꢀ1ꢀthroughꢀ13.
•ꢀStepꢀ1:ꢀApplyꢀVDDꢀbeforeꢀorꢀatꢀtheꢀsameꢀtimeꢀasꢀVDDQ.
•ꢀStepꢀ2:ꢀCKEꢀmustꢀmaintainꢀLVCMOSꢀLowꢀuntilꢀVREFꢀisꢀstable.ꢀApplyꢀVDDQꢀbeforeꢀapplyingꢀVTTꢀandꢀVREF.
•ꢀStepꢀ3:ꢀThereꢀmustꢀbeꢀatꢀleastꢀ200ꢀμsꢀofꢀvalidꢀclocksꢀbeforeꢀanyꢀcommandꢀmayꢀbeꢀgivenꢀtoꢀtheꢀDRAM.ꢀDuringꢀthisꢀ
timeꢀNOPꢀorꢀDESELECTꢀcommandsꢀmustꢀbeꢀissuedꢀonꢀtheꢀcommandꢀbusꢀandꢀCKEꢀshouldꢀbeꢀbroughtꢀHIGH.
•ꢀStepꢀ4:ꢀIssueꢀaꢀPRECHARGEꢀALLꢀcommand.
•ꢀStepꢀ5:ꢀProvideꢀNOPsꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtRPꢀtime.
•ꢀStepꢀ6:ꢀIssueꢀEMRSꢀcommand
•ꢀStepꢀ7:ꢀIssueꢀMRSꢀcommand,ꢀloadꢀtheꢀbaseꢀmodeꢀregisterꢀandꢀtoꢀresetꢀtheꢀDLL.ꢀSetꢀtheꢀdesiredꢀoperatingꢀmodes.
•ꢀStepꢀ8:ꢀProvideꢀNOPsꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtMRDꢀtime.
•ꢀStepꢀ9:ꢀIssueꢀaꢀPRECHARGEꢀALLꢀcommand
•ꢀStepꢀ10:ꢀIssueꢀ2ꢀorꢀmoreꢀAUTOꢀREFRESHꢀcycles
•ꢀStepꢀ11:ꢀIssueꢀMRSꢀcommandꢀwithꢀtheꢀresetꢀDLLꢀbitꢀdeactivatedꢀtoꢀprogramꢀoperatingꢀparametersꢀwithoutꢀresettingꢀ
theꢀDLL
•ꢀStepꢀ12:ꢀProvideꢀNOPꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtMRDꢀtime.
•ꢀStepꢀ13:ꢀTheꢀDRAMꢀhasꢀbeenꢀproperlyꢀinitializedꢀandꢀisꢀreadyꢀforꢀanyꢀvalidꢀcommand.
Integrated Silicon Solution, Inc. ꢀ
13
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
Initialization Waveform Sequence
VDD
tVDT≥ 0
VDDQ
VTT
(system1)
VREF
t
CK
t
tCL
CH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CK
CK
( (
) )
( (
) )
( (
( (
) )
( (
) )
( (
) )
) )
tIS tIH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
LVCMOS LOW LEVEL
CKE
((
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
)
)
t
tIH
IS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
NOP
PRE
EMRS
MRS
PRE
AR
AR
MRS
ACT
COMMAND
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DM
( (
) )
( (
) )
( (
) )
( (
) )
( (
( (
) )
)
)
tIS tIH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CODE
CODE
CODE
CODE
CODE
RA
( (
) )
( (
( (
) )
Address
AP4
( (
) )
( (
) )
( (
) )
)
)
t
IS
tIH
ALL BANKS
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
RA
BA
( (
) )
( (
( (
) )
( (
) )
( (
) )
( (
) )
) )
tIS tIH
tIS tIH
t
tIH
IS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
BA0=H,
BA1=L
BA0=L,
BA1=L
BA0=L,
BA1=L
BA0, BA1
( (
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
)
)
High-- Z
((
((
((
((
((
((
DQS
)
)
)
)
)
)
)
)
)
)
)
)
High-- Z
((
)
((
((
((
((
((
DQ
)
)
)
)
)
)
)
)
)
)
)
T = 200 µs
tMRD2
tMRD2
tRP
tRFC
tRFC
tMRD2
Power--up:
VDD and
CLK stable
Extended
Mode
Register
Set
200 cycles of CK**
Load
Mode
Register
(with A8= L)
Load
Mode
Register,
Reset DLL
(with A8 = H)
DON’T CARE
Notes:
1.ꢀꢀVTTꢀisꢀnotꢀappliedꢀdirectlyꢀtoꢀtheꢀdevice,ꢀhoweverꢀtVTDꢀmustꢀbeꢀgreaterꢀthanꢀorꢀequalꢀtoꢀzeroꢀtoꢀavoidꢀdeviceꢀlatch--up.
2.ꢀꢀtMRDꢀisꢀrequiredꢀbeforeꢀanyꢀcommandꢀcanꢀbeꢀapplied,ꢀandꢀ200ꢀcyclesꢀofꢀCKꢀareꢀrequiredꢀbeforeꢀanyꢀexecutableꢀcommandꢀ
can be applied
3.ꢀꢀTheꢀtwoꢀAutoꢀRefreshꢀcommandsꢀmayꢀbeꢀmovedꢀtoꢀfollowꢀtheꢀfirstꢀMRSꢀbutꢀprecedeꢀtheꢀsecondꢀPRECHARGEꢀALLꢀcom-
mand.
4.ꢀꢀAPꢀisꢀA8ꢀforꢀx32,ꢀandꢀA10ꢀforꢀx8/x16.ꢀAddressꢀisꢀA0ꢀtoꢀA12ꢀexceptꢀAP.
14
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
MODE REGISTER (MR) DEFINITION
TheꢀModeꢀRegisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀofꢀoperationꢀofꢀtheꢀDDRꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀ
theꢀdefinitionꢀofꢀaꢀburstꢀlength,ꢀaꢀburstꢀtype,ꢀandꢀaꢀCASꢀlatency.ꢀTheꢀModeꢀRegisterꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀ
REGISTERꢀSETꢀcommandꢀ(withꢀBA0=0ꢀandꢀBA1=0)ꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀreprogrammed,ꢀ
orꢀtheꢀdeviceꢀlosesꢀpower.ꢀꢀModeꢀRegisterꢀbitsꢀA0-A2ꢀspecifyꢀtheꢀburstꢀlength,ꢀA3ꢀtheꢀtypeꢀofꢀburstꢀ(sequentialꢀorꢀ
interleave),ꢀA4-A6ꢀtheꢀCASꢀlatency,ꢀandꢀA8ꢀDLLꢀreset.ꢀAꢀlogicꢀ0ꢀshouldꢀbeꢀprogrammedꢀtoꢀallꢀtheꢀundefinedꢀaddressesꢀ
bitsꢀtoꢀensureꢀfutureꢀcompatibility.ꢀꢀTheꢀModeꢀRegisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀ
progress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀtMRDꢀbeforeꢀinitiatingꢀanyꢀsubsequentꢀoperation.ꢀViolatingꢀ
eitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.ꢀReservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀ
operation or incompatibility with future versions may result
MODE REGISTER
AddressꢀBusꢀ(Ax)
BA1 BA0 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ModeꢀReg.ꢀ(Ex)
A2 A1 A0 Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
A3 Burst Type
0
1
Sequential
Interleave
A6 A5 A4 CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
A12 A11 A10 A9 A8 A7 DLL
3
0
0
0
0
0
0
0
0
0
1
0
0
Normal operation
Reset DLL
Reserved
Reserved
2.5
Reserved
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
Notes:
1. A logic 0 should be programmed to all unused / undefined
address bits to ensure future compatibility.
Reserved
Integrated Silicon Solution, Inc.
15
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
BURST LENGTH
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀDDRꢀSDRAMꢀareꢀburstꢀoriented,ꢀwithꢀtheꢀburstꢀlengthꢀbeingꢀsetꢀandꢀtheꢀburstꢀorderꢀ
asꢀinꢀBurstꢀDefinition.ꢀTheꢀburstꢀlengthꢀdeterminesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀbeꢀaccessedꢀforꢀ
aꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀlengthsꢀofꢀ2,ꢀ4,ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀsequentialꢀandꢀtheꢀ
interleaved burst types.
BURST DEFINITION
Burst
Starting Column Address
Order of Accesses Within a Burst
Length
Type = Sequential
Type = Interleaved
A 0
0
2
0-1
1-0
0-1
1-0
1
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
0
1
1
0
1
1
A 2
0
A 1
0
A 0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
ꢀ2-3-4-5-6-7-0-1
ꢀ3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Notes:
1.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀtwo,ꢀA1-Anꢀselectsꢀtheꢀtwoꢀdataꢀelementꢀblock;ꢀA0ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
2.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀfour,ꢀA2-Anꢀselectsꢀtheꢀfourꢀdataꢀelementꢀblock;ꢀA0-A1ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
3.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀeight,ꢀA3-Anꢀselectsꢀtheꢀeightꢀdataꢀelementꢀblock;ꢀA0-A2ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
4.ꢀ Wheneverꢀaꢀboundaryꢀofꢀtheꢀblockꢀisꢀreachedꢀwithinꢀaꢀgivenꢀsequence,ꢀtheꢀfollowingꢀaccessꢀwrapsꢀwithinꢀtheꢀblock.
16
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀcolumnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.
TheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo,ꢀbyꢀA2-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀ
toꢀ4,ꢀbyꢀA3-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀ8.ꢀAnꢀisꢀtheꢀmostꢀsignificantꢀcolumnꢀaddressꢀbit,ꢀwhichꢀdependsꢀifꢀtheꢀ
deviceꢀisꢀx8,ꢀx16ꢀorꢀx32.ꢀTheꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀbothꢀreadꢀandꢀwriteꢀbursts.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀA3.ꢀ
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀtheꢀburstꢀlength,ꢀtheꢀburstꢀtypeꢀandꢀtheꢀstartingꢀcolumnꢀ
address.
READ LATENCY
TheꢀREADꢀlatency,ꢀorꢀCASꢀlatency,ꢀisꢀtheꢀdelayꢀbetweenꢀtheꢀregistrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
the first piece of output data.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀaꢀclockꢀedgeꢀnꢀandꢀtheꢀlatencyꢀisꢀ3ꢀclocks,ꢀtheꢀfirstꢀdataꢀelementꢀwillꢀbeꢀvalidꢀatꢀ
nꢀ+ꢀ2tCKꢀ+ꢀtAC.ꢀIfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀaꢀclockꢀedgeꢀnꢀandꢀtheꢀlatencyꢀisꢀ2ꢀclocks,ꢀtheꢀfirstꢀdataꢀelementꢀ
willꢀbeꢀvalidꢀatꢀnꢀ+ꢀtCKꢀ+ꢀtAC.
OPERATING MODE
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀissuingꢀaꢀModeꢀRegisterꢀSetꢀcommandꢀwithꢀbitsꢀA7ꢀtoꢀA12ꢀeachꢀsetꢀtoꢀ
zero,ꢀandꢀbitsꢀA0ꢀtoꢀA6ꢀsetꢀtoꢀtheꢀdesiredꢀvalues.ꢀAꢀDLLꢀresetꢀisꢀinitiatedꢀbyꢀissuingꢀaꢀModeꢀRegisterꢀSetꢀcommandꢀ
withꢀbitsꢀA7ꢀandꢀA9ꢀtoꢀA12ꢀeachꢀsetꢀtoꢀzero,ꢀbitꢀA8ꢀsetꢀtoꢀone,ꢀandꢀbitsꢀA0ꢀtoꢀA6ꢀsetꢀtoꢀtheꢀdesiredꢀvalues.ꢀAꢀModeꢀ
RegisterꢀSetꢀcommandꢀissuedꢀtoꢀresetꢀtheꢀDLLꢀmustꢀalwaysꢀbeꢀfollowedꢀbyꢀaꢀModeꢀRegisterꢀSetꢀcommandꢀtoꢀselectꢀ
normalꢀoperatingꢀmodeꢀ(A8=0).
AllꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀA7ꢀtoꢀA12ꢀareꢀreservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTestꢀmodesꢀandꢀreservedꢀ
states should not be used because unknown operation or incompatibility with future versions may result.
Integrated Silicon Solution, Inc. ꢀ
17
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
CAS LATENCIES
18
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
EXTENDED MODE REGISTER (EMR) DEFINITION
TheꢀExtendedꢀModeꢀRegisterꢀcontrolsꢀfunctionsꢀbeyondꢀthoseꢀcontrolledꢀbyꢀtheꢀModeꢀRegister;ꢀtheseꢀadditionalꢀ
functionsꢀincludeꢀDLLꢀenable/disable,ꢀandꢀoutputꢀdriveꢀstrengthꢀselection.ꢀTheꢀExtendedꢀModeꢀRegisterꢀisꢀ
programmedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀ(withꢀBA1=0ꢀandꢀBA0=1)ꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
untilꢀitꢀisꢀreprogrammed,ꢀꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀTheꢀExtendedꢀModeꢀRegisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀ
areꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀprogress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀtMRDꢀbeforeꢀinitiatingꢀanyꢀ
subsequentꢀoperation.ꢀViolatingꢀeitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.ꢀReservedꢀstatesꢀ
should not be used, as unknown operation or incompatibility with future versions may result.
DLL Enable/Disable
TheꢀDLLꢀmustꢀbeꢀenabledꢀforꢀnormalꢀoperation.ꢀDLLꢀenableꢀisꢀrequiredꢀduringꢀpower-upꢀinitialization,ꢀandꢀuponꢀ
returningꢀtoꢀnormalꢀoperationꢀafterꢀhavingꢀdisabledꢀtheꢀDLLꢀforꢀtheꢀpurposeꢀofꢀdebugꢀorꢀevaluationꢀ(uponꢀexitingꢀSelfꢀ
RefreshꢀMode,ꢀtheꢀDLLꢀisꢀenabledꢀautomatically).ꢀAnyꢀtimeꢀtheꢀDLLꢀisꢀenabledꢀaꢀDLLꢀResetꢀmustꢀfollowꢀandꢀ200ꢀclockꢀ
cycles must occur before any executable command can be issued.
OUTPUT DRIVE STRENGTH (DS)
TheꢀnormalꢀdriveꢀstrengthꢀforꢀallꢀoutputsꢀisꢀspecifiedꢀtoꢀbeꢀSSTL_2,ꢀClassꢀII.ꢀThisꢀDRAMꢀalsoꢀsupportsꢀaꢀreducedꢀ
driver strength option, intended for lighter load and/or point-to-point environments.
EXTENDED MODE REGISTER
AddressꢀBusꢀ(Ax)
BA1 BA0 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Ext.ꢀModeꢀReg.ꢀ(Ex)
Reserved(1)
A0 DLL
0
1
Enable
Disable
A1 Drive Strength
0
1
Normal
Reduced
BA1 BA0 Mode Register Definition
NOTES:
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
1. A logic 0 should be programmed to all unused/undefined ad-
dress bits to ensure future compatibility
Reserved
Integrated Silicon Solution, Inc. ꢀ
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Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
Absolute Maximum Rating
Parameter
Symbol
Vin,ꢀVout
Vdd,ꢀVddq
Tstg
Value
-1.0ꢀ~ꢀ3.6
-1.0ꢀ~ꢀ3.6
-55ꢀ~ꢀ+150
1.5
Unit
V
VoltageꢀonꢀanyꢀpinꢀrelativeꢀtoꢀVSS
VoltageꢀonꢀVDDꢀ&ꢀVDDQꢀsupplyꢀrelativeꢀtoꢀVSS
Storage temperature
V
oC
Power dissipation
Pd
W
Short circuit current
Ios
50
mA
Note:
PermanentꢀdeviceꢀdamageꢀmayꢀoccurꢀifꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀareꢀexceeded.
Functionalꢀoperationꢀshouldꢀbeꢀrestrictedꢀtoꢀrecommendꢀoperationꢀcondition.
Exposureꢀtoꢀhigherꢀthanꢀrecommendedꢀvoltageꢀforꢀextendedꢀperiodsꢀofꢀtimeꢀcouldꢀaffectꢀdeviceꢀreliability
AC/DC Electrical Characteristics and Operating Conditions
Recommendedꢀoperatingꢀconditionsꢀ(VoltageꢀreferencedꢀtoꢀVSS=0V;ꢀTA=0ꢀtoꢀ70oCꢀforꢀCommercial,ꢀTAꢀ=ꢀ-40oCꢀtoꢀ+85oC for Industrial and A1,
TAꢀ=ꢀ-40oCꢀtoꢀ+105oC for A2)
Parameter
Symbol
Min
Max
Unit
V
Note
Supplyꢀvoltageꢀ(withꢀaꢀnominalꢀVDDꢀofꢀ2.5Vꢀforꢀ-6)
Supplyꢀvoltageꢀ(withꢀaꢀnominalꢀVDDꢀofꢀ2.6Vꢀforꢀ-4,ꢀ-5)
I/OꢀSupplyꢀvoltageꢀ(withꢀaꢀnominalꢀVDDꢀofꢀ2.5Vꢀforꢀ-6)
I/OꢀSupplyꢀvoltageꢀ(withꢀaꢀnominalꢀVDDꢀofꢀ2.6Vꢀforꢀ-4,ꢀ-5)
I/OꢀReferenceꢀvoltage
Vdd
2.3
2.7
Vdd
2.5
2.7
V
V
V
ddq
ddq
2.3
2.7
V
2.5
2.7
V
V
ref
tt
dc
0.49*VDDQ
0.51*VDDQ
V
1
2
I/OꢀTerminationꢀvoltageꢀ(system)
V
VREF-0.04
VREF+0.04
V
Input logic high voltage
V
ih
(
)
VREF+0.15
VDDQ+0.3
V
Input logic low voltage
V
il
(
dc
)
-0.3
-0.3
0.36
0.71
-2
VREF-0.15
V
InputꢀVoltageꢀLevel,ꢀCLKꢀandꢀCLKꢀinputs
InputꢀDifferentialꢀVoltage,ꢀCLKꢀandꢀCLKꢀinputs
V-IꢀMatching:ꢀPullupꢀtoꢀPulldownꢀCurrentꢀRatio
Input leakage current
Vin
(
dc
)
)
VDDQ+0.3
V
Vid
(
dc
VDDQ+0.6
V
3
4
V
i(Ratio)
1.4
2
–
I
l
uA
uA
mA
mA
mA
mA
Outputꢀleakageꢀcurrent
I
oz
oh
ol
ohr
olr
-5
5
OutputꢀHighꢀCurrentꢀ(Normalꢀstrengthꢀdriver)ꢀ;ꢀVOUTꢀ=ꢀVTTꢀ+ꢀ0.84V
OutputꢀLowꢀCurrentꢀ(Normalꢀstrengthꢀdriver)ꢀ;ꢀVOUTꢀ=ꢀVTTꢀ-ꢀ0.84V
OutputꢀHighꢀCurrentꢀ(Halfꢀstrengthꢀdriver);ꢀVOUTꢀ=ꢀVTTꢀ+ꢀ0.45V
OutputꢀLowꢀCurrentꢀ(Halfꢀstrengthꢀdriver);ꢀVOUTꢀ=ꢀVTTꢀ-ꢀ0.45V
AmbientꢀOperatingꢀTemperature
I
-16.8
16.8
-9
–
I
–
I
–
I
9
–
Commercial
T
Ta
Ta
Ta
a
0
+70
+85
+85
oC
oC
oC
oC
Industrial
A1
-40
-40
-40
A2
+105
Note :
1.ꢀVREFꢀisꢀexpectedꢀtoꢀbeꢀequalꢀtoꢀ0.5*VDDQꢀofꢀtheꢀtransmittingꢀdevice,ꢀandꢀtoꢀtrackꢀvariationsꢀinꢀtheꢀdcꢀlevelꢀofꢀsame.ꢀPeak-toꢀ
peakꢀnoiseꢀonꢀVREFꢀmayꢀnotꢀexceedꢀ+/-2%ꢀofꢀtheꢀdcꢀvalue.
2.ꢀVTTꢀisꢀnotꢀappliedꢀdirectlyꢀtoꢀtheꢀdevice.ꢀVTTꢀisꢀaꢀsystemꢀsupplyꢀforꢀsignalꢀterminationꢀresistors,ꢀisꢀexpectedꢀtoꢀbeꢀsetꢀequalꢀtoꢀ
VREF,ꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀVREF
3.ꢀVIDꢀisꢀtheꢀmagnitudeꢀofꢀtheꢀdifferenceꢀbetweenꢀtheꢀinputꢀlevelꢀonꢀCLKꢀandꢀtheꢀinputꢀlevelꢀonꢀCLK.
4.ꢀTheꢀratioꢀofꢀtheꢀpullupꢀcurrentꢀtoꢀtheꢀpulldownꢀcurrentꢀisꢀspecifiedꢀforꢀtheꢀsameꢀtemperatureꢀandꢀvoltage,ꢀoverꢀtheꢀentireꢀtem-
peratureꢀandꢀvoltageꢀrange,ꢀforꢀdeviceꢀdrainꢀtoꢀsourceꢀvoltagesꢀfromꢀ0.25Vꢀtoꢀ1.0V.ꢀForꢀaꢀgivenꢀoutput,ꢀitꢀrepresentsꢀtheꢀmaxi-
mumꢀdifferenceꢀbetweenꢀpullupꢀandꢀpulldownꢀdriversꢀdueꢀtoꢀprocessꢀvariation.ꢀTheꢀfullꢀvariationꢀinꢀtheꢀratioꢀofꢀtheꢀmaximumꢀtoꢀ
minimumꢀpullupꢀandꢀpulldownꢀcurrentꢀwillꢀnotꢀexceedꢀ1.7ꢀforꢀdeviceꢀdrainꢀtoꢀsourceꢀvoltagesꢀfromꢀ0.1ꢀtoꢀ1.0.
20
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
CAPACITANCE CHARACTERISTICS(1)
(Vdd =ꢀVddqꢀ=ꢀ2.5Vꢀ+ꢀ0.2Vꢀ(-6),ꢀVdd =ꢀVddqꢀ=ꢀ2.6Vꢀ+ꢀ0.1Vꢀ(ꢀ-5),ꢀVssꢀ=ꢀVssQꢀ=ꢀ0V,ꢀunlessꢀotherwiseꢀnoted)
Symbol Parameter
Test Condition
Limits
Units
Min Max
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
VI=1.25v
1.3
1.3
1.3
3
3
3
3
5
pF
pF
pF
pF
Input Capacitance, control pin
InputꢀCapacitance,ꢀCLKꢀpin
f=100MHz
VI=25mVrms
I/OꢀCapacitance,ꢀI/O,ꢀDQS,ꢀDMꢀpin
Note:
1.ꢀThisꢀparameterꢀisꢀcharacterized.
THERMAL RESISTANCE
Package
Substrate
Theta-ja
Theta-ja
Theta-ja
Theta-jc
Units
(Airflow = 0m/s)
(Airflow = 1m/s)
(Airflow = 2m/s)
TSOP2(66)
BGA(60)
4-layer
4-layer
4-layer
52.5
32.3
28.1
49.9
29.1
23.4
46.9
26.9
20.7
7.7
5.5
3.4
C/W
C/W
C/W
BGA(144)
Integrated Silicon Solution, Inc.
21
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
IDD Specification Parameters and Test Conditions: x8, x16
(Vddꢀ=ꢀVddqꢀ=ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-6),ꢀVddꢀ=ꢀVddqꢀ=ꢀ2.6Vꢀ±ꢀ0.1Vꢀ(-5),ꢀVssꢀ=ꢀVssQꢀ=ꢀ0V,ꢀOutputꢀOpen,ꢀunlessꢀotherwiseꢀnoted)
Symbol Parameter/ Test Condition
-5
-6
Units
IDD0
Operatingꢀcurrentꢀforꢀoneꢀbankꢀactive-precharge;ꢀtRCꢀ=ꢀtRC(min);ꢀ
145 130
mA
tCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀonceꢀperꢀclockꢀ
cycle; address and control inputs changing once every two clock
cycles; CS = high between valid commands
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
Operatingꢀcurrentꢀforꢀoneꢀbankꢀoperation;ꢀoneꢀbankꢀopen;ꢀBLꢀ=ꢀ4;ꢀ
tRCꢀ=ꢀtRC(min);ꢀtCKꢀ=ꢀtCK(min);ꢀIout=0mA;ꢀAddressꢀandꢀcontrolꢀ
inputs changing once per clock cycle;
155 140
mA
mA
mA
mA
mA
Precharge power-down standby current; all banks idle; power-down
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
30
30
65
35
85
Prechargeꢀfloatingꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀallꢀbanksꢀidle;ꢀCKEꢀ 65
VIH(min);ꢀtCKꢀ=ꢀtCK(min);ꢀaddressꢀandꢀotherꢀcontrolꢀinputsꢀchangingꢀ
onceꢀperꢀclockꢀcycle;ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀDM
Active power-down standby current; one bank active; power-down
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
35
Activeꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀCKEꢀVIH(min);ꢀoneꢀbankꢀ
active;ꢀtRCꢀ=ꢀtRAS(max);ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDQSꢀandꢀDMꢀinputsꢀ
changing twice per clock cycle; address and other control inputs
changing once per clock cycle
85
IDD4R
Operatingꢀcurrentꢀforꢀburstꢀread;ꢀburstꢀlengthꢀ=ꢀ2;ꢀreads;ꢀcontinuousꢀ
burst; one bank active; address and control inputs changing once per
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀ50%ꢀofꢀdataꢀchangingꢀonꢀeveryꢀtransfer;ꢀ
lOUTꢀ=ꢀ0mA
330 280
mA
mA
IDD4W Operatingꢀcurrentꢀforꢀburstꢀwrite;ꢀburstꢀlengthꢀ=ꢀ2;ꢀwrites;ꢀcontinuousꢀ 340 290
burst; one bank active address and control inputs changing once per
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀtwiceꢀ
perꢀclockꢀcycle,ꢀ50%ꢀofꢀinputꢀdataꢀchangingꢀatꢀeveryꢀtransfer
IDD5
IDD6
IDD7
Autoꢀrefreshꢀcurrent;ꢀtRCꢀ=ꢀtRFC(min)
Selfꢀrefreshꢀcurrent;ꢀCKEꢀ0.2V
180 180
mA
mA
mA
8
8
Operatingꢀcurrentꢀforꢀfourꢀbankꢀoperation;ꢀfourꢀbankꢀinterleavingꢀ
READsꢀ(BL=4)ꢀwithꢀautoꢀprecharge;ꢀtRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min);ꢀ
AddressꢀandꢀcontrolꢀinputsꢀchangeꢀonlyꢀduringꢀACTIVE,ꢀREAD,ꢀorꢀ
WRITEꢀcommands;ꢀ50%ꢀofꢀdataꢀchangingꢀonꢀeveryꢀtransfer
430 370
22
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
IDD Specification Parameters and Test Conditions: x32
(Vddꢀ=ꢀVddqꢀ=ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-6),ꢀVddꢀ=ꢀVddqꢀ=ꢀ2.6Vꢀ±ꢀ0.1Vꢀ(-5)ꢀVssꢀ=ꢀVssQꢀ=ꢀ0V,ꢀOutputꢀOpen,ꢀunlessꢀotherwiseꢀnoted)
Symbol Parameter/ Test Condition
-5
-6 Units
IDD0
Operatingꢀcurrentꢀforꢀoneꢀbankꢀactive-precharge;ꢀtRCꢀ=ꢀtRC(min);ꢀ
170 150
mA
tCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀonceꢀperꢀclockꢀ
cycle; address and control inputs changing once every two clock
cycles; CS = high between valid commands.
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
Operatingꢀcurrentꢀforꢀoneꢀbankꢀoperation;ꢀoneꢀbankꢀopen,ꢀBLꢀ=ꢀ4,ꢀ
tRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min),ꢀIout=0mA,ꢀAddressꢀandꢀcontrolꢀ
inputs changing once per clock cycle.
195 170
mA
mA
mA
mA
mA
Precharge power-down standby current; all banks idle; power-down
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
35
30
60
35
80
Prechargeꢀfloatingꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀallꢀbanksꢀidle;ꢀCKEꢀ 75
VIH(min);ꢀtCKꢀ=ꢀtCK(min);ꢀaddressꢀandꢀotherꢀcontrolꢀinputsꢀchangingꢀ
onceꢀperꢀclockꢀcycle;ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀDM
Active power-down standby current; one bank active; power-down
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
35
Activeꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀCKEꢀVIH(min);ꢀoneꢀbankꢀ
active;ꢀtRCꢀ=ꢀtRAS(max);ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDQSꢀandꢀDMꢀinputsꢀ
changing twice per clock cycle; address and other control inputs
changing once per clock cycle
95
IDD4R
Operatingꢀcurrentꢀforꢀburstꢀread;ꢀburstꢀlengthꢀ=ꢀ2;ꢀreads;ꢀcontinuousꢀ
burst; one bank active; address and control inputs changing once per
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀ50%ꢀofꢀdataꢀchangingꢀonꢀeveryꢀtransfer;ꢀ
lOUTꢀ=ꢀ0mA
480 420
mA
mA
IDD4W Operatingꢀcurrentꢀforꢀburstꢀwrite;ꢀburstꢀlengthꢀ=ꢀ2;ꢀwrites;ꢀcontinuousꢀ 490 430
burst; one bank active address and control inputs changing once per
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀtwiceꢀ
perꢀclockꢀcycle,ꢀ50%ꢀofꢀinputꢀdataꢀchangingꢀatꢀeveryꢀtransfer
IDD5
IDD6
IDD7
Autoꢀrefreshꢀcurrent;ꢀtRCꢀ=ꢀtRFC(min);
Selfꢀrefreshꢀcurrent;ꢀCKEꢀ0.2V;
230 230
mA
mA
mA
4
4
Operatingꢀcurrentꢀforꢀfourꢀbankꢀoperation;ꢀfourꢀbankꢀinterleavingꢀ
READsꢀ(BL=4)ꢀwithꢀautoꢀprecharge;ꢀtRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min);ꢀ
AddressꢀandꢀcontrolꢀinputsꢀchangeꢀonlyꢀduringꢀACTIVE,ꢀREAD,ꢀorꢀ
WRITEꢀcommands;ꢀ50%ꢀofꢀdataꢀchangingꢀonꢀeveryꢀtransfer
590 560
Integrated Silicon Solution, Inc. ꢀ
23
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
AC TIMING REQUIREMENTS
AbsoluteꢀSpecificationsꢀ(VDD,ꢀVDDQꢀ=ꢀ+2.5Vꢀ±0.2ꢀV@-6;ꢀVDD,ꢀVDDQꢀ=ꢀ+2.6Vꢀ±0.1ꢀV@-5)ꢀ
PARAMETER
SYMBOL
-5
-6
UNITS
MIN
-0.7
-0.6
0.45
0.45
min
MAX
0.7
MIN
-0.7
-0.6
0.45
0.45
min
MAX
0.7
DQꢀoutputꢀaccessꢀtimeꢀforꢀCLK,/CLK
DQSꢀoutputꢀaccessꢀtimeꢀforꢀCLK,/CLK
CLKꢀhigh-levelꢀwidth
tAC
ns
ns
tDQSCK
tCH
0.6
0.6
0.55
0.55
–
0.55
0.55
–
tCK
tCK
ns
CLKꢀlow-levelꢀwidth
tCL
CLKꢀhalfꢀperiod
tHP
(tCL,tCH)
(tCL,tCH)
CLKꢀcycleꢀtimeꢀCL=3
tCK(3)
tCK(2.5)
tCK(2)
tDH
5
12
12
12
–
6
12
12
12
–
ns
ns
ns
ns
ns
ns
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCL=2.5
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCL=2
6
6
7.5
0.4
0.4
2.2
7.5
0.45
0.45
2.2
DQꢀandꢀDMꢀinputꢀholdꢀtimeꢀ
DQꢀandꢀDMꢀinputꢀsetupꢀtime
tDS
–
–
Controlꢀ&ꢀAddressꢀinputꢀpulseꢀwidthꢀ(forꢀeachꢀ
tIPW
–
–
input)
DQꢀandꢀDMꢀinputꢀpulseꢀwidthꢀ(forꢀeachꢀinput)
DQꢀ&ꢀDQSꢀhigh-impedanceꢀtimeꢀfromꢀCLK,/CLK
DQꢀ&ꢀDQSꢀlow--impedanceꢀtimeꢀfromꢀCLK,/CLK
tDIPW
tHZ
1.75
–
–
1.75
–
–
0.7
–
ns
ns
ns
ns
0.7
–
tLZ
-0.7
–
-0.7
–
DQS--DQꢀSkew,ꢀDQSꢀtoꢀlastꢀDQꢀvalid,ꢀperꢀgroup, tDQSQ
0.4
0.45
per access
DQ/DQSꢀoutputꢀholdꢀtimeꢀfromꢀDQS
tQH
tHP-tQHS
–
tHP-
–
ns
tQHS
DataꢀHoldꢀSkewꢀFactor
tQHS
–
0.5
1.28
–
–
0.55
1.28
–
ns
WriteꢀcommandꢀtoꢀfirstꢀDQSꢀlatchingꢀtransition
DQSꢀinputꢀhighꢀpulseꢀwidth
DQSꢀinputꢀlowꢀpulseꢀwidth
tDQSS
tDQSH
tDQSL
tDSS
0.72
0.35
0.35
0.2
0.2
2
0.75
0.35
0.35
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
ns
–
–
DQSꢀfallingꢀedgeꢀtoꢀCLKꢀsetupꢀtime
DQSꢀfallingꢀedgeꢀholdꢀtimeꢀfromꢀCLK
MODEꢀREGISTERꢀSETꢀcommandꢀcycleꢀtime
Write preamble setup time
–
–
tDSH
–
–
tMRD
–
–
tWPRES
tWPST
tWPRE
tIHF
0
–
0
–
Write postamble
0.4
0.25
0.6
0.6
–
0.4
0.25
0.75
0.6
–
tCK
tCK
ns
Write preamble
AddressꢀandꢀControlꢀinputꢀholdꢀtimeꢀ(fastꢀslewꢀ
–
–
rate)
AddressꢀandꢀControlꢀinputꢀsetupꢀtimeꢀ(fastꢀslewꢀ
tISF
tIH
0.6
0.7
0.7
–
–
–
0.75
0.8
–
-–
–
ns
ns
ns
rate)
AddressꢀandꢀControlꢀinputꢀholdꢀtimeꢀ(slowꢀslewꢀ
rate)
AddressꢀandꢀControlꢀinputꢀsetupꢀtimeꢀ(slowꢀslewꢀ tIS
0.8
rate)
Readꢀpreamble
tRPRE
0.9
0.4
40
1.1
0.6
0.9
0.4
42
1.1
0.6
tCK
tCK
ns
Readꢀpostamble
tRPST
tRAS
ACTIVEꢀtoꢀPRECHARGEꢀcommand
70,000
120,000
24
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
AC TIMING REQUIREMENTS
AbsoluteꢀSpecificationsꢀ(VDD,ꢀVDDQꢀ=ꢀ+2.5ꢀVꢀ±0.2ꢀV@-6;ꢀVDD,ꢀVDDQꢀ=ꢀ+2.6ꢀVꢀ±0.1ꢀV@-5)ꢀ
PARAMETER
SYMBOL
-5
-6
UNITS
MIN
MAX
MIN
MAX
ACTIVEꢀtoꢀACTIVE/AutoꢀRefreshꢀcommandꢀ
tRC
55
–ꢀ
60
–
ns
period
AutoꢀRefreshꢀtoꢀActive/Auto
tRFC
tRCD
tRP
70
15
15
15
10
15
–
–
72
15
15
15
12
15
–
–
ns
ns
ACTIVEꢀtoꢀREADꢀorꢀWRITEꢀdelay
PRECHARGEꢀcommandꢀperiod
–
–
ns
ActiveꢀtoꢀAutoprechargeꢀDelay
tRAP
tRRD
tWR
–
–
ns
ACTIVEꢀbankꢀAꢀtoꢀACTIVEꢀbankꢀBꢀcommand
Write recovery time
–
–
ns
–
–
ns
AutoꢀPrechargeꢀwriteꢀrecoveryꢀ+ꢀprechargeꢀtime
InternalꢀWriteꢀtoꢀReadꢀCommandꢀDelay
Exitꢀselfꢀrefreshꢀtoꢀnon-READ
tDAL
tWR+tRP
–
tWR+tRP
–
tCK
tCK
ns
tWTR
tXSNR
tXSRD
tREFI
tREFI
2
70
200
–
–
1
70
200
–
–
–
–
ExitꢀselfꢀrefreshꢀtoꢀREADꢀcommand
AverageꢀPeriodicꢀRefreshꢀInterval Ta ≤ 85 ºC
–
–
tCK
μs
7.8
1.95
7.8
1.95
AverageꢀPeriodicꢀRefreshꢀInterval Ta > 85 ºC,
–
–
μs
A2 only
Output Load Condition
VREF
DQS
V
TT=VREF
DQ
50
VREF
Ω
V
OUT
Zo=50
Ω
V
REF
30pF
OutputTiming
Measurement
ReferencePoint
Integrated Silicon Solution, Inc.
25
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
Notes
1.ꢀAllꢀvoltagesꢀreferencedꢀtoꢀVss.
2.ꢀTestsꢀforꢀACꢀtiming,ꢀIDD,ꢀandꢀelectrical,ꢀACꢀandꢀDCꢀcharacteristics,ꢀmayꢀbeꢀconductedꢀatꢀnominalꢀreference/supplyꢀvoltageꢀ
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3.ꢀACꢀtimingꢀandꢀIDDꢀtestsꢀmayꢀuseꢀaꢀVILꢀtoꢀVIHꢀswingꢀofꢀupꢀtoꢀ1.5Vꢀinꢀtheꢀtestꢀenvironment,ꢀbutꢀinputꢀtimingꢀisꢀstillꢀreferencedꢀtoꢀ
VREFꢀ(orꢀtoꢀtheꢀcrossingꢀpointꢀforꢀCK//CK),ꢀandꢀparameterꢀspecificationsꢀareꢀguaranteedꢀforꢀtheꢀspecifiedꢀACꢀinputꢀlevelsꢀun-
derꢀnormalꢀuseꢀconditions.ꢀTheꢀminimumꢀslewꢀrateꢀforꢀtheꢀinputꢀsignalsꢀisꢀ1V/nsꢀinꢀtheꢀrangeꢀbetweenꢀVIL(AC)ꢀandꢀVIH(AC).
4.ꢀTheꢀACꢀandꢀDCꢀinputꢀlevelꢀspecificationsꢀareꢀasꢀdefinedꢀinꢀtheꢀSSTL_2ꢀStandardꢀ(i.e.ꢀtheꢀreceiverꢀwillꢀeffectivelyꢀswitchꢀasꢀaꢀ
result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above
(below)ꢀtheꢀDCꢀinputꢀLOWꢀ(HIGH)ꢀlevel.
5.ꢀVREFꢀisꢀexpectedꢀtoꢀbeꢀequalꢀtoꢀ0.5*VddQꢀofꢀtheꢀtransmittingꢀdevice,ꢀandꢀtoꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀtheꢀsame.ꢀ
Peak-to-peakꢀnoiseꢀonꢀVREFꢀmayꢀnotꢀexceedꢀ+2%ꢀofꢀtheꢀDCꢀvalue.
6.ꢀVTTꢀisꢀnotꢀappliedꢀdirectlyꢀtoꢀtheꢀdevice.ꢀVTTꢀisꢀaꢀsystemꢀsupplyꢀforꢀsignalꢀterminationꢀresistors,ꢀisꢀexpectedꢀtoꢀbeꢀsetꢀequalꢀtoꢀ
VREF,ꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀVREF.
7.ꢀVIDꢀisꢀtheꢀmagnitudeꢀofꢀtheꢀdifferenceꢀbetweenꢀtheꢀinputꢀlevelꢀonꢀCLKꢀandꢀtheꢀinputꢀlevelꢀonꢀ/CLK.
8.ꢀTheꢀvalueꢀofꢀVIXꢀisꢀexpectedꢀtoꢀequalꢀ0.5*VddQꢀofꢀtheꢀtransmittingꢀdeviceꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀtheꢀ
same.
9.ꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
10.ꢀIDDꢀspecificationsꢀareꢀtestedꢀafterꢀtheꢀdeviceꢀisꢀproperlyꢀinitialized.
11.ꢀThisꢀparameterꢀisꢀsampled.ꢀVddqꢀ=ꢀ2.5V,ꢀVddꢀ=ꢀ2.5V,ꢀfꢀ=ꢀ100ꢀMHz,ꢀTaꢀ=ꢀ25oC,ꢀVOUT(DC)ꢀ=ꢀVddQ/2,ꢀVOUT(PEAKꢀTOꢀPEAK)ꢀ
=ꢀ25mV.ꢀDMꢀinputsꢀareꢀgroupedꢀwithꢀI/Oꢀpinsꢀ-ꢀreflectingꢀtheꢀfactꢀthatꢀtheyꢀareꢀmatchedꢀinꢀloadingꢀ(toꢀfacilitateꢀtraceꢀmatchingꢀ
at the board level).
12.ꢀTheꢀCLK//CLKꢀinputꢀreferenceꢀlevelꢀ(forꢀtimingꢀreferencedꢀtoꢀCLK//CLK)ꢀisꢀtheꢀpointꢀatꢀwhichꢀCLKꢀandꢀ/CLKꢀcross;ꢀtheꢀinputꢀ
referenceꢀlevelꢀforꢀsignalsꢀotherꢀthanꢀCLK//CLK,ꢀisꢀVREF.
13.ꢀInputsꢀareꢀnotꢀrecognizedꢀasꢀvalidꢀuntilꢀVREFꢀstabilizes.ꢀException:ꢀduringꢀtheꢀperiodꢀbeforeꢀVREFꢀstabilizes,ꢀCKE<ꢀ0.3VddQꢀ
isꢀrecognizedꢀasꢀLOW.
14.ꢀtHZꢀandꢀtLZꢀtransitionsꢀoccurꢀinꢀtheꢀsameꢀaccessꢀtimeꢀwindowsꢀasꢀvalidꢀdataꢀtransitions.ꢀTheseꢀparametersꢀareꢀnotꢀrefer-
encedꢀtoꢀaꢀspecificꢀvoltageꢀlevel,ꢀbutꢀspecifyꢀwhenꢀtheꢀdeviceꢀoutputꢀisꢀnoꢀlongerꢀdrivingꢀ(HZ),ꢀorꢀbeginsꢀdrivingꢀ(LZ).
15.ꢀTheꢀmaximumꢀlimitꢀforꢀthisꢀparameterꢀisꢀnotꢀaꢀdeviceꢀlimit.ꢀTheꢀdeviceꢀwillꢀoperateꢀwithꢀaꢀgreaterꢀvalueꢀforꢀthisꢀparameter,ꢀbutꢀ
systemꢀperformanceꢀ(busꢀturnaround)ꢀwillꢀdegradeꢀaccordingly.
16.ꢀTheꢀspecificꢀrequirementꢀisꢀthatꢀDQSꢀbeꢀvalidꢀ(HIGH,ꢀLOW,ꢀorꢀatꢀsomeꢀpointꢀonꢀaꢀvalidꢀtransition)ꢀonꢀorꢀbeforeꢀthisꢀCLKꢀ
edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes
wereꢀpreviouslyꢀinꢀprogressꢀonꢀtheꢀbus,ꢀDQSꢀwillꢀbeꢀtransitioningꢀfromꢀHigh-ZꢀtoꢀlogicꢀLOW.ꢀIfꢀaꢀpreviousꢀwriteꢀwasꢀinꢀprog-
ress,ꢀDQSꢀcouldꢀbeꢀHIGH,ꢀLOW,ꢀorꢀtransitioningꢀfromꢀHIGHꢀtoꢀLOWꢀatꢀthisꢀtime,ꢀdependingꢀonꢀtDQSS.
17.ꢀAꢀmaximumꢀofꢀeightꢀAUTOꢀREFRESHꢀcommandsꢀcanꢀbeꢀpostedꢀtoꢀanyꢀgivenꢀDDRꢀSDRAMꢀdevice.
18.ꢀtXPRDꢀshouldꢀbeꢀ200ꢀtCLKꢀinꢀtheꢀconditionꢀofꢀtheꢀunstableꢀCLKꢀoperationꢀduringꢀtheꢀpowerꢀdownꢀmode.
19.ꢀForꢀcommand/addressꢀandꢀCKꢀ&ꢀ/CKꢀslewꢀrateꢀ>ꢀ1.0V/ns.
20.ꢀMinꢀ(tCL,tCH)ꢀrefersꢀtoꢀtheꢀsmallerꢀofꢀtheꢀactualꢀclockꢀlowꢀtimeꢀandꢀtheꢀactualꢀclockꢀhighꢀtimeꢀasꢀprovidedꢀtoꢀtheꢀdevice.
26
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
OUTPUT SLEW RATE CHARACTERISTICS
Slew Rate Characteristic
Typical Range
(V/ns)
Min
(V/ns) (V/ns)
Max
PullupꢀSlewꢀRate
1.2-2.5
1.2-2.5
0.7
0.7
5.0
5.0
PulldownꢀSlewꢀRate
AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS AND CONTROL PINS
Parameter
Peak amplitude allowed for overshoot
Peak amplitude allowed for undershoot
AreaꢀbetweenꢀtheꢀovershootꢀsignalꢀandꢀVDDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
AreaꢀbetweenꢀtheꢀundershootꢀsignalꢀandꢀGNDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
Max
Units
V
V
V-ns
V-ns
1.5
1.5
4.5
4.5
+5
+4
Max. amplitude = 1.5 V
Overshoot
+3
V
DD
+2
+1
0
Volts
(V)
Ground
-1
-2
-3
Undershoot
Max. area = 4.5 V-ns
0
1
2
3
4
5
6
Time (ns)
AddressꢀandꢀControlꢀACꢀOvershootꢀandꢀUndershootꢀDefinition
OVERSHOOT/UNDERSHOOT SPECIFICATION FOR DATA, STROBE, AND MASK PINS
Parameter
Peak amplitude allowed for overshoot
Peak amplitude allowed for undershoot
AreaꢀbetweenꢀtheꢀovershootꢀsignalꢀandꢀVDDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
AreaꢀbetweenꢀtheꢀundershootꢀsignalꢀandꢀGNDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
Max
1.2
1.2
2.4
2.4
Units
V
V
V-ns
V-ns
+5
+4
Max. amplitude = 1.2 V
Overshoot
+3
V
DD
+2
+1
0
Volts
(V)
Ground
-1
-2
-3
Undershoot
Max. area = 2.4 V--ns
0
1
2
3
4
5
6
Time (ns)
DQ/DM/DQSꢀACꢀOvershootꢀandꢀUndershootꢀDefinition
Integrated Silicon Solution, Inc. ꢀ
27
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
64Mx8 ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
ꢀꢀ ꢀ
5ꢀ
ꢀ
ꢀ
IS43R86400D-5BLꢀ
IS43R86400D-5Bꢀ
IS43R86400D-5TLꢀ
60-ballꢀBGA,ꢀLead-freeꢀ
60-ballꢀBGAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS43R86400D-6BLꢀ
IS43R86400D-6TLꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
Industrial Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS43R86400D-5BLIꢀ
IS43R86400D-5TLIꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
ꢀ ꢀ
6ꢀ
ꢀ
ꢀ
IS43R86400D-6BLIꢀ
IS43R86400D-6BIꢀ
IS43R86400D-6TLIꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
60-ballꢀBGAꢀ
ꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
Automotive (A1) Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS46R86400D-6BLA1ꢀ
IS46R86400D-6TLA1ꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
28
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
32Mx16 ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS43R16320D-5BLꢀ
IS43R16320D-5TLꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS43R16320D-6BLꢀ
IS43R16320D-6TLꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
Industrial Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS43R16320D-5BLIꢀ
IS43R16320D-5TLIꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
ꢀ ꢀ
6ꢀ
ꢀ
ꢀ
IS43R16320D-6BLIꢀ
IS43R16320D-6BIꢀ
IS43R16320D-6TLIꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
60-ballꢀBGAꢀ
ꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
Automotive (A1) Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS46R16320D-5BLA1ꢀ
IS46R16320D-5TLA1ꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS46R16320D-6BLA1ꢀ
IS46R16320D-6TLA1ꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
Automotive (A2) Range: -40°C to +105°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS46R16320D-6BLA2ꢀ
IS46R16320D-6TLA2ꢀ
60-ballꢀBGA,ꢀLead-freeꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
Note: Contact ISSI for leaded parts support.
Integrated Silicon Solution, Inc. ꢀ
29
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
16Mx32 ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Package
ꢀꢀ 200ꢀMHzꢀ
ꢀ 166ꢀMHzꢀ
5ꢀ
6ꢀ
IS43R32160D-5BLꢀ
IS43R32160D-6BLꢀ
144-ballꢀFBGA,ꢀLead-free
144-ballꢀFBGA,ꢀLead-freeꢀ
Industrial Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ 200ꢀMHzꢀ
ꢀ 166ꢀMHzꢀ
5ꢀ
6ꢀ
IS43R32160D-5BLIꢀ
IS43R32160D-6BLIꢀ
144-ballꢀFBGA,ꢀLead-free
144-ballꢀFBGA,ꢀLead-freeꢀ
Automotive (A1) Range: -40°C to +85°C
Frequency Speed (ns)
ꢀ 166ꢀMHzꢀ 6ꢀ
Order Part No.
Package
IS46R32160D-6BLA1ꢀ
144-ballꢀFBGA,ꢀLead-freeꢀ
Automotive (A2) Range: -40°C to +105°C
Frequency Speed (ns)
ꢀ 166ꢀMHzꢀ 6ꢀ
Order Part No.
Package
IS46R32160D-6BLA2ꢀ
144-ballꢀFBGA,ꢀLead-freeꢀ
30
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
Integrated Silicon Solution, Inc. ꢀ
31
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
Mini Ball Grid Array
Package Code: B (60-Ball) 8mm x 13mm
32
Integrated Silicon Solution, Inc.
Rev. D
05/18/2015
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
Integrated Silicon Solution, Inc. ꢀ
33
Rev. D
05/18/2015
相关型号：
IS43R16320D-6TLI-TR
Cache DRAM Module, 32MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, TSOP2-66
ISSI
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