IS43R83200D-6TL [ISSI]
8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM; 8Mx32 ， 16Mx16 ， 32Mx8 256Mb的DDR SDRAM
| 型号： | IS43R83200D-6TL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM |
| 文件： | 总32页 (文件大小：1097K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS43R83200D
IS43/46R16160D, IS43/46R32800D
8Mx32,ꢀ16Mx16,ꢀ32Mx8ꢀ
256MbꢀDDRꢀSDRAM
JUNEꢀ2012
ꢀ
FEATURES
DEVICEꢀOVERVIEW
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ ꢀ0.2Vꢀ
•ꢀ SSTL_2ꢀcompatibleꢀI/O
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
perꢀclockꢀcycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
receivedꢀwithꢀdata,ꢀtoꢀbeꢀusedꢀinꢀcapturingꢀdataꢀ
atꢀtheꢀreceiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ
transitions
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀdataꢀ
andꢀdataꢀmaskꢀreferencedꢀtoꢀbothꢀedgesꢀofꢀDQS
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
ISSI’sꢀ256-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ
transferꢀusingꢀpipelineꢀarchitectureꢀandꢀtwoꢀdataꢀwordꢀ
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ268,435,456-bitꢀmemoryꢀ
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ64Mbꢀtoꢀ
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ
andꢀWriteꢀburstꢀaccessesꢀtoꢀbeꢀvirtuallyꢀcontinuous,ꢀwithꢀ
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ
programmableꢀfeaturesꢀofꢀburstꢀlength,ꢀburstꢀsequenceꢀ
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
atꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀofꢀdataꢀstrobe
ADDRESSꢀTABLE
Parameter
8Mꢀxꢀ32
16Mꢀxꢀ16
32Mꢀxꢀ8
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrecharge
Configuration 2Mꢀxꢀ32ꢀxꢀ4ꢀ
banks
4Mꢀxꢀ16ꢀxꢀ4ꢀꢀ 8Mꢀxꢀ8ꢀxꢀ4ꢀꢀ
banks
banks
BankꢀAddressꢀ BA0,ꢀBA1
Pins
BA0,ꢀBA1
BA0,ꢀBA1
Autoprechargeꢀ A8/AP
Pins
A10/AP
A10/AP
•ꢀ TRASꢀLockoutꢀsupportedꢀ(tRAPꢀ=ꢀtRCD)
RowꢀAddress 4K(A0ꢀ–ꢀA11) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
OPTIONS
Columnꢀ
Address
512(A0ꢀ–ꢀA7,ꢀ 512(A0ꢀ–ꢀA8) 1K(A0ꢀ–ꢀA9)
A9)
•ꢀ Configuration(s):ꢀ8Mx32,ꢀ16Mx16,ꢀ32Mx8
•ꢀ Package(s):ꢀ
ꢀ 144ꢀBallꢀBGAꢀ(x32)
RefreshꢀCountꢀ
ꢀ
ꢀ
ꢀ
Com./Ind./A1ꢀ 4Kꢀ/ꢀ64msꢀ
A2 4Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64msꢀ
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
ꢀ
66-pinꢀTSOP-IIꢀ(x8,ꢀx16)ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)
•ꢀ Lead-freeꢀpackageꢀavailable
•ꢀ TemperatureꢀRange:ꢀ
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)
KEYꢀTIMINGꢀPARAMETERS
SpeedꢀGradeꢀ
-5ꢀ
-6ꢀ
ꢀUnitsꢀ
ꢀ
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)ꢀ
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)ꢀ
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
F
F
F
CkꢀMaxꢀCLꢀ=ꢀ3ꢀ
CkꢀMaxꢀCLꢀ=ꢀ2.5ꢀ
CkꢀMaxꢀCLꢀ=ꢀ2ꢀ
200ꢀ
200ꢀ
133ꢀ
167ꢀ
167ꢀ
133ꢀ
ꢀ MHz
ꢀ MHz
ꢀ MHz
Copyrightꢀ©ꢀ2012ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. ꢀ
1
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
FUNCTIONAL BLOCK DIAGRAM (x32)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
DM0-DM3
I/O 0-31
4
DATA IN
BUFFER
&
CLOCK
GENERATOR
32
32
REFRESH
CONTROLLER
DQS0-DQS3
Mode Registers and
Ext. Mode Registers
4
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
CONTROLLER
14
32
32
A11
A10
A9
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
A3
A2
4096
4096
12
MEMORY CELL
ARRAY
4096
4096
12
A1
BANK 0
ROW
A0
ROW
ADDRESS
LATCH
BA0
BA1
ADDRESS
BUFFER
12
12
12
SENSE AMP I/O GATE
2
512
(x 32)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
FUNCTIONAL BLOCK DIAGRAM (x16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
LDM, UDM
2
DATA IN
BUFFER
&
CLOCK
GENERATOR
16
16
I/O 0-15
REFRESH
CONTROLLER
LDQS, UDQS
Mode Registers and
Ext. Mode Registers
2
VDD/VDDQ
Vss/VssQ
SELF
DATA OUT
BUFFER
REFRESH
A12
A11
A10
A9
CONTROLLER
15
16
16
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
A3
A2
8192
8192
13
MEMORY CELL
ARRAY
8192
8192
13
A1
BANK 0
ROW
A0
ROW
ADDRESS
LATCH
BA0
BA1
ADDRESS
BUFFER
13
13
13
SENSE AMP I/O GATE
2
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
Integrated Silicon Solution, Inc. ꢀ
3
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
PIN CONFIGURATIONS
66ꢀpinꢀTSOPꢀ-ꢀTypeꢀIIꢀꢀforꢀx8
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC
DQ4
V
SS
Q
VDDQ
NC
NC
DDQ
NC
NC
NC
NC
V
V
SSQ
DQS
NC
VDD
NC
VREF
VSS
DM
CK
NC
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PINꢀDESCRIPTION:ꢀx8
A0-A12ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
DMꢀꢀ
DataꢀWriteꢀMask
A0-A9
DQS
DataꢀStrobe
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ7ꢀ
CK,ꢀCKꢀ
CKEꢀ
VDDꢀ
VDDQꢀ
VSSꢀ
VSSQꢀ
VREF
NCꢀ
Power
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
SystemꢀClockꢀInput
ClockꢀEnable
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
NoꢀConnection
CSꢀ
ChipꢀSelect
CASꢀ
ColumnꢀAddressꢀStrobeꢀ
Command
RASꢀ
WEꢀ
RowꢀAddressꢀStrobeꢀ
Command
WriteꢀEnable
4ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
PINꢀCONFIGURATION
PackageꢀCodeꢀB:ꢀ60-ballꢀFBGAꢀ(topꢀview)ꢀforꢀx8
(8mmꢀxꢀ13mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
TopꢀView
(BallsꢀseenꢀthroughꢀtheꢀꢀPackage)
: Ball Existing
: Depopulated Ball
1
2
3
7
8
9
Top View
(See the balls through the Package)
VSSQ DQ7
VSS
VDD
DQ0 VDDQ
A
B
C
D
1
2 3 6 7 8 9
4 5
NC
NC
VDDQ DQ6
VSSQ DQ5
DQ1 VSSQ
DQ2 VDDQ
NC
NC
NC
NC
A
B
C
D
E
F
NC
VDDQ DQ4
DQ3 VSSQ
DQS
NC
VSSQ
NC
NC
VDDQ
VDD
CAS
CS
E
F
VREF
DM
NC
VSS
CK
CKE
A9
WE
RAS
BA1
CK
A12
A11
A8
G
H
J
G
H
J
BA0
K
L
A7
A0 A10/AP
K
A6
A4
A5
A2
A1
A3
L
M
VSS
VDD
M
BGA Package Ball Pattern
Top View
x8 Device Ball Pattern
PINꢀDESCRIPTION:ꢀx8
A0-A12
A0-A9
RowꢀAddressꢀInput
DQS
DataꢀStrobe
Power
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
VDDꢀ
VDDQꢀ
VSSꢀ
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ7
CK,ꢀCKꢀ
CKEꢀ
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
SystemꢀClockꢀInput
ClockꢀEnable
VSSQꢀ
VREF
NCꢀ
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
NoꢀConnection
CSꢀ
ChipꢀSelect
CASꢀ
ColumnꢀAddressꢀStrobeꢀ
Command
RASꢀ
WEꢀ
DMꢀ
RowꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
DataꢀWriteꢀMask
Integrated Silicon Solution, Inc. ꢀ
5
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
PIN CONFIGURATIONS
66ꢀpinꢀTSOPꢀ-ꢀTypeꢀIIꢀꢀforꢀx16
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
NC
DQ8
NC
V
DDQ
LDQS
NC
VSSQ
UDQS
NC
VDD
NC
VREF
VSS
UDM
CK
LDM
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PINꢀDESCRIPTION:ꢀx16
A0-A12ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
LDM,ꢀUDMꢀꢀ
DataꢀWriteꢀMask
A0-A8ꢀ
LDQS,ꢀUDQS
VDDꢀ
DataꢀStrobe
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ15ꢀ
CK,ꢀCKꢀ
CKEꢀ
Power
VDDQꢀ
VSSꢀ
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
SystemꢀClockꢀInput
ClockꢀEnable
VSSQꢀ
VREF
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
NoꢀConnection
CSꢀ
ChipꢀSelect
CASꢀ
ColumnꢀAddressꢀStrobeꢀ
Command
NCꢀ
RASꢀ
WEꢀ
RowꢀAddressꢀStrobeꢀ
Command
WriteꢀEnable
6ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
PINꢀCONFIGURATION
PackageꢀCodeꢀB:ꢀ60-ballꢀFBGAꢀ(topꢀview)ꢀforꢀx16
(8mmꢀxꢀ13mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
TopꢀView
(BallsꢀseenꢀthroughꢀtheꢀꢀPackage)
: Ball Existing
: Depopulated Ball
1
2
3
7
8
9
Top View
(See the balls through the Package)
VSSQ DQ15
VSS
VDD
DQ0 VDDQ
A
B
C
D
1
2 3 6 7 8 9
4 5
DQ14 VDDQ DQ13
DQ12 VSSQ DQ11
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
A
B
C
D
E
F
DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
DQ8 VSSQ UDQS
VREF
E
F
NC
VSS
UDM
CK
LDM
WE
VDD
CAS
CS
CK
A12
A11
A8
G
H
J
G
H
J
RAS
BA1
CKE
A9
BA0
K
L
A7
A0 A10/AP
K
A6
A4
A5
A2
A1
A3
L
M
VSS
VDD
M
BGA Package Ball Pattern
Top View
x16 Device Ball Pattern
PINꢀDESCRIPTION:ꢀx16
A0-A12
A0-A8
RowꢀAddressꢀInput
LDQS,ꢀUDQSꢀ
DataꢀStrobe
Power
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
VDDꢀ
VDDQꢀ
VSSꢀ
BA0,ꢀBA1ꢀ
DQ0ꢀ–ꢀDQ15ꢀ
CK,ꢀCKꢀ
CKEꢀ
PowerꢀSupplyꢀforꢀI/OꢀPins
Ground
SystemꢀClockꢀInput
ClockꢀEnable
VSSQꢀ
VREF
NCꢀ
GroundꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
NoꢀConnection
CSꢀ
ChipꢀSelect
CASꢀ
ColumnꢀAddressꢀStrobeꢀ
Command
RASꢀ
RowꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
WEꢀ
LDM,ꢀUDMꢀ
DataꢀWriteꢀMask
Integrated Silicon Solution, Inc. ꢀ
7
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
PINꢀCONFIGURATION
PackageꢀCodeꢀB:ꢀ144-ballꢀFBGAꢀ(topꢀview)
(12mmꢀxꢀ12mmꢀBody,ꢀ0.8mmꢀBallꢀPitch)
TopꢀViewꢀ(Ballsꢀseenꢀthroughꢀtheꢀpackage)
1 2 3 4 5 6 7 8 9 10 11 12
A
B
C
D
E
F
DQ28 VSSQ DM3 DQS3
VDDQ NC VDDQ DQ27
VSSQ VSSQ DQ26 DQ25
VSS VDD VDDQ DQ24
VSSQ VDDQ DQ15 DQ14
VSSQ VDDQ DQ13 DQ12
DQ2 DQ0 DQ31 DQ29
DQ1 VDDQ VDDQ DQ30
VSSQ VDD VDD VSSQ
VSSQ VSS VSS VSSQ
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
DQS0 DM0 VSSQ DQ3
DQ4 VDDQ NC VDDQ
DQ6 DQ5 VSSQ VSSQ
DQ7 VDDQ VDD VSS
DQ17 DQ16 VDDQ VSSQ
DQ19 DQ18 VDDQ VSSQ
G
H
J
VSSQ NC
DM1 DQS1
DQS2 DM2
NC VSSQ
VSSQ VDDQ DQ11 DQ10
VSSQ VDDQ DQ9 DQ8
DQ21 DQ20 VDDQ VSSQ
DQ22 DQ23 VDDQ VSSQ
K
L
NC
NC
A10 VDD VDD
NC
A5
A6
VSS VDD
NC
CAS
RAS
CS
WE VDD VSS
CK
A8
CK
NC
BA1
A0
A2
A1
A11
A3
A9
A4
NC
A7
NC
NC
M
CKE VREF
BA0
Note:ꢀVssꢀballsꢀinsideꢀtheꢀdottedꢀboxꢀareꢀoptionalꢀforꢀpurposesꢀofꢀthermalꢀdissipation.
PINꢀDESCRIPTION:ꢀforꢀx32
A0-A11
A0-A7,ꢀA9
BA0,ꢀBA1
DQ0ꢀ–ꢀDQ31
CK,ꢀCK
CKE
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
WE
WriteꢀEnable
DM0-DM3
DQS0-DQS3
VDD
DataꢀWriteꢀMask
DataꢀStrobeꢀ
Power
SystemꢀClockꢀInput
ClockꢀEnable
VDDQ
VREF
VSS
PowerꢀSupplyꢀforꢀI/OꢀPins
SSTL_2ꢀreferenceꢀvoltage
Ground
CS
ChipꢀSelect
CAS
ColumnꢀAddressꢀStrobeꢀ
Command
VSSQ
NC
GroundꢀforꢀI/OꢀPins
NoꢀConnection
RAS
RowꢀAddressꢀStrobeꢀ
Command
8ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
PINꢀFUNCTIONALꢀDESCRIPTIONS
Symbol
Type Description
CK,ꢀCK
Input Clock:ꢀCKꢀandꢀCKꢀareꢀdifferentialꢀclockꢀinputs.ꢀAllꢀaddressꢀandꢀcontrolꢀinputꢀsignalsꢀareꢀsampledꢀ
onꢀtheꢀcrossingꢀofꢀtheꢀpositiveꢀedgeꢀofꢀCKꢀandꢀnegativeꢀedgeꢀofꢀCK.ꢀInputꢀandꢀoutputꢀdataꢀisꢀ
referencedꢀtoꢀtheꢀcrossingꢀofꢀCKꢀandꢀCKꢀ(bothꢀdirectionsꢀofꢀcrossing).ꢀInternalꢀclockꢀsignalsꢀareꢀ
derivedꢀfromꢀCK/ꢀCK.
CKE
Input ClockꢀEnable:ꢀCKEꢀHIGHꢀactivates,ꢀandꢀCKEꢀLOWꢀdeactivatesꢀinternalꢀclockꢀsignals,ꢀandꢀdeviceꢀ
inputꢀbuffersꢀandꢀoutputꢀdrivers.ꢀTakingꢀCKEꢀLOWꢀprovidesꢀPRECHARGEꢀPOWER-DOWNꢀandꢀ
SELFꢀREFRESHꢀoperationꢀ(allꢀbanksꢀidle),ꢀorꢀACTIVEꢀPOWERDOWNꢀ(rowꢀACTIVEꢀinꢀanyꢀ
bank).ꢀCKEꢀisꢀsynchronousꢀforꢀallꢀfunctionsꢀexceptꢀforꢀSELFꢀREFRESHꢀEXIT,ꢀwhichꢀisꢀachievedꢀ
asynchronously.ꢀInputꢀbuffers,ꢀexcludingꢀCK,ꢀCKꢀandꢀCKE,ꢀareꢀdisabledꢀduringꢀpower-downꢀandꢀ
selfꢀrefreshꢀmodeꢀwhichꢀareꢀcontrivedꢀforꢀlowꢀstandbyꢀpowerꢀconsumption.
CS
Input ChipꢀSelect:ꢀCSꢀenablesꢀ(registeredꢀLOW)ꢀandꢀdisablesꢀ(registeredꢀHIGH)ꢀtheꢀcommandꢀ
decoder.ꢀAllꢀcommandsꢀareꢀmaskedꢀwhenꢀCSꢀisꢀregisteredꢀHIGH.ꢀCSꢀprovidesꢀforꢀexternalꢀbankꢀ
selectionꢀonꢀsystemsꢀwithꢀmultipleꢀbanks.ꢀCSꢀisꢀconsideredꢀpartꢀofꢀtheꢀcommandꢀcode.
Input CommandꢀInputs:ꢀRAS,ꢀCASꢀandꢀWEꢀ(alongꢀwithꢀCS)ꢀdefineꢀtheꢀcommandꢀbeingꢀentered.
RAS,ꢀCAS,ꢀ
WE
DM:ꢀx8;ꢀꢀ
LDM,ꢀUDM:ꢀ
x16;ꢀꢀ
Input InputꢀDataꢀMask:ꢀDMꢀisꢀanꢀinputꢀmaskꢀsignalꢀforꢀwriteꢀdata.ꢀInputꢀdataꢀisꢀmaskedꢀwhenꢀDMꢀisꢀ
sampledꢀHIGHꢀalongꢀwithꢀthatꢀinputꢀdataꢀduringꢀaꢀWRITEꢀaccess.ꢀDMꢀisꢀsampledꢀonꢀbothꢀedgesꢀ
ofꢀDQS.ꢀAlthoughꢀDMꢀpinsꢀareꢀinput-only,ꢀtheꢀDMꢀloadingꢀmatchesꢀtheꢀDQꢀandꢀDQSꢀloading.
DM0-DM3:ꢀ
x32
Forꢀx16ꢀdevices,ꢀLDMꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀUDMꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15.
Forꢀx32ꢀdevices,ꢀDM0ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀDM1ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15,ꢀDM2ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ16-DQ23,ꢀandꢀDM3ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ24-DQ31.
BA0,ꢀBA1
Aꢀ[12:0]
Input InputꢀBankꢀAddressꢀInputs:ꢀBA0ꢀandꢀBA1ꢀdefineꢀtoꢀwhichꢀbankꢀanꢀACTIVE,ꢀREAD,ꢀWRITEꢀorꢀ
PRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
Input AddressꢀInputs:ꢀprovideꢀtheꢀrowꢀaddressꢀforꢀACTIVEꢀcommands,ꢀandꢀtheꢀcolumnꢀaddressꢀandꢀ
AUTOꢀPRECHARGEꢀbitꢀforꢀREADꢀ/ꢀWRITEꢀcommands,ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀofꢀtheꢀmemoryꢀ
arrayꢀinꢀtheꢀrespectiveꢀbank.ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀopcodeꢀduringꢀaꢀMODEꢀ
REGISTERꢀSETꢀcommand.ꢀA12ꢀisꢀnotꢀusedꢀforꢀx32.
DQ:ꢀ
DQ0-DQ7:ꢀx8;ꢀ
DQ0-DQ15:ꢀ
x16ꢀ
I/O
DataꢀBus:ꢀInputꢀ/ꢀOutput
DQ0-DQ31:ꢀ
x32
DQS:ꢀx8:
I/O
DataꢀStrobe:ꢀOutputꢀwithꢀreadꢀdata,ꢀinputꢀwithꢀwriteꢀdata.ꢀEdge-alignedꢀwithꢀreadꢀdata,ꢀcenteredꢀ
withꢀwriteꢀdata.ꢀUsedꢀtoꢀcaptureꢀwriteꢀdata.
LDQS,ꢀUDQSꢀ
x16:ꢀꢀ
DQS0-DQS3:ꢀ
x32
Forꢀx16ꢀdevice,ꢀLDQSꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀUDQSꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15.
Forꢀx32ꢀdevice,ꢀDQS0ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ0-DQ7,ꢀDQS1ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀ
DQ8-DQ15,ꢀDQS2ꢀcorrespondsꢀtoꢀtheꢀdataꢀonꢀDQ16-DQ23,ꢀandꢀDQS3ꢀcorrespondsꢀtoꢀtheꢀdataꢀ
onꢀDQ24-DQ31.
NC
--
NoꢀConnect:ꢀShouldꢀbeꢀleftꢀunconnected.
VREF
VDDQ
VSSQ
VDD
Supply SSTL_2ꢀreferenceꢀvoltage.
Supply I/OꢀPowerꢀSupply.
Supply I/OꢀGround.
Supply PowerꢀSupply.
Supply Ground.
VSS
Integrated Silicon Solution, Inc. ꢀ
9
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
COMMANDSꢀTRUTHꢀTABLES
Allꢀcommandsꢀ(addressꢀandꢀcontrolꢀsignals)ꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀclockꢀ(crossingꢀofꢀCKꢀgoingꢀhighꢀ
andꢀCKꢀgoingꢀlow).ꢀTruthꢀTableꢀshowsꢀbasicꢀtimingꢀparametersꢀforꢀallꢀcommands.ꢀ
TRUTHꢀTABLEꢀ-ꢀCOMMANDS
NAMEꢀ(FUNCTION)ꢀ
CS
H
L
RAS CAS WE
BA
X
AP
X
Address Notes
DESELECTꢀ(NOP)ꢀ
X
H
L
X
H
H
L
X
H
H
H
X
X
2
2
NOꢀOPERATIONꢀ(NOP)ꢀ
ACTIVEꢀ(selectꢀbankꢀandꢀactivateꢀrow)ꢀ
X
X
L
Valid
Valid
X
Row
Column
READꢀ(selectꢀbankꢀandꢀcolumnꢀandꢀstartꢀreadꢀ
burst)ꢀ
L
H
L
READꢀwithꢀAPꢀ(readꢀburstꢀwithꢀAutoꢀPrecharge)ꢀ
L
L
H
H
L
L
H
L
Valid
Valid
H
L
Column
Column
3
3
WRITEꢀ(selectꢀbankꢀandꢀcolumnꢀandꢀstartꢀwriteꢀ
burst)ꢀ
WRITEꢀwithꢀAPꢀ(writeꢀburstꢀwithꢀAutoꢀ
Precharge)ꢀ
L
H
L
L
Valid
H
Column
BURSTꢀTERMINATE
L
L
H
L
H
H
L
L
X
X
L
X
X
4
5
PRECHARGEꢀ(deactivateꢀrowꢀinꢀselectedꢀ
bank)ꢀ
Valid
PRECHARGEꢀALLꢀ(deactivateꢀrowsꢀinꢀallꢀ
banks)ꢀ
L
L
H
L
X
H
X
X
X
5
AUTOꢀREFRESHꢀorꢀenterꢀSELFꢀREFRESHꢀ
MODEꢀREGISTERꢀSETꢀ
L
L
L
L
L
L
H
L
X
6,7,8
9
Valid
Op-code
Notes:
1.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
2.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
3.ꢀ Autoprechargeꢀisꢀnon-persistent.ꢀAPꢀHighꢀenablesꢀAutoꢀPrecharge,ꢀwhileꢀAPꢀLowꢀdisablesꢀAutoprecharge.
4.ꢀ BurstꢀTerminateꢀappliesꢀtoꢀonlyꢀReadꢀburstsꢀwithꢀAutoꢀPrechargeꢀdisabled.ꢀThisꢀcommandꢀisꢀundefinedꢀandꢀshouldꢀnotꢀbeꢀ
usedꢀforꢀReadꢀwithꢀAutoꢀPrechargeꢀenabled,ꢀandꢀforꢀWriteꢀbursts.
5.ꢀ IfꢀAPꢀisꢀLow,ꢀbankꢀaddressꢀdeterminesꢀwhichꢀbankꢀisꢀtoꢀbeꢀprecharged.ꢀIfꢀAPꢀisꢀHigh,ꢀallꢀbanksꢀareꢀprechargedꢀandꢀBA0-
BA1areꢀdon’tꢀcare.
6.ꢀ ThisꢀcommandꢀisꢀAUTOꢀREFRESHꢀifꢀCKEꢀisꢀHigh,ꢀandꢀSELFꢀREFRESHꢀifꢀCKEꢀisꢀlow.
7.ꢀ AllꢀaddressꢀinputsꢀandꢀI/Oꢀareꢀ‘don'tꢀcare’ꢀexceptꢀforꢀCKE.ꢀInternalꢀrefreshꢀcountersꢀcontrolꢀbankꢀandꢀrowꢀaddressing.
8.ꢀ AllꢀbanksꢀmustꢀbeꢀprechargedꢀbeforeꢀissuingꢀanꢀAUTO-REFRESHꢀorꢀSELFꢀREFRESHꢀcommand.
9.ꢀ BA0ꢀandꢀBA1ꢀvalueꢀselectꢀbetweenꢀMRSꢀandꢀEMRS.
10.ꢀCKEꢀisꢀHIGHꢀforꢀallꢀcommandsꢀshownꢀexceptꢀSELFꢀREFRESH.
ADDRESSING
TRUTHꢀTABLEꢀ-ꢀDMꢀOperations
ꢀ
x32
x16
x8
FUNCTIONꢀ
WriteꢀEnableꢀ
WriteꢀInhibitꢀ
DM
Lꢀ
DQ
Valid
X
AutoꢀPrechargeꢀ(AP)ꢀ
RowꢀAddressꢀ(RA)ꢀ
A8
A10
A10
A0-A11 A0-A12 A0-A12
H
ColumnꢀAddressꢀ(CA) A0-A7,ꢀ
A9
A0-A8
A0-A9
Note:ꢀUsedꢀtoꢀmaskꢀwriteꢀdata,ꢀprovidedꢀcoincidentꢀwithꢀtheꢀ
correspondingꢀdata.
10ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
TRUTHꢀTABLEꢀ-ꢀCKE
CKEꢀn-1 CKEꢀn CurrentꢀState
COMMANDꢀn
ACTIONꢀn
NOTES
L
L
L
L
PowerꢀDown
SelfꢀRefresh
PowerꢀDown
SelfꢀRefresh
AllꢀBanksꢀIdle
Bank(s)ꢀActive
AllꢀBanksꢀIdle
X
MaintainꢀPowerꢀDown
MaintainꢀSelfꢀRefresh
ExitꢀPowerꢀDown
X
L
H
H
L
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
NOPꢀorꢀDESELECT
AUTOꢀREFRESH
6
L
ExitꢀSelfꢀRefresh
6,ꢀ7
6
H
H
H
H
PrechargeꢀPowerꢀDownꢀEntry
ActiveꢀPowerꢀDownꢀEntry
SelfꢀRefreshꢀentry
L
6
L
H
SeeꢀTruthꢀTablesꢀ-ꢀCommands
Notes:
1.ꢀ CKEnꢀisꢀtheꢀlogicꢀstateꢀofꢀCKEꢀatꢀclockꢀedgeꢀn;ꢀCKEn-1ꢀwasꢀtheꢀstateꢀofꢀCKEꢀatꢀtheꢀpreviousꢀclockꢀedge.
2.ꢀ CurrentꢀstateꢀisꢀtheꢀstateꢀofꢀDDRꢀimmediatelyꢀpriorꢀtoꢀclockꢀedgeꢀn.
3.ꢀ COMMANDnꢀisꢀtheꢀcommandꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀACTIONnꢀisꢀtheꢀresultꢀofꢀCOMMANDn.
4.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
5.ꢀ CKEꢀmustꢀnotꢀgoꢀLOWꢀduringꢀaꢀReadꢀorꢀWrite,ꢀandꢀmustꢀstayꢀHIGHꢀuntilꢀafterꢀtRPStꢀorꢀtwR,ꢀrespectively.ꢀ
6.ꢀ DESELECTꢀandꢀNOPꢀareꢀfunctionallyꢀinterchangeable.
7.ꢀꢀNOPsꢀorꢀDeselectsꢀmustꢀbeꢀissuedꢀforꢀatꢀleastꢀtSnRꢀafterꢀSelf-Refreshꢀexitꢀbeforeꢀanyꢀotherꢀcommand.ꢀAfterꢀDLLꢀReset,ꢀatꢀ
leastꢀtxSRDꢀmustꢀelapseꢀbeforeꢀanyꢀReadꢀcommandsꢀoccur.
BasicꢀTimingꢀParametersꢀforꢀCommands
tCK
tCH
tCL
CK
CK
tIS tIH
Valid
Input
Valid
Valid
= Don't Care
NOTE: Input = A0 - An, BA0, BA1, CKE, CS, RAS, CAS, WE;
An = Address bus MSB
Integrated Silicon Solution, Inc. ꢀ
11
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
SIMPLIFIEDꢀSTATEꢀDIAGRAM
Power
Applied
Power
On
Precharge
PREALL
Self
Refresh
REFS
REFSX
MRS
MRS
REFA
Auto
Refresh
Idle
EMRS
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Read
Write
Write
Read
Write A
Read A
Read
Read
Write
Read A
Write A
Read
A
PRE
Write
A
Read
A
PRE
PRE
Precharge
PRE
PREALL
Automatic Sequence
Command Sequence
PREALLꢀ=ꢀPrechargeꢀAllꢀBanksꢀ
CKELꢀ=ꢀEnterꢀPowerꢀDown
MRSꢀ=ꢀModeꢀRegisterꢀSetꢀ
CKEHꢀ=ꢀExitꢀPowerꢀDown
REFSꢀ=ꢀEnterꢀSelfꢀRefreshꢀ
WriteꢀAꢀ=ꢀWriteꢀwithꢀAutoprecharge
REFSXꢀ=ꢀExitꢀSelfꢀRefreshꢀ
ReadꢀAꢀ=ꢀReadꢀwithꢀAutoprecharge
REFAꢀ=ꢀAutoꢀRefreshꢀ
EMRSꢀ=ꢀExtendedꢀModeꢀRegisterꢀSetꢀ
ACTꢀ=ꢀActive
PREꢀ=ꢀPrecharge
12ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
FUNCTIONALꢀDESCRIPTION
TheꢀDDRꢀSDRAMꢀisꢀaꢀhighꢀspeedꢀCMOS,ꢀdynamicꢀrandom-accessꢀmemoryꢀinternallyꢀconfiguredꢀasꢀaꢀquad-bankꢀ
DRAM.ꢀTheꢀ256Mbꢀdevicesꢀcontains:ꢀ268,435,456ꢀbits.ꢀ
TheꢀDDRꢀSDRAMꢀusesꢀdoubleꢀdataꢀrateꢀarchitectureꢀtoꢀachieveꢀhighꢀspeedꢀoperation.ꢀTheꢀdoubleꢀdataꢀrateꢀ
architectureꢀisꢀessentiallyꢀaꢀ2nꢀprefetchꢀarchitectureꢀwithꢀanꢀinterfaceꢀdesignedꢀtoꢀtransferꢀtwoꢀdataꢀwordsꢀperꢀclockꢀ
cycleꢀatꢀtheꢀI/Oꢀpins.ꢀAꢀsingleꢀreadꢀorꢀwriteꢀaccessꢀforꢀtheꢀDDRꢀSDRAMꢀeffectivelyꢀconsistsꢀofꢀaꢀsingleꢀ2n-bitꢀwide,ꢀ
oneꢀclockꢀcycleꢀdataꢀtransferꢀatꢀtheꢀinternalꢀDRAMꢀcoreꢀandꢀtwoꢀcorrespondingꢀn-bitꢀwide,ꢀone-half-clock-cycleꢀ
dataꢀtransfersꢀatꢀtheꢀI/Oꢀpins.ꢀReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀDDRꢀSDRAMꢀareꢀburstꢀoriented;ꢀaccessesꢀstartꢀatꢀaꢀ
selectedꢀlocationꢀandꢀcontinueꢀforꢀaꢀprogrammedꢀnumberꢀofꢀlocationsꢀinꢀaꢀprogrammedꢀsequence.ꢀAccessesꢀbeginꢀ
withꢀtheꢀregistrationꢀofꢀanꢀACTIVEꢀcommand,ꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀaddressꢀ
bitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀtheꢀrowꢀtoꢀbeꢀaccessed.ꢀTheꢀ
addressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀREADꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀtheꢀstartingꢀ
columnꢀlocationꢀforꢀtheꢀburstꢀaccess.ꢀ
Priorꢀtoꢀnormalꢀoperation,ꢀtheꢀDDRꢀSDRAMꢀmustꢀbeꢀinitialized.ꢀTheꢀfollowingꢀsectionꢀprovidesꢀdetailedꢀinformationꢀ
coveringꢀdeviceꢀinitialization,ꢀregisterꢀdefinition,ꢀcommandꢀdescriptionꢀandꢀdeviceꢀoperation
INITIALIZATION
DDRꢀSDRAMsꢀmustꢀbeꢀpoweredꢀupꢀandꢀinitializedꢀinꢀaꢀpredefinedꢀmanner.ꢀOperationsꢀproceduresꢀotherꢀthanꢀthoseꢀ
specifiedꢀmayꢀresultꢀinꢀundefinedꢀoperation.ꢀIfꢀthereꢀisꢀanyꢀinterruptionꢀtoꢀtheꢀdeviceꢀpower,ꢀtheꢀinitializationꢀroutineꢀ
shouldꢀbeꢀfollowed.ꢀTheꢀstepsꢀtoꢀbeꢀfollowedꢀforꢀdeviceꢀinitializationꢀareꢀlistedꢀbelow.ꢀTheꢀInitializationꢀFlowꢀdiagramꢀ
andꢀtheꢀInitializationꢀFlowꢀsequenceꢀareꢀshownꢀinꢀtheꢀfollowingꢀfigures.ꢀ
TheꢀModeꢀRegisterꢀandꢀExtendedꢀModeꢀRegisterꢀdoꢀnotꢀhaveꢀdefaultꢀvalues.ꢀIfꢀtheyꢀareꢀnotꢀprogrammedꢀduringꢀtheꢀ
initializationꢀsequence,ꢀitꢀmayꢀleadꢀtoꢀunspecifiedꢀoperation.ꢀTheꢀclockꢀstopꢀfeatureꢀisꢀnotꢀavailableꢀuntilꢀtheꢀdeviceꢀhasꢀ
beenꢀproperlyꢀinitializedꢀfromꢀStepꢀ1ꢀthroughꢀ13.
ꢀ
•ꢀStepꢀ1:ꢀApplyꢀVDDꢀbeforeꢀorꢀatꢀtheꢀsameꢀtimeꢀasꢀVDDQ.
•ꢀStepꢀ2:ꢀCKEꢀmustꢀmaintainꢀLVCMOSꢀLowꢀuntilꢀVREFꢀisꢀstable.ꢀApplyꢀVDDQꢀbeforeꢀapplyingꢀVTTꢀandꢀVREF.
•ꢀStepꢀ3:ꢀThereꢀmustꢀbeꢀatꢀleastꢀ200ꢀμsꢀofꢀvalidꢀclocksꢀbeforeꢀanyꢀcommandꢀmayꢀbeꢀgivenꢀtoꢀtheꢀDRAM.ꢀDuringꢀthisꢀ
timeꢀNOPꢀorꢀDESELECTꢀcommandsꢀmustꢀbeꢀissuedꢀonꢀtheꢀcommandꢀbusꢀandꢀCKEꢀshouldꢀbeꢀbroughtꢀHIGH.
•ꢀStepꢀ4:ꢀIssueꢀaꢀPRECHARGEꢀALLꢀcommand.
•ꢀStepꢀ5:ꢀProvideꢀNOPsꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtRPꢀtime.
•ꢀStepꢀ6:ꢀIssueꢀEMRSꢀcommand
•ꢀStepꢀ7:ꢀIssueꢀMRSꢀcommand,ꢀloadꢀtheꢀbaseꢀmodeꢀregisterꢀandꢀtoꢀresetꢀtheꢀDLL.ꢀSetꢀtheꢀdesiredꢀoperatingꢀmodes.
•ꢀStepꢀ8:ꢀProvideꢀNOPsꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtMRDꢀtime.
•ꢀStepꢀ9:ꢀIssueꢀaꢀPRECHARGEꢀALLꢀcommand
•ꢀStepꢀ10:ꢀIssueꢀ2ꢀorꢀmoreꢀAUTOꢀREFRESHꢀcycles
•ꢀStepꢀ11:ꢀIssueꢀMRSꢀcommandꢀwithꢀtheꢀresetꢀDLLꢀbitꢀdeactivatedꢀtoꢀprogramꢀoperatingꢀparametersꢀwithoutꢀresettingꢀ
theꢀDLL
•ꢀStepꢀ12:ꢀProvideꢀNOPꢀorꢀDESELECTꢀcommandsꢀforꢀatꢀleastꢀtMRDꢀtime.
•ꢀStepꢀ13:ꢀTheꢀDRAMꢀhasꢀbeenꢀproperlyꢀinitializedꢀandꢀisꢀreadyꢀforꢀanyꢀvalidꢀcommand.
ꢀ
Integrated Silicon Solution, Inc. ꢀ
13
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
InitializationꢀWaveformꢀSequence
VDD
tVDT≥ 0
VDDQ
VTT
(system1)
VREF
t
CK
t
tCL
CH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CK
CK
( (
) )
( (
) )
( (
( (
) )
( (
) )
( (
) )
) )
tIS tIH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
LVCMOS LOW LEVEL
CKE
((
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
)
)
t
tIH
IS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
NOP
PRE
EMRS
MRS
PRE
AR
AR
MRS
ACT
COMMAND
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DM
( (
) )
( (
) )
( (
) )
( (
) )
( (
( (
) )
)
)
tIS tIH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CODE
CODE
CODE
CODE
CODE
RA
( (
) )
( (
( (
) )
Address
AP4
( (
) )
( (
) )
( (
) )
)
)
t
IS
tIH
ALL BANKS
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
RA
BA
( (
) )
( (
( (
) )
( (
) )
( (
) )
( (
) )
) )
tIS tIH
tIS tIH
t
tIH
IS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
BA0=H,
BA1=L
BA0=L,
BA1=L
BA0=L,
BA1=L
BA0, BA1
( (
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
)
)
High--Z
((
((
((
((
((
((
DQS
)
)
)
)
)
)
)
)
)
)
)
)
High--Z
((
)
((
((
((
((
((
DQ
)
)
)
)
)
)
)
)
)
)
)
T = 200 µs
tMRD2
tMRD2
tRP
tRFC
tRFC
tMRD2
Power--up:
VDD and
CLK stable
Extended
Mode
Register
Set
200 cycles of CK**
Load
Mode
Register
(with AP= L)
Load
Mode
Register,
Reset DLL
(with AP = H)
DON’T CARE
Notes:
1.ꢀꢀVTTꢀisꢀnotꢀappliedꢀdirectlyꢀtoꢀtheꢀdevice,ꢀhoweverꢀtVTDꢀmustꢀbeꢀgreaterꢀthanꢀorꢀequalꢀtoꢀzeroꢀtoꢀavoidꢀdeviceꢀlatch--up.
2.ꢀꢀtMRDꢀisꢀrequiredꢀbeforeꢀanyꢀcommandꢀcanꢀbeꢀapplied,ꢀandꢀ200ꢀcyclesꢀofꢀCKꢀareꢀrequiredꢀbeforeꢀanyꢀexecutableꢀcommandꢀ
canꢀbeꢀapplied
3.ꢀꢀTheꢀtwoꢀAutoꢀRefreshꢀcommandsꢀmayꢀbeꢀmovedꢀtoꢀfollowꢀtheꢀfirstꢀMRSꢀbutꢀprecedeꢀtheꢀsecondꢀPRECHARGEꢀALLꢀcom-
mand.
4.ꢀꢀAPꢀisꢀA8ꢀforꢀx32,ꢀandꢀA10ꢀforꢀx8/x16.ꢀAddressꢀisꢀA0ꢀtoꢀA12ꢀexceptꢀAP.
14ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
MODEꢀREGISTERꢀ(MR)ꢀDEFINITIONꢀ
TheꢀModeꢀRegisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀofꢀoperationꢀofꢀtheꢀDDRꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀ
theꢀdefinitionꢀofꢀaꢀburstꢀlength,ꢀaꢀburstꢀtype,ꢀandꢀaꢀCASꢀlatency.ꢀTheꢀModeꢀRegisterꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀ
REGISTERꢀSETꢀcommandꢀ(withꢀBA0=0ꢀandꢀBA1=0)ꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀreprogrammed,ꢀ
orꢀtheꢀdeviceꢀlosesꢀpower.ꢀꢀModeꢀRegisterꢀbitsꢀA0-A2ꢀspecifyꢀtheꢀburstꢀlength,ꢀA3ꢀtheꢀtypeꢀofꢀburstꢀ(sequentialꢀorꢀ
interleave),ꢀA4-A6ꢀtheꢀCASꢀlatency,ꢀandꢀA8ꢀDLLꢀreset.ꢀAꢀlogicꢀ0ꢀshouldꢀbeꢀprogrammedꢀtoꢀallꢀtheꢀundefinedꢀaddressesꢀ
bitsꢀtoꢀensureꢀfutureꢀcompatibility.ꢀꢀTheꢀModeꢀRegisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀ
progress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀtMRDꢀbeforeꢀinitiatingꢀanyꢀsubsequentꢀoperation.ꢀViolatingꢀ
eitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.ꢀReservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀ
operationꢀorꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult
MODEꢀREGISTER
BA1ꢀ BA0ꢀ A121ꢀ A11ꢀ A10ꢀ A9ꢀ
AddressꢀBusꢀ(Ax)
A8ꢀ
A7ꢀ
A6ꢀ
A5ꢀ
A4ꢀ
A3ꢀ
A2ꢀ
A1ꢀ
A0
ModeꢀReg.ꢀ(Ex)
ꢀ
A2 A1 A0 BurstꢀLength
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
ꢀ
A3 BurstꢀType
0
1
Sequential
Interleave
ꢀ
A6 A5 A4 CASꢀLatency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
ꢀ
A12 A11 A10 A9 A8 A7 DLL
3
0
0
0
0
0
0
0
0
0
1
0
0
Normal operation
Reset DLL
Reserved
Reserved
2.5
Reserved
ꢀ
BA1 BA0 ModeꢀRegisterꢀDefinition
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
Notes:
1.ꢀA12ꢀisꢀnotꢀusedꢀinꢀx32ꢀandꢀshouldꢀbeꢀignoredꢀforꢀthisꢀoption.
2.ꢀAꢀlogicꢀ0ꢀshouldꢀbeꢀprogrammedꢀtoꢀallꢀunusedꢀ/ꢀundefinedꢀ
addressꢀbitsꢀtoꢀensureꢀfutureꢀcompatibility.
Reserved
Integrated Silicon Solution, Inc. ꢀ
15
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
BURSTꢀLENGTH
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀDDRꢀSDRAMꢀareꢀburstꢀoriented,ꢀwithꢀtheꢀburstꢀlengthꢀbeingꢀsetꢀandꢀtheꢀburstꢀorderꢀ
asꢀinꢀBurstꢀDefinition.ꢀTheꢀburstꢀlengthꢀdeterminesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀbeꢀaccessedꢀforꢀ
aꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀlengthsꢀofꢀ2,ꢀ4,ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀsequentialꢀandꢀtheꢀ
interleavedꢀburstꢀtypes.
BURSTꢀDEFINITION
ꢀ
Burstꢀ
StartingꢀColumnꢀAddress
OrderꢀofꢀAccessesꢀWithinꢀaꢀBurst
Length
Typeꢀ=ꢀSequential
Typeꢀ=ꢀInterleaved
A 0
0
2
4
0-1
1-0
0-1
1-0
1
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A 2
0
A 1
0
A 0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
ꢀ2-3-4-5-6-7-0-1
ꢀ3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
ꢀ0
1
8
0
ꢀ1
0
1
0
1
0
1
1
1
0
1
1
1
Notes:
1.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀtwo,ꢀA1-Anꢀselectsꢀtheꢀtwoꢀdataꢀelementꢀblock;ꢀA0ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
2.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀfour,ꢀA2-Anꢀselectsꢀtheꢀfourꢀdataꢀelementꢀblock;ꢀA0-A1ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
3.ꢀ Forꢀaꢀburstꢀlengthꢀofꢀeight,ꢀA3-Anꢀselectsꢀtheꢀeightꢀdataꢀelementꢀblock;ꢀA0-A2ꢀselectsꢀtheꢀfirstꢀaccessꢀwithinꢀtheꢀblock.
4.ꢀ Wheneverꢀaꢀboundaryꢀofꢀtheꢀblockꢀisꢀreachedꢀwithinꢀaꢀgivenꢀsequence,ꢀtheꢀfollowingꢀaccessꢀwrapsꢀwithinꢀtheꢀblock.
16ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀcolumnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ
accessesꢀforꢀthatꢀburstꢀtakeꢀplaceꢀwithinꢀtheꢀblock,ꢀmeaningꢀthatꢀtheꢀburstꢀwillꢀwrapꢀwithinꢀtheꢀblockꢀifꢀaꢀboundaryꢀisꢀ
reached.ꢀ
TheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo,ꢀbyꢀA2-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀ
toꢀ4,ꢀbyꢀA3-Anꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀ8.ꢀAnꢀisꢀtheꢀmostꢀsignificantꢀcolumnꢀaddressꢀbit,ꢀwhichꢀdependsꢀifꢀtheꢀ
deviceꢀisꢀx8,ꢀx16ꢀorꢀx32.ꢀAnꢀ=ꢀA9ꢀforꢀx8,ꢀAnꢀ=ꢀA8ꢀforꢀx16ꢀandꢀAnꢀ=ꢀA9ꢀforꢀx32.ꢀTheꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀ
bothꢀreadꢀandꢀwriteꢀbursts.
BURSTꢀTYPE
Accessesꢀwithinꢀaꢀgivenꢀburstꢀmayꢀbeꢀprogrammedꢀtoꢀbeꢀeitherꢀsequentialꢀorꢀinterleaved;ꢀthisꢀisꢀreferredꢀtoꢀasꢀtheꢀ
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀA3.ꢀ
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀtheꢀburstꢀlength,ꢀtheꢀburstꢀtypeꢀandꢀtheꢀstartingꢀcolumnꢀ
address.
READꢀLATENCY
TheꢀREADꢀlatency,ꢀorꢀCASꢀlatency,ꢀisꢀtheꢀdelayꢀbetweenꢀtheꢀregistrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀ
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀaꢀclockꢀedgeꢀnꢀandꢀtheꢀlatencyꢀisꢀ3ꢀclocks,ꢀtheꢀfirstꢀdataꢀelementꢀwillꢀbeꢀvalidꢀatꢀ
nꢀ+ꢀ2tCKꢀ+ꢀtAC.ꢀIfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀaꢀclockꢀedgeꢀnꢀandꢀtheꢀlatencyꢀisꢀ2ꢀclocks,ꢀtheꢀfirstꢀdataꢀelementꢀ
willꢀbeꢀvalidꢀatꢀnꢀ+ꢀtCKꢀ+ꢀtAC.
OPERATINGꢀMODE
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀissuingꢀaꢀModeꢀRegisterꢀSetꢀcommandꢀwithꢀbitsꢀA7ꢀtoꢀAnꢀeachꢀsetꢀtoꢀzero,ꢀ
andꢀbitsꢀA0ꢀtoꢀA6ꢀsetꢀtoꢀtheꢀdesiredꢀvalues.ꢀAꢀDLLꢀresetꢀisꢀinitiatedꢀbyꢀissuingꢀaꢀModeꢀRegisterꢀSetꢀcommandꢀwithꢀ
bitsꢀA7ꢀandꢀA9ꢀtoꢀAnꢀeachꢀsetꢀtoꢀzero,ꢀbitꢀA8ꢀsetꢀtoꢀone,ꢀandꢀbitsꢀA0ꢀtoꢀA6ꢀsetꢀtoꢀtheꢀdesiredꢀvalues.ꢀAꢀModeꢀRegisterꢀ
SetꢀcommandꢀissuedꢀtoꢀresetꢀtheꢀDLLꢀmustꢀalwaysꢀbeꢀfollowedꢀbyꢀaꢀModeꢀRegisterꢀSetꢀcommandꢀtoꢀselectꢀnormalꢀ
operatingꢀmodeꢀ(A8=0).
AllꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀA7ꢀtoꢀAnꢀareꢀreservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTestꢀmodesꢀandꢀreservedꢀ
statesꢀshouldꢀnotꢀbeꢀusedꢀbecauseꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
Integrated Silicon Solution, Inc. ꢀ
17
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
CASꢀLATENCIES
18ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
EXTENDEDꢀMODEꢀREGISTERꢀ(EMR)ꢀDEFINITIONꢀ
TheꢀExtendedꢀModeꢀRegisterꢀcontrolsꢀfunctionsꢀbeyondꢀthoseꢀcontrolledꢀbyꢀtheꢀModeꢀRegister;ꢀtheseꢀadditionalꢀ
functionsꢀincludeꢀDLLꢀenable/disable,ꢀandꢀoutputꢀdriveꢀstrengthꢀselection.ꢀTheꢀExtendedꢀModeꢀRegisterꢀisꢀ
programmedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀ(withꢀBA1=0ꢀandꢀBA0=1)ꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
untilꢀitꢀisꢀreprogrammed,ꢀꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀTheꢀExtendedꢀModeꢀRegisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀ
areꢀidleꢀandꢀnoꢀburstsꢀareꢀinꢀprogress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀtMRDꢀbeforeꢀinitiatingꢀanyꢀ
subsequentꢀoperation.ꢀViolatingꢀeitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.ꢀReservedꢀstatesꢀ
shouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
DLLꢀEnable/Disable
TheꢀDLLꢀmustꢀbeꢀenabledꢀforꢀnormalꢀoperation.ꢀDLLꢀenableꢀisꢀrequiredꢀduringꢀpower-upꢀinitialization,ꢀandꢀuponꢀ
returningꢀtoꢀnormalꢀoperationꢀafterꢀhavingꢀdisabledꢀtheꢀDLLꢀforꢀtheꢀpurposeꢀofꢀdebugꢀorꢀevaluationꢀ(uponꢀexitingꢀSelfꢀ
RefreshꢀMode,ꢀtheꢀDLLꢀisꢀenabledꢀautomatically).ꢀAnyꢀtimeꢀtheꢀDLLꢀisꢀenabledꢀaꢀDLLꢀResetꢀmustꢀfollowꢀandꢀ200ꢀclockꢀ
cyclesꢀmustꢀoccurꢀbeforeꢀanyꢀexecutableꢀcommandꢀcanꢀbeꢀissued.
OUTPUTꢀDRIVEꢀSTRENGTHꢀ(DS)
TheꢀnormalꢀdriveꢀstrengthꢀforꢀallꢀoutputsꢀisꢀspecifiedꢀtoꢀbeꢀSSTL_2,ꢀClassꢀII.ꢀThisꢀDRAMꢀalsoꢀsupportsꢀaꢀreducedꢀ
driverꢀstrengthꢀoption,ꢀintendedꢀforꢀlighterꢀloadꢀand/orꢀpoint-to-pointꢀenvironments.
EXTENDEDꢀMODEꢀREGISTER
BA1ꢀ BA0ꢀ A122ꢀ A11ꢀ A10ꢀ A9ꢀ
A8ꢀ
A7ꢀ
A6ꢀ
A5ꢀ
A4ꢀ
A3ꢀ
A2ꢀ
A1ꢀ
A0
AddressꢀBusꢀ(Ax)
Ext.ꢀModeꢀReg.ꢀ(Ex)
ꢀ
Reserved(1)
A0 DLL
0
1
Enable
Disable
ꢀ
A1 DriveꢀStrength
0
1
Normal
Reduced
ꢀ
BA1 BA0 ModeꢀRegisterꢀDefinition
NOTES:
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
1.ꢀAꢀlogicꢀ0ꢀshouldꢀbeꢀprogrammedꢀtoꢀallꢀunused/undefinedꢀad-
dressꢀbitsꢀtoꢀensureꢀfutureꢀcompatibility
2.ꢀA12ꢀisꢀnotꢀusedꢀforꢀx32ꢀandꢀshouldꢀbeꢀignoredꢀforꢀthisꢀoption.
Reserved
Integrated Silicon Solution, Inc. ꢀ
19
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
AbsoluteꢀMaximumꢀRating
Parameter
Symbol
Vin,ꢀVout
VDD,ꢀVDDq
TStg
Value
-1.0ꢀ~ꢀ3.6
-1.0ꢀ~ꢀ3.6
-55ꢀ~ꢀ+150
1.5
Unit
V
VoltageꢀonꢀanyꢀpinꢀrelativeꢀtoꢀVSS
VoltageꢀonꢀVDDꢀ&ꢀVDDQꢀsupplyꢀrelativeꢀtoꢀVSS
Storageꢀtemperature
V
oC
Powerꢀdissipation
PD
W
Shortꢀcircuitꢀcurrent
IoS
50
mA
Note:ꢀ
PermanentꢀdeviceꢀdamageꢀmayꢀoccurꢀifꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀareꢀexceeded.
Functionalꢀoperationꢀshouldꢀbeꢀrestrictedꢀtoꢀrecommendꢀoperationꢀcondition.
Exposureꢀtoꢀhigherꢀthanꢀrecommendedꢀvoltageꢀforꢀextendedꢀperiodsꢀofꢀtimeꢀcouldꢀaffectꢀdeviceꢀreliability
AC/DCꢀElectricalꢀCharacteristicsꢀandꢀOperatingꢀConditions
Recommendedꢀoperatingꢀconditionsꢀ(VoltageꢀreferencedꢀtoꢀVSS=0V;ꢀTA=0ꢀtoꢀ70oCꢀforꢀCommercial,ꢀTAꢀ=ꢀ-40oCꢀtoꢀ+85oCꢀforꢀIndustrialꢀandꢀA1,ꢀ
TAꢀ=ꢀ-40oCꢀtoꢀ+105oCꢀforꢀA2)
Parameter
Symbol
Min
Max
Unit
V
Note
Supplyꢀvoltageꢀ(withꢀaꢀnominalꢀVDDꢀofꢀ2.5V)
I/OꢀSupplyꢀvoltageꢀ(withꢀaꢀnominalꢀVDDꢀofꢀ2.5V)
I/OꢀReferenceꢀvoltage
V
DD
DDq
Ref
tt
DC
2.3
2.7
V
2.3
2.7
V
V
0.49*VDDQ
0.51*VDDQ
V
1
2
I/OꢀTerminationꢀvoltageꢀ(system)
V
VREF-0.04
VREF+0.04
V
Inputꢀlogicꢀhighꢀvoltage
V
ih
(
)
VREF+0.15
VDDQ+0.3
V
Inputꢀlogicꢀlowꢀvoltage
V
il
(
DC
)
-0.3
-0.3
0.36
0.71
-2
VREF-0.15
V
InputꢀVoltageꢀLevel,ꢀCLKꢀandꢀCLKꢀinputs
InputꢀDifferentialꢀVoltage,ꢀCLKꢀandꢀCLKꢀinputs
V-IꢀMatching:ꢀPullupꢀtoꢀPulldownꢀCurrentꢀRatio
Inputꢀleakageꢀcurrent
V
V
in
(
DC
)
)
VDDQ+0.3
V
iD
(
DC
VDDQ+0.6
V
3
4
V
i
(Ratio)
1.4
2
–
I
l
uA
uA
mA
mA
mA
mA
Outputꢀleakageꢀcurrent
I
oz
oh
ol
ohR
olR
-5
5
OutputꢀHighꢀCurrentꢀ(Normalꢀstrengthꢀdriver)ꢀ;ꢀVOUTꢀ=ꢀVTTꢀ+ꢀ0.84V
OutputꢀLowꢀCurrentꢀ(Normalꢀstrengthꢀdriver)ꢀ;ꢀVOUTꢀ=ꢀVTTꢀ-ꢀ0.84V
OutputꢀHighꢀCurrentꢀ(Halfꢀstrengthꢀdriver);ꢀVOUTꢀ=ꢀVTTꢀ+ꢀ0.45V
OutputꢀLowꢀCurrentꢀ(Halfꢀstrengthꢀdriver);ꢀVOUTꢀ=ꢀVTTꢀ-ꢀ0.45V
AmbientꢀOperatingꢀTemperature
I
-16.8
16.8
-9
–
I
–
I
–
I
9
–
Commercialꢀ
T
TA
TA
TA
A
0ꢀ
+70ꢀ
+85ꢀ
+85ꢀ
+105
oC
oC
oC
oC
Industrialꢀ
A1ꢀ
-40ꢀ
-40ꢀ
-40
A2
Noteꢀ:
1.ꢀVREFꢀisꢀexpectedꢀtoꢀbeꢀequalꢀtoꢀ0.5*VDDQꢀofꢀtheꢀtransmittingꢀdevice,ꢀandꢀtoꢀtrackꢀvariationsꢀinꢀtheꢀdcꢀlevelꢀofꢀsame.ꢀPeak-toꢀ
peakꢀnoiseꢀonꢀVREFꢀmayꢀnotꢀexceedꢀ+/-2%ꢀofꢀtheꢀdcꢀvalue.
2.ꢀVTTꢀisꢀnotꢀappliedꢀdirectlyꢀtoꢀtheꢀdevice.ꢀVTTꢀisꢀaꢀsystemꢀsupplyꢀforꢀsignalꢀterminationꢀresistors,ꢀisꢀexpectedꢀtoꢀbeꢀsetꢀequalꢀtoꢀ
VREF,ꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀVREF
3.ꢀVIDꢀisꢀtheꢀmagnitudeꢀofꢀtheꢀdifferenceꢀbetweenꢀtheꢀinputꢀlevelꢀonꢀCLKꢀandꢀtheꢀinputꢀlevelꢀonꢀCLK.
4.ꢀTheꢀratioꢀofꢀtheꢀpullupꢀcurrentꢀtoꢀtheꢀpulldownꢀcurrentꢀisꢀspecifiedꢀforꢀtheꢀsameꢀtemperatureꢀandꢀvoltage,ꢀoverꢀtheꢀentireꢀtem-
peratureꢀandꢀvoltageꢀrange,ꢀforꢀdeviceꢀdrainꢀtoꢀsourceꢀvoltagesꢀfromꢀ0.25Vꢀtoꢀ1.0V.ꢀForꢀaꢀgivenꢀoutput,ꢀitꢀrepresentsꢀtheꢀmaxi-
mumꢀdifferenceꢀbetweenꢀpullupꢀandꢀpulldownꢀdriversꢀdueꢀtoꢀprocessꢀvariation.ꢀTheꢀfullꢀvariationꢀinꢀtheꢀratioꢀofꢀtheꢀmaximumꢀtoꢀ
minimumꢀpullupꢀandꢀpulldownꢀcurrentꢀwillꢀnotꢀexceedꢀ1.7ꢀforꢀdeviceꢀdrainꢀtoꢀsourceꢀvoltagesꢀfromꢀ0.1ꢀtoꢀ1.0.
20ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
CAPACITANCEꢀCHARACTERISTICS(1,ꢀ2)
(VDD =ꢀVDDqꢀ=ꢀ2.5Vꢀ+ꢀ0.2V,ꢀunlessꢀotherwiseꢀnoted)
Symbol Parameter
TestꢀCondition
Limits
Units
Min Max
CI(A)
CI(C)
CI(K)
CI/O
InputꢀCapacitance,ꢀaddressꢀpin
InputꢀCapacitance,ꢀcontrolꢀpin
InputꢀCapacitance,ꢀCLKꢀpin
VI=1.25v
1.3
1.3
1.3
3
3
3
3
5
pF
pF
pF
pF
f=100MHz
VI=25mVrms
I/OꢀCapacitance,ꢀI/O,ꢀDQS,ꢀDMꢀpin
Notes:
1.ꢀThisꢀparameterꢀisꢀcharacterized.
2.ꢀConditions:ꢀFrequencyꢀ=ꢀ100MHz;ꢀVout(DC)ꢀ=ꢀVDD/2;ꢀVout(peak-to-peak)ꢀ=ꢀ0.2V;ꢀVRefꢀ=ꢀVss.
THERMALꢀRESISTANCE
Package
Substrate
Theta-ja
Theta-ja
Theta-ja
Theta-jc
Units
(Airflowꢀ=ꢀ0m/s) (Airflowꢀ=ꢀ1m/s) (Airflowꢀ=ꢀ2m/s)
TSOP2(66)
BGA(60)
4-layer
4-layer
4-layer
69.7
40.1
29.4
61.2
36.5
29
57.5
34.2
27.1
12.7
7.9
C/W
C/W
C/W
BGA(144)
4.5
Integrated Silicon Solution, Inc. ꢀ
21
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
IDDꢀSpecificationꢀParametersꢀandꢀTestꢀConditions:ꢀx8,ꢀx16
(VDDꢀ=ꢀVDDqꢀ=ꢀ2.5Vꢀ ꢀ0.2V,ꢀVssꢀ=ꢀVssQꢀ=ꢀ0V,ꢀOutputꢀOpen,ꢀunlessꢀotherwiseꢀnoted)
Symbol Parameter/ꢀTestꢀCondition
-5
-6
Units
IDD0
Operatingꢀcurrentꢀforꢀoneꢀbankꢀactive-precharge;ꢀtRCꢀ=ꢀtRC(min);ꢀ
tCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀonceꢀperꢀclockꢀ
cycle;ꢀaddressꢀandꢀcontrolꢀinputsꢀchangingꢀonceꢀeveryꢀtwoꢀclockꢀ
cycles;ꢀCSꢀ=ꢀhighꢀbetweenꢀvalidꢀcommands.
130 120
mA
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
Operatingꢀcurrentꢀforꢀoneꢀbankꢀoperation;ꢀoneꢀbankꢀopen,ꢀBLꢀ=ꢀ4,ꢀ
tRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min),ꢀIout=0mA,ꢀAddressꢀandꢀcontrolꢀ
inputsꢀchangingꢀonceꢀperꢀclockꢀcycle.
140 130
mA
mA
mA
mA
mA
Prechargeꢀpower-downꢀstandbyꢀcurrent;ꢀallꢀbanksꢀidle;ꢀpower-downꢀ
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
30
30
60
35
75
Prechargeꢀfloatingꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀallꢀbanksꢀidle;ꢀCKEꢀ 60
VIH(min);ꢀtCKꢀ=ꢀtCK(min);ꢀaddressꢀandꢀotherꢀcontrolꢀinputsꢀchangingꢀ
onceꢀperꢀclockꢀcycle;ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀDM
Activeꢀpower-downꢀstandbyꢀcurrent;ꢀoneꢀbankꢀactive;ꢀpower-downꢀ
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
35
Activeꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀCKEꢀVIH(min);ꢀoneꢀbankꢀ
active;ꢀtRCꢀ=ꢀtRAS(max);ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDQSꢀandꢀDMꢀinputsꢀ
changingꢀtwiceꢀperꢀclockꢀcycle;ꢀaddressꢀandꢀotherꢀcontrolꢀinputsꢀ
changingꢀonceꢀperꢀclockꢀcycle
75
IDD4R
Operatingꢀcurrentꢀforꢀburstꢀread;ꢀburstꢀlengthꢀ=ꢀ2;ꢀreads;ꢀcontinuousꢀ
burst;ꢀoneꢀbankꢀactive;ꢀaddressꢀandꢀcontrolꢀinputsꢀchangingꢀonceꢀperꢀ
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀ50%ꢀofꢀdataꢀchangingꢀonꢀeveryꢀtransfer;ꢀ
lOUTꢀ=ꢀ0mA
240 210
mA
mA
IDD4W Operatingꢀcurrentꢀforꢀburstꢀwrite;ꢀburstꢀlengthꢀ=ꢀ2;ꢀwrites;ꢀcontinuousꢀ 260 220
burst;ꢀoneꢀbankꢀactiveꢀaddressꢀandꢀcontrolꢀinputsꢀchangingꢀonceꢀperꢀ
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀtwiceꢀ
perꢀclockꢀcycle,ꢀ50%ꢀofꢀinputꢀdataꢀchangingꢀatꢀeveryꢀtransfer
IDD5
IDD6
IDD7
Autoꢀrefreshꢀcurrent;ꢀtRCꢀ=ꢀtRFC(min);
Selfꢀrefreshꢀcurrent;ꢀCKEꢀ0.2V;
140 140
10 10
330 280
mA
mA
mA
Operatingꢀcurrentꢀforꢀfourꢀbankꢀoperation;ꢀfourꢀbankꢀinterleavingꢀ
READsꢀ(BL=4)ꢀwithꢀautoꢀprecharge;ꢀtRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min);ꢀ
AddressꢀandꢀcontrolꢀinputsꢀchangeꢀonlyꢀduringꢀACTIVE,ꢀREAD,ꢀorꢀ
WRITEꢀcommands
22ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
IDDꢀSpecificationꢀParametersꢀandꢀTestꢀConditions:ꢀx32
(VDDꢀ=ꢀVDDqꢀ=ꢀ2.5Vꢀ ꢀ0.2V,ꢀVssꢀ=ꢀVssQꢀ=ꢀ0V,ꢀOutputꢀOpen,ꢀunlessꢀotherwiseꢀnoted)
Symbol Parameter/ꢀTestꢀCondition
-5
-6 Units
IDD0
Operatingꢀcurrentꢀforꢀoneꢀbankꢀactive-precharge;ꢀtRCꢀ=ꢀtRC(min);ꢀ
tCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀonceꢀperꢀclockꢀ
cycle;ꢀaddressꢀandꢀcontrolꢀinputsꢀchangingꢀonceꢀeveryꢀtwoꢀclockꢀ
cycles;ꢀCSꢀ=ꢀhighꢀbetweenꢀvalidꢀcommands.
180 160
mA
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
Operatingꢀcurrentꢀforꢀoneꢀbankꢀoperation;ꢀoneꢀbankꢀopen,ꢀBLꢀ=ꢀ4,ꢀ
tRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min),ꢀIout=0mA,ꢀAddressꢀandꢀcontrolꢀ
inputsꢀchangingꢀonceꢀperꢀclockꢀcycle.
190 170
mA
mA
mA
mA
mA
Prechargeꢀpower-downꢀstandbyꢀcurrent;ꢀallꢀbanksꢀidle;ꢀpower-downꢀ
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
35
35
65
45
80
Prechargeꢀfloatingꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀallꢀbanksꢀidle;ꢀCKEꢀ 65
VIH(min);ꢀtCKꢀ=ꢀtCK(min);ꢀaddressꢀandꢀotherꢀcontrolꢀinputsꢀchangingꢀ
onceꢀperꢀclockꢀcycle;ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀDM
Activeꢀpower-downꢀstandbyꢀcurrent;ꢀoneꢀbankꢀactive;ꢀpower-downꢀ
mode;ꢀCKEꢀVIL(max);ꢀtCKꢀ=ꢀtCK(min);ꢀVINꢀ=ꢀVREFꢀforꢀDQ,ꢀDQSꢀandꢀ
DM
45
Activeꢀstandbyꢀcurrent;ꢀCSꢀVIH(min);ꢀCKEꢀVIH(min);ꢀoneꢀbankꢀ
active;ꢀtRCꢀ=ꢀtRAS(max);ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDQSꢀandꢀDMꢀinputsꢀ
changingꢀtwiceꢀperꢀclockꢀcycle;ꢀaddressꢀandꢀotherꢀcontrolꢀinputsꢀ
changingꢀonceꢀperꢀclockꢀcycle
80
IDD4R
Operatingꢀcurrentꢀforꢀburstꢀread;ꢀburstꢀlengthꢀ=ꢀ2;ꢀreads;ꢀcontinuousꢀ
burst;ꢀoneꢀbankꢀactive;ꢀaddressꢀandꢀcontrolꢀinputsꢀchangingꢀonceꢀperꢀ
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀ50%ꢀofꢀdataꢀchangingꢀonꢀeveryꢀtransfer;ꢀ
lOUTꢀ=ꢀ0mA
330 300
mA
mA
IDD4W Operatingꢀcurrentꢀforꢀburstꢀwrite;ꢀburstꢀlengthꢀ=ꢀ2;ꢀwrites;ꢀcontinuousꢀ 340 310
burst;ꢀoneꢀbankꢀactiveꢀaddressꢀandꢀcontrolꢀinputsꢀchangingꢀonceꢀperꢀ
clockꢀcycle;ꢀtCKꢀ=ꢀtCK(min);ꢀDQ,ꢀDMꢀandꢀDQSꢀinputsꢀchangingꢀtwiceꢀ
perꢀclockꢀcycle,ꢀ50%ꢀofꢀinputꢀdataꢀchangingꢀatꢀeveryꢀtransfer
IDD5
IDD6
IDD7
Autoꢀrefreshꢀcurrent;ꢀtRCꢀ=ꢀtRFC(min);
Selfꢀrefreshꢀcurrent;ꢀCKEꢀ0.2V;
220 220
10 10
460 430
mA
mA
mA
Operatingꢀcurrentꢀforꢀfourꢀbankꢀoperation;ꢀfourꢀbankꢀinterleavingꢀ
READsꢀ(BL=4)ꢀwithꢀautoꢀprecharge;ꢀtRCꢀ=ꢀtRC(min),ꢀtCKꢀ=ꢀtCK(min);ꢀ
AddressꢀandꢀcontrolꢀinputsꢀchangeꢀonlyꢀduringꢀACTIVE,ꢀREAD,ꢀorꢀ
WRITEꢀcommands
Integrated Silicon Solution, Inc. ꢀ
23
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
ACꢀTIMINGꢀREQUIREMENTS
AbsoluteꢀSpecificationsꢀ(VDD,ꢀVDDQꢀ=ꢀ+2.5ꢀVꢀ 0.2ꢀV)
PARAMETER
SYMBOL
-5
-6
UNITS
MIN
-0.7
-0.6
0.45
0.45
minꢀ
MAX
0.7
MIN
-0.7
-0.6
0.45
0.45
minꢀ
MAX
0.7
DQꢀoutputꢀaccessꢀtimeꢀforꢀCLK,/CLK
DQSꢀoutputꢀaccessꢀtimeꢀforꢀCLK,/CLK
CLKꢀhigh-levelꢀwidth
tAC
ns
ns
tDQSCK
tCH
0.6
0.6
0.55
0.55
–
0.55
0.55
–
tCK
tCK
ns
CLKꢀlow-levelꢀwidth
tCL
CLKꢀhalfꢀperiod
tHP
(tCL,tCH)
(tCL,tCH)
CLKꢀcycleꢀtimeꢀCL=3
tCK(3)
tCK(2.5)
tCK(2)
tDH
5
12
12
12
–
6
12
12
12
–
ns
ns
ns
ns
ns
ns
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCL=2.5
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCL=2
5
6
7.5
0.4
0.4
2.2
7.5
0.45
0.45
2.2
DQꢀandꢀDMꢀinputꢀholdꢀtimeꢀ
DQꢀandꢀDMꢀinputꢀsetupꢀtime
tDS
–
–
Controlꢀ&ꢀAddressꢀinputꢀpulseꢀwidthꢀ(forꢀeachꢀ
input)
tIPW
–
–
DQꢀandꢀDMꢀinputꢀpulseꢀwidthꢀ(forꢀeachꢀinput)
DQꢀ&ꢀDQSꢀhigh-impedanceꢀtimeꢀfromꢀCLK,/CLK
DQꢀ&ꢀDQSꢀlow--impedanceꢀtimeꢀfromꢀCLK,/CLK
tDIPW
tHZ
1.75
–
–
1.75
–
–
0.7
–
ns
ns
ns
ns
0.7
–
tLZ
-0.7
–
-0.7
–
DQS--DQꢀSkew,ꢀDQSꢀtoꢀlastꢀDQꢀvalid,ꢀperꢀgroup,ꢀ tDQSQ
perꢀaccess
0.4
0.45
DQ/DQSꢀoutputꢀholdꢀtimeꢀfromꢀDQS
tQH
tHP-tQHS
–
tHP-
–
ns
tQHS
DataꢀHoldꢀSkewꢀFactor
tQHS
–
0.5
1.28
–
–
0.55
1.28
–
ns
WriteꢀcommandꢀtoꢀfirstꢀDQSꢀlatchingꢀtransition
DQSꢀinputꢀhighꢀpulseꢀwidth
DQSꢀinputꢀlowꢀpulseꢀwidth
tDQSS
tDQSH
tDQSL
tDSS
0.72
0.35
0.35
0.2
0.2
2
0.75
0.35
0.35
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
ns
–
–
DQSꢀfallingꢀedgeꢀtoꢀCLKꢀsetupꢀtime
DQSꢀfallingꢀedgeꢀholdꢀtimeꢀfromꢀCLK
MODEꢀREGISTERꢀSETꢀcommandꢀcycleꢀtime
Writeꢀpreambleꢀsetupꢀtime
–
–
tDSH
–
–
tMRD
–
–
tWPRES
tWPST
tWPRE
tIHF
0
–
0
–
Writeꢀpostamble
0.4
0.25
0.6
0.6
–
0.4
0.25
0.75
0.6
–
tCK
tCK
ns
Writeꢀpreamble
AddressꢀandꢀControlꢀinputꢀholdꢀtimeꢀ(fastꢀslewꢀ
rate)
–
–
AddressꢀandꢀControlꢀinputꢀsetupꢀtimeꢀ(fastꢀslewꢀ
rate)
tISF
tIH
0.6
0.7
0.7
–
–
–
0.75
0.8
–
-–
–
ns
ns
ns
AddressꢀandꢀControlꢀinputꢀholdꢀtimeꢀ(slowꢀslewꢀ
rate)
AddressꢀandꢀControlꢀinputꢀsetupꢀtimeꢀ(slowꢀslewꢀ tIS
rate)
0.8
Readꢀpreamble
tRPRE
0.9
0.4
40
1.1
0.6
0.9
0.4
42
1.1
0.6
tCK
tCK
ns
Readꢀpostamble
tRPST
tRAS
ACTIVEꢀtoꢀPRECHARGEꢀcommand
70,000
120,000
24ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
ACꢀTIMINGꢀREQUIREMENTS
AbsoluteꢀSpecificationsꢀ(VDD,ꢀVDDQꢀ=ꢀ+2.5ꢀVꢀ 0.2ꢀV@-5/-6)
PARAMETER
SYMBOL
-5
-6
UNITS
MIN
MAX
MIN
MAX
ACTIVEꢀtoꢀACTIVE/AutoꢀRefreshꢀcommandꢀ
period
tRC
55
–ꢀ
60
–
ns
AutoꢀRefreshꢀtoꢀActive/Auto
tRFC
tRCD
tRP
70
15
15
15
10
15
–
–
72
15
15
15
12
15
–
–
ns
ns
ACTIVEꢀtoꢀREADꢀorꢀWRITEꢀdelay
PRECHARGEꢀcommandꢀperiod
–
–
ns
ActiveꢀtoꢀAutoprechargeꢀDelay
tRAP
tRRD
tWR
–
–
ns
ACTIVEꢀbankꢀAꢀtoꢀACTIVEꢀbankꢀBꢀcommand
Writeꢀrecoveryꢀtime
–
–
ns
–
–
ns
AutoꢀPrechargeꢀwriteꢀrecoveryꢀ+ꢀprechargeꢀtime
InternalꢀWriteꢀtoꢀReadꢀCommandꢀDelay
Exitꢀselfꢀrefreshꢀtoꢀnon-READ
tDAL
tWR+tRP
–
tWR+tRP
–
tCK
tCK
ns
tWTR
tXSNR
tXSRD
tREFI
tREFI
2
70
200
–
–
1
75
200
–
–
–
–
ExitꢀselfꢀrefreshꢀtoꢀREADꢀcommand
AverageꢀPeriodicꢀRefreshꢀInterval TAꢀ≤ꢀ85ꢀºC
–
–
tCK
ms
7.8
1.9
7.8
1.9
(x8/x16)
TAꢀ>ꢀ85ꢀºC,
A2ꢀonly
–
–
ms
AverageꢀPeriodicꢀRefreshꢀInterval TAꢀ≤ꢀ85ꢀºC
tREFI
tREFI
–
–
15.6
3.9
–
–
15.6
3.9
ms
ms
(x32)
TAꢀ>ꢀ85ꢀºC,
A2ꢀonly
OutputꢀLoadꢀCondition
VREF
DQS
V
TT=VREF
DQ
50
VREF
Ω
V
OUT
Zo=50
Ω
V
REF
30pF
OutputTiming
Measurement
ReferencePoint
Integrated Silicon Solution, Inc. ꢀ
25
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
Notes:
1.ꢀAllꢀvoltagesꢀreferencedꢀtoꢀVss.
2.ꢀTestsꢀforꢀACꢀtiming,ꢀIDD,ꢀandꢀelectrical,ꢀACꢀandꢀDCꢀcharacteristics,ꢀmayꢀbeꢀconductedꢀatꢀnominalꢀreference/supplyꢀvoltageꢀ
levels,ꢀbutꢀtheꢀrelatedꢀspecificationsꢀandꢀdeviceꢀoperationꢀareꢀguaranteedꢀforꢀtheꢀfullꢀvoltageꢀrangeꢀspecified.
3.ꢀACꢀtimingꢀandꢀIDDꢀtestsꢀmayꢀuseꢀaꢀVILꢀtoꢀVIHꢀswingꢀofꢀupꢀtoꢀ1.5Vꢀinꢀtheꢀtestꢀenvironment,ꢀbutꢀinputꢀtimingꢀisꢀstillꢀreferencedꢀtoꢀ
VREFꢀ(orꢀtoꢀtheꢀcrossingꢀpointꢀforꢀCK//CK),ꢀandꢀparameterꢀspecificationsꢀareꢀguaranteedꢀforꢀtheꢀspecifiedꢀACꢀinputꢀlevelsꢀun-
derꢀnormalꢀuseꢀconditions.ꢀTheꢀminimumꢀslewꢀrateꢀforꢀtheꢀinputꢀsignalsꢀisꢀ1V/nsꢀinꢀtheꢀrangeꢀbetweenꢀVIL(AC)ꢀandꢀVIH(AC).
4.ꢀTheꢀACꢀandꢀDCꢀinputꢀlevelꢀspecificationsꢀareꢀasꢀdefinedꢀinꢀtheꢀSSTL_2ꢀStandardꢀ(i.e.ꢀtheꢀreceiverꢀwillꢀeffectivelyꢀswitchꢀasꢀaꢀ
resultꢀofꢀtheꢀsignalꢀcrossingꢀtheꢀACꢀinputꢀlevel,ꢀandꢀwillꢀremainꢀinꢀthatꢀstateꢀasꢀlongꢀasꢀtheꢀsignalꢀdoesꢀnotꢀringꢀbackꢀaboveꢀ
(below)ꢀtheꢀDCꢀinputꢀLOWꢀ(HIGH)ꢀlevel.
5.ꢀVREFꢀisꢀexpectedꢀtoꢀbeꢀequalꢀtoꢀ0.5*VddQꢀofꢀtheꢀtransmittingꢀdevice,ꢀandꢀtoꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀtheꢀsame.ꢀ
Peak-to-peakꢀnoiseꢀonꢀVREFꢀmayꢀnotꢀexceedꢀ+2%ꢀofꢀtheꢀDCꢀvalue.
6.ꢀVTTꢀisꢀnotꢀappliedꢀdirectlyꢀtoꢀtheꢀdevice.ꢀVTTꢀisꢀaꢀsystemꢀsupplyꢀforꢀsignalꢀterminationꢀresistors,ꢀisꢀexpectedꢀtoꢀbeꢀsetꢀequalꢀtoꢀ
VREF,ꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀVREF.
7.ꢀVIDꢀisꢀtheꢀmagnitudeꢀofꢀtheꢀdifferenceꢀbetweenꢀtheꢀinputꢀlevelꢀonꢀCLKꢀandꢀtheꢀinputꢀlevelꢀonꢀ/CLK.
8.ꢀTheꢀvalueꢀofꢀVIXꢀisꢀexpectedꢀtoꢀequalꢀ0.5*VddQꢀofꢀtheꢀtransmittingꢀdeviceꢀandꢀmustꢀtrackꢀvariationsꢀinꢀtheꢀDCꢀlevelꢀofꢀtheꢀ
same.
9.ꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
10.ꢀIDDꢀspecificationsꢀareꢀtestedꢀafterꢀtheꢀdeviceꢀisꢀproperlyꢀinitialized.
11.ꢀThisꢀparameterꢀisꢀsampled.ꢀVddQꢀ=ꢀ2.5V+0.2V,ꢀVddꢀ=ꢀ2.5Vꢀ+ꢀ0.2Vꢀ,ꢀfꢀ=ꢀ100ꢀMHz,ꢀTaꢀ=ꢀ25°C,ꢀVOUT(DC)ꢀ=ꢀVddQ/2,ꢀ
VOUT(PEAKꢀTOꢀPEAK)ꢀ=ꢀ25mV.ꢀDMꢀinputsꢀareꢀgroupedꢀwithꢀI/Oꢀpinsꢀ-ꢀreflectingꢀtheꢀfactꢀthatꢀtheyꢀareꢀmatchedꢀinꢀloadingꢀ(toꢀ
facilitateꢀtraceꢀmatchingꢀatꢀtheꢀboardꢀlevel).
12.ꢀTheꢀCLK//CLKꢀinputꢀreferenceꢀlevelꢀ(forꢀtimingꢀreferencedꢀtoꢀCLK//CLK)ꢀisꢀtheꢀpointꢀatꢀwhichꢀCLKꢀandꢀ/CLKꢀcross;ꢀtheꢀinputꢀ
referenceꢀlevelꢀforꢀsignalsꢀotherꢀthanꢀCLK//CLK,ꢀisꢀVREF.
13.ꢀInputsꢀareꢀnotꢀrecognizedꢀasꢀvalidꢀuntilꢀVREFꢀstabilizes.ꢀException:ꢀduringꢀtheꢀperiodꢀbeforeꢀVREFꢀstabilizes,ꢀCKE<ꢀ0.3VddQꢀ
isꢀrecognizedꢀasꢀLOW.
14.ꢀtHZꢀandꢀtLZꢀtransitionsꢀoccurꢀinꢀtheꢀsameꢀaccessꢀtimeꢀwindowsꢀasꢀvalidꢀdataꢀtransitions.ꢀTheseꢀparametersꢀareꢀnotꢀrefer-
encedꢀtoꢀaꢀspecificꢀvoltageꢀlevel,ꢀbutꢀspecifyꢀwhenꢀtheꢀdeviceꢀoutputꢀisꢀnoꢀlongerꢀdrivingꢀ(HZ),ꢀorꢀbeginsꢀdrivingꢀ(LZ).
15.ꢀTheꢀmaximumꢀlimitꢀforꢀthisꢀparameterꢀisꢀnotꢀaꢀdeviceꢀlimit.ꢀTheꢀdeviceꢀwillꢀoperateꢀwithꢀaꢀgreaterꢀvalueꢀforꢀthisꢀparameter,ꢀbutꢀ
systemꢀperformanceꢀ(busꢀturnaround)ꢀwillꢀdegradeꢀaccordingly.
16.ꢀTheꢀspecificꢀrequirementꢀisꢀthatꢀDQSꢀbeꢀvalidꢀ(HIGH,ꢀLOW,ꢀorꢀatꢀsomeꢀpointꢀonꢀaꢀvalidꢀtransition)ꢀonꢀorꢀbeforeꢀthisꢀCLKꢀ
edge.ꢀAꢀvalidꢀtransitionꢀisꢀdefinedꢀasꢀmonotonic,ꢀandꢀmeetingꢀtheꢀinputꢀslewꢀrateꢀspecificationsꢀofꢀtheꢀdevice.ꢀWhenꢀnoꢀwritesꢀ
wereꢀpreviouslyꢀinꢀprogressꢀonꢀtheꢀbus,ꢀDQSꢀwillꢀbeꢀtransitioningꢀfromꢀHigh-ZꢀtoꢀlogicꢀLOW.ꢀIfꢀaꢀpreviousꢀwriteꢀwasꢀinꢀprog-
ress,ꢀDQSꢀcouldꢀbeꢀHIGH,ꢀLOW,ꢀorꢀtransitioningꢀfromꢀHIGHꢀtoꢀLOWꢀatꢀthisꢀtime,ꢀdependingꢀonꢀtDQSS.
17.ꢀAꢀmaximumꢀofꢀeightꢀAUTOꢀREFRESHꢀcommandsꢀcanꢀbeꢀpostedꢀtoꢀanyꢀgivenꢀDDRꢀSDRAMꢀdevice.
18.ꢀtXPRDꢀshouldꢀbeꢀ200ꢀtCLKꢀinꢀtheꢀconditionꢀofꢀtheꢀunstableꢀCLKꢀoperationꢀduringꢀtheꢀpowerꢀdownꢀmode.
19.ꢀForꢀcommand/addressꢀandꢀCKꢀ&ꢀ/CKꢀslewꢀrateꢀ>ꢀ1.0V/ns.
20.ꢀMinꢀ(tCL,tCH)ꢀrefersꢀtoꢀtheꢀsmallerꢀofꢀtheꢀactualꢀclockꢀlowꢀtimeꢀandꢀtheꢀactualꢀclockꢀhighꢀtimeꢀasꢀprovidedꢀtoꢀtheꢀdevice.
21.ꢀForꢀA2ꢀtemperatureꢀgradeꢀwithꢀTA > 85°C:ꢀIDD2F,ꢀIDD3N,ꢀandꢀIDD7ꢀareꢀderegulatedꢀtoꢀ10%ꢀaboveꢀtheseꢀvalues;ꢀIDD2Pꢀandꢀ
IDD6ꢀareꢀderegulatedꢀtoꢀ20%ꢀaboveꢀtheseꢀvalues.
26ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
OUTPUTꢀSLEWꢀRATEꢀCHARACTERISTICS
SlewꢀRateꢀCharacteristic
TypicalꢀRangeꢀ
(V/ns)
Minꢀ
(V/ns) (V/ns)
Maxꢀ
PullupꢀSlewꢀRate
1.2-2.5
1.2-2.5
0.7
0.7
5.0
5.0
PulldownꢀSlewꢀRate
ACꢀOVERSHOOT/UNDERSHOOTꢀSPECIFICATIONꢀFORꢀADDRESSꢀANDꢀCONTROLꢀPINS
Parameter
Peakꢀamplitudeꢀallowedꢀforꢀovershoot
Peakꢀamplitudeꢀallowedꢀforꢀundershoot
AreaꢀbetweenꢀtheꢀovershootꢀsignalꢀandꢀVDDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
AreaꢀbetweenꢀtheꢀundershootꢀsignalꢀandꢀGNDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
Max
Units
V
V
V-ns
V-ns
1.5
1.5
4.5
4.5
+5
+4
Max. amplitude = 1.5 V
Overshoot
+3
V
DD
+2
+1
0
Volts
(V)
Ground
-1
-2
-3
Undershoot
Max. area = 4.5 V-ns
0
1
2
3
4
5
6
Time (ns)
AddressꢀandꢀControlꢀACꢀOvershootꢀandꢀUndershootꢀDefinition
OVERSHOOT/UNDERSHOOTꢀSPECIFICATIONꢀFORꢀDATA,ꢀSTROBE,ꢀANDꢀMASKꢀPINS
Parameter
Peakꢀamplitudeꢀallowedꢀforꢀovershoot
Peakꢀamplitudeꢀallowedꢀforꢀundershoot
AreaꢀbetweenꢀtheꢀovershootꢀsignalꢀandꢀVDDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
AreaꢀbetweenꢀtheꢀundershootꢀsignalꢀandꢀGNDꢀmustꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀ(seeꢀfigureꢀbelow)
Max
1.2
1.2
2.4
2.4
Units
V
V
V-ns
V-ns
+5
+4
Max. amplitude = 1.2 V
Overshoot
+3
V
DD
+2
+1
0
Volts
(V)
Ground
-1
-2
-3
Undershoot
Max. area = 2.4 V--ns
0
1
2
3
4
5
6
Time (ns)
DQ/DM/DQSꢀACꢀOvershootꢀandꢀUndershootꢀDefinition
Integrated Silicon Solution, Inc. ꢀ
27
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
32Mx8ꢀORDERINGꢀINFORMATIONꢀ-ꢀVDDꢀ=ꢀ2.5V
CommercialꢀRange:ꢀ0°Cꢀtoꢀ+70°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ 200ꢀMHzꢀ
ꢀ 166ꢀMHzꢀ
5ꢀ
6ꢀ
IS43R83200D-5TLꢀ
IS43R83200D-6TLꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ 200ꢀMHzꢀ
ꢀ 166ꢀMHzꢀ
5ꢀ
6ꢀ
IS43R83200D-5TLIꢀ
IS43R83200D-6TLIꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
28ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
16Mx16ꢀORDERINGꢀINFORMATIONꢀ-ꢀVDDꢀ=ꢀ2.5V
CommercialꢀRange:ꢀ0°Cꢀtoꢀ+70°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS43R16160D-5BLꢀ
IS43R16160D-5TLꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS43R16160D-6BLꢀ
IS43R16160D-6TLꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
ꢀ ꢀ
5ꢀ
ꢀ
ꢀ
IS43R16160D-5BLIꢀ
IS43R16160D-5BIꢀ
IS43R16160D-5TLIꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
60-ballꢀFBGAꢀ
ꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
ꢀ ꢀ
6ꢀ
ꢀ
ꢀ
IS43R16160D-6BLIꢀ
IS43R16160D-6BIꢀ
IS43R16160D-6TLIꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
60-ballꢀFBGAꢀ
ꢀ ꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
Automotiveꢀ(A1)ꢀRange:ꢀ-40°Cꢀtoꢀ+85°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Packageꢀ
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS46R16160D-5BLA1ꢀ
IS46R16160D-5TLA1ꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS46R16160D-6BLA1ꢀ
IS46R16160D-6TLA1ꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
Automotiveꢀ(A2)ꢀRange:ꢀ-40°Cꢀtoꢀ+105°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Packageꢀ
ꢀ 166ꢀMHzꢀ
ꢀ ꢀ
6ꢀ
ꢀ
IS46R16160D-6BLA2ꢀ
IS46R16160D-6TLA2ꢀ
60-ballꢀFBGA,ꢀLead-freeꢀ
66-pinꢀTSOP-II,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
8Mx32ꢀORDERINGꢀINFORMATIONꢀ-ꢀVDDꢀ=ꢀ2.5V
CommercialꢀRange:ꢀ0°Cꢀtoꢀ+70°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀꢀ 200ꢀMHzꢀ
ꢀ 166ꢀMHzꢀ
5ꢀ
6ꢀ
IS43R32800D-5BLꢀ
IS43R32800D-6BLꢀ
144-ballꢀFBGA,ꢀLead-free
144-ballꢀFBGA,ꢀLead-freeꢀ
IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ 200ꢀMHzꢀ
ꢀ ꢀ
5ꢀ
ꢀ
IS43R32800D-5BLIꢀ
IS43R32800D-5BIꢀ
IS43R32800D-6BLIꢀ
144-ballꢀFBGA,ꢀLead-free
144-ballꢀFBGA
ꢀ 166ꢀMHzꢀ
6ꢀ
144-ballꢀFBGA,ꢀLead-freeꢀ
Automotiveꢀ(A1)ꢀRange:ꢀ-40°Cꢀtoꢀ+85°C
ꢀ Frequencyꢀ Speedꢀ(ns)ꢀꢀ
ꢀ 166ꢀMHzꢀ 6ꢀ
OrderꢀPartꢀNo.ꢀ
Package
IS46R32800D-6BLA1ꢀ
144-ballꢀFBGA,ꢀLead-freeꢀ
Integrated Silicon Solution, Inc. ꢀ
29
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
30ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
MiniꢀBallꢀGridꢀArray
PackageꢀCode:ꢀBꢀ(60-Ball)ꢀ8mmꢀxꢀ13mm
Integrated Silicon Solution, Inc. ꢀ
31
Rev.ꢀ B
06/19/2012
IS43R83200D
IS43/46R16160D, IS43/46R32800D
32ꢀ
Integrated Silicon Solution, Inc.
Rev.ꢀ B
06/19/2012
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