IS45R16800E-8BLA2 [ISSI]
Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-54;
| 型号： | IS45R16800E-8BLA2 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-54 动态存储器 内存集成电路 |
| 文件： | 总61页 (文件大小：1002K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42/45R81600E
IS42/45R16800E
16M x 8, 8M x16
APRIL 2010
128Mb SYNCHRONOUS DRAM
OVERVIEW
FEATURES
ISSI'sꢀ128MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
Theꢀ128MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ
•ꢀ Clockꢀfrequency:ꢀ133,ꢀ125ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Powerꢀsupply:ꢀ2.5Vꢀꢀ
•ꢀ LVTTLꢀinterface
IS42/45R81600Eꢀ IS42/45R16800Eꢀ
4Mꢀx8ꢀx4ꢀBanksꢀ 2Mꢀx16ꢀx4ꢀBanksꢀ
•ꢀ Programmableꢀburstꢀlengthꢀ
– (1, 2, 4, 8, full page)
54-pinꢀTSOPIIꢀ
54-pinꢀTSOPII
54-ballꢀTF-BGA
•ꢀ Programmableꢀburstꢀsequence:ꢀ
ꢀ
ꢀ
Sequential/Interleave
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ SelfꢀRefresh
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ16ꢀmsꢀ(A2ꢀgrade)ꢀorꢀ
64ꢀmsꢀ(A1ꢀgrade)
KEY TIMING PARAMETERS
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
Parameter
-75
-8
Unit
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
ClkꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
9.6ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
7.5ꢀ
9.6ꢀ
nsꢀ
ns
operations capability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
ClkꢀFrequencyꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
command
133ꢀ
104ꢀ
125ꢀ
104ꢀ
Mhzꢀ
Mhz
•ꢀ OperatingꢀTemperatureꢀRange:
Commercial: 0oC to +70oC
AccessꢀTimeꢀꢀfromꢀClockꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
5.4ꢀ
6ꢀ
nsꢀ
ns
Industrial: -40oC to +85oC
Automotive Grade A1: -40oC to +85oC
Automotive Grade A2: -40oC to +105oC
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated
Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
DEVICE OVERVIEW
A self-timed row precharge initiated at the end of the burst
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ
enabled. Precharge one bank while accessing one of the
otherthreebankswillhidetheprechargecyclesandprovide
seamless, high-speed, random-access operation.
Theꢀ 128Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ
random-accessꢀmemoryꢀdesignedꢀtoꢀoperateꢀinꢀ2.5VꢀVd d
andꢀ2.5VꢀVd d q memoryꢀsystemsꢀcontainingꢀ134,217,728ꢀ
bits.ꢀꢀInternallyꢀconfiguredꢀasꢀaꢀquad-bankꢀDRAMꢀwithꢀaꢀ
synchronousꢀinterface.ꢀꢀEachꢀ33,554,432-bitꢀbankꢀisꢀorga-
nizedꢀasꢀ4,096ꢀrowsꢀbyꢀ512ꢀcolumnsꢀbyꢀ16ꢀbitsꢀorꢀ4,096ꢀ
rows by 1,024 columns by 8 bits.
SDRAM readandwriteaccessesareburstorientedstarting
at a selected location and continuing for a programmed
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ
command in conjunction with address bits registered are
usedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀ
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ
registered are used to select the starting column location
for the burst access.
Theꢀ128MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ
and a power-saving, power-down mode. All signals are
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.
Theꢀ128MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ
data at a high data rate with automatic column-address
generation, theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
DQMLꢀ
DQMH
DATA ꢀIN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
REFRESH
CONTROLLER
MODE
REGISTER
2
DQꢀ0-15
12
V
DD/VDDQ
ss/Vss
ꢀSELF
DATA ꢀOUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORYꢀCELL
4096
4096
ARRAY
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSEꢀAMPꢀI/OꢀGATE
512
(xꢀ16)
COLUMN
ADDRESSꢀLATCH
BANKꢀCONTROLꢀLOGIC
9
BURSTꢀCOUNTER
COLUMNꢀDECODER
COLUMN
ADDRESSꢀBUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
VSS
NC
DQM
CLK
CKE
NC
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
A0-A9ꢀ
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
ꢀ
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
DQMꢀ
Vd d
DataꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ7ꢀ
Vssꢀ
Vd d q ꢀ
Vssqꢀ
NCꢀ
Ground
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
Chip Select
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
VDD
VSS
DQML
WE
CAS
RAS
CS
NC
DQMH
CLK
CKE
NC
BA0
BA1
A10
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
A0-A8
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
DQMLꢀ x16ꢀLowerꢀByte,ꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByte,ꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vd d
Power
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Vssꢀ
Vd d q ꢀ
Vssqꢀ
NCꢀ
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
Chip Select
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
PIN CONFIGURATION
54-ball TF-BGA for x16 (TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ8.00ꢀmmꢀBody,ꢀ0.8ꢀmmꢀBallꢀPitch)
PACKAGEꢀCODE:ꢀ54Bꢀ(8x8)
1 2 3 4 5 6 7 8 9
A
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
B
C
D
E
F
DQ8 NC
VSS
DQMH CLK CKE
G
H
J
NC
A8
A11
A7
A9
A6
A4
A0
A3
A1
A10
VSS
A5
A2 VDD
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
A0-A8
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
DQMLꢀ x16ꢀLowerꢀByteꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByteꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vd d
Power
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Vssꢀ
Vd d q ꢀ
Vssqꢀ
NCꢀ
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
Chip Select
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
PIN FUNCTIONS
Symbol
A0-A11
ꢀ
Type
Input Pin
ꢀ
Function (In Detail)
ꢀ
AddressꢀInputs:ꢀA0-A11ꢀareꢀsampledꢀduringꢀtheꢀACTIVE
ꢀ
ꢀ
commandꢀ(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(columnꢀaddressꢀA0-
A9ꢀ(x8),ꢀorꢀA0-A8ꢀ(x16);ꢀwithꢀA10ꢀdefiningꢀautoꢀprecharge)ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀ
ofꢀtheꢀmemoryꢀarrayꢀinꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀ
commandꢀtoꢀdetermineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀ
selectedꢀbyꢀBA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀ
LOADꢀMODEꢀREGISTERꢀcommand.
BA0,ꢀBA1
CAS
Input Pin
Input Pin
Input Pin
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
CKEꢀ
ꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refresh mode. CKEꢀisꢀan asynchronous input.
CLKꢀ
Input Pin
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
TheꢀCS input determines whether command input is enabled within the device.
Command input is enabled when CSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
device remains in the previous state when CSꢀisꢀHIGH.
ꢀ
ꢀ
DQML,ꢀ
DQMHꢀ
Input Pin
ꢀ
DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀInꢀread
ꢀ
ꢀ
ꢀ
mode,DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenDQMLꢀorDQMHꢀisꢀLOW,ꢀtheꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀtoꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenDQML/DQMHꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀtoꢀ
OEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀinputꢀbuffer.ꢀ
WhenꢀDQMLꢀorꢀDQMHꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀ
canꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀmaskedꢀ
andꢀcannotꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀForꢀIS45S16800Eꢀonly.
ꢀ
DQMꢀ
InputꢀPinꢀ
ForꢀIS45S81600Eꢀonly.
ꢀDQ0-DQ7 or
ꢀ DQ0-DQ15
ꢀ
ꢀ Input/Outputꢀ
DataꢀonꢀtheꢀDataꢀBusꢀisꢀlatchedꢀonꢀDQꢀpinsꢀduringꢀWriteꢀcommands,ꢀandꢀbufferedꢀfor
outputꢀafterꢀReadꢀcommands.
RAS
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vd d q
Vd d
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
ꢀ
ꢀ
ꢀ
ꢀ
Vd d q is the output buffer power supply.
Vd d is the device internal power supply.
Vs s q is the output buffer ground.
Vs s q
Vs s
Vs s is the device internal ground.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
GENERAL DESCRIPTION
READ
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
and starts a burst read access to an active row. Inputs A0-
A9ꢀ(x8);ꢀA0-A8ꢀ(x16)ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀ
WhenꢀA10ꢀisꢀHIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀ
PRECHARGEꢀcommand.ꢀꢀWhenꢀtheꢀautoꢀprechargeꢀisꢀ
selected, the row being accessed will be precharged at
theꢀendꢀofꢀtheꢀREADꢀburst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀ
subsequentꢀaccessesꢀwhenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀ
selected.ꢀꢀDQ’sꢀreadꢀdataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀ
theꢀDQMꢀinputsꢀtwoꢀclocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀ
signalꢀwasꢀregisteredꢀHIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀ
beꢀHigh-Zꢀtwoꢀclocksꢀlater.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀ
whenꢀtheꢀDQMꢀsignalꢀwasꢀregisteredꢀLOW.
PRECHARGEꢀfunctionꢀinꢀconjunctionꢀwithꢀaꢀspecificꢀREADꢀ
orꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀ
command, auto precharge is either enabled or disabled.
AUTOꢀPRECHARGEꢀdoesꢀnotꢀapplyꢀexceptꢀinꢀfull-pageꢀ
burstꢀ mode.ꢀ Uponꢀ completionꢀ ofꢀ theꢀ READꢀ orꢀWRITEꢀ
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ(tr c )is
required for a single refresh operation, and no other com-
mandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀcommandꢀ
isꢀexecutedꢀatꢀleastꢀ4096ꢀtimesꢀforꢀeveryꢀTr e f .ꢀDuringꢀanꢀ
AUTOꢀREFRESHꢀcommand,ꢀaddressꢀbitsꢀareꢀ“Don’tꢀCare”.ꢀ
ThisꢀcommandꢀcorrespondsꢀtoꢀCBRꢀAuto-refresh.
WRITE
A burst write access to an active row is initiated with the
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀandꢀ
theꢀstartingꢀcolumnꢀlocationꢀisꢀprovidedꢀbyꢀinputsꢀA0-A9ꢀ
(x8);ꢀA0-A8ꢀ(x16).ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀ
used is determined by A10.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ
TERMINATE.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
open for subsequent accesses.
A memory array is written with corresponding input data
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/column location.
COMMAND INHIBIT
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled
NO OPERATION
WhenꢀCSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ
commands from being registered during idle or wait
states.
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ
open row in a particular bank or the open row in all banks.
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bank(s) is executed after passage of the period tRP, which
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ
has been precharged, it is in the idle state and must be
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ
issued to that bank.
LOAD MODE REGISTER
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ
registerꢀisꢀloadedꢀfromꢀA0-A11.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ
be issued when all banks are idle.
ACTIVE COMMAND
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ
inputs selects a bank to be accessed, and the address
inputsꢀonꢀA0-A11ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ
command is issued to the bank, the row remains open
for accesses.
AUTO PRECHARGE
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-
charge is initiated at the earliest valid stage within a burst.
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ
requiringꢀanꢀexplicitꢀcommand.ꢀA10ꢀtoꢀenableꢀtheꢀAUTOꢀ
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
COMMAND TRUTH TABLE
CKE
A11
Function
n – 1
Hꢀꢀ
n
CS
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
RAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
CAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
WE
×ꢀꢀ
Hꢀ
BA1
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
BA0
×ꢀꢀ
×ꢀ
A10 A9 - A0
Deviceꢀdeselectꢀ(DESL)ꢀꢀ
Noꢀoperationꢀ(NOP)ꢀ ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀ
×
Hꢀꢀ
×
Burstꢀstopꢀ(BST)ꢀꢀ
Readꢀꢀ
ꢀ
ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
×ꢀꢀ
Lꢀꢀ
Hꢀ
Lꢀ
×
ꢀ
Hꢀꢀ
Vꢀ
Vꢀ
V
V
V
×
Readꢀwithꢀautoꢀprechargeꢀꢀ Hꢀꢀ
Writeꢀꢀ ꢀꢀ Hꢀꢀ
Writeꢀwithꢀautoꢀprechargeꢀꢀ Hꢀ
Bankꢀactivateꢀ(ACT)ꢀꢀꢀ Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀꢀ
Lꢀ
Hꢀ
Vꢀ
Hꢀꢀ
Vꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀ
×ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀ
ꢀVꢀꢀ
Vꢀ
Prechargeꢀselectꢀbankꢀ(PRE)ꢀ Hꢀꢀ
Prechargeꢀallꢀbanksꢀ(PALL)ꢀ Hꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Vꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀ
×
CBRꢀAuto-Refreshꢀ(REF)ꢀ
Self-Refreshꢀ(SELF)ꢀ ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×ꢀ
×
Modeꢀregisterꢀsetꢀ(MRS)ꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Vꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
DQM TRUTH TABLE
CKE
DQM
Function
n-1
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
n
U
L
L
Dataꢀwriteꢀ/ꢀoutputꢀenableꢀꢀꢀ
Dataꢀmaskꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
ꢀ×ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
H
×
L
Upperꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Lowerꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Upperꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
×
H
Lowerꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
CKE TRUTH TABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CKE
CurrentꢀStateꢀ/Functionꢀꢀ
ActivatingꢀClockꢀsuspendꢀmodeꢀentryꢀꢀ
AnyꢀClockꢀsuspendꢀmodeꢀꢀ
Clockꢀsuspendꢀmodeꢀexitꢀꢀ
AutoꢀrefreshꢀcommandꢀIdleꢀ(REF)ꢀꢀ
SelfꢀrefreshꢀentryꢀIdleꢀ(SELF)ꢀꢀ
PowerꢀdownꢀentryꢀIdleꢀꢀ
nꢀ–ꢀ1ꢀꢀ nꢀꢀ
CS
×ꢀ
RAS
×ꢀꢀ
×ꢀꢀ
×ꢀ
CAS WE
Address
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀ
×
×
×
×
×
×ꢀꢀ
×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀ
ꢀ
Selfꢀrefreshꢀexitꢀꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×
ꢀ
ꢀ
Powerꢀdownꢀexitꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
FUNCTIONAL TRUTH TABLE
Current State
CS
RAS CAS WE
Address
Xꢀ
Command
DESLꢀꢀ
Action
Idleꢀ
Hꢀꢀ Xꢀ
Xꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown
ILLEGALꢀ(3)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
Xꢀ
NOPꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Xꢀ
BSTꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
A,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGAL(3)
Rowꢀactivating
Nop
AutoꢀrefreshꢀorꢀSelf-refresh(4)
Modeꢀregisterꢀset
Nop
Lꢀꢀ
Lꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
OC,ꢀBA1=Lꢀꢀ
Xꢀ
RowꢀActiveꢀ
Hꢀꢀ Xꢀ
Xꢀ
DESLꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Xꢀ
NOPꢀꢀ
Nop
Hꢀꢀ
Hꢀ
Xꢀ
BSTꢀ
Nop
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀreadꢀ(5)
Beginꢀwriteꢀ(5)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Lꢀ
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
Precharge
Precharge all banks(6)ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
OC,ꢀBAꢀꢀ
Readꢀ
ꢀ
Hꢀꢀ Xꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
DESLꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀtoꢀꢀ
Rowꢀactive
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
Xꢀ
ꢀ
NOPꢀꢀ
ꢀ
ꢀ
ꢀ
ContinueꢀburstꢀtoꢀendꢀꢀRowꢀꢀ
Rowꢀꢀactive
ꢀ
ꢀ
Lꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
Hꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
Terminateꢀburst,ꢀꢀ ꢀ
ꢀ
ꢀ
begin new read (7)
ꢀ
Lꢀ
Hꢀꢀ
Lꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
WRIT/WRITAꢀꢀ
ꢀ
Terminateꢀꢀburst,ꢀꢀꢀ
begin write (7,8)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
BA,ꢀRAꢀꢀ
ACTꢀꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
Lꢀꢀ
BA,ꢀA10ꢀꢀ
PRE/PALLꢀꢀ
Terminateꢀburstꢀꢀꢀ ꢀ
ꢀ
Precharging
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
OC,ꢀBAꢀꢀ
Writeꢀ
ꢀ
Hꢀ
ꢀꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
DESLꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Writeꢀrecovering
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
Xꢀ
ꢀ
NOPꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Writeꢀrecovering
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
READ/READAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀstartꢀreadꢀ:ꢀꢀ
DetermineꢀAPꢀ(7,8)
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Lꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
WRIT/WRITAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀnewꢀwriteꢀ:ꢀꢀ
DetermineꢀAPꢀ(7)
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
BA,ꢀRAꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
RAꢀACTꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
TerminateꢀburstꢀPrechargingꢀ(9)
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
ILLEGAL
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
RAS CAS
WE
Address
Command
Action
Readꢀwithꢀautoꢀ
Hꢀ
ꢀ×ꢀꢀ
×ꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
DESLꢀ
Continueꢀburstꢀtoꢀend,ꢀPrechargeꢀꢀ
Precharging
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
xꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀPrecharge
ILLEGAL
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(11)
ꢀ
ꢀ
ꢀ
ꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3)
ILLEGALꢀ(11)
ILLEGAL
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
WriteꢀwithꢀAutoꢀ
ꢀ×ꢀꢀ
DESLꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
Precharge
recovering with auto precharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
×ꢀꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
recovering with auto precharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(11)
ꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Prechargingꢀ
Hꢀꢀ ×ꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
×ꢀꢀ
NOPꢀꢀ
×ꢀꢀ
BSTꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
ꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGAL(3)
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
NopꢀꢀEnterꢀidleꢀafterꢀtRP
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
ꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
RowꢀActivatingꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
NOPꢀꢀ
×ꢀꢀ
BSTꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
Lꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGALꢀ(3,9)
ILLEGALꢀ(3)
ILLEGAL
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
Hꢀ
Lꢀꢀ
Lꢀ
RAS CAS
WE
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Address
×ꢀꢀ
Command
DESLꢀꢀ
NOPꢀꢀ
Action
WriteꢀRecoveringꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
ꢀ
×ꢀꢀ
ꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ Beginꢀread (8)
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀnewꢀwrite
ILLEGALꢀ(3)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
WriteꢀRecoveringꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
withꢀAutoꢀ
×ꢀꢀ
NOPꢀꢀ
Prechargeꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
ꢀ×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(3,8,11)
ꢀ
Lꢀꢀ
Hꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Refreshꢀ
Hꢀꢀ ×ꢀꢀ
×ꢀ
DESLꢀꢀꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRC
Nop,ꢀEnterꢀidleꢀafterꢀtRC
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
NOP/BSTꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL
ꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ILLEGAL
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
ꢀ×ꢀꢀ
ILLEGAL
ModeꢀRegisterꢀ
Accessingꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
ILLEGAL
Hꢀꢀ
Lꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
NOPꢀ
Lꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/WRITEꢀꢀ ILLEGAL
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
×ꢀꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
BA,ꢀRAꢀꢀ
ꢀ
ACT/PRE/PALLꢀꢀ ILLEGALꢀ
REF/MRSꢀ
ꢀ
ꢀ
ꢀ
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Notes:ꢀ
1.ꢀAllꢀentriesꢀassumeꢀthatꢀCKEꢀisꢀactiveꢀ(CKEn-1=CKEn=H).
2.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀPowerꢀDownꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
3.ꢀIllegalꢀtoꢀbankꢀinꢀspecifiedꢀstates;ꢀFunctionꢀmayꢀbeꢀlegalꢀinꢀtheꢀbankꢀindicatedꢀbyꢀBankꢀAddressꢀ(BA),ꢀdependingꢀonꢀtheꢀstateꢀofꢀ
that bank.
4.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀSelf-Refreshꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
5.ꢀIllegalꢀifꢀtRCDꢀisꢀnotꢀsatisfied.
6.ꢀIllegalꢀifꢀtRASꢀisꢀnotꢀsatisfied.
7.ꢀMustꢀsatisfyꢀburstꢀinterruptꢀcondition.
8.ꢀMustꢀsatisfyꢀbusꢀcontention,ꢀbusꢀturnꢀaround,ꢀand/orꢀwriteꢀrecoveryꢀrequirements.
9.ꢀMustꢀmaskꢀprecedingꢀdataꢀwhichꢀdon’tꢀsatisfyꢀtDPL.
10.ꢀIllegalꢀifꢀtRRDꢀisꢀnotꢀsatisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
ꢀ
ꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
—
—
—
X
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
Power-Down(3)ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
Anyꢀstateꢀ
otherꢀthanꢀ
listedꢀaboveꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
Hꢀ
BothꢀBanksꢀIdleꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTable
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
IS42/45R81600E, IS42/45R16800E
CKE RELATED COMMAND TRUTH TABLE(1)
CKE
Current State
Operation
n-1
n
CS
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
RAS
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
CAS
Xꢀ
Xꢀ
Hꢀ
Lꢀ
WE Address
Self-Refreshꢀ(S.R.)ꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀS.R.ꢀ
Self-RefreshꢀRecovery(2)
Self-RefreshꢀRecovery(2)
Illegalꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
—
—
—
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
MaintainꢀS.R.ꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Self-RefreshꢀRecoveryꢀIdleꢀAfterꢀꢀtr c
ꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Idle After tr c
ꢀ
ꢀ
Illegalꢀ
Illegalꢀ
ꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Beginꢀclockꢀsuspendꢀnextꢀcycle(5)
Beginꢀclockꢀsuspendꢀnextꢀcycle(5)
Illegalꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Exitꢀclockꢀsuspendꢀnextꢀcycle(2)
Maintainꢀclockꢀsuspendꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀP.D.ꢀ
EXITꢀP.D.ꢀ-->ꢀIdle(2)
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Power-Downꢀ(P.D.)ꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
Maintainꢀpowerꢀdownꢀmodeꢀ
Lꢀ
ꢀ
Auto-Refreshꢀ
Hꢀ
Lꢀ
ꢀ
Self-Refresh(3)ꢀ
Hꢀ
Lꢀ
Lꢀ
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
Beginꢀclockꢀsuspendꢀnextꢀcycle(4)
Exitꢀclockꢀsuspendꢀnextꢀcycleꢀ
Maintainꢀclockꢀsuspendꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Notes:
1.ꢀHꢀ:ꢀHighꢀlevel,ꢀLꢀ:ꢀlowꢀlevel,ꢀXꢀ:ꢀHighꢀorꢀlowꢀlevelꢀ(Don’tꢀcare).
2.ꢀCKEꢀLowꢀtoꢀHighꢀtransitionꢀwillꢀre-enableꢀCLKꢀandꢀotherꢀinputsꢀasynchronously.ꢀAꢀminimumꢀsetupꢀ
time must be satisfied
beforeꢀanyꢀcommandꢀotherꢀthanꢀEXIT.
3.ꢀPowerꢀdownꢀandꢀSelfꢀrefreshꢀcanꢀbeꢀenteredꢀonlyꢀfromꢀtheꢀbothꢀbanksꢀidleꢀstate.
4.ꢀMustꢀbeꢀlegalꢀcommandꢀasꢀdefinedꢀinꢀOperativeꢀCommandꢀTable.
5. Illegal if tx s r is not satisfied.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
STATE DIAGRAM
Self
Refresh
SELF
SELFꢀexit
REF
Mode
Register
Set
MRS
CBRꢀ(Auto)
Refresh
IDLE
CKE
CKE
ACT
Power
Down
CKE
Active
Power
Down
Row
Active
CKE
BST
Write
BST
Read
Auto Prech
Write
Read
arge
Read
CKE
CKE
CKE
WRITE
SUSPEND
READ
SUSPEND
READ
WRITE
Write
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
CKE
Precharge
POWER
ONꢀ
Precharge
Automatic sequence
ManualꢀInput
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vd d m a x ꢀ
Vd d q m a x
Vinꢀ
Parameters
Rating
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀVd d ꢀ+ꢀ0.5ꢀ
–1.0ꢀtoꢀVd d q ꢀ+ꢀ0.5ꢀ
1ꢀ
Unit
V
V
V
V
W
mA
°Cꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
AllowableꢀPowerꢀDissipationꢀ
output Shorted Current
operatingꢀTemperatureꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vo u t ꢀ
Pd m a x
Ic s
50
ꢀ
ꢀ
To p r
Com.ꢀ
Ind./A1
A2
0ꢀtoꢀ+70ꢀ
-40 to +85
-40 to +105
ꢀ
ꢀ
Ts t g ꢀ
StorageꢀTemperatureꢀ
ꢀ
–55ꢀtoꢀ+150ꢀ
°C
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximum rating conditions for extended periods may affect reliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
DC RECOMMENDED OPERATING CONDITIONS
Taꢀ=ꢀ0oC to +70oCꢀforꢀCom.ꢀtemperature.ꢀTaꢀ=ꢀ-40oC to +85oCꢀforꢀInd./A1ꢀtemperature.ꢀꢀTaꢀ=ꢀ-40oC to +105oC for A2 temperature.
Symbol
Vd d ꢀ
Parameter
Min.
2.3ꢀ
2.3ꢀ
2.0ꢀ
-0.3ꢀ
Typ.
2.5ꢀ
2.5ꢀ
—ꢀ
Max.
2.7ꢀ
2.7ꢀ
Unit
V
V
V
V
ꢀ
SupplyꢀVoltageꢀ
I/OꢀSupplyꢀVoltageꢀ
InputꢀHighꢀVoltageꢀ
InputꢀLowꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vd d q ꢀ
(1)
ꢀ
ꢀ
Vih ꢀ
Vd d q +ꢀ0.3ꢀ
+0.55ꢀ
(2)
Vil ꢀ
—ꢀ
Note:
1.ꢀꢀVih (max)ꢀ=ꢀVd d q +1.2V (p u l s e w id t h < 3n s ).
2.ꢀꢀVilꢀ(min)ꢀꢀ=ꢀ-1.2V (p u l s e w id t h < 3n s ).
3.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
CAPACITANCE CHARACTERISTICS (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVd d ꢀ=ꢀVd d q =ꢀ2.5ꢀ±ꢀ0.2V)
Symbol
Parameter
Min.
Max.
Unit
Cin1ꢀ
Cin2ꢀ
Ci/oꢀ
InputꢀCapacitance:ꢀCLKꢀ
InputꢀCapacitance:Allꢀotherꢀinputꢀpinsꢀ
DataꢀInput/OutputꢀCapacitance:I/Osꢀ
2.5ꢀ ꢀ ꢀ 4.0ꢀ
2.5ꢀ ꢀ ꢀ 5.0ꢀ
4.0ꢀ ꢀ ꢀ 6.5ꢀ
pF
pF
pF
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
DC ELECTRICAL CHARACTERISTICS 1 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
-75
-8
Unit
i
d d 1 (1)
ꢀ
OperatingꢀCurrentꢀ
Oneꢀbankꢀactive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ 120ꢀ
110ꢀ
ꢀ
ꢀ
mA
tc l k ꢀ=ꢀtc l k (min), tr c ꢀ=ꢀtr c (min)
i
d d 2p
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil
(InꢀPower-DownꢀMode)ꢀ CS ≥ Vd d ꢀ-ꢀ0.2V
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil m a x ),ꢀCLKꢀ≤ Vil
CS ≥ Vd d ꢀ-ꢀ0.2V
(m a x ), tc k ꢀ=ꢀ15nsꢀ
ꢀ
ꢀ
2ꢀ
2ꢀ
mA
i
d d 2p s
ꢀ
(
(
m a x
)
1
1
mA
with clock stop
(InꢀPower-DownꢀMode)
(2)
i
d d 2n
Precharge Standby Current
CS ≥ Vd d ꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
c k ꢀ=ꢀ15ns
CS ≥ Vd d ꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
(
m in
)
)
25
15
25
15
mA
mA
(InꢀNonꢀPower-DownꢀMode)
t
I
d d 2n s
Precharge Standby Current
with clock stop
(
m in
(InꢀNonꢀPower-DownꢀMode) All inputs stable
(2)
i
d d 3p
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
(InꢀPower-DownꢀMode)ꢀ
CKEꢀ≤ Vil
c k ꢀ=ꢀ15ns
CKEꢀ≤ Vil
(
m a x ), CS ≥ Vd d ꢀ-ꢀ0.2Vꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
mA
t
i
d d 3p s
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
with clock stop
(InꢀPower-DownꢀMode)
(m a x ),ꢀCLKꢀ≤ Vil
(m a x ),
2
2
mA
CS ≥ Vd d ꢀ-ꢀ0.2V
(2)
id d 3n
Active Standby Current
CS ≥ Vd d ꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
c k ꢀ=ꢀ15ns
(m in )ꢀ
30ꢀ
30ꢀ
mA
(InꢀNonꢀPower-DownꢀMode)
t
I
d d 3n s
Active Standby Current
with clock stop
CS ≥ Vd d ꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
All inputs stable
(m in
)
20
20
mA
(InꢀNonꢀPower-DownꢀMode)ꢀꢀꢀꢀꢀ
OperatingꢀCurrentꢀ
i
d d 4
ꢀ
Allꢀꢀbanksꢀactive,ꢀBLꢀ=ꢀ4,ꢀCLꢀ=ꢀ3,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ 130ꢀ
120ꢀ
ꢀ
ꢀ
mA
t
c k ꢀ=ꢀtc k (min)
id d 5
ꢀ
ꢀ
Auto-RefreshꢀCurrentꢀ
Self-RefreshꢀCurrentꢀ
t
r c ꢀ=ꢀtr c (min), tc l k ꢀ=ꢀtc l k ꢀ(min)ꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ 160ꢀ
140ꢀ
mA
id d 6
CKEꢀ≤ 0.2V
2
2
mA
Notes:
1. Id d (m a x ) is specified at the output open condition.
2.ꢀ Inputꢀsignalsꢀareꢀchangedꢀoneꢀtimeꢀduringꢀ30ns.
DC ELECTRICAL CHARACTERISTICS 2 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
Min
Max
Unit
i
ꢀꢀ
i
il
ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀꢀ≤ꢀVinꢀ≤ꢀVd d , with pins other than
-5
5
µA
theꢀtestedꢀpinꢀatꢀ0Vꢀ
ꢀ
o l
o h
o l
ꢀ
OutputꢀLeakageꢀCurrentꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
Outputꢀisꢀdisabled,ꢀ0Vꢀꢀ≤ꢀVoutꢀ≤ꢀVd d
,
-5
5
µA
V
V
ꢀ
I
o h ꢀꢀ=ꢀꢀ-2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
o l ꢀꢀ=ꢀꢀ2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
d d -0.2
—
V
ꢀ
I
—
0.2
V
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-75
-8
Symbol Parameter
Min. Max.
Min. Max.
Units
tc k 3ꢀ
tc k 2
ClockꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7.5ꢀ
9.6ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
8ꢀ
9.6ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ta c 3ꢀ
ta c 2
AccessꢀTimeꢀFromꢀCLKꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ ꢀ 5.4ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
7ꢀ
8ꢀ
ꢀ
ꢀ
ns
ns
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
ꢀ
6ꢀ
tc h iꢀ
tc l ꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
to h 3ꢀ
to h 2
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2.7ꢀ
2.7ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.7ꢀ
2.7ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
tl z ꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
OutputꢀHIGHꢀImpedanceꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
ꢀ
ns
th z 3ꢀ
th z 2
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2.7ꢀ ꢀ 5.4ꢀ
2.7ꢀ
2.7ꢀ
ꢀ
ꢀ
7ꢀ
8ꢀ
ꢀ
ꢀ
nsꢀ ꢀ
ns
ꢀ
2.7ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
6ꢀ
td s ꢀ
InputꢀDataꢀSetupꢀTime(2)
InputꢀDataꢀHoldꢀTime(2)
AddressꢀSetupꢀTime(2)
AddressꢀHoldꢀTime(2)
CKEꢀSetupꢀTime(2)
CKEꢀHoldꢀTime(2)
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)(2)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
80ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
100K
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td h ꢀ
ꢀ
ta s ꢀ
ꢀ
ta h ꢀ
ꢀ
tc k s ꢀ
tc k h ꢀ
tc s ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tc h ꢀ
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)(2)
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
tr c ꢀ
67.5ꢀ ꢀ —ꢀ
tr a s ꢀ
tr p ꢀ
44ꢀ
19ꢀ
19ꢀ
15ꢀ
15ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
100K
—ꢀ
48
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
19ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tr c d ꢀ
tr r d ꢀ
td p l ꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
—ꢀ
19ꢀ
—ꢀ
16ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtime
—ꢀ
16ꢀ
ꢀ ꢀ ꢀ
td a l ꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
ꢀ
ꢀ
ꢀ
ꢀ
37.5
—
40
—ꢀ
ꢀ
ns
ꢀ ꢀ ꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)
tm r d
td d e
tx s r
ttꢀ
ModeꢀRegisterꢀProgramꢀTimeꢀ
PowerꢀDownꢀExitꢀSetupꢀTimeꢀ
ExitꢀSelf-RefreshꢀtoꢀActiveꢀTime(4)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
15ꢀ
7.5ꢀ
75ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
16ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ꢀ
88ꢀ
TransitionꢀTimeꢀ
0.3ꢀ ꢀ 1.2ꢀ
0.3ꢀ ꢀ 1.2ꢀ
tr e f ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ
ꢀ
ꢀ
Ta ≤ 70oCꢀꢀCom,ꢀInd,ꢀA1,ꢀA2ꢀ
Ta ≤ 85oCꢀꢀInd,ꢀA1,ꢀA2ꢀ
Ta > 85oCꢀꢀA2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
64ꢀ
64ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
64ꢀ
64ꢀ
16ꢀ
ꢀ
ꢀ
ꢀ
msꢀ ꢀ
msꢀ ꢀ
ms
ꢀ
ꢀ
Notes:
1.ꢀ Theꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2. measured with tt =ꢀ1ꢀns.ꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(tr /2 - 0.5) ns should be added to the parameter.
3.ꢀꢀTheꢀreferenceꢀlevelꢀisꢀ1.25Vꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih(min.)ꢀandꢀVil
(max).
4.ꢀꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTa >ꢀ85oC.
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-75
7.5ꢀ
133ꢀ
-8
8ꢀ
UNITS
ns
—ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ—ꢀ
OperatingꢀFrequencyꢀ(CASꢀꢀLatencyꢀ=ꢀ3)ꢀ
125ꢀ
MHz
tc a c
tr c d ꢀ
tr a c
tr c
CASꢀꢀLatencyꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
3ꢀ
6ꢀ
9ꢀ
6ꢀ
3ꢀ
2ꢀ
1ꢀ
3ꢀ
3ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(tr c d + tc a c )
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
6ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
6ꢀ
tr a s ꢀ
tr p ꢀ
3ꢀ
tr r d ꢀ
2ꢀ
tc c d ꢀ
ꢀꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
1ꢀ
td p l ꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
ꢀ
ꢀ
cycle
cycle
td a l ꢀ
ꢀꢀ
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(DuringꢀAuto-Precharge)
tr b d
ꢀꢀ
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime CASꢀꢀLatencyꢀ=ꢀ3ꢀ
(Read)
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
cycle
cycle
cycle
cycle
tw b d ꢀ
ꢀꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀꢀ
(Write)ꢀ
tr q l
ꢀꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime CASꢀꢀLatencyꢀ=ꢀ3ꢀ
(Read)ꢀ
tw d l ꢀ
ꢀꢀ
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀꢀ
(Write)
tp q l
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read) CASꢀꢀLatencyꢀ=ꢀ3ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-2ꢀ
2ꢀ
0ꢀ
2ꢀ
–2ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
cycle
cycle
cycle
cycle
tq m d ꢀ
td m d ꢀ
tm r d ꢀ
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
2ꢀ
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
AC TEST CONDITIONS
Input Load
Output Load
t
CK
t
CHI
t
CL
2.5V
1.25V
1.25V
CLK
50Ω
0V
Z = 50Ω
tCS
tCH
Output
2.5V
50 pF
1.25V
INPUT
0V
t
AC
tOH
OUTPUT
1.25V
1.25V
AC TEST CONDITIONS
Parameter
Rating
ACꢀInputꢀLevelsꢀꢀ
0Vꢀtoꢀ2.5V
1ꢀns
ꢀ
ꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
InputꢀTimingꢀReferenceꢀLevelꢀ
OutputꢀTimingꢀMeasurementꢀReferenceꢀLevelꢀ
1.25V
1.25V
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19
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
Initialization
FUNCTIONAL DESCRIPTION
SDRAMsꢀ mustꢀ beꢀ poweredꢀ upꢀ andꢀ initializedꢀ inꢀ aꢀ
predefined manner.
Theꢀ128MbꢀSDRAMsꢀareꢀquad-bankꢀDRAMsꢀwhichꢀoperateꢀ
atꢀ2.5Vꢀandꢀincludeꢀaꢀsynchronousꢀinterfaceꢀ(allꢀsignalsꢀ
are registered on the positive edge of the clock signal,
CLK).ꢀEachꢀofꢀtheꢀ33,554,432-bitꢀbanksꢀisꢀorganizedꢀasꢀ
4,096ꢀrowsꢀbyꢀ512ꢀcolumnsꢀbyꢀ16ꢀbitsꢀorꢀ4,096ꢀrowsꢀbyꢀ
1,024 columns by 8 bits.
Theꢀ128MꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ
toꢀVd d ꢀandꢀVd d q (simultaneously) and the clock is stable
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ
A 100µs delay is required prior to issuing any command
other than a COMMANDꢀINHIBIT or a NOP.ꢀTheꢀCOMMANDꢀ
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100usꢀperiodꢀandꢀ
should continue at least through the end of the period.
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented;ꢀ
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorꢀ
WRITEꢀcommand.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀ
withꢀtheꢀACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀ
and row to be accessed (BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀA0-
A11 select the row).ꢀTheꢀaddressꢀbitsꢀA0-A9ꢀ(x8);ꢀA0-A8ꢀ(x16)
registeredꢀcoincidentꢀwithꢀtheꢀREADꢀorꢀWRITEꢀcommandꢀ
are used to select the starting column location for the
burst access.
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ
be applied once the 100µs delay has been satisfied. All
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀanꢀ
idle state after which at least two AUTOꢀREFRESH cycles
must be performed. After the AUTOꢀREFRESH cycles are
complete,ꢀ theꢀ SDRAMꢀ isꢀ thenꢀ readyꢀ forꢀ modeꢀ registerꢀ
programming.
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ
any operational command because it will power up in an
unknown state.
Priorꢀ toꢀ normalꢀ operation,ꢀ theꢀ SDRAMꢀ mustꢀ beꢀ initial-
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ
covering device initialization, register definition, command
descriptions and device operation.
20
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Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
INITIALIꢀE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
To+1
t
CL
Tp+1
Tp+2
Tp+3
tCK
t
CH
CLK
CKE
tCKS t
CKH
t
CMH
tCMS
t
CMH
tCMS
tCMH tCMS
AUTO
REFRESH
AUTO
Load MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
REFRESH
DQM/
DQML, DQMH
t
t
t
AS
tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
AS
tAH
ALL BANKS
CODE
SINGLE BANK
ALL BANKS
AS
tAH
BA0, BA1
DQ
CODE
t
RP
t
RC
t
RC
tMRD
T
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
and CLK stable all banks
DON'T CARE
T = 100µs Min.
Notes:
1. If CSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.
3.ꢀꢀJEDECꢀandꢀPC100ꢀspecifyꢀthreeꢀclocks.
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.
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21
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
AUTO-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
tCK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
tAS
tAH
High-Z
t
RP
t
RC
t
RC
DON'T CARE
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
22
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
SELF-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
tCH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
tRAS
t
CKS
tCMS
tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
High-Z
tRP
tXSR
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1. Self-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTa >ꢀ85oC.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
23
Rev. A
04/15/2010
initiatingꢀtheꢀsubsequentꢀoperation.
Violatingꢀeitherꢀofꢀtheseꢀ
IS42/45R81600E, IS42/45R16800E
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀ
ModeꢀregisterꢀbitsꢀM0-M2ꢀspecifyꢀtheꢀburstꢀlength,ꢀM3ꢀ
specifiesthetypeofburst(sequentialorinterleaved),ꢀM4-ꢀM6ꢀ
specifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀ
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ
M11ꢀareꢀreservedꢀforꢀfutureꢀuse.
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
until it is programmed again or the device loses power.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle, and the controller must wait the specified time before
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
0
Defined Standard Operation
All Other States Reserved
—
—
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0"
1
24
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Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
BURST LENGTH
ing that the burst will wrap within the block if a boundary
isꢀreached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A8ꢀ(x16)ꢀ
whenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo;ꢀbyꢀA2-A8ꢀ(x16)ꢀwhenꢀ
theꢀburstꢀlengthꢀisꢀsetꢀtoꢀfour;ꢀandꢀbyꢀA3-A8ꢀ(x16)ꢀwhenꢀtheꢀ
burstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀ
address bit(s) is (are) used to select the starting location
withinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀ
the boundary is reached.
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀ
with the burst length being programmable, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-
mines the maximum number of column locations that can
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ
command to generate arbitrary burst lengths.
BurstꢀType
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀM3.
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀ
or incompatibility with future versions may result.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ
columnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within this block, mean-
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ
the burst length, the burst type and the starting column
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Length
Type = Sequential
Type = Interleaved
A 0
2
0
1
0-1
1-0
0-1
1-0
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
ꢀ
1ꢀ
1ꢀ
A 2
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
ꢀ2-3-4-5-6-7-0-1ꢀ
ꢀ3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
ꢀ0ꢀ
1ꢀ
8ꢀ
ꢀ
ꢀ1ꢀ
0ꢀ
0ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
1ꢀ
1ꢀ
ꢀ
ꢀ
Fullꢀ
Pageꢀ
(y)
nꢀ=ꢀA0-A7ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...
…Cn - 1,
ꢀ
(location 0-y)
Cn…
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25
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
CAS Latency
Operating Mode
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ
the registrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ
three clocks.
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ
toꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀareꢀ
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ
the latency is m clocks, the data will be available by clock
edge n + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycle time is such that all relevant access times are met,
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
isꢀprogrammedꢀtoꢀtwoꢀclocks,ꢀtheꢀDQsꢀwillꢀstartꢀdrivingꢀ
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀTheꢀAllowableꢀOperatingꢀFrequencyꢀ
table indicates the operating frequencies at which each
CAS latency setting can be used.
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ
write accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
-75
-8
CAS Latency = 2
CAS Latency = 3
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ
or incompatibility with future versions may result.
104
104
133
125
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
CHIP OPERATION
BANK/ROW ACTIVATION
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ
toꢀaꢀbankꢀwithinꢀtheꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀbeꢀ
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ
which selects both the bank and the row to be activated
(see ActivatingꢀSpecificꢀRowꢀWithinꢀSpecificꢀBank).
CLK
HIGH
CKE
CS
After opening a row (issuingꢀanꢀACTIVEꢀcommand),ꢀaꢀREADꢀ
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ
the tr c d ꢀspecification.ꢀMinimumꢀtr c d should be divided by
the clock period and rounded up to the next whole number
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ
entered.ꢀForꢀexample,ꢀaꢀtr c d specification of 18ns with a
125ꢀMHzꢀclockꢀ(8nsꢀperiod)ꢀresultsꢀinꢀ2.25ꢀclocks,ꢀroundedꢀ
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[tr c d ꢀ(MIN)/tc k ] ≤ꢀ3.ꢀ(Theꢀsameꢀ
procedure is used to convert other specification limits from
time units to clock cycles).
RAS
CAS
WE
A0-A11
BA0, BA1
ROW ADDRESS
BANK ADDRESS
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ
same bank can only be issued after the previous active
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ
same bank is defined by tr c .
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ
issuedwhilethefirstbankisbeingaccessed, whichresults
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ
different banks is defined by tr r d .
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
t
RCD
DON'T CARE
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27
Rev. A
04/15/2010
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.Theꢀ128Mbꢀ
IS42/45R81600E, IS42/45R16800E
READS
READ COMMAND
READꢀ burstsꢀ areꢀ initiatedꢀ withꢀ aꢀ READꢀ command,ꢀ asꢀ
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.
CLK
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀREADꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀ
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-
lowing illustrations, auto precharge is disabled.
HIGH
CKE
CS
RAS
DuringꢀREADꢀbursts,ꢀtheꢀvalidꢀdata-outꢀelementꢀfromꢀtheꢀ
starting column address will be available following the
CASꢀlatencyꢀafterꢀtheꢀREADꢀcommand.ꢀEachꢀsubsequentꢀ
data-out element will be valid by the next positive clock
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtiming
for each possible CAS latency setting.
CAS
WE
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀREADꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note:ꢀA9ꢀisꢀ"Don'tꢀCare"ꢀforꢀx16.
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀtwoꢀclocksꢀforꢀoutputꢀbuffers)ꢀ
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀthatꢀtruncatedꢀtheꢀREADꢀcommand.ꢀIfꢀnot,ꢀtheꢀ
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ
be invalid.
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesbefore
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀConsecutiveꢀREADꢀBurstsꢀforꢀCASꢀlatenciesꢀofꢀ
two and three; data element n +ꢀ3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀ
SDRAMꢀusesꢀaꢀpipelinedꢀarchitectureꢀandꢀthereforeꢀdoesꢀ
not require the 2n rule associated with a prefetch architec-
ture.ꢀAꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀ
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ
read accesses can be performed to the same bank, as
shownꢀinꢀRandomꢀREADꢀAccesses,ꢀorꢀeachꢀsubsequentꢀ
READꢀmayꢀbeꢀperformedꢀtoꢀaꢀdifferentꢀbank.
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀzeroꢀclocksꢀforꢀinputꢀbuffers)ꢀ
to ensure that the written data is not masked.
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀWRITEꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-
mediately following the last (or last desired) data element
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ
avoided. In a given system design, there may be a pos-
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ
a single-cycle delay should occur between the last read
dataꢀandꢀtheꢀWRITEꢀcommand.
Aꢀfixed-lengthꢀREADꢀburstꢀmayꢀbeꢀfollowedꢀby,ꢀorꢀtruncatedꢀ
with, aPRECHARGE commandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
sameꢀbank.TheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
28
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ
diagram for each possible CAS latency; data element n +
3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀ
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequent command to the same bank cannot be issued
until tr p ꢀisꢀmet.ꢀNoteꢀthatꢀpartꢀofꢀtheꢀrowꢀprechargeꢀtimeꢀisꢀ
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
and address buses be available at the appropriate time to
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.TheꢀBURSTꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cycles before
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleCASlatency;dataelementn+ꢀ3ꢀisꢀtheꢀlastꢀdesiredꢀ
data element of a longer burst.
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29
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
D
OUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
DON'T CARE
30
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Rev. A
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IS42/45R81600E, IS42/45R16800E
CONSECUTIVE READ BURSTS
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 3
DON'T CARE
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31
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
RANDOM READ ACCESSES
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
32
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Rev. A
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IS42/45R81600E, IS42/45R16800E
READ BURST TERMINATION
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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33
Rev. A
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IS42/45R81600E, IS42/45R16800E
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
t
LZ
tOH
t
OH
tOH
tOH
tOH
DQ
DOUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m+
3
D
OUT
b
tAC
tAC
tAC
tAC
tAC
tAC
tRCD - BANK 0
tRRD
CAS Latency - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
34
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Rev. A
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IS42/45R81600E, IS42/45R16800E
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
tAS tAH
ROW
tAS tAH
BA0, BA1
BANK
BANK
tAC
tAC
tAC
tAC
tAC
tAC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+
1
DQ
tLZ
t
OH
t
OH
t
OH
tOH
t
OH
tOH
tRCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1) CAS latency = 2, Burst Length = Full Page
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
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Rev. A
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IS42/45R81600E, IS42/45R16800E
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
OH
t
OH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
tAC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1) CAS latency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
36
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Rev. A
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IS42/45R81600E, IS42/45R16800E
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
RQL
High-Z
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
t
RQL
High-Z
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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37
Rev. A
04/15/2010
precharge.TheꢀdisadvantageꢀofꢀtheꢀPRECHARGEcommand
IS42/45R81600E, IS42/45R16800E
WRITES
AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ
n + 1 is either the last of a burst of two or the last desired
ofꢀaꢀlongerꢀburst.ꢀTheꢀ128MbꢀSDRAMꢀusesꢀaꢀpipelinedꢀ
architecture and therefore does not require the 2n rule as-
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ
can be initiated on any clock cycle following a previous
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ
a page can be performed to the same bank, as shown in
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ
be performed to a different bank.
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ
shownꢀinꢀWRITEꢀCommandꢀdiagram.
WRITE COMMAND
CLK
HIGH
CKE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀ
command.ꢀOnceꢀtheꢀREADꢀcomꢀmandꢀisꢀregistered,ꢀtheꢀ
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
CS
RAS
CAS
WE
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
same bank (provided that auto precharge was not acti-
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtd p l after the
clock edge at which the last desired input data element
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtd p l of
at least one clock plus time, regardless of frequency. In
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ
must be used to mask input data for the clock edge prior
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-
CHARGEꢀdiagram.ꢀDataꢀn+1 is either the last of a burst
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ
same bank cannot be issued until tr p is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note:ꢀA9ꢀisꢀ"Don'tꢀCare"ꢀforꢀx16.
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ
following illustrations, auto precharge is disabled.
Inthecaseofafixed-lengthburstbeingexecutedtocomple-
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-in element will be
registeredcoincidentwiththeWRITEꢀcommand.Subsequent
data elements will be registered on each successive posi-
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ
assuming no other commands have been initiated, the
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-
tinue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
is that it requires that the command and address buses be
availableattheappropriatetimetoissuethecommand;the
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ
used to truncate fixed-length or full-page bursts.
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ
will be the input data applied one clock previous to the
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ
BurstꢀTermination,ꢀwhereꢀdataꢀn is the last desired data
element of a longer burst.
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ
data provided coincident with the new command applies to
the new command.
38
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE BURST
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE TO WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
RANDOM WRITE CYCLES
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
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39
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
D
IN n+1
DIN n+2
DON'T CARE
40
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Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
ADDRESS
DQ
PRECHARGE
WRITE
NOP
NOP
NOP
NOP
ACTIVE
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
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41
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
42
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
tCL
t
CH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
tDS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
2
DIN m+3
DQ
t
RCD
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
43
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
ALTERNATING BANK WRITE ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
tDS
t
DH
tDS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN
b
D
IN b+
1
D
IN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
DPL - BANK 0
tRP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tDPL - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
44
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Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
CLOCK SUSPEND
of a suspended internal clock edge is ignored; any data
presentꢀonꢀtheꢀDQꢀpinsꢀremainsꢀdriven;ꢀandꢀburstꢀcountersꢀ
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode occurs when a column access/burst
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ
the synchronous logic.
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ
the internal clock and related operation will resume on the
subsequent positive clock edge.
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ
Any command or data present on the input pins at the time
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
D
IN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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45
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCKS tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
tAS tAH
tAS tAH
BA0, BA1
BANK
BANK
tDS tDH
tAC
tAC
tHZ
DQ
DOUT
m
D
OUT m+1
DIN e
D
IN e+1
t
LZ
tOH
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled.
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
46
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
allꢀbanks.Theꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀ
IS42/45R81600E, IS42/45R16800E
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀ(seeꢀfigure)ꢀisꢀusedꢀtoꢀdeac-
PRECHARGE Command
tivate the open row in a particular bank or the open row in
CLK
access some specified time (tr p )ꢀafterꢀtheꢀPRECHARGEꢀ
command is issued.Input A10 determines whether one or
all banks are to be precharged, and in the case where only
oneꢀbankꢀisꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀBA1ꢀselectꢀtheꢀ
bank.ꢀWhenꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀ
BA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare.”ꢀOnceꢀaꢀbankꢀhasꢀbeenꢀ
precharged, it is in the idle state and must be activated
priorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀ
that bank.
HIGH
CKE
CS
RAS
CAS
WE
POWER-DOWN
Power-downꢀoccursꢀifꢀCKEꢀisꢀregisteredꢀLOWꢀcoincidentꢀ
withꢀaꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀwhenꢀnoꢀaccessesꢀ
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Enteringꢀ power-downꢀ deactivatesꢀ theꢀ inputꢀ andꢀ outputꢀ
buffers,ꢀexcludingꢀCKE,ꢀforꢀmaximumꢀpowerꢀsavingsꢀwhileꢀ
inꢀstandby.ꢀTheꢀdeviceꢀmayꢀnotꢀremainꢀinꢀtheꢀpower-downꢀ
stateꢀlongerꢀthanꢀtheꢀrefreshꢀperiodꢀ(64ms)ꢀsinceꢀnoꢀrefreshꢀ
operations are performed in this mode.
A0-A9, A11
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
Theꢀpower-downꢀstateꢀisꢀexitedꢀbyꢀregisteringꢀaꢀNOPꢀorꢀ
COMMANDꢀINHIBITꢀandꢀCKEꢀHIGHꢀatꢀtheꢀdesiredꢀclockꢀ
edge (meeting tc k s ). See figure below.
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
tRCD
tRAS
t
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than 64ms
DON'T CARE
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47
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
tCH
CLK
CKE
tCKS
t
CKH
t
CKS
tCKS
t
CMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/DQML
DQMH
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
48
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Rev. A
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IS42/45R81600E, IS42/45R16800E
BURST READ/SINGLE WRITE
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occurs are defined below.
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccess
columns according to the programmed burst length and
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ
=ꢀ0).
READ with Auto Precharge
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.
CONCURRENT AUTO PRECHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
whenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀthreeꢀclocksꢀpriorꢀ
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bank m is registered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
while an access command with auto precharge enabled is
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSI
READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK n,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tDPL - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
49
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE with Auto Precharge
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
WRITE tobankmwillinterruptaWRITE onbanknwhen
3.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀwhenꢀ
registered, with the data-out appearing (CAS latency)
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtd p l
is met, where td p l ꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀ
registered.ꢀTheꢀlastꢀvalidꢀWRITE to bank n will be data-in
registeredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ
td p l is met, where td p l ꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ
bank m.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
t
RP - BANK n
Internal States
tDPL - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tOH
t
AC
DOUT m
DQ
tHZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1) CAS latency = 2, Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
51
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tOH
t
OH
tOH
tOH
t
t
t
RCD
RAS
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
52
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
tAH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
t
AC
D
OUT
m
t
LZ
tHZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
tRP
Notes:
1) CAS latency = 2, Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
53
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ROW
AS
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+1
D
OUT m+2
DOUT m+3
t
LZ
t
OH
t
OH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
tRP
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
SINGLE WRITE WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
ACTIVE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
tCMS tCMH
DQM/DQML, DQMH
tAS tAH
A0-A9, A11
A10
COLUMN m(2)
ROW
ROW
BANK
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BA0, BA1
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tDPL
tRP
tRAS
DON'T CARE
tRC
Notes:
1) Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
3) tr a s must not be violated.
Integrated Silicon Solution, Inc. — www.issi.com
55
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN m(2)
ROW
A0-A9, A11
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
tAS tAH
BA0, BA1
BANK
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tDPL(3)
tRP
tRAS
tRC
DON'T CARE
Notes:
1) Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
3) tr a s must not be violated.
56
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
ALL BANKS
ROW
AS
tAH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
tDS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
t
DH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
t
t
t
RCD
RAS
RC
t
DPL(3)
t
RP
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
3) tr a s must not be violated.
Integrated Silicon Solution, Inc. — www.issi.com
57
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
t
t
t
RCD
RAS
RC
tDPL
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
ORDERING INFORMATION - VD D = 2.5V
Commercial Range: 0°C to +70°C
Frequency
Speed (ns) Order Part No.
Package
ꢀ133ꢀMHzꢀ
7.5ꢀ
ꢀ
IS42R16800E-75TLꢀ 54-PinꢀTSOPII,ꢀLead-freeꢀꢀꢀꢀ
IS42R16800E-75BLꢀ 54-ballꢀBGA,ꢀLead-freeꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ125ꢀMHzꢀ
8ꢀ
ꢀ
IS42R16800E-8TLꢀ
IS42R16800E-8BLꢀ
54-PinꢀTSOPII,ꢀLead-freeꢀꢀꢀꢀ
54-ballꢀBGA,ꢀLead-freeꢀ
ꢀ
ꢀ
Industrial Range: -40°C to +85°C
Frequency
Speed (ns) Order Part No.
Package
ꢀ133ꢀMHzꢀ
7.5ꢀ
ꢀ
IS42R16800E-75TLIꢀ 54-PinꢀTSOPII,ꢀLead-freeꢀ ꢀ
IS42R16800E-75BLIꢀ 54-ballꢀBGA,ꢀLead-free
ꢀ
ꢀ
ꢀ
ꢀ125ꢀMHzꢀ
8ꢀ
ꢀ
IS42R16800E-8TLIꢀ 54-PinꢀTSOPII,ꢀLead-freeꢀꢀꢀꢀ
IS42R16800E-8BLIꢀ 54-ballꢀBGA,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ORDERING INFORMATION - VD D = 2.5V
Automotive Range A1: -40°C to +85°C
Frequency Speed (ns) Order Part No.
Package
ꢀ133ꢀMHzꢀ
7.5ꢀ
ꢀ
IS45R16800E-75TLA1ꢀ
IS45R16800E-75BLA1ꢀ
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
ꢀ
ꢀ
ꢀ125ꢀMHzꢀ
8ꢀ
IS45R16800E-8BLA1ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
Automotive Range A2: -40°C to +105°C
Frequency Speed (ns) Order Part No.
Package
ꢀ133ꢀMHzꢀ
ꢀ125ꢀMHzꢀ
7.5ꢀ
8ꢀ
IS45R16800E-75BLA2ꢀ
IS45R16800E-8BLA2ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀ
Notes:
1.ꢀContactꢀProductꢀMarketingꢀforꢀLeadedꢀpartsꢀsupport.
2.ꢀPartꢀnumbersꢀwithꢀ"L"ꢀareꢀleadfree,ꢀandꢀRoHSꢀcompliant.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
59
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
60
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/15/2010
IS42/45R81600E, IS42/45R16800E
Integrated Silicon Solution, Inc. — www.issi.comꢀ
61
Rev. A
04/15/2010
相关型号：
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