IS45S16800E-7TLA2-TR [ISSI]
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54;
| 型号： | IS45S16800E-7TLA2-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总62页 (文件大小：885K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS45S81600E
IS45S16800E
16M x 8, 8M x16
DECEMBER 2011
128Mb SYNCHRONOUS DRAM
OVERVIEW
FEATURES
ISSI'sꢀ128MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ
dataꢀtransferꢀusingꢀpipelineꢀarchitecture.ꢀꢀAllꢀinputsꢀandꢀ
outputsꢀsignalsꢀreferꢀꢀtoꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.
Theꢀ128MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ
•ꢀ Clockꢀfrequency:ꢀ166,ꢀ143ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positiveꢀclockꢀedge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Powerꢀsupply
ꢀ ꢀ
ꢀ
Vddꢀ
Vddq ꢀ ꢀ
ꢀ
IS45S81600Eꢀ
IS45S16800Eꢀ
IS45S81600Eꢀ
ꢀ IS45S16800Eꢀ
•ꢀ LVTTLꢀinterface
ꢀ3.3Vꢀ 3.3Vꢀꢀ
4Mꢀx8ꢀx4ꢀBanksꢀ 2Mꢀx16ꢀx4ꢀBanksꢀ
ꢀ3.3Vꢀ 3.3Vꢀꢀ
54-pinꢀTSOPIIꢀ
54-pinꢀTSOPII
ꢀ
ꢀ
ꢀ
54-ballꢀBGA
ꢀ
•ꢀ Programmableꢀburstꢀlengthꢀꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
ꢀ
ꢀ
ꢀ
•ꢀ Programmableꢀburstꢀsequence:ꢀꢀ
Sequential/Interleaveꢀ
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ SelfꢀRefresh
KEY TIMING PARAMETERS
Parameter
-6
-7
Unit
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ16ꢀmsꢀ(A2ꢀgrade)ꢀorꢀ
64ꢀmsꢀ(A1ꢀgrade)
ClkꢀCycleꢀTimeꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
6ꢀ
10ꢀ
ꢀ
7ꢀ
10ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
nsꢀ
ns
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
ClkꢀFrequencyꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
166ꢀ
100ꢀ
143ꢀ
100ꢀ
Mhzꢀ
Mhz
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀꢀ
operationsꢀcapability
AccessꢀTimeꢀꢀfromꢀClockꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
5.4ꢀ
6.5ꢀ
5.4ꢀ
6.5ꢀ
nsꢀ
ns
•ꢀ AutomotiveꢀTemperatureꢀRange:ꢀ
OptionꢀA1:ꢀ-40oCꢀtoꢀ+85oC
OptionꢀA2:ꢀ-40oCꢀtoꢀ+105oC
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwith-
outꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀ
theꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀ
expectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀ
SiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
1
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
DEVICE OVERVIEW
Aꢀself-timedꢀrowꢀprechargeꢀinitiatedꢀatꢀtheꢀendꢀofꢀtheꢀburstꢀ
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ
enabled.ꢀ Prechargeꢀoneꢀbankꢀwhileꢀaccessingꢀoneꢀofꢀtheꢀ
otherꢀthreeꢀbanksꢀwillꢀhideꢀtheꢀprechargeꢀcyclesꢀandꢀprovideꢀ
seamless,ꢀhigh-speed,ꢀrandom-accessꢀoperation.
Theꢀ 128Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ
random-accessꢀmemoryꢀdesignedꢀtoꢀoperateꢀinꢀ3.3VꢀVddꢀ
andꢀ3.3VꢀVddq memoryꢀsystemsꢀcontainingꢀ134,217,728ꢀ
bits.ꢀꢀInternallyꢀconfiguredꢀasꢀaꢀquad-bankꢀDRAMꢀwithꢀaꢀ
synchronousꢀinterface.ꢀꢀEachꢀ33,554,432-bitꢀbankꢀisꢀorga-
nizedꢀasꢀ4,096ꢀrowsꢀbyꢀ512ꢀcolumnsꢀbyꢀ16ꢀbitsꢀorꢀ4,096ꢀ
rowsꢀbyꢀ1,024ꢀcolumnsꢀbyꢀ8ꢀbits.
SDRAMꢀreadꢀandꢀwriteꢀaccessesꢀareꢀburstꢀorientedꢀstartingꢀ
atꢀaꢀselectedꢀlocationꢀandꢀcontinuingꢀforꢀaꢀprogrammedꢀ
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ
commandꢀinꢀconjunctionꢀwithꢀaddressꢀbitsꢀregisteredꢀareꢀ
usedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀ
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ
registeredꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀcolumnꢀlocationꢀ
forꢀtheꢀburstꢀaccess.
Theꢀ128MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ
andꢀaꢀpower-saving,ꢀpower-downꢀmode.ꢀAllꢀsignalsꢀareꢀ
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.
Theꢀ128MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ
dataꢀatꢀaꢀhighꢀdataꢀrateꢀwithꢀautomaticꢀcolumn-addressꢀ
generation,ꢀtheꢀabilityꢀtoꢀinterleaveꢀbetweenꢀinternalꢀbanksꢀ
toꢀ hideꢀ prechargeꢀ timeꢀ andꢀ theꢀ capabilityꢀ toꢀ randomlyꢀ
changeꢀ columnꢀ addressesꢀ onꢀ eachꢀ clockꢀ cycleꢀ duringꢀ
burstꢀaccess.
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ
1,ꢀ2,ꢀ4ꢀandꢀ8ꢀlocationsꢀorꢀfullꢀpage,ꢀwithꢀaꢀburstꢀterminateꢀ
option.ꢀ
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONlY)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
REFRESH
CONTROLLER
MODE
REGISTER
2
DQ 0-15
12
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
VSS
NC
DQM
CLK
CKE
NC
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
A0-A9ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
WEꢀ
WriteꢀEnable
ꢀ
DQMꢀ
Vddꢀ
DataꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ7ꢀ
Vssꢀ
Ground
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Vddqꢀ
Vssqꢀ
NCꢀ
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
VDD
VSS
DQML
WE
CAS
RAS
CS
NC
DQMH
CLK
CKE
NC
BA0
BA1
A10
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
A0-A8ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
WEꢀ
WriteꢀEnable
ꢀ
DQMLꢀ x16ꢀLowerꢀByte,ꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByte,ꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
Power
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
PIN CONFIGURATION
54-baꢀꢀ BGA for x16ꢀ(TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ8.00ꢀmmꢀBody,ꢀ0.8ꢀmmꢀBallꢀPitch)
PACKAGEꢀCODE:ꢀ54Bꢀ(8x8)ꢀꢀ
1 2 3 4 5 6 7 8 9
A
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
B
C
D
E
F
DQ8 NC
VSS
DQMH CLK CKE
G
H
J
NC
A8
A11
A7
A9
A6
A4
A0
A3
A1
A10
VSS
A5
A2 VDD
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
A0-A8ꢀ
ꢀ
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
DQMLꢀ x16ꢀLowerꢀByteꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByteꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
Power
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
Integrated Silicon Solution, Inc. — www.issi.comꢀ
5
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
PIN FUNCTIONS
Symboꢀ
A0-A11ꢀ
ꢀ
Type
InputꢀPin
ꢀ
Function (In Detaiꢀ)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
AddressꢀInputs:ꢀA0-A11ꢀareꢀsampledꢀduringꢀtheꢀACTIVE
commandꢀ(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(columnꢀaddressꢀA0-
A9ꢀ(x8),ꢀorꢀA0-A8ꢀ(x16);ꢀwithꢀA10ꢀdefiningꢀautoꢀprecharge)ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀ
ofꢀtheꢀmemoryꢀarrayꢀinꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀ
commandꢀtoꢀdetermineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀ
selectedꢀbyꢀBA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀ
LOADꢀMODEꢀREGISTERꢀcommand.
ꢀ
ꢀ
ꢀ
BA0,ꢀBA1
ꢀ
ꢀ
ꢀ
ꢀ
InputꢀPin
InputꢀPin
InputꢀPin
ꢀ
ꢀ
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CASꢀ
CAS,ꢀinꢀconjunctionꢀwithꢀtheꢀRASꢀandꢀꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
CKEꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refreshꢀmode.ꢀCKEꢀisꢀanꢀasynchronousꢀinput.
ꢀ
ꢀ
CLKꢀ
ꢀ
ꢀ
InputꢀPin
InputꢀPin
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
areꢀacquiredꢀinꢀsynchronizationꢀwithꢀtheꢀrisingꢀedgeꢀofꢀthisꢀpin.
CSꢀ
TheꢀCSꢀinputꢀdeterminesꢀwhetherꢀcommandꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀ
CommandꢀinputꢀisꢀenabledꢀwhenꢀCSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
deviceꢀremainsꢀinꢀtheꢀpreviousꢀstateꢀwhenꢀCSꢀisꢀHIGH.
ꢀ
ꢀ
DQML,ꢀ
DQMHꢀ
ꢀ
ꢀ
InputꢀPin
ꢀ
ꢀ
DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀInꢀread
mode,DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenDQMLꢀorDQMHꢀisꢀLOW,ꢀtheꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀtoꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenDQML/DQMHꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀtoꢀ
OEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀinputꢀbuffer.ꢀ
WhenꢀDQMLꢀorꢀDQMHꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀ
canꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀmaskedꢀ
andꢀcannotꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀForꢀIS45S16800Eꢀonly.
ꢀ
DQMꢀ
ꢀ
InputꢀPinꢀ
ForꢀIS45S81600Eꢀonly.
ꢀDQ0-DQ7ꢀorꢀꢀꢀꢀꢀ
ꢀ DQ0-DQ15ꢀ
ꢀ Input/Outputꢀ
DataꢀonꢀtheꢀDataꢀBusꢀisꢀlatchedꢀonꢀDQꢀpinsꢀduringꢀWriteꢀcommands,ꢀandꢀbufferedꢀfor
outputꢀafterꢀReadꢀcommands.
ꢀ
ꢀ
ꢀ
RASꢀ
ꢀ
InputꢀPin
ꢀ
RAS,ꢀinꢀconjunctionꢀwithꢀCASꢀandꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ"Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
ꢀ
WEꢀ
ꢀ
ꢀInputꢀPin
ꢀ
WE,ꢀinꢀconjunctionꢀwithꢀRASꢀandꢀCAS,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ"Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddqꢀ
Vddꢀ
ꢀPowerꢀSupplyꢀPin
ꢀPowerꢀSupplyꢀPin
ꢀPowerꢀSupplyꢀPin
ꢀPowerꢀSupplyꢀPin
ꢀ
ꢀ
ꢀ
ꢀ
Vddq isꢀtheꢀoutputꢀbufferꢀpowerꢀsupply.
Vddꢀisꢀtheꢀdeviceꢀinternalꢀpowerꢀsupply.
Vssqꢀisꢀtheꢀoutputꢀbufferꢀground.
Vssqꢀ
Vssꢀ
Vssꢀisꢀtheꢀdeviceꢀinternalꢀground.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
GENERAl DESCRIPTION
READ
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
andꢀstartsꢀaꢀburstꢀreadꢀaccessꢀtoꢀanꢀactiveꢀrow.ꢀꢀInputsꢀA0-
A9ꢀ(x8);ꢀA0-A8ꢀ(x16)ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀ
WhenꢀA10ꢀisꢀHIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀ
PRECHARGEꢀcommand.ꢀꢀWhenꢀtheꢀautoꢀprechargeꢀisꢀ
selected,ꢀtheꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀ
theꢀendꢀofꢀtheꢀREADꢀburst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀ
subsequentꢀaccessesꢀwhenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀ
selected.ꢀꢀDQ’sꢀreadꢀdataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀ
theꢀDQMꢀinputsꢀtwoꢀclocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀ
signalꢀwasꢀregisteredꢀHIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀ
beꢀHigh-Zꢀtwoꢀclocksꢀlater.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀ
whenꢀtheꢀDQMꢀsignalꢀwasꢀregisteredꢀLOW.
PRECHARGEꢀfunctionꢀinꢀconjunctionꢀwithꢀaꢀspecificꢀREADꢀ
orꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀ
command,ꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀdisabled.ꢀ
AUTOꢀPRECHARGEꢀdoesꢀnotꢀapplyꢀexceptꢀinꢀfull-pageꢀ
burstꢀ mode.ꢀ Uponꢀ completionꢀ ofꢀ theꢀ READꢀ orꢀWRITEꢀ
burst,ꢀaꢀprechargeꢀofꢀtheꢀbank/rowꢀthatꢀisꢀaddressedꢀisꢀ
automaticallyꢀperformed.
AUTO REFRESH COMMAND
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ(trc)ꢀisꢀ
requiredꢀforꢀaꢀsingleꢀrefreshꢀoperation,ꢀandꢀnoꢀotherꢀcom-
mandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀcommandꢀ
isꢀexecutedꢀatꢀleastꢀ4096ꢀtimesꢀforꢀeveryꢀTref.ꢀDuringꢀanꢀ
AUTOꢀREFRESHꢀcommand,ꢀaddressꢀbitsꢀareꢀ“Don’tꢀCare”.ꢀ
ThisꢀcommandꢀcorrespondsꢀtoꢀCBRꢀAuto-refresh.
WRITE
Aꢀburstꢀwriteꢀaccessꢀtoꢀanꢀactiveꢀrowꢀisꢀinitiatedꢀwithꢀtheꢀ
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀandꢀ
theꢀstartingꢀcolumnꢀlocationꢀisꢀprovidedꢀbyꢀinputsꢀA0-A9ꢀ
(x8);ꢀA0-A8ꢀ(x16).ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀ
usedꢀisꢀdeterminedꢀbyꢀA10.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ
theꢀburstꢀreadꢀandꢀwriteꢀoperationsꢀbyꢀtruncatingꢀeitherꢀ
fixed-lengthꢀ orꢀ full-pageꢀ burstsꢀ andꢀ theꢀ mostꢀ recentlyꢀ
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ
TERMINATE.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
openꢀforꢀsubsequentꢀaccesses.
Aꢀmemoryꢀarrayꢀisꢀwrittenꢀwithꢀcorrespondingꢀinputꢀdataꢀ
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/columnꢀlocation.
COMMAND INHIBIT
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled
NO OPERATION
WhenꢀCSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ
commandsꢀ fromꢀ beingꢀ registeredꢀ duringꢀ idleꢀ orꢀ waitꢀ
states.
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ
openꢀrowꢀinꢀaꢀparticularꢀbankꢀorꢀtheꢀopenꢀrowꢀinꢀallꢀbanks.ꢀ
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ
whetherꢀoneꢀorꢀallꢀbanksꢀareꢀprecharged.ꢀAfterꢀexecut-
ingꢀ thisꢀ command,ꢀ theꢀ nextꢀ commandꢀ forꢀ theꢀ selectedꢀ
bank(s)ꢀisꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtRP,ꢀwhichꢀ
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ
hasꢀbeenꢀprecharged,ꢀitꢀisꢀinꢀtheꢀidleꢀstateꢀandꢀmustꢀbeꢀ
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ
issuedꢀtoꢀthatꢀbank.
lOAD MODE REGISTER
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ
registerꢀisꢀloadedꢀfromꢀA0-A11.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ
beꢀissuedꢀwhenꢀallꢀbanksꢀareꢀidle.ꢀ
ACTIVE COMMAND
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ
inputsꢀselectsꢀaꢀbankꢀtoꢀbeꢀaccessed,ꢀandꢀtheꢀaddressꢀ
inputsꢀonꢀA0-A11ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ
commandꢀisꢀissuedꢀtoꢀtheꢀbank,ꢀtheꢀrowꢀremainsꢀopenꢀ
forꢀaccesses.
AUTO PRECHARGE
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-
chargeꢀisꢀinitiatedꢀatꢀtheꢀearliestꢀvalidꢀstageꢀwithinꢀaꢀburst.ꢀ
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ
requiringꢀanꢀexplicitꢀcommand.ꢀA10ꢀtoꢀenableꢀtheꢀAUTOꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
COMMAND TRUTH TABlE
ꢀ
ꢀ
ꢀ
CKE
n – 1
Hꢀꢀ
A11
Function
n
CS
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
RAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
CAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
WE
×ꢀꢀ
Hꢀ
BA1
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
BA0
×ꢀꢀ
×ꢀ
A10 A9 - A0
Deviceꢀdeselectꢀ(DESL)ꢀꢀ
Noꢀoperationꢀ(NOP)ꢀ ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀ
×
Hꢀꢀ
×
Burstꢀstopꢀ(BST)ꢀꢀ
Readꢀꢀ
ꢀ
ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
×ꢀꢀ
Lꢀꢀ
Hꢀ
Lꢀ
×
ꢀ
Hꢀꢀ
Vꢀ
Vꢀ
V
V
V
×
Readꢀwithꢀautoꢀprechargeꢀꢀ Hꢀꢀ
Writeꢀꢀ ꢀꢀ Hꢀꢀ
Writeꢀwithꢀautoꢀprechargeꢀꢀ Hꢀ
Bankꢀactivateꢀ(ACT)ꢀꢀꢀ Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀꢀ
Lꢀ
Hꢀ
Vꢀ
Hꢀꢀ
Vꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀ
×ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀ
ꢀVꢀꢀ
Vꢀ
Prechargeꢀselectꢀbankꢀ(PRE)ꢀ Hꢀꢀ
Prechargeꢀallꢀbanksꢀ(PALL)ꢀ Hꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Vꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀ
×
CBRꢀAuto-Refreshꢀ(REF)ꢀ
Self-Refreshꢀ(SELF)ꢀ ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×ꢀ
×
Modeꢀregisterꢀsetꢀ(MRS)ꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Vꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
DQM TRUTH TABlE
ꢀ
ꢀ
ꢀ
CKE
DQM
Function
n-1
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
n
U
l
L
ꢀ
ꢀ
Dataꢀwriteꢀ/ꢀoutputꢀenableꢀꢀꢀ
Dataꢀmaskꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
ꢀ×ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
H
×
L
Upperꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Lowerꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Upperꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
×
H
Lowerꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
CKE TRUTH TABlE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CKE
CurrentꢀStateꢀ/Functionꢀꢀ
ActivatingꢀClockꢀsuspendꢀmodeꢀentryꢀꢀ
AnyꢀClockꢀsuspendꢀmodeꢀꢀ
Clockꢀsuspendꢀmodeꢀexitꢀꢀ
AutoꢀrefreshꢀcommandꢀIdleꢀ(REF)ꢀꢀ
SelfꢀrefreshꢀentryꢀIdleꢀ(SELF)ꢀꢀ
PowerꢀdownꢀentryꢀIdleꢀꢀ
nꢀ–ꢀ1ꢀꢀ nꢀꢀ
CSꢀꢀ RASꢀ ꢀCASꢀ ꢀWEꢀꢀꢀ Address
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀ
×
×
×
×
×
×ꢀ
×ꢀꢀ
×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Lꢀꢀ
ꢀ
ꢀ
Selfꢀrefreshꢀexitꢀꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×
ꢀ
Powerꢀdownꢀexitꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
FUNCTIONAl TRUTH TABlE
Current State
CSꢀ ꢀRASꢀꢀ CASꢀ WE
Address
Command
DESLꢀꢀ
Action
Idleꢀ
Hꢀꢀ Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown
ILLEGALꢀ(3)
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
Xꢀ
NOPꢀꢀ
ꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Xꢀ
BSTꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
A,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ꢀ
ILLEGAL(3)
ꢀ
Rowꢀactivating
Nop
AutoꢀrefreshꢀorꢀSelf-refresh(4)
Modeꢀregisterꢀset
Nop
ꢀ
Lꢀꢀ
Lꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
OC,ꢀBA1=Lꢀꢀ
Xꢀ
RowꢀActiveꢀ
Hꢀꢀ Xꢀ
Xꢀ
DESLꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Xꢀ
NOPꢀꢀ
Nop
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀ
Xꢀ
BSTꢀ
Nop
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀreadꢀ(5)
Beginꢀwriteꢀ(5)
ILLEGALꢀ(3)
ꢀ
ꢀ
Lꢀ
Hꢀꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀ
Lꢀꢀ
ꢀ
BA,ꢀA10ꢀꢀ
ꢀ
PRE/PALLꢀꢀ
ꢀ
ꢀ
ꢀ
Prechargeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Prechargeꢀallꢀbanks(6)ꢀ
ILLEGAL
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
OC,ꢀBAꢀꢀ
ILLEGAL
Readꢀ
ꢀ
Hꢀꢀ Xꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
DESLꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀtoꢀꢀ
Rowꢀactive
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
Xꢀ
ꢀ
NOPꢀꢀ
ꢀ
ꢀ
ꢀ
ContinueꢀburstꢀtoꢀendꢀꢀRowꢀꢀ
Rowꢀꢀactive
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
READ/READAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀꢀ ꢀ
beginꢀnewꢀreadꢀ(7)
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Lꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
WRIT/WRITAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀꢀburst,ꢀꢀꢀ
beginꢀwriteꢀ(7,8)
ꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
BA,ꢀRAꢀꢀ
ACTꢀꢀ
ꢀ
ILLEGALꢀ(3)
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀꢀ
ꢀ
BA,ꢀA10ꢀꢀ
ꢀ
PRE/PALLꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburstꢀꢀꢀ ꢀ
Precharging
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
OC,ꢀBAꢀꢀ
Writeꢀ
ꢀ
Hꢀ
ꢀꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
DESLꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Writeꢀrecovering
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
Xꢀ
ꢀ
NOPꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Writeꢀrecovering
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
READ/READAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀstartꢀreadꢀ:ꢀꢀ
DetermineꢀAPꢀ(7,8)
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Lꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
WRIT/WRITAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀnewꢀwriteꢀ:ꢀꢀ
DetermineꢀAPꢀ(7)ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
BA,ꢀRAꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
RAꢀACTꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
TerminateꢀburstꢀPrechargingꢀ(9)
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
ILLEGAL
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
FUNCTIONAl TRUTH TABlE Continued:
Current State
CSꢀ ꢀRASꢀꢀ CASꢀ ꢀWE
Address
Command
Action
Readꢀwithꢀautoꢀ
Precharging
Hꢀ
ꢀ×ꢀꢀ
×ꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
DESLꢀ
Continueꢀburstꢀtoꢀend,ꢀPrechargeꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
xꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀPrecharge
ILLEGAL
Hꢀꢀ
Hꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(11)
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3)
ILLEGALꢀ(11)
ILLEGAL
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
OC,ꢀBAꢀꢀ
ILLEGAL
WriteꢀwithꢀAutoꢀ
Prechargeꢀ
Hꢀ
ꢀ
ꢀ×ꢀ
ꢀ
ꢀ×ꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
DESLꢀꢀ
ꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
recoveringꢀwithꢀautoꢀprecharge
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
NOPꢀꢀ
ꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
recoveringꢀwithꢀautoꢀprecharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
BSTꢀꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(11)
ꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Prechargingꢀ
Hꢀꢀ ×ꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
×ꢀꢀ
NOPꢀꢀ
ꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
ꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGAL(3)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
NopꢀꢀEnterꢀidleꢀafterꢀtRP
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
ꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
RowꢀActivatingꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
×ꢀꢀ
NOPꢀꢀ
×ꢀꢀ
BSTꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
Lꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGALꢀ(3,9)
ILLEGALꢀ(3)
ILLEGAL
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Integrated Silicon Solution, Inc. — www.issi.comꢀ
11
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
FUNCTIONAl TRUTH TABlE Continued:
Current State
CSꢀ ꢀRASꢀꢀ CASꢀ ꢀWE
Address
×ꢀꢀ
Command
DESLꢀꢀ
NOPꢀꢀ
Action
WriteꢀRecoveringꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
ꢀ
×ꢀꢀ
ꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ Beginꢀreadꢀ(8)
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀnewꢀwrite
ILLEGALꢀ(3)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
WriteꢀRecoveringꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
withꢀAutoꢀ
×ꢀꢀ
NOPꢀꢀ
Prechargeꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
ꢀ×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(3,8,11)
ꢀ
Lꢀꢀ
Hꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Refreshꢀ
Hꢀꢀ ×ꢀꢀ
×ꢀ
DESLꢀꢀꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRC
Nop,ꢀEnterꢀidleꢀafterꢀtRC
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
NOP/BSTꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL
ꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ILLEGAL
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
ꢀ×ꢀꢀ
ILLEGAL
ModeꢀRegisterꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
ILLEGAL
Accessingꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
NOPꢀ
ꢀ
ꢀ
Lꢀ
×ꢀꢀ
BSTꢀꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/WRITEꢀꢀ ILLEGAL
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
×ꢀꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
BA,ꢀRAꢀꢀ
ꢀ
ACT/PRE/PALLꢀꢀ ILLEGALꢀ
REF/MRSꢀ
ꢀ
ꢀ
ꢀ
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Notes:ꢀ
1.ꢀAllꢀentriesꢀassumeꢀthatꢀCKEꢀisꢀactiveꢀ(CKEn-1=CKEn=H).
2.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀPowerꢀDownꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
3.ꢀIllegalꢀtoꢀbankꢀinꢀspecifiedꢀstates;ꢀFunctionꢀmayꢀbeꢀlegalꢀinꢀtheꢀbankꢀindicatedꢀbyꢀBankꢀAddressꢀ(BA),ꢀdependingꢀonꢀtheꢀstateꢀofꢀ
thatꢀbank.
4.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀSelf-Refreshꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
5.ꢀIllegalꢀifꢀtRCDꢀisꢀnotꢀsatisfied.
6.ꢀIllegalꢀifꢀtRASꢀisꢀnotꢀsatisfied.
7.ꢀMustꢀsatisfyꢀburstꢀinterruptꢀcondition.
8.ꢀMustꢀsatisfyꢀbusꢀcontention,ꢀbusꢀturnꢀaround,ꢀand/orꢀwriteꢀrecoveryꢀrequirements.
9.ꢀMustꢀmaskꢀprecedingꢀdataꢀwhichꢀdon’tꢀsatisfyꢀtDPL.
10.ꢀIllegalꢀifꢀtRRDꢀisꢀnotꢀsatisfied.
11.ꢀIllegalꢀforꢀsingleꢀbank,ꢀbutꢀlegalꢀforꢀotherꢀbanks.
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
CKE RElATED COMMAND TRUTH TABlE(1)
CKE
Current State
Operation
n-1
n
CSꢀ
Xꢀ
Hꢀ
Lꢀ
RASꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
CASꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
WEꢀ Address
Self-Refreshꢀ(S.R.)ꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀS.R.ꢀ
Self-RefreshꢀRecovery(2)ꢀ
Self-RefreshꢀRecovery(2)ꢀ
Illegalꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
—
—
—
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Illegalꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
MaintainꢀS.R.ꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Self-RefreshꢀRecoveryꢀIdleꢀAfterꢀꢀtrc
ꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
IdleꢀAfterꢀꢀtrc
Illegalꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Beginꢀclockꢀsuspendꢀnextꢀcycle(5)ꢀ
Beginꢀclockꢀsuspendꢀnextꢀcycle(5)ꢀ
Illegalꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀ
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Exitꢀclockꢀsuspendꢀnextꢀcycle(2)ꢀ
Maintainꢀclockꢀsuspendꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀP.D.ꢀ
EXITꢀP.D.ꢀ-->ꢀIdle(2)ꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Power-Downꢀ(P.D.)ꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
Maintainꢀpowerꢀdownꢀmodeꢀ
Lꢀ
BothꢀBanksꢀIdleꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Auto-Refreshꢀ
Hꢀ
Lꢀ
Lꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
ꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
—
—
—
X
ꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀ
ꢀ
Self-Refresh(3)ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
Power-Down(3)ꢀ
Lꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableHꢀ ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
Anyꢀstateꢀ
otherꢀthanꢀ
listedꢀaboveꢀ
ꢀ
Beginꢀclockꢀsuspendꢀnextꢀcycle(4)ꢀ
Exitꢀclockꢀsuspendꢀnextꢀcycleꢀ
Maintainꢀclockꢀsuspendꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Notes:
1.ꢀHꢀ:ꢀHighꢀlevel,ꢀLꢀ:ꢀlowꢀlevel,ꢀXꢀ:ꢀHighꢀorꢀlowꢀlevelꢀ(Don’tꢀcare).
2.ꢀCKEꢀLowꢀtoꢀHighꢀtransitionꢀwillꢀre-enableꢀCLKꢀandꢀotherꢀinputsꢀasynchronously.ꢀAꢀminimumꢀsetupꢀ
timeꢀmustꢀbeꢀsatisfied
beforeꢀanyꢀcommandꢀotherꢀthanꢀEXIT.
3.ꢀPowerꢀdownꢀandꢀSelfꢀrefreshꢀcanꢀbeꢀenteredꢀonlyꢀfromꢀtheꢀbothꢀbanksꢀidleꢀstate.
4.ꢀMustꢀbeꢀlegalꢀcommandꢀasꢀdefinedꢀinꢀOperativeꢀCommandꢀTable.
5.ꢀIllegalꢀifꢀtsrxꢀisꢀnotꢀsatisfied.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
STATE DIAGRAM
Self
Refresh
SELF
SELF exit
REF
Mode
Register
Set
MRS
CBR (Auto)
Refresh
IDLE
CKE
CKE
ACT
Power
Down
CKE
Active
Power
Down
Row
Active
CKE
BST
Write
BST
Read
Auto Prech
Write
Read
arge
Read
CKE
CKE
CKE
WRITE
SUSPEND
READ
SUSPEND
READ
WRITE
Write
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
CKE
Precharge
POWER
ON
Precharge
Automatic sequence
Manual Input
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
ABSOlUTE MAXIMUM RATINGS(1)
Symboꢀ
Parameters
Rating
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–1.0ꢀtoꢀVddqꢀ+ꢀ0.5ꢀ
1ꢀ
Unit
V
V
V
V
W
mA
°C
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vdd maxꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
AllowableꢀPowerꢀDissipationꢀ
outputꢀShortedꢀCurrentꢀ
operatingꢀTemperatureꢀ
ꢀ
Vddq max
ꢀ
Vinꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Voutꢀ
Pd max
Ics
50ꢀ
-40ꢀtoꢀ+85ꢀ
-40ꢀtoꢀ+105
ꢀ
ꢀ
Topr
ꢀ
A1ꢀ
A2ꢀ
ꢀ
ꢀ
Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–55ꢀtoꢀ+150ꢀ
°C
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
DC RECOMMENDED OPERATING CONDITIONS
Taꢀ=ꢀ-40oCꢀtoꢀ+85oCꢀforꢀA1ꢀtemperature.ꢀꢀTaꢀ=ꢀ-40oCꢀtoꢀ+105oCꢀforꢀA2ꢀtemperature.
Symboꢀ
Parameter
Min.
3.0ꢀ
3.0ꢀ
2.0ꢀ
-0.3ꢀ
Typ.
3.3ꢀ
3.3ꢀ
—ꢀ
Max.
3.6ꢀ
3.6ꢀ
Unit
V
V
V
V
ꢀ
ꢀ
ꢀ
ꢀ
Vdd ꢀ
SupplyꢀVoltageꢀ
I/OꢀSupplyꢀVoltageꢀ
InputꢀHighꢀVoltageꢀ
InputꢀLowꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddqꢀ
(1)
Vih ꢀ
Vddq +ꢀ0.3ꢀ
+0.8ꢀ
(2)
Vil ꢀ
—ꢀ
Note:
1.ꢀꢀVih (max)ꢀ=ꢀVddq +2V (pulse width < 3ns).
2.ꢀꢀVilꢀ(min)ꢀꢀ=ꢀ-2V (pulse width < 3ns).
3.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
CAPACITANCE CHARACTERISTICS (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVddꢀ=ꢀVddq =ꢀ3.3ꢀ ꢀ0.3V)
Symboꢀ
Parameter
Min.
Max.
-7
Unit
-6
ꢀ
ꢀ
ꢀ
Cin1ꢀ
Cin2ꢀ
Ci/oꢀ
InputꢀCapacitance:ꢀCLKꢀ
InputꢀCapacitance:Allꢀotherꢀinputꢀpinsꢀ
DataꢀInput/OutputꢀCapacitance:I/Osꢀ
2.5ꢀ
2.5ꢀ
4.0ꢀ
ꢀ
ꢀ
ꢀ
3.5ꢀ ꢀ 4.0ꢀ
3.8ꢀ ꢀ 5.0ꢀ
6.5ꢀ ꢀ 6.5ꢀ
ꢀ
ꢀ
ꢀ
pF
pF
pF
Integrated Silicon Solution, Inc. — www.issi.comꢀ
15
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
DC ElECTRICAl CHARACTERISTICS 1 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symboꢀꢀ Parameterꢀ
Test Conditionꢀ
-6
ꢀ 140ꢀ
ꢀ
-7ꢀ
Unit
ꢀidd1ꢀ(1)
ꢀ
OperatingꢀCurrentꢀ
ꢀ
Oneꢀbankꢀactive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
120ꢀ
ꢀ
mA
ꢀꢀ
tclkꢀ=ꢀtclkꢀ(min),ꢀtrcꢀ=ꢀtrcꢀ(min)ꢀ
ꢀidd2p
ꢀ
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ꢀVilꢀꢀ(max),ꢀtckꢀ=ꢀ15nsꢀ
(InꢀPower-DownꢀMode)ꢀ CSꢀ ≥ Vddꢀ-ꢀ0.2V
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ꢀVilꢀꢀ(max),ꢀCLKꢀ≤ꢀVilꢀꢀ(max)ꢀ
withꢀclockꢀstopꢀ
(InꢀPower-DownꢀMode)
ꢀ
ꢀ
2ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
mA
i
ꢀꢀ
ꢀ
dd2ps
ꢀ
ꢀ
ꢀ
1ꢀ
mAꢀ
ꢀ
ꢀ
CSꢀ ≥ Vddꢀ-ꢀ0.2V
ꢀ
ꢀ
(2)
i
dd2n
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CSꢀ ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vihꢀꢀ(min)ꢀ
(InꢀNonꢀPower-DownꢀMode) ꢀtckꢀ=ꢀ15ns
ꢀ
ꢀ
ꢀ
25ꢀ
25ꢀ
15ꢀ
ꢀ
ꢀ
mA
ꢀ
I
dd2ns
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CSꢀ ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vihꢀꢀ(min)ꢀ
ꢀꢀ
15ꢀ
mAꢀ
ꢀꢀ
withꢀclockꢀstopꢀ
ꢀ
i
ꢀ
(InꢀNonꢀPower-DownꢀMode) Allꢀinputsꢀstable
ꢀ
ꢀ
(2)
dd3p
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
(InꢀPower-DownꢀMode)ꢀ
CKEꢀ≤ꢀVilꢀꢀ(max),ꢀCSꢀ ≥ Vddꢀ-ꢀ0.2Vꢀ
ckꢀ=ꢀ15ns
ꢀ
ꢀ
2ꢀ
2ꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
mA
t
i
ꢀꢀ
ꢀ
dd3ps
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
withꢀclockꢀstopꢀ
CKEꢀ≤ꢀVilꢀꢀ(max),ꢀCLKꢀ≤ꢀVilꢀꢀ(max),ꢀ
CSꢀ ≥ Vddꢀ-ꢀ0.2V
ꢀ
mAꢀ
ꢀ
ꢀ
(InꢀPower-DownꢀMode)
(2)
i
dd3n
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
CSꢀ ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vihꢀꢀ(min)ꢀ
ꢀ
ꢀ
ꢀ
30ꢀ
20ꢀ
30ꢀ
20ꢀ
ꢀ
ꢀ
mA
ꢀ
(InꢀNonꢀPower-DownꢀMode) ꢀtckꢀ=ꢀ15ns
I
ꢀꢀ
dd3ns
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
withꢀclockꢀstopꢀ
CSꢀ ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vihꢀꢀ(min)ꢀ
Allꢀinputsꢀstable
ꢀꢀ
mAꢀ
ꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀꢀꢀꢀꢀ
OperatingꢀCurrentꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
i
dd4
ꢀ
Allꢀꢀbanksꢀactive,ꢀBLꢀ=ꢀ4,ꢀCLꢀ=ꢀ3,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ 150ꢀ
ꢀ 180ꢀ
130ꢀ
ꢀ
mA
ꢀꢀ
i
ꢀ
t
ckꢀ=ꢀtckꢀ(min)ꢀ
rcꢀ=ꢀtrcꢀ(min),ꢀtclkꢀ=ꢀtclkꢀ(min)ꢀꢀꢀꢀꢀꢀꢀꢀ
CKEꢀ≤ꢀ 0.2Vꢀꢀꢀꢀꢀꢀꢀ
ꢀ
dd5
ꢀ
ꢀ
Auto-RefreshꢀCurrentꢀ
Self-RefreshꢀCurrentꢀ
t
160ꢀ
2ꢀ
ꢀ
ꢀ
mA
mA
i
dd6
ꢀ
ꢀ
2ꢀ
ꢀNotes:
1.ꢀ Iddꢀ(max)ꢀisꢀspecifiedꢀatꢀtheꢀoutputꢀopenꢀcondition.
2.ꢀ Inputꢀsignalsꢀareꢀchangedꢀoneꢀtimeꢀduringꢀ30ns.
DC ElECTRICAl CHARACTERISTICS 2 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symboꢀꢀ Parameterꢀ
Test Conditionꢀ
Minꢀ
Max
Unit
ꢀiil
ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀꢀ≤ꢀVinꢀ≤ꢀVdd,ꢀwithꢀpinsꢀotherꢀthanꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
-5ꢀ
5ꢀ
µA
ꢀꢀ
theꢀtestedꢀpinꢀatꢀ0Vꢀ
ꢀ
ꢀiol
ꢀ
OutputꢀLeakageꢀCurrentꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
Outputꢀisꢀdisabled,ꢀ0Vꢀꢀ≤ꢀVoutꢀ≤ꢀVdd,ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-5ꢀ
5ꢀ
µA
V
Voh
ꢀ
Iohꢀꢀ=ꢀꢀ-2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
olꢀꢀ=ꢀꢀ2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
2.4ꢀ
—ꢀ
Vol
ꢀ
I
—
ꢀ
0.4
ꢀ
V
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
AC ElECTRICAl CHARACTERISTICS (1,2,3)
-6
-7
Symboꢀ Parameter
Min. Max.
Min. Max.
Units
ꢀ tck3ꢀ
ꢀ tck2ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
6ꢀ
10ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
7ꢀ
10ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tac3ꢀ
ꢀ tac2ꢀ
AccessꢀTimeꢀFromꢀCLKꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ ꢀ 5.4ꢀ
—ꢀ ꢀ 6.5ꢀ
—ꢀ ꢀ 5.4ꢀ
—ꢀ ꢀ 6.5ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tchꢀ
ꢀ tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ꢀ toh3ꢀ
ꢀ toh2ꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2.7ꢀ
2.7ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.7ꢀ
2.7ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
OutputꢀHIGHꢀImpedanceꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ thzꢀ
2.7ꢀ ꢀ 5.4ꢀ
2.7ꢀ ꢀ 5.4ꢀ
ꢀ tdsꢀ
InputꢀDataꢀSetupꢀTime(2)
InputꢀDataꢀHoldꢀTime(2)
AddressꢀSetupꢀTime(2)
AddressꢀHoldꢀTime(2)
CKEꢀSetupꢀTime(2)
CKEꢀHoldꢀTime(2)
ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
60ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
100K
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ tdhꢀ
ꢀ tasꢀ
ꢀ
ꢀ
ꢀ tahꢀ
ꢀ
ꢀ tcksꢀ
ꢀ tckhꢀ
ꢀ tcmsꢀ
ꢀ tcmhꢀ
ꢀ trcꢀ
ꢀ trasꢀ
ꢀ trpꢀ
ꢀ
ꢀ
CommandꢀSetupꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)(2)
CommandꢀHoldꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)(2)
ꢀ
ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
67.5ꢀ ꢀ —ꢀ
42ꢀ
ꢀ
45ꢀ
20ꢀ
20ꢀ
14ꢀ
14ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
100K
ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
18ꢀ
—ꢀ
ꢀ trcdꢀ
ꢀ trrdꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
18ꢀ
—ꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
ꢀ
ꢀ
12ꢀ
—ꢀ
ꢀ tdplꢀ
ꢀ ꢀ ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtime
12ꢀ
—ꢀ
ꢀ tdalꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
ꢀ
ꢀ
ꢀ
ꢀ
30
—ꢀ
35
—ꢀ
ꢀ
ns
ꢀ ꢀ ꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)
ꢀ tmrd
ꢀ tdde
ꢀ txsr
ꢀ ttꢀ
ModeꢀRegisterꢀProgramꢀTimeꢀ
PowerꢀDownꢀExitꢀSetupꢀTimeꢀ
exit Self-RefreshꢀtoꢀActiveꢀTime(4)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
12ꢀ
6.0ꢀ
67ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀ
7.0ꢀ
75ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ꢀ
TransitionꢀTimeꢀ
0.3ꢀ ꢀ 1.2ꢀ
0.3ꢀ ꢀ 1.2ꢀ
ꢀ trefꢀ
ꢀ ꢀ ꢀ
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ
ꢀ
Tꢀ aꢀ≤ꢀ85oCꢀꢀA1,ꢀA2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
64ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
64ꢀ
16ꢀ
ꢀ
ꢀ
msꢀ ꢀ
ms
ꢀ
ꢀ Taꢀ>ꢀ85oCꢀꢀA2ꢀ ꢀ
Notes:
1.ꢀ Theꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2.ꢀ measuredꢀwithꢀtt =ꢀ1ꢀns.ꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(ttꢀ/2ꢀ-ꢀ0.5)ꢀnsꢀshouldꢀbeꢀaddedꢀtoꢀtheꢀparameter.
3.ꢀꢀTheꢀreferenceꢀlevelꢀisꢀ1.4Vꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih(min.)ꢀandꢀVilꢀ(max).
4.ꢀꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ+85oC.ꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
17
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
OPERATING FREQUENCY / lATENCY RElATIONSHIPS
SYMBOl PARAMETER
-6
6ꢀ
-7
7ꢀ
UNITS
ns
ꢀ
—ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ—ꢀ
OperatingꢀFrequencyꢀ(CASꢀꢀLatencyꢀ=ꢀ3)ꢀ
166ꢀ
143ꢀ
MHz
ꢀtcacꢀ
ꢀtrcdꢀ
ꢀtracꢀ
ꢀtrc
CASꢀꢀLatencyꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
3ꢀ
3ꢀ
3ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(trcdꢀ+ꢀtcac)ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
6ꢀ
6ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
7ꢀ
10ꢀ
7ꢀ
ꢀtrasꢀ
ꢀtrpꢀ
3ꢀ
3ꢀ
ꢀtrrdꢀ
2ꢀ
2ꢀ
ꢀtccdꢀ
ꢀꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
1ꢀ
1ꢀ
ꢀtdplꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
ꢀ
ꢀ
cycle
cycle
ꢀtdalꢀ
ꢀꢀ
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(DuringꢀAuto-Precharge)
ꢀtrbdꢀ
ꢀꢀ
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ CASꢀꢀLatencyꢀ=ꢀ3ꢀ
(Read)
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
cycle
cycle
cycle
cycle
ꢀtwbdꢀ
ꢀꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀꢀ
(Write)ꢀ
ꢀtrqlꢀ
ꢀꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ CASꢀꢀLatencyꢀ=ꢀ3ꢀ
(Read)ꢀ
ꢀtwdlꢀ
ꢀꢀ
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀꢀ
(Write)
ꢀtpqlꢀ
ꢀtqmdꢀ
ꢀtdmdꢀ
ꢀtmrdꢀ
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read)ꢀ CASꢀꢀLatencyꢀ=ꢀ3ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-2ꢀ
2ꢀ
0ꢀ
2ꢀ
–2ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
cycle
cycle
cycle
cycle
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
2ꢀ
18ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
AC TEST CONDITIONS
Input load
Output load
t
CK
t
CH
t
CL
3.0V
1.4V
1.4V
CLK
50Ω
0V
Z = 50Ω
tCMS
t
CMH
Output
3.0V
1.4V
50 pF
INPUT
0V
t
AC
tOH
OUTPUT
1.4V
1.4V
AC TEST CONDITIONS
Parameter
Rating
ACꢀInputꢀLevelsꢀꢀ
0Vꢀtoꢀ3.0V
1ꢀns
ꢀ
ꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
InputꢀTimingꢀReferenceꢀLevelꢀ
OutputꢀTimingꢀMeasurementꢀReferenceꢀLevelꢀ
1.4V
1.4V
Integrated Silicon Solution, Inc. — www.issi.comꢀ
19
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
Initiaꢀization
FUNCTIONAl DESCRIPTION
SDRAMsꢀ mustꢀ beꢀ poweredꢀ upꢀ andꢀ initializedꢀ inꢀ aꢀ
predefinedꢀmanner.
Theꢀ128MbꢀSDRAMsꢀareꢀquad-bankꢀDRAMsꢀwhichꢀoperateꢀ
atꢀ3.3Vꢀandꢀincludeꢀaꢀsynchronousꢀinterfaceꢀ(allꢀsignalsꢀ
areꢀregisteredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀ
CLK).ꢀEachꢀofꢀtheꢀ33,554,432-bitꢀbanksꢀisꢀorganizedꢀasꢀ
4,096ꢀrowsꢀbyꢀ512ꢀcolumnsꢀbyꢀ16ꢀbitsꢀorꢀ4,096ꢀrowsꢀbyꢀ
1,024ꢀcolumnsꢀbyꢀ8ꢀbits.
Theꢀ128MꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ
toꢀVddꢀandꢀVddqꢀ(simultaneously)ꢀandꢀtheꢀclockꢀisꢀstableꢀ
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ
Aꢀ100µsꢀdelayꢀisꢀrequiredꢀpriorꢀtoꢀissuingꢀanyꢀcommandꢀ
otherꢀthanꢀaꢀCOMMANDꢀINHIBITꢀorꢀaꢀNOP.ꢀTheꢀCOMMANDꢀ
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100usꢀperiodꢀandꢀ
shouldꢀcontinueꢀatꢀleastꢀthroughꢀtheꢀendꢀofꢀtheꢀperiod.ꢀ
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented;ꢀ
accessesꢀ startꢀ atꢀ aꢀ selectedꢀ locationꢀ andꢀ continueꢀ forꢀ
aꢀ programmedꢀ numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ
sequence.ꢀ Accessesꢀ beginꢀ withꢀ theꢀ registrationꢀ ofꢀ anꢀ
ACTIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorꢀ
WRITEꢀcommand.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀ
withꢀtheꢀACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀ
andꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀA0-
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ
beꢀappliedꢀonceꢀtheꢀ100µsꢀdelayꢀhasꢀbeenꢀsatisfied.ꢀꢀAllꢀ
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀanꢀ
idleꢀstateꢀafterꢀwhichꢀatꢀleastꢀtwoꢀAUTOꢀREFRESHꢀcyclesꢀ
mustꢀbeꢀperformed.ꢀ AfterꢀtheꢀAUTOꢀREFRESHꢀcyclesꢀareꢀ
complete,ꢀ theꢀ SDRAMꢀ isꢀ thenꢀ readyꢀ forꢀ modeꢀ registerꢀ
programming.
A11ꢀselectꢀtheꢀrow).ꢀTheꢀaddressꢀbitsꢀA0-A9ꢀ(x8);ꢀA0-A8ꢀ(x16)
ꢀ
registeredꢀcoincidentꢀwithꢀtheꢀREADꢀorꢀWRITEꢀcommandꢀ
areꢀ usedꢀ toꢀ selectꢀ theꢀ startingꢀ columnꢀ locationꢀ forꢀ theꢀ
burstꢀaccess.ꢀ
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ
anyꢀoperationalꢀcommandꢀbecauseꢀitꢀwillꢀpowerꢀupꢀinꢀanꢀ
unknownꢀstate.
Priorꢀ toꢀ normalꢀ operation,ꢀ theꢀ SDRAMꢀ mustꢀ beꢀ initial-
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ
coveringꢀdeviceꢀinitialization,ꢀregisterꢀdefinition,ꢀcommandꢀ
descriptionsꢀandꢀdeviceꢀoperation.ꢀ
20ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
INITIAlIꢁE AND lOAD MODE REGISTER(1)
T0
T1
Tn+1
To+1
t
CL
Tp+1
Tp+2
Tp+3
tCK
tCH
CLK
CKE
tCKS t
CKH
t
CMS
tCMH
tCMS
tCMH
tCMS tCMH
AUTO
REFRESH
AUTO
Load MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
REFRESH
DQM/
DQML, DQMH
t
t
t
AS
tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
AS
tAH
ALL BANKS
CODE
SINGLE BANK
ALLBANKS
AS
tAH
BA0, BA1
DQ
CODE
t
RP
t
RC
t
RC
tMRD
T
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
and CLK stable all banks
DON'T CARE
T = 100µs Min.
Notes:
1.ꢀꢀIfꢀCSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.
3.ꢀꢀJEDECꢀandꢀPC100ꢀspecifyꢀthreeꢀclocks.
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
21
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
AUTO-REFRESH CYClE
T0
T1
T2
Tn+1
To+1
tCK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
tAS
tAH
High-Z
t
RP
t
RC
tRC
DON'T CARE
Notes:
1.ꢀꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
22ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
SElF-REFRESH CYClE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
tCH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
tRAS
t
CKS
tCMS
tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
High-Z
tRP
tXSR
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1.ꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ+85oC.ꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
23
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selectionꢀofꢀaꢀburstꢀlength,ꢀaꢀburstꢀtype,ꢀaꢀCASꢀlatency,ꢀ
anꢀoperatingꢀmodeꢀandꢀaꢀwriteꢀburstꢀmode,ꢀasꢀshownꢀinꢀ
MODEꢀREGISTERꢀDEFINITION.ꢀ
ModeꢀregisterꢀbitsꢀM0-M2ꢀspecifyꢀtheꢀburstꢀlength,ꢀM3ꢀ
specifiesꢀtheꢀtypeꢀofꢀburstꢀ(sequentialꢀorꢀinterleaved),ꢀM4-ꢀM6ꢀ
specifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀ
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ
M11ꢀareꢀreservedꢀforꢀfutureꢀuse.
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
untilꢀitꢀisꢀprogrammedꢀagainꢀorꢀtheꢀdeviceꢀlosesꢀpower.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀbeforeꢀ
initiatingꢀtheꢀsubsequentꢀoperation.ꢀViolatingꢀeitherꢀofꢀtheseꢀ
requirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.
MODE REGISTER DEFINITION
Address Bus
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
0
Defined Standard Operation
AllOtherStatesReserved
—
—
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0"
1
24ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
BURST lENGTH
ingꢀthatꢀtheꢀburstꢀwillꢀwrapꢀwithinꢀtheꢀblockꢀifꢀaꢀboundaryꢀ
isꢀreached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A8ꢀ(x16)ꢀ
whenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo;ꢀbyꢀA2-A8ꢀ(x16)ꢀwhenꢀ
theꢀburstꢀlengthꢀisꢀsetꢀtoꢀfour;ꢀandꢀbyꢀA3-A8ꢀ(x16)ꢀwhenꢀtheꢀ
burstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀ
addressꢀbit(s)ꢀisꢀ(are)ꢀusedꢀtoꢀselectꢀtheꢀstartingꢀlocationꢀ
withinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀ
theꢀboundaryꢀisꢀreached.
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀ
withꢀtheꢀburstꢀlengthꢀbeingꢀprogrammable,ꢀasꢀshownꢀinꢀ
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-
minesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀ
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ
lengthsꢀofꢀ1,ꢀ2,ꢀ4ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀ
sequentialꢀandꢀtheꢀinterleavedꢀburstꢀtypes,ꢀandꢀaꢀfull-pageꢀ
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ
commandꢀtoꢀgenerateꢀarbitraryꢀburstꢀlengths.
BurstꢀType
Accessesꢀwithinꢀaꢀgivenꢀburstꢀmayꢀbeꢀprogrammedꢀtoꢀbeꢀ
eitherꢀsequentialꢀorꢀinterleaved;ꢀthisꢀisꢀreferredꢀtoꢀasꢀtheꢀ
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀM3.
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀ
orꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ
columnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ
accessesꢀforꢀthatꢀburstꢀtakeꢀplaceꢀwithinꢀthisꢀblock,ꢀmean-
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ
theꢀburstꢀlength,ꢀtheꢀburstꢀtypeꢀandꢀtheꢀstartingꢀcolumnꢀ
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
BURST DEFINITION
Burst
Starting Coꢀumn
Address
Order of Accesses Within a Burst
length
Type = Sequentiaꢀ
Type = Interꢀeaved
A 0
ꢀ
ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
ꢀ
0-1ꢀ
1-0ꢀ
ꢀ
ꢀ
0-1
1-0
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
ꢀ
1ꢀ
1ꢀ
A 2
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
ꢀ2-3-4-5-6-7-0-1ꢀ
ꢀ3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
ꢀ0ꢀ
1ꢀ
8ꢀ
ꢀ
ꢀ1ꢀ
0ꢀ
0ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
1ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fullꢀ
Pageꢀ
(y)ꢀ
nꢀ=ꢀA0-A7ꢀ
ꢀ
(locationꢀ0-y)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...
…Cnꢀ-ꢀ1,
ꢀ
Cn…
Integrated Silicon Solution, Inc. — www.issi.comꢀ
25
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
CAS latency
Operating Mode
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ
theꢀregistrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ
threeꢀclocks.
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ
toꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀareꢀ
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ
theꢀlatencyꢀisꢀm clocks,ꢀtheꢀdataꢀwillꢀbeꢀavailableꢀbyꢀclockꢀ
edgeꢀn + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ
clockꢀedgeꢀoneꢀcycleꢀearlierꢀ(n + m -ꢀ1),ꢀandꢀprovidedꢀthatꢀ
theꢀrelevantꢀaccessꢀtimesꢀareꢀmet,ꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀ
clockꢀedgeꢀn + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycleꢀtimeꢀisꢀsuchꢀthatꢀallꢀrelevantꢀaccessꢀtimesꢀareꢀmet,ꢀ
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
isꢀprogrammedꢀtoꢀtwoꢀclocks,ꢀtheꢀDQsꢀwillꢀstartꢀdrivingꢀ
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀTheꢀAllowableꢀOperatingꢀFrequencyꢀ
tableꢀindicatesꢀtheꢀoperatingꢀfrequenciesꢀatꢀwhichꢀeachꢀ
CASꢀlatencyꢀsettingꢀcanꢀbeꢀused.
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-
causeꢀ unknownꢀ operationꢀ orꢀ incompatibilityꢀ withꢀ futureꢀ
versionsꢀmayꢀresult.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ
writeꢀaccessesꢀareꢀsingle-locationꢀ(nonburst)ꢀaccesses.
CAS latency
Aꢀꢀowabꢀe Operating Frequency (MHz)
Speed
CAS latency = 2
CAS latency = 3
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ
orꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
-6
100
100
166
143
-7
CAS lATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
DOUT
t
LZ
tOH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
DOUT
t
LZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
26ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
CHIP OPERATION
BANK/ROW ACTIVATION
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ
toꢀaꢀbankꢀwithinꢀtheꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀbeꢀ
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ
whichꢀselectsꢀbothꢀtheꢀbankꢀandꢀtheꢀrowꢀtoꢀbeꢀactivatedꢀ
(seeꢀActivatingꢀSpecificꢀRowꢀWithinꢀSpecificꢀBank).
CLK
HIGH
CKE
CS
Afterꢀopeningꢀaꢀrowꢀ(issuingꢀanꢀACTIVEꢀcommand),ꢀaꢀREADꢀ
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ
theꢀtrcdꢀspecification.ꢀMinimumꢀtrcdꢀshouldꢀbeꢀdividedꢀbyꢀ
theꢀclockꢀperiodꢀandꢀroundedꢀupꢀtoꢀtheꢀnextꢀwholeꢀnumberꢀ
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ
entered.ꢀForꢀexample,ꢀaꢀtrcdꢀspecificationꢀofꢀ18nsꢀwithꢀaꢀ
125ꢀMHzꢀclockꢀ(8nsꢀperiod)ꢀresultsꢀinꢀ2.25ꢀclocks,ꢀroundedꢀ
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[trcdꢀ(MIN)/tck]ꢀ≤ꢀ3.ꢀ(Theꢀsameꢀ
procedureꢀisꢀusedꢀtoꢀconvertꢀotherꢀspecificationꢀlimitsꢀfromꢀ
timeꢀunitsꢀtoꢀclockꢀcycles).
RAS
CAS
WE
A0-A11
BA0,BA1
ROW ADDRESS
BANK ADDRESS
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ
sameꢀbankꢀcanꢀonlyꢀbeꢀissuedꢀafterꢀtheꢀpreviousꢀactiveꢀ
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ
sameꢀbankꢀisꢀdefinedꢀbyꢀtrc.
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ
issuedꢀwhileꢀtheꢀfirstꢀbankꢀisꢀbeingꢀaccessed,ꢀwhichꢀresultsꢀ
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ
differentꢀbanksꢀisꢀdefinedꢀbyꢀtrrd.
EXAMPlE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
t
RCD
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
27
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READS
READ COMMAND
READꢀ burstsꢀ areꢀ initiatedꢀ withꢀ aꢀ READꢀ command,ꢀ asꢀ
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.
CLK
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀREADꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀ
disabledꢀforꢀthatꢀburstꢀaccess.ꢀIfꢀautoꢀprechargeꢀisꢀenabled,ꢀ
theꢀrowꢀbeingꢀaccessedꢀisꢀprechargedꢀatꢀtheꢀcompletionꢀofꢀ
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-
lowingꢀillustrations,ꢀautoꢀprechargeꢀisꢀdisabled.
HIGH
CKE
CS
RAS
DuringꢀREADꢀbursts,ꢀtheꢀvalidꢀdata-outꢀelementꢀfromꢀtheꢀ
startingꢀ columnꢀ addressꢀ willꢀ beꢀ availableꢀ followingꢀ theꢀ
CASꢀlatencyꢀafterꢀtheꢀREADꢀcommand.ꢀEachꢀsubsequentꢀ
data-outꢀelementꢀwillꢀbeꢀvalidꢀbyꢀtheꢀnextꢀpositiveꢀclockꢀ
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtimingꢀ
forꢀeachꢀpossibleꢀCASꢀlatencyꢀsetting.
CAS
WE
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ
willꢀcontinueꢀuntilꢀterminated.ꢀ(Atꢀtheꢀendꢀofꢀtheꢀpage,ꢀitꢀwillꢀ
wrapꢀtoꢀcolumnꢀ0ꢀandꢀcontinue.)
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀREADꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ
burstꢀfollowsꢀeitherꢀtheꢀlastꢀelementꢀofꢀaꢀcompletedꢀburstꢀ
orꢀtheꢀlastꢀdesiredꢀdataꢀelementꢀofꢀaꢀlongerꢀburstꢀwhichꢀ
isꢀbeingꢀtruncated.
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note:ꢀA9ꢀisꢀ"Don'tꢀCare"ꢀforꢀx16.
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀtwoꢀclocksꢀforꢀoutputꢀbuffers)ꢀ
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀthatꢀtruncatedꢀtheꢀREADꢀcommand.ꢀIfꢀnot,ꢀtheꢀ
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ
beꢀinvalid.
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesꢀbeforeꢀ
theꢀclockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀdataꢀelementꢀisꢀ
valid,ꢀwhereꢀx equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀConsecutiveꢀREADꢀBurstsꢀforꢀCASꢀlatenciesꢀofꢀ
twoꢀandꢀthree;ꢀdataꢀelementꢀn +ꢀ3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀ
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀTheꢀ128Mbꢀ
SDRAMꢀusesꢀaꢀpipelinedꢀarchitectureꢀandꢀthereforeꢀdoesꢀ
notꢀrequireꢀtheꢀ2n ruleꢀassociatedꢀwithꢀaꢀprefetchꢀarchitec-
ture.ꢀAꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀ
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ
readꢀaccessesꢀcanꢀbeꢀperformedꢀtoꢀtheꢀsameꢀbank,ꢀasꢀ
shownꢀinꢀRandomꢀREADꢀAccesses,ꢀorꢀeachꢀsubsequentꢀ
READꢀmayꢀbeꢀperformedꢀtoꢀaꢀdifferentꢀbank.
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀzeroꢀclocksꢀforꢀinputꢀbuffers)ꢀ
toꢀensureꢀthatꢀtheꢀwrittenꢀdataꢀisꢀnotꢀmasked.ꢀ
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀWRITEꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-
mediatelyꢀfollowingꢀtheꢀlastꢀ(orꢀlastꢀdesired)ꢀdataꢀelementꢀ
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ
avoided.ꢀInꢀaꢀgivenꢀsystemꢀdesign,ꢀthereꢀmayꢀbeꢀaꢀpos-
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ
aꢀsingle-cycleꢀdelayꢀshouldꢀoccurꢀbetweenꢀtheꢀlastꢀreadꢀ
dataꢀandꢀtheꢀWRITEꢀcommand.
Aꢀfixed-lengthꢀREADꢀburstꢀmayꢀbeꢀfollowedꢀby,ꢀorꢀtruncatedꢀ
with,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbankꢀ(providedꢀ
thatꢀautoꢀprechargeꢀwasꢀnotꢀactivated),ꢀandꢀaꢀfull-pageꢀburstꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
sameꢀbank.ꢀTheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ
x cyclesꢀbeforeꢀtheꢀclockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀ
dataꢀelementꢀisꢀvalid,ꢀwhereꢀx equalsꢀtheꢀCASꢀlatencyꢀ
28ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ
diagramꢀforꢀeachꢀpossibleꢀCASꢀlatency;ꢀdataꢀelementꢀn +ꢀ
3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀ
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequentꢀcommandꢀtoꢀtheꢀsameꢀbankꢀcannotꢀbeꢀissuedꢀ
untilꢀtrpꢀisꢀmet.ꢀNoteꢀthatꢀpartꢀofꢀtheꢀrowꢀprechargeꢀtimeꢀisꢀ
hiddenꢀduringꢀtheꢀaccessꢀofꢀtheꢀlastꢀdataꢀelement(s).
Inꢀ theꢀ caseꢀ ofꢀ aꢀ fixed-lengthꢀ burstꢀ beingꢀ executedꢀ toꢀ
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimumꢀtimeꢀ(asꢀdescribedꢀabove)ꢀprovidesꢀtheꢀsameꢀ
operationꢀ thatꢀ wouldꢀ resultꢀ fromꢀ theꢀ sameꢀ fixed-lengthꢀ
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
andꢀaddressꢀbusesꢀbeꢀavailableꢀatꢀtheꢀappropriateꢀtimeꢀtoꢀ
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
commandꢀisꢀthatꢀitꢀcanꢀbeꢀusedꢀtoꢀtruncateꢀfixed-lengthꢀ
orꢀfull-pageꢀbursts.
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.ꢀTheꢀBURSTꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cyclesꢀbeforeꢀ
theꢀclockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀdataꢀelementꢀisꢀ
valid,ꢀwhereꢀx equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleꢀCASꢀlatency;ꢀdataꢀelementꢀn+ꢀ3ꢀisꢀtheꢀlastꢀdesiredꢀ
dataꢀelementꢀofꢀaꢀlongerꢀburst.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
29
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
D
OUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
DON'T CARE
30ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
CONSECUTIVE READ BURSTS
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
31
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
RANDOM READ ACCESSES
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
32ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READ BURST TERMINATION
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
x=1cycle
BANK a,
COL n
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
33
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
AlTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
t
LZ
tOH
t
OH
tOH
tOH
tOH
DQ
DOUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m+
3
D
OUT
b
tAC
tAC
tAC
tAC
tAC
tAC
tRCD - BANK 0
tRRD
CAS Latency - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1) CASꢀlatency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
34ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READ - FUll-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
tAS tAH
ROW
tAS tAH
BA0, BA1
BANK
BANK
tAC
tAC
tAC
tAC
tAC
tAC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+
1
DQ
tLZ
t
OH
tOH
tOH
tOH
t
OH
tOH
tRCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1) CASꢀlatency = 2, Burst Length = Full Page
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
35
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
OH
t
OH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
tAC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1) CASꢀlatency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
36ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
RQL
High-Z
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
t
RQL
High-Z
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
37
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITES
AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ
n +ꢀ1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀ
ofꢀaꢀlongerꢀburst.ꢀTheꢀ128MbꢀSDRAMꢀusesꢀaꢀpipelinedꢀ
architectureꢀandꢀthereforeꢀdoesꢀnotꢀrequireꢀtheꢀ2n ruleꢀas-
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ
canꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀfollowingꢀaꢀpreviousꢀ
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ
aꢀpageꢀcanꢀbeꢀperformedꢀtoꢀtheꢀsameꢀbank,ꢀasꢀshownꢀinꢀ
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ
beꢀperformedꢀtoꢀaꢀdifferentꢀbank.
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ
shownꢀinꢀWRITEꢀCommandꢀdiagram.
WRITE COMMAND
CLK
HIGH
CKE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀ
command.ꢀOnceꢀtheꢀREADꢀcomꢀmandꢀisꢀregistered,ꢀtheꢀ
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn
+ꢀ1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀ
ofꢀaꢀlongerꢀburst.
CS
RAS
CAS
WE
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
sameꢀbankꢀ(providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀacti-
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtdplꢀafterꢀtheꢀ
clockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀinputꢀdataꢀelementꢀ
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtdplꢀofꢀ
atꢀleastꢀoneꢀclockꢀplusꢀtime,ꢀregardlessꢀofꢀfrequency.ꢀInꢀ
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ
mustꢀbeꢀusedꢀtoꢀmaskꢀinputꢀdataꢀforꢀtheꢀclockꢀedgeꢀpriorꢀ
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-
CHARGEꢀdiagram.ꢀDataꢀn+1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀ
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ
sameꢀbankꢀcannotꢀbeꢀissuedꢀuntilꢀtrpꢀisꢀmet.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note:ꢀA9ꢀisꢀ"Don'tꢀCare"ꢀforꢀx16.
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ
orꢀdisabledꢀforꢀthatꢀaccess.ꢀIfꢀautoꢀprechargeꢀisꢀenabled,ꢀ
theꢀrowꢀbeingꢀaccessedꢀisꢀprechargedꢀatꢀtheꢀcompletionꢀofꢀ
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ
followingꢀillustrations,ꢀautoꢀprechargeꢀisꢀdisabled.
Inꢀtheꢀcaseꢀofꢀaꢀfixed-lengthꢀburstꢀbeingꢀexecutedꢀtoꢀcomple-
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ
timeꢀ(asꢀdescribedꢀabove)ꢀprovidesꢀtheꢀsameꢀoperationꢀthatꢀ
wouldꢀresultꢀfromꢀtheꢀsameꢀfixed-lengthꢀburstꢀwithꢀautoꢀ
precharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀ
isꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀandꢀaddressꢀbusesꢀbeꢀ
availableꢀatꢀtheꢀappropriateꢀtimeꢀtoꢀissueꢀtheꢀcommand;ꢀtheꢀ
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ
usedꢀtoꢀtruncateꢀfixed-lengthꢀorꢀfull-pageꢀbursts.
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-inꢀelementꢀwillꢀbeꢀ
registeredꢀcoincidentꢀwithꢀtheꢀWRITEꢀcommand.ꢀSubsequentꢀ
dataꢀelementsꢀwillꢀbeꢀregisteredꢀonꢀeachꢀsuccessiveꢀposi-
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ
assumingꢀnoꢀotherꢀcommandsꢀhaveꢀbeenꢀinitiated,ꢀtheꢀ
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-
tinueꢀuntilꢀterminated.ꢀ(Atꢀtheꢀendꢀofꢀtheꢀpage,ꢀitꢀwillꢀwrapꢀ
toꢀcolumnꢀ0ꢀandꢀcontinue.)
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ
willꢀbeꢀtheꢀinputꢀdataꢀappliedꢀoneꢀclockꢀpreviousꢀtoꢀtheꢀ
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ
BurstꢀTermination,ꢀwhereꢀdataꢀn isꢀtheꢀlastꢀdesiredꢀdataꢀ
elementꢀofꢀaꢀlongerꢀburst.
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ
dataꢀprovidedꢀcoincidentꢀwithꢀtheꢀnewꢀcommandꢀappliesꢀtoꢀ
theꢀnewꢀcommand.
38ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE BURST
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE TO WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
RANDOM WRITE CYClES
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
Integrated Silicon Solution, Inc. — www.issi.comꢀ
39
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
D
IN n+1
DIN n+2
DON'T CARE
40ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
ADDRESS
DQ
PRECHARGE
WRITE
NOP
NOP
NOP
NOP
ACTIVE
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
41
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE - FUll PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
42ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
tCK
tCL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
tDS
t
DH
tDS
t
DH
D
IN
m
D
IN m+
2
DIN m+3
DQ
tRCD
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
43
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
AlTERNATING BANK WRITE ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
tDS
t
DH
tDS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN
b
D
IN b+
1
D
IN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
DPL - BANK 0
tRP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tDPL - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
44ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
ClOCK SUSPEND
ofꢀaꢀsuspendedꢀinternalꢀclockꢀedgeꢀisꢀignored;ꢀanyꢀdataꢀ
presentꢀonꢀtheꢀDQꢀpinsꢀremainsꢀdriven;ꢀandꢀburstꢀcountersꢀ
areꢀnotꢀincremented,ꢀasꢀlongꢀasꢀtheꢀclockꢀisꢀsuspended.ꢀ
(Seeꢀfollowingꢀexamples.)
Clockꢀsuspendꢀmodeꢀoccursꢀwhenꢀaꢀcolumnꢀaccess/burstꢀ
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ
theꢀsynchronousꢀlogic.
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ
theꢀinternalꢀclockꢀandꢀrelatedꢀoperationꢀwillꢀresumeꢀonꢀtheꢀ
subsequentꢀpositiveꢀclockꢀedge.
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ
Anyꢀcommandꢀorꢀdataꢀpresentꢀonꢀtheꢀinputꢀpinsꢀatꢀtheꢀtimeꢀ
Cꢀock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
D
IN
n
DIN n+1
DIN n+2
DON'T CARE
Cꢀock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
45
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
ClOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCKS tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
tAS tAH
tAS tAH
BA0, BA1
BANK
BANK
tDS tDH
tAC
tAC
tHZ
DQ
DOUT
m
D
OUT m+1
DIN e
D
IN e+1
tLZ
tOH
DON'T CARE
UNDEFINED
Notes:
1) CASꢀlatency = 3, Burst Length = 2, Auto Precharge is disabled.
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
46ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
PRECHARGE
PRECHARGE Command
The PRECHARGE command (see figure) is used to deac-
tivate the open row in a particular bank or the open row in
allbanks.Thebank(s)willbeavailableforasubsequentrow
access some specified time (trp) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
CLK
HIGH
CKE
CS
RAS
CAS
WE
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings while
in standby.The device may not remain in the power-down
statelongerthantherefreshperiod(64ms)sincenorefresh
operations are performed in this mode.
A0-A9,A11
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tcks). See figure below.
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
tRCD
tRAS
t
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than 64ms
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
47
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
POWER-DOWN MODE CYClE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
tCH
CLK
CKE
tCKS
t
CKH
t
CKS
tCKS
t
CMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/DQML
DQMH
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
48ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
BURST READ/SINGlE WRITE
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occursꢀareꢀdefinedꢀbelow.
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
theꢀwriteꢀburstꢀmodeꢀbitꢀ(M9)ꢀinꢀtheꢀmodeꢀregisterꢀtoꢀaꢀlogicꢀ
1.ꢀInꢀthisꢀmode,ꢀallꢀWRITEꢀcommandsꢀresultꢀinꢀtheꢀaccessꢀ
ofꢀaꢀsingleꢀcolumnꢀlocationꢀ(burstꢀofꢀone),ꢀregardlessꢀofꢀ
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccessꢀ
columnsꢀaccordingꢀtoꢀtheꢀprogrammedꢀburstꢀlengthꢀandꢀ
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ
=ꢀ0).
READ with Auto Precharge
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.
CONCURRENT AUTO PRECHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
whenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀthreeꢀclocksꢀpriorꢀ
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bankꢀmꢀisꢀregistered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
whileꢀanꢀaccessꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀisꢀ
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSIꢀ
READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP -BANKm
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK n,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tDPL -BANKm
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.comꢀ
49
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE with Auto Precharge
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
WRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀwhenꢀ
3.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀwhenꢀ
registered,ꢀ withꢀ theꢀ data-outꢀ appearingꢀ (CASꢀ latency)ꢀ
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtdplꢀ
isꢀmet,ꢀwhereꢀtdplꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀ
registered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀ
registeredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ
tdplꢀisꢀmet,ꢀwhereꢀtdplꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ
bankꢀm.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst,Write-Back
DPL - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP -BANKm
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst,Write-Back
DPL - BANK n
Precharge
t
t
RP - BANK n
Internal States
tDPL -BANKm
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
50ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
SINGlE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tOH
t
AC
DOUT m
DQ
tHZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1) CASꢀlatency = 2, Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
51
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tOH
t
OH
tOH
tOH
t
t
t
RCD
RAS
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1) CASꢀlatency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
52ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
SINGlE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
tAH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
t
AC
D
OUT
m
t
LZ
tHZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
tRP
Notes:
1) CASꢀlatency = 2, Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
53
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ROW
AS
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+1
D
OUT m+2
DOUT m+3
t
LZ
tOH
t
OH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
tRP
UNDEFINED
Notes:
1) CASꢀlatency = 2, Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
54ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
SINGlE WRITE WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN m(2)
ROW
A0-A9, A11
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
tAS tAH
BA0, BA1
BANK
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tDPL(3)
tRP
tRAS
tRC
DON'T CARE
Notes:
1) Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
3) tras must not be violated.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
55
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
SINGlE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN m(2)
ROW
A0-A9, A11
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
tAS tAH
BA0, BA1
BANK
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tDPL(3)
tRP
tRAS
tRC
DON'T CARE
Notes:
1) Burst Length = 1
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
3) tras must not be violated.
56ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
ALL BANKS
ROW
AS
tAH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
tDS
t
DH
tDS
t
DH
tDS
t
DH
tDS
t
DH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
t
t
t
RCD
RAS
RC
t
DPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
3) tras must not be violated.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
57
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
t
t
t
RCD
RAS
RC
tDPL
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x16: A9 and A11 = "Don't Care"
x8: A11 = "Don't Care"
58ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
ORDERING INFORMATION - VDD = 3.3V
Automotive Range A1: -40°C to +85°C
Frequency Speed (ns) Order Part No.
Package
ꢀ166ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
6ꢀ
7ꢀ
IS45S81600E-6TLA1ꢀ
IS45S81600E-7TLA1ꢀ
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSn
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS45S81600E-7CTLA1ꢀ
IS45S81600E-7CTNA1ꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAu
ꢀ
Frequency Speed (ns) Order Part No.
Package
ꢀ166ꢀMHzꢀ
6ꢀ
ꢀ
IS45S16800E-6TLA1ꢀ
IS45S16800E-6BLA1ꢀ
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
ꢀꢀ143ꢀMHzꢀ
7ꢀ
ꢀ
ꢀ
IS45S16800E-7TLA1ꢀ
IS45S16800E-7CTLA1ꢀ
IS45S16800E-7CTNA1ꢀ
IS45S16800E-7BLA1ꢀ
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAuꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
ꢀ
ꢀ
ꢀ
Automotive Range A2: -40°C to +105°C
Frequency Speed (ns) Order Part No.
Package
ꢀ143ꢀMHzꢀ
7ꢀ
ꢀ
ꢀ
IS45S81600E-7TLA2ꢀ
IS45S81600E-7CTLA2ꢀ
IS45S81600E-7CTNA2ꢀ
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAu
ꢀ
Frequency Speed (ns) Order Part No.
Package
ꢀ143ꢀMHzꢀ
7ꢀ
ꢀ
ꢀ
IS45S16800E-7TLA2ꢀ
IS45S16800E-7CTLA2ꢀ
IS45S16800E-7CTNA2ꢀ
IS45S16800E-7BLA2ꢀ
54-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-pinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAuꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notes:ꢀ
1.ꢀContactꢀProductꢀMarketingꢀforꢀLeadedꢀandꢀcopperꢀleadframeꢀpartsꢀsupport.
2.ꢀPartꢀnumbersꢀwithꢀ"L"ꢀorꢀ"N"ꢀareꢀleadfree,ꢀandꢀRoHSꢀcompliant.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
59
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
ForꢀAlloy42ꢀandꢀCuꢀlead-framesꢀwithꢀmatteꢀSnꢀplating
60ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
Integrated Silicon Solution, Inc. — www.issi.comꢀ
61
Rev. E
12/01/2011
IS45S81600E, IS45S16800E
62ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
12/01/2011
相关型号：
IS45S16800F-7BLA2
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-54
ISSI
©2020 ICPDF网 联系我们和版权申明