IS61C1024-12KI [ISSI]
128K x 8 HIGH-SPEED CMOS STATIC RAM; 128K ×8高速CMOS静态RAM
| 型号： | IS61C1024-12KI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总11页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61C1024
ISSI
IS61C1024L
128K x 8 HIGH-SPEED
CMOS STATIC RAM
MAY 1999
DESCRIPTION
FEATURES
The ISSI IS61C1024 and IS61C1024L are very high-speed,
low power, 131,072-word by 8-bit CMOS static RAMs. They
are fabricated using ISSI's high-performance CMOS
technology.Thishighlyreliableprocesscoupledwithinnovative
circuit design techniques, yields higher performance and low
power consumption devices.
• High-speed access time: 12, 15, 20, 25 ns
• Low active power: 600 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
• Fully static operation: no clock or refresh
required
EasymemoryexpansionisprovidedbyusingtwoChipEnable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Low power version available: IS61C1024L
The IS61C1024 and IS61C1024L are available in 32-pin
300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I,
8 x 13.4) packages.
• Commercial and industrial temperature ranges
available
FUNCTIONAL BLOCK DIAGRAM
512 x 2048
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
SR028-1K
05/12/99
®
IS61C1024
IS61C1024L
ISSI
PIN CONFIGURATION
32-Pin SOJ
PIN CONFIGURATION
32-Pin TSOP (Type 1) (T) and sTSOP (Type 1) (H)
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
CE1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
CE2
OE
WE
I/O0-I/O7
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
TRUTH TABLE
Mode
WE
CE1 CE2 OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled H
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Read
Write
H
L
X
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
®
IS61C1024
ISSI
IS61C1024L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.5
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
°C
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
5
7
COUT
Notes:
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.2
VCC + 0.5
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–2
–5
2
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC
Outputs Disabled
Com.
Ind.
–2
–5
2
5
µA
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
SR028-1K
05/12/99
®
IS61C1024
IS61C1024L
ISSI
IS61C1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12 ns
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB1
Vcc Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
85
110
—
—
85
110
—
—
85
110
—
—
85
110
mA
IOUT = 0 mA, f = 0
Ind.
Vcc Dynamic Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
170
180
—
—
160
170
—
—
150
160
—
—
140
150
mA
mA
IOUT = 0 mA, f = fMAX
Ind.
TTL Standby Current
(TTL Inputs)
VCC = VCC MAX.,
VIN = VIH or VIL
CE1 ≥ VIH, f = 0 or
CE2 ≤ VIL, f = 0
Com.
Ind.
—
—
40
60
—
—
40
60
—
—
40
60
—
—
40
60
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = VCC MAX.,
CE1 ≤ VCC – 0.2V,
CE2 ≤ 0.2V
Com.
Ind.
—
—
30
40
—
—
30
40
—
—
30
40
—
—
30
40
mA
VIN > VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS61C1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB1
Vcc Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
85
110
—
—
85
110
—
—
85
110
mA
IOUT = 0 mA, f = 0
Ind.
Vcc Dynamic Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
160
170
—
—
150
160
—
—
140
150
mA
mA
IOUT = 0 mA, f = fMAX
Ind.
TTL Standby Current
(TTL Inputs)
VCC = VCC MAX,
VIN = VIH or VIL
CE1 ≥ VIH, f = 0 or
CE2 ≤ VIL, f = 0
Com.
Ind.
—
—
40
60
—
—
40
60
—
—
40
60
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = VCC MAX.,
CE1 ≤ VCC – 0.2V,
CE2 ≤ 0.2V
Com.
Ind.
—
—
500
750
—
—
500
750
—
—
500
750
µA
VIN > VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
®
IS61C1024
ISSI
IS61C1024L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
(2)
-12
Min.
-15 ns
Min.
-20 ns
Min.
-25 ns
Symbol Parameter
Max.
—
12
—
12
12
6
Max.
—
15
—
15
15
7
Max.
—
20
—
20
20
9
Min.
25
—
3
Max.
Unit
tRC
Read Cycle Time
12
—
3
15
—
3
20
—
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
25
—
tOHA
tACE1
tACE2
tDOE
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
0
25
25
9
(3)
tLZOE
OE to Low-Z Output
OE to High-Z Output
—
6
—
6
—
7
—
(3)
tHZOE
0
0
0
0
10
—
tLZCE1(3) CE1 to Low-Z Output
tLZCE2(3) CE2 to Low-Z Output
2
—
—
7
2
—
—
8
3
—
—
9
3
2
2
3
3
—
(3)
tHZCE
CE1 or CE2 to High-Z Output
0
0
0
0
10
—
(4)
tPU
CE1 or CE2 to Power-Up
0
—
12
0
—
12
0
—
18
0
(4)
tPD
CE1 or CE2 to Power-Down
—
—
—
—
20
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. -12 ns device for IS61C1024 only.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
SR028-1K
05/12/99
®
IS61C1024
IS61C1024L
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
CE2
t
t
ACE1
ACE2
t
t
HZCE1
HZCE2
t
t
LZCE1
LZCE2
HIGH-Z
DOUT
DATA VALID
CE2_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
®
IS61C1024
ISSI
IS61C1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
(3)
-12 ns
Min.
-15 ns
Min.
-20 ns
-25 ns
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
7
Max.
—
—
—
—
—
—
—
—
—
7
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
12
10
10
10
0
15
12
12
12
0
20
15
15
15
0
—
25
20
20
20
0
—
tSCE1
tSCE2
tAW
CE1 to Write End
—
—
CE2 to Write End
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
tHA
—
—
tSA
0
0
0
—
0
—
(4)
tPWE
tSD
WE Pulse Width
10
7
10
8
12
10
0
—
15
12
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
tHD
0
0
—
—
(5)
tHZWE
—
2
—
2
—
2
10
—
—
2
12
—
(5)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IS61C1024 only.
4. Tested with OE HIGH.
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
SR028-1K
05/12/99
®
IS61C1024
IS61C1024L
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
tWC
VALID ADDRESS
ADDRESS
tSCE1
tSCE2
tSA
tHA
CE1
CE2
tAW
tPWE1
tPWE2
WE
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
DOUT
tSD
tHD
DATAIN VALID
DIN
CE2_WR1.eps
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
tWC
ADDRESS
OE
VALID ADDRESS
tHA
LOW
HIGH
CE1
CE2
tAW
tPWE1
WE
tHZWE
tLZWE
tSA
HIGH-Z
DATA UNDEFINED
DOUT
tSD
tHD
DATAIN VALID
DIN
CE2_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
®
IS61C1024
ISSI
IS61C1024L
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
OE
CE1
LOW
HIGH
CE2
WE
t
t
AW
t
PWE2
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE2_WR3.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
SR028-1K
05/12/99
®
IS61C1024
IS61C1024L
ISSI
IS61C1024 STANDARD VERSION
ORDERING INFORMATION
IS61C1024 STANDARD VERSION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
12
12
12
12
IS61C1024-12J
IS61C1024-12K
IS61C1024-12H
IS61C1024-12T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
12
12
12
12
IS61C1024-12JI
IS61C1024-12KI
IS61C1024-12HI
IS61C1024-12TI
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
TSOP (Type I)
TSOP (Type I)
15
15
15
15
IS61C1024-15J
IS61C1024-15K
IS61C1024-15H
IS61C1024-15T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
15
15
15
15
IS61C1024-15JI
IS61C1024-15KI
IS61C1024-15HI
IS61C1024-15TI
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
TSOP (Type I)
TSOP (Type I)
20
20
20
20
IS61C1024-20J
IS61C1024-20K
IS61C1024-20H
IS61C1024-20T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
20
20
20
20
IS61C1024-20JI
IS61C1024-20KI
IS61C1024-20HI
IS61C1024-20TI
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
TSOP (Type I)
TSOP (Type I)
25
25
25
25
IS61C1024-25J
IS61C1024-25K
IS61C1024-25H
IS61C1024-25T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
25
25
25
25
IS61C1024-25JI
IS61C1024-25KI
IS61C1024-25HI
IS61C1024-25TI
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
TSOP (Type I)
TSOP (Type I)
IS61C1024L LOW POWER VERSION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
IS61C1024L LOW POWER VERSION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
15
20
25
IS61C1024L-15JI
300-mil Plastic SOJ
15
20
25
IS61C1024L-15J
IS61C1024L-15K
IS61C1024L-15H
IS61C1024L-15T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
IS61C1024L-15KI 400-mil Plastic SOJ
IS61C1024L-12HI sTSOP (Type I)
IS61C1024L-15TI TSOP (Type I)
TSOP (Type I)
IS61C1024L-20JI
300-mil Plastic SOJ
IS61C1024L-20J
IS61C1024L-20K
IS61C1024L-20H
IS61C1024L-20T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
IS61C1024L-20KI 400-mil Plastic SOJ
IS61C1024L-12HI sTSOP (Type I)
IS61C1024L-20TI TSOP (Type I)
TSOP (Type I)
IS61C1024L-25JI
300-mil Plastic SOJ
IS61C1024L-25J
IS61C1024L-25K
IS61C1024L-25H
IS61C1024L-25T
300-mil Plastic SOJ
400-mil Plastic SOJ
sTSOP (Type I)
IS61C1024L-25KI 400-mil Plastic SOJ
IS61C1024L-12HI sTSOP (Type I)
IS61C1024L-25TI TSOP (Type I)
TSOP (Type I)
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
®
IS61C1024
IS61C1024L
ISSI
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
SR028-1K
05/12/99
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