IS61LF12836EC-6.5TQL [ISSI]
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM;
| 型号： | IS61LF12836EC-6.5TQL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM 静态存储器 |
| 文件： | 总36页 (文件大小：2452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH
SRAM
OCTOBER 2015
FEATURES
DESCRIPTION
The 4Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and
networking applications. The IS61(64)LF/VF12836EC are
organized as 131,072 words by 36bits. The
IS61(64)LF/VF12832EC are organized as 131,072 words by
32bits. The IS61(64)LF/VF25618EC are organized as 262,144
words by 18 bits. Fabricated with ISSI's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (/BWE) input combined with one or more
individual byte write signals (/BWx). In addition, Global
Write (/GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Power supply:
LF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
VF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
JTAG Boundary Scan for BGA packages
Industrial and Automotive temperature support
Lead-free available
Bursts can be initiated with either /ADSP (Address Status
Processor) or /ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the /ADV (burst address
advance) input pin.
Error Detection and Error Correction
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
Clock Access Time
Cycle time
-6.5
6.5
-7.5
7.5
Units
ns
tKC
7.5
8.5
ns
Frequency
133
117
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
1
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
BLOCK DIAGRAM
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
2
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
PIN CONFIGURATION
128K x 36, 165-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
A
11
NC
A
B
C
D
E
F
NC
A
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
/BWc /BWb /CE2
/BWd /BWa CLK
/BWE /ADSC /ADV
NC
A
A
NC
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
/OE
VSS
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
G
H
J
DQd
DQd
DQd
DQd
DQPd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
NC
K
L
M
N
P
R
NC
TDI
TMS
TDO
TCK
MODE
NC
A
A
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
A0,A1
A
Synchronous Burst Address Inputs
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
/BWx (x=a-d)
/GW
/OE
DQx
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
DQPx
TCK,TDI,TDO,TMS JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
VDD
VDDQ
VSS
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
3
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 32, 165-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
/BWc /BWb /CE2
/BWd /BWa CLK
NC
/BWE /ADSC /ADV
NC
A
A
NC
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
/OE
VSS
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
NC
DQc
DQc
DQc
DQc
NC
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
DQb
DQb
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
NC
K
L
M
N
P
R
NC
NC
TDI
TMS
TDO
TCK
NC
MODE
NC
A
A
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
JTAG Pins
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
TCK,TDI,TDO,TMS
ZZ
Asynchronous Power Sleep Mode
No Connect
NC
VDD
Power Supply
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
VDDQ
VSS
I/O Power Supply
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
4
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
256K x 18, 165-Ball BGA (Top View)
1
2
3
4
/BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
6
7
8
9
10
A
11
A
A
B
C
D
E
F
NC
A
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
/CE2
/BWE /ADSC /ADV
NC
A
/BWa CLK
A
NC
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
/OE
VSS
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQb
DQb
DQb
DQb
VSS
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
K
L
NC
NC
M
N
P
R
NC
NC
TDI
TMS
TDO
TCK
NC
MODE
A
A
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
A0,A1
A
Synchronous Burst Address Inputs
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
/BWx (x=a-b)
/GW
/OE
DQx
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
DQPx
TCK,TDI,TDO,TMS JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
VDD
VDDQ
VSS
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
5
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 36, 119-Ball BGA (Top View)
1
2
3
4
/ADSP
/ADSC
VDD
5
6
7
VDDQ
A
A
A
A
VDDQ
A
B
C
D
E
F
NC
NC
CE2
A
A
A
A
A
/CE2
A
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
VSS
VSS
VSS
/BWc
VSS
NC
NC
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
/CE
/OE
/ADV
/GW
VDD
G
H
J
DQd
DQd
DQd
DQd
DQPd
A
VSS
/BWd
VSS
VSS
VSS
MODE
A
CLK
NC
DQa
DQa
DQa
DQa
DQPa
A
K
L
/BWE
A1*
M
N
P
R
T
A0*
VDD
NC
NC
A
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
A0,A1
A
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,TDO,TMS JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
119-Ball, 14 mm x 22 mm BGA
7 x 17 Ball Array
VDD
VDDQ
VSS
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
6
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 32, 119-Ball BGA (Top View)
1
2
3
4
/ADSP
/ADSC
VDD
5
6
7
VDDQ
A
A
A
A
VDDQ
A
B
C
D
E
F
NC
NC
CE2
A
A
A
A
A
/CE2
A
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VSS
VSS
VSS
/BWc
VSS
NC
NC
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
/CE
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
NC
/OE
/ADV
/GW
VDD
G
H
J
VSS
/BWd
VSS
VSS
VSS
MODE
A
CLK
NC
K
L
/BWE
A1*
M
N
P
R
T
A0*
A
VDD
A
NC
NC
A
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
A0,A1
A
Synchronous Burst Address Inputs
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
/BWx (x=a-b)
/GW
/OE
DQx
Synchronous Data Inputs/Outputs
TCK,TDI,TDO,TMS JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
Power Supply
I/O Power Supply
Ground
VDD
VDDQ
VSS
Bottom View
119-Ball, 14 mm x 22 mm BGA
7 x 17 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
7
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
256K x 18, 119-Ball BGA (Top View)
1
2
3
4
/ADSP
/ADSC
VDD
5
6
7
VDDQ
A
A
A
A
VDDQ
A
B
C
D
E
F
NC
NC
CE2
A
A
A
A
A
/CE2
A
NC
NC
DQb
NC
NC
VSS
VSS
VSS
/BWb
VSS
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
DQPa
NC
NC
DQb
NC
/CE
DQa
VDDQ
DQa
NC
VDDQ
NC
/OE
DQa
NC
DQb
NC
/ADV
/GW
VDD
G
H
J
DQb
VDDQ
NC
DQa
VDD
NC
VDD
DQb
NC
VDDQ
DQa
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
CLK
NC
K
L
DQb
VDDQ
DQb
NC
DQa
NC
DQb
NC
/BWE
A1*
VDDQ
NC
M
N
P
R
T
DQa
NC
DQPb
A
A0*
DQa
NC
NC
VDD
A
NC
A
NC
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
A0,A1
A
Synchronous Burst Address Inputs
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
/BWx (x=a-b)
/GW
/OE
DQx
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
DQPx
TCK,TDI,TDO,TMS JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
119-Ball, 14 mm x 22 mm BGA
7 x 17 Ball Array
VDD
VDDQ
VSS
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
8
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 36, 100PIN QFP (Top View)
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
128K x 36
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
Symbol
/GW
Pin Name
Synchronous Global Write Enable
A0,A1
Synchronous Burst Address Inputs
Synchronous Address Inputs
/OE
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
Asynchronous Power Sleep Mode
No Connect
A
DQx
DQPx
ZZ
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADSP
/ADSC
MODE
NC
VDD
VDDQ
VSS
Power Supply
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
I/O Power Supply
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Ground
/BWx (x=a-d)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
9
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 32, 100PIN QFP (Top View)
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
128K x 32
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
Symbol
/BWx (x=a-d)
Pin Name
Synchronous Byte Write Inputs
A0,A1
A
Synchronous Burst Address Inputs
Synchronous Address Inputs
/GW
/OE
Synchronous Global Write Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Asynchronous Power Sleep Mode
No Connect
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
DQx
ZZ
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
NC
VDD
VDDQ
VSS
Power Supply
Synchronous Chip Enable
I/O Power Supply
Synchronous Byte Write Enable
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
10
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
256K x 18, 100PIN QFP (Top View)
NC
NC
NC
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
256K x 18
VDD
ZZ
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
NC
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
Pin Name
Synchronous Clock
Symbol
/GW
Pin Name
Synchronous Global Write Enable
A0,A1
Synchronous Burst Address Inputs
Synchronous Address Inputs
/OE
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
Asynchronous Power Sleep Mode
No Connect
A
DQx
DQPx
ZZ
/ADV
Synchronous Burst Address Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Burst Sequence Selection
/ADSP
/ADSC
MODE
NC
VDD
VDDQ
VSS
Power Supply
/CE,CE2,/CE2
/BWE
Synchronous Chip Enable
I/O Power Supply
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Ground
/BWx (x=a-b)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
11
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
TRUTH TABLE
SYNCHRONOUS TRUTH TABLE
OPERATION
ADDRESS /CE /CE2 CE2
ZZ ADSP ADSC
ADV WRITE
/OE
CLK
DQ
None
None
H
L
X
X
H
X
H
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
High-Z
D
Read Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Write Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Q
Read Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
Read Cycle, Begin Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (/BWa-d) and /BWE are LOW or /GW is LOW. /WRITE = H for all /BWx, /BWE, /GW HIGH.
3. /BWa enables WRITEs to DQa’s and DQPa. /BWb enables WRITEs to DQb’s and DQPb. /BWc enables WRITEs to DQc’s and DQPc. /BWd enables
WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except /OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, /OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. /ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and
/BWE LOW or /GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
12
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
PARTIAL TRUTH TABLE
Operation
/GW
H
/BWE
/BWa
/BWb
/BWc
/BWd
READ
H
L
L
L
L
L
L
X
X
H
L
X
H
H
L
X
H
H
H
L
X
H
H
H
H
L
READ
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
H
H
H
H
L
H
H
H
L
H
H
L
H
L
L
X
X
X
X
Notes:
1.
2.
X means "Don't Care".
All inputs in this table must beet setup and hold time around the rising edge of CLK.
ADDRESS SEQUENCE IN BURST MODE
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
00
A1 A0
01
A1 A0
10
A1 A0
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss )
0,0
A1', A0' = 1,1
0,1
1,0
Power Up Sequence
Vddq → Vdd1 → I/O Pins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is stable. The inputs of the I/O pins can be applied at the same time as Vddq as long as Vih (level of I/O
pins) is lower than Vddq.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
13
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
ERROR DETECTION AND CORRECTION
Independent ECC with Hamming code for each byte.
Detect and correct one bit error per byte.
Better reliability than parity code schemes that could detect error bit but NOT correct it.
Backward compatible : Drop in replacement to current in industry standard devices without ECC.
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
TSTG
PD
Parameter
LF Value
–65 to +150
1.6
VF Value
–65 to +150
1.6
Unit
°C
W
mA
V
Storage Temperature
Power Dissipation
Output Current (per I/O)
IOUT
100
100
VIN, VOUT Voltage Relative to Vss for I/O Pins
VDD
–0.5 to VDDQ+0.5
–0.5 to VDD+0.5
–0.3 to VDDQ + 0.3
–0.3 to VDD + 0.3
Voltage Relative to Vss for Address and Control
Inputs
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to
avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Option
IS61LFXXXXX
Range
Commercial
Industrial
Commercial
Industrial
Automotive
Automotive
VDD
VDDQ
Ambient Temperature
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
2.5V ± 5%
3.3V ± 5%
2.5V ± 5%
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
3.3V / 2.5V ± 5%
2.5V ± 5%
IS61VFXXXXX
IS64LFXXXXX
IS64VFXXXXX
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
14
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Over operating temperature range)
Symbol
Parameter
Output HIGH Voltage
Output LOW Voltage
Test Conditions
3.3V
Max.
2.5V
Max.
Unit
V
Min.
2.4
Min.
2.0
Voh
Ioh=-4.0 mA(3.3V)
Ioh=–1.0 mA(2.5V)
Iol=8.0 mA(3.3V)
Iol=1.0 mA(2.5V)
—
—
Vol
—
0.4
—
0.4
V
Vih
Vil
Ili
Input HIGH Voltage
Input LOW Voltage
2.0
–0.3
–5
Vdd+0.3
1.7
–0.3
–5
Vdd+0.3
V
V
0.8
5
0.7
5
Input Leakage Current
Output Leakage Current
Vss≤Vin≤Vdd
μA
μA
Ilo
Vss≤Vout≤Vddq,/OE=Vih
–5
5
–5
5
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Temp.
-6.5
-7.5
Unit
range
MAX
MAX
x18 x36/32
x18
x36/32
155
Device Selected, OE = Vih, ZZ ≤ Vil,All Inputs
≤ 0.2V or ≥ Vdd – 0.2V,Cycle Time ≥ tkc min.
Icc
AC Operating,
Supply Current
Com.
Ind.
175
180
190
100
175
180
190
100
155
160
175
100
mA
mA
160
Auto
Com.
175
Device Deselected,Vdd = Max.,All Inputs ≤ Vil
or ≥ Vih,ZZ ≤ Vil, f = Max.
Isb
Standby Current
TTL Input
100
Ind.
Auto
Com.
Ind.
110
130
80
110
130
80
110
130
80
110
130
80
Device Deselected,Vdd = Max.,Vin ≤ Vss +
0.2V or ≥Vdd – 0.2V,f = 0
Isb1
Standby Current
CMOS Input
mA
85
85
85
85
Auto
100
100
100
100
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥Vdd–0.2V.
CAPACITANCE
Symbol
Cin
Cout
Parameter
Conditions
Vin = 0V
Vout = 0V
Max.
Unit
pF
pF
Input Capacitance
Input/Output Capacitance
6
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
15
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-6.5
-7.5
Unit
Min.
—
7.5
2.2
2.2
—
2.5
2.5
—
Max.
133
—
—
—
6.5
—
—
3.8
3.2
—
3.5
—
—
—
—
—
—
—
—
—
Min.
—
8.5
2.5
2.5
—
2.5
2.5
—
Max.
117
—
—
—
7.5
—
—
4.0
3.4
—
3.5
—
—
—
—
—
—
—
—
—
fMAX
tKC
tKH
tKL
tKQ
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Clock Access Time
tKQX(2)
tKQLZ(2,3)
tKQHZ(2,3)
tOEQ
tOELZ(2,3)
tOEHZ(2,3)
tAS
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
—
0
—
—
0
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
tSS
tWS
tCES
tSE
tADVS
tDS
tAH
tSH
tHE
tWH
Address Hold Time
Address Status Hold Time
Clock Enable Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
—
—
—
—
—
—
—
—
—
—
—
—
tCEH
tADVH
tDH
tPOWER(4)
VDD (typical) to First Access
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. tPOWER is the time that the power needs to be supplied above VDD (min) initially before READ or WRITE operation can be initiated.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
16
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
Input Rise and Fall Times
0V to 3.0V
1.5 ns
Input and Output Timing and Reference Level
1.5V
VTT
1.5V
VLOAD
3.3V
R1, R2
Output Load
317Ω, 351Ω
See Figures 1 and 2
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
Input Rise and Fall Times
0V to 2.5V
1.5 ns
Input and Output Timing and Reference Level
1.25V
VTT
1.25V
VLOAD
2.5V
R1, R2
Output Load
1667Ω, 1538Ω
See Figures 1 and 2
I/O OUTPUT LOAD EQUIVALENT
R1
VLOAD
OUTPUT
ZO=50
Ω
OUTPUT
50
Ω
5 pF
Including
jig and
scope
R2
VTT
Figure1
Figure2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
17
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
READ/WRITE CYCLE TIMING
tKC
CLK
tKH
tSS
tSH
/ADSP is blocked by /CE inactive
tKL
/ADSP
/ADSC
tSS
tSH
/ADV
Address
/GW
tAS
tAH
RD1
WR1
RD2
RD3
tWS
tWH
tWH
tWS
/BWE
tWH
tWS
WR1
/BWd-/BWa
/CE
/CE Masks /ADSP
tCES
tCES
tCEH
tCEH
CE2 and /CE2 only sampled with /ADSP or /ADSC
CE2
tCEH
Unselected with /CE2
tCES
/CE2
tOELZ
tOEHZ
tOEQ
/OE
tKQX
DATAOUT
High-Z
tKQLZ
tKQ
High-Z
tKQLZ
tKQ
1a
2a
2b
tKQX
2c
2d
tKQHZ
DATAIN
1a
High-Z
tDH
tDS
Single Read
Flow-through
Single Write
Burst Read
Unselected
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
18
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
WRITE CYCLE TIMING
tKC
CLK
tKH
tSS
tSH
/ADSP is blocked by /CE inactive
/ADSC initiates Write
tKL
/ADSP
/ADSC
/ADV must be inactive for /ADSP Write
tAVS
tAVH
/ADV
tAS
tAH
Address
WR1
WR2
WR3
tWS
tWH
tWH
/GW
tWS
/BWE
tWS
tWH
tWS
tWH
/BWx
/CE
WR1
tCEH
WR2
WR3
tCES
/CE Masks /ADSP
tCEH
tCEH
tCES
tCES
Unselected with CE2
CE2 and /CE2 only sampled with /ADSP or/ ADSC
CE2
/CE2
/OE
High-Z
DATAOUT
DATAIN
tDS
tDH
/BW1-/BW4 only are applied to first cycle of WR2
1a
2a
2b
2c
2d
3a
High-Z
Single Write
Burst Write
Write
Unselected
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SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions Temperature Range
Min.
—
—
—
—
2
Max.
35
40
60
2
—
2
—
Unit
Isb2
Current during SNOOZE MODE ZZ ≥ Vih
Com.
Ind.
Auto.
—
—
—
mA
tpds
tpus
tzzi
ZZ active to input ignored
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
—
0
trzzi
—
SLEEP MODE TIMING
CLK
ZZ
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
tZZI
Isupply
ISB2
tRZZI
Deselect or Read Only
All Inputs
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs (Q)
High-Z
Don't Care
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IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed
circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary
scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal
is not required
Disabling the JTAG feature
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They
may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up,
the device will come up in a reset state, which will not interfere with device operation.
Test Access Port Signal List:
1. Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
2. Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is
sampled on the rising edge of TCK.
3. Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information
into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant
bit (MSB) of any register. For more information regarding instruction register loading, please see the TAP
Controller State Diagram.
4. Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data
out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states.
In all other states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register. For more information, please see the TAP Controller
State Diagram.
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TAP Controller State and Block Diagram
...
Boundary Scan Register (75 bits)
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
Instruction Register (3 bits)
Control Signals
TDO
TMS
TCK
TAP Controller
TAP Controller State Machine
1
Test Logic
Reset
0
1
1
1
Run Test
Idle
Select DR
0
Select IR
0
0
1
1
Capture
Capture
DR
IR
0
0
0
0
Shift DR
1
Shift IR
1
1
1
Exit1 DR
0
Exit1 IR
0
0
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
Update
DR
Update IR
1
0
1
0
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Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while
the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that
TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
1. Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a
reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs
are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
2. Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to
be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
3. Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are
also included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the
SRAM Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on
the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
4. Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out
when the TAP controller is in the shift-DR state.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size
3
1
ID
32
75
Boundary Scan
TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be
used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the
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TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
1. EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register
cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first
test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the
PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the
PRELOAD data is driven onto the output balls.
2. IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the
device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller is given a test logic reset state.
3. SAMPLE Z
If the SAMPLE-Z instruction is loaded in the instruction register, all SRAM outputs are forced to an inactive drive
state (high-Z), moving the TAP controller into the capture-DR state loads the data in the SRAMs input into the
boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP
controller is moved to the shift-DR state.
4. SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the
capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the
SRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is
possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to
capture a signal while in transition. This will not harm the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time. The SRAM clock input might not be captured correctly if there is no way in a design to stop
(or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other
signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is
captured, it is possible to shift out the data by putting the TAP into the shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
6. BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the
bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected together on a board.
7. PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
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JTAG TAP DC ELECTRICAL CHARACTERISTICS (VDDQ=3.3V Operating Range)
Parameter
Symbol
Min
2.0
–0.3
2.4
-
Max
VDD+0.3
0.8
Units
Notes
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
VIH1
V
VIL1
V
VOH1
VOL1
VOH2
VOL2
IX
-
V
|IOH1|=2mA
IOL1=2mA
0.4
V
2.9
-
-
V
|IOH2|=100uA
IOL2=100uA
0 ≤ Vin ≤ VDD
0.2
V
JTAG Input Load Current
-10
+10
uA
Notes:
1.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG TAP DC ELECTRICAL CHARACTERISTICS (VDDQ=2.5V Operating Range)
Parameter
Symbol
VIH1
VIL1
VOH1
VOL1
VOH2
VOL2
IX
Min
1.7
–0.3
2.0
-
2.1
-
-10
Max
VDD+0.3
0.7
Units
V
V
V
V
V
V
uA
Notes
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
-
|IOH1|=2mA
IOL1=2mA
|IOH2|=100uA
IOL2=100uA
0 ≤ Vin ≤ VDD
0.4
-
0.2
+10
JTAG Input Load Current
Notes:
2.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG AC Test Conditions
(Over the Operating Temperature Range)
Parameter
Symbol
VIH1
VIL1
2.5V Option
3.3V Option
Units
V
V
Input Pulse High Level
Input Pulse Low Level
2.5
0
3.0
0
Input rise and fall time
Test load termination supply voltage
Input and Output Timing Reference Level
TR1
VREF
VREF
1.5
1.25
1.25
1.5
1.5
1.5
ns
V
V
TAP Output Load Equivalent
VREF
50Ω
50Ω
Output
20pF
Test Comparator
VREF
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JTAG AC Characteristics
(Over the Operating Temperature Range)
Parameter
Symbol
tTHTH
tTHTL
Min
100
40
40
10
10
10
10
–
Max
–
Units
ns
TCK cycle time
TCK high pulse width
TCK low pulse width
TMS Setup
–
ns
tTLTH
–
ns
tMVTH
tTHMX
tDVTH
tTHDX
tTLOV
–
ns
TMS Hold
–
ns
TDI Setup
–
ns
TDI Hold
–
ns
TCK Low to Valid Data*
20
ns
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
TMS
TDI
tDVTH
tTHDX
tTLOV
TDO
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Instruction Set
Code
000
Instruction
EXTEST
TDO Output
Notes
2, 6
Boundary Scan Register
001
010
IDCODE
SAMPLE-Z
32-bit Identification Register
Boundary Scan Register
1, 2
5
011
100
101
110
111
PRIVATE
SAMPLE(/PRELOAD)
PRIVATE
Do Not Use
Boundary Scan Register
Do Not Use
4
5
PRIVATE
Do Not Use
5
BYPASS
Bypass Register
3
Notes:
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the
shift-DR state.
4. SAMPLE instruction does not place Qs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6.
This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high, Q will be updated with
information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the
internal register can be changed during SAMPLE and EXTEST only.
ID Register Definition
Instruction Field
Revision Number (31:28) Reserved for version number.
Description
128K x 36/32
xxxx
256K x 18
xxxx
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
Defines depth of SRAM. 128K or 256K
Defines Width of the SRAM. x36/32 or x18
Reserved for future use.
00110
00100
xxxxx
00011010101
1
00111
00011
xxxxx
00011010101
1
Allows unique identification of SRAM vendor.
ID Register Presence (0) Indicate the presence of an ID register.
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Boundary Scan Order
165 BGA
119 BGA
X36/32
X36/32
Bump ID
X18
Bump ID
X18
Bit #
Signal
MODE
NC
Signal
MODE
NC
Bit #
1
2
Signal
MODE
NC
Bump ID
3R
4L
Signal Bump ID
1
2
1R
6N
1R
6N
MODE
NC
3R
4L
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
A
A
A
A
A
A
A
11P
8P
8R
9R
9P
NC
A
A
A
A
A
A
A
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
A
A
A
11P
8P
8R
9R
9P
3
4
5
6
7
8
9
NC
A
A
A
A
A
A
A
7R
4T
3T
5B
5C
5A
5T
6R
7T
6P
7N
6M
7P
6N
7L
NC
A
A
A
A
A
A
A
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
A
A
A
7R
2T
3T
5B
5C
5A
5T
6R
7T
6P
7N
6M
7L
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10A
10B
9A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10A
10B
9A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ZZ
ZZ
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
DQPa
DQa
DQa
DQPa
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
6K
7P
6N
6L
6K
6L
7K
6H
7G
7H
6F
7E
6G
6E
7D
6D
6T
6A
6C
4G
4A
4B
4F
4M
4H
4K
7C
7K
6H
7G
6F
7E
6D
6G
6E
7D
7H
6T
6A
6C
4G
4A
4B
4F
4M
4H
4K
7C
A
A
A
A
/ADV
/ADSP
/ADSC
/OE
/BWE
/GW
CLK
NC
/ADV
/ADSP
/ADSC
/OE
/BWE
/GW
CLK
NC
/ADV
/ADSP
/ADSC
/OE
/BWE
/GW
CLK
NC
/ADV
/ADSP
/ADSC
/OE
/BWE
/GW
CLK
NC
9B
8A
8B
7A
7B
6B
11B
9B
8A
8B
7A
7B
6B
11B
35
36
37
38
39
40
Continue next page
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165 BGA
119 BGA
X36/32
Bump ID
X18
Bump ID
X36/32
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
X18
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Signal
NC
Signal
NC
/CE2
/BWa
NC
/BWb
NC
CE2
/CE
A
A
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
A
A
A
A
A1
Signal
NC
Bump ID
1B
6B
5L
Signal Bump ID
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1K
1L
1M
2J
2K
2L
2M
1N
3P
3R
4R
4P
6P
6R
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
NC
/CE2
/BWa
NC
/BWb
NC
CE2
/CE
A
A
NC
NC
NC
1B
6B
5L
5G
3G
3L
/CE2
/BWa
/BWb
/BWc
/BWd
CE2
/CE
A
/CE2
/BWa
/BWb
/BWc
/BWd
CE2
/CE
A
5G
3G
3L
2B
4E
3A
2A
1C
2D
1E
2F
1D
2E
1G
2H
2G
1H
2K
1L
1K
2M
1N
2L
2N
1P
2P
2R
2C
3B
3C
4N
4P
2B
4E
3A
2A
1C
2D
1E
2F
1G
2H
1D
2E
2G
1H
2K
1L
2M
1N
2P
2L
2N
1P
1K
2R
2C
3B
3C
4N
4P
A
NC
A
NC
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
A
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
A
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
A
A
A
A
A1
1K
1L
1M
1N
2K
2L
2M
2J
3P
3R
4R
4P
6P
6R
A
A
A
A1
A
A
A
A1
A0
A0
A0
A0
Note : DQPa, DQPb, DQPc, and DQPd pins of x36 IO option are NC of x32 IO option.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
29
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
ORDERING INFORMATION
The ordering code information of the product family
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
30
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Commercial Range: 0°C to 70°C
VDD
SPEED
X36
X32
X18
Package
100 QFP
IS61LF12836EC-6.5TQ
IS61LF12836EC-6.5B3
IS61LF12836EC-6.5B2
IS61LF12832EC-6.5TQ
IS61LF12832EC-6.5B3
IS61LF12832EC-6.5B2
IS61LF25618EC-6.5TQ
IS61LF25618EC-6.5B3
IS61LF25618EC-6.5B2
VDD =3.3V
VDDQ=2.5V
or
6.5ns
165 BGA
119 BGA
VDDQ=3.3V
IS61LF12836EC-6.5TQL IS61LF12832EC-6.5TQL IS61LF25618EC-6.5TQL 100 QFP, Lead-free
IS61LF12836EC-6.5B3L
IS61LF12836EC-6.5B2L
IS61LF12836EC-7.5TQ
IS61LF12836EC-7.5B3
IS61LF12836EC-7.5B2
IS61LF12832EC-6.5B3L
IS61LF12832EC-6.5B2L
IS61LF12832EC-7.5TQ
IS61LF12832EC-7.5B3
IS61LF12832EC-7.5B2
IS61LF25618EC-6.5B3L
IS61LF25618EC-6.5B2L
IS61LF25618EC-7.5TQ
IS61LF25618EC-7.5B3
IS61LF25618EC-7.5B2
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
7.5ns
6.5ns
7.5ns
165 BGA
119 BGA
IS61LF12836EC-7.5TQL IS61LF12832EC-7.5TQL IS61LF25618EC-7.5TQL 100 QFP, Lead-free
IS61LF12836EC-7.5B3L
IS61LF12836EC-7.5B2L
IS61VF12836EC-6.5TQ
IS61VF12836EC-6.5B3
IS61VF12836EC-6.5B2
IS61LF12832EC-7.5B3L
IS61LF12832EC-7.5B2L
IS61VF12832EC-6.5TQ
IS61VF12832EC-6.5B3
IS61VF12832EC-6.5B2
IS61LF25618EC-7.5B3L
IS61LF25618EC-7.5B2L
IS61VF25618EC-6.5TQ
IS61VF25618EC-6.5B3
IS61VF25618EC-6.5B2
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
VDD =2.5V
VDDQ=2.5V
165 BGA
119 BGA
IS61VF12836EC-6.5TQL IS61VF12832EC-6.5TQL IS61VF25618EC-6.5TQL 100 QFP, Lead-free
IS61VF12836EC-6.5B3L IS61VF12832EC-6.5B3L IS61VF25618EC-6.5B3L 165 BGA, Lead-free
IS61VF12836EC-6.5B2L IS61VF12832EC-6.5B2L IS61VF25618EC-6.5B2L 119 BGA, Lead-free
IS61VF12836EC-7.5TQ
IS61VF12836EC-7.5B3
IS61VF12836EC-7.5B2
IS61VF12832EC-7.5TQ
IS61VF12832EC-7.5B3
IS61VF12832EC-7.5B2
IS61VF25618EC-7.5TQ
IS61VF25618EC-7.5B3
IS61VF25618EC-7.5B2
100 QFP
165 BGA
119 BGA
IS61VF12836EC-7.5TQL IS61VF12832EC-7.5TQL IS61VF25618EC-7.5TQL 100 QFP, Lead-free
IS61VF12836EC-7.5B3L IS61VF12832EC-7.5B3L IS61VF25618EC-7.5B3L 165 BGA, Lead-free
IS61VF12836EC-7.5B2L IS61VF12832EC-7.5B2L IS61VF25618EC-7.5B2L 119 BGA, Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
31
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Industrial Range: -40°C to 85°C
VDD
SPEED
X36
X32
X18
Package
100 QFP
IS61LF12836EC-6.5TQI
IS61LF12836EC-6.5B3I
IS61LF12836EC-6.5B2I
IS61LF12836EC-6.5TQLI
IS61LF12836EC-6.5B3LI
IS61LF12836EC-6.5B2LI
IS61LF12836EC-7.5TQI
IS61LF12836EC-7.5B3I
IS61LF12836EC-7.5B2I
IS61LF12836EC-7.5TQLI
IS61LF12836EC-7.5B3LI
IS61LF12836EC-7.5B2LI
IS61VF12836EC-6.5TQI
IS61VF12836EC-6.5B3I
IS61VF12836EC-6.5B2I
IS61VF12836EC-6.5TQLI
IS61VF12836EC-6.5B3LI
IS61VF12836EC-6.5B2LI
IS61VF12836EC-7.5TQI
IS61VF12836EC-7.5B3I
IS61VF12836EC-7.5B2I
IS61VF12836EC-7.5TQLI
IS61VF12836EC-7.5B3LI
IS61VF12836EC-7.5B2LI
IS61LF12832EC-6.5TQI
IS61LF12832EC-6.5B3I
IS61LF12832EC-6.5B2I
IS61LF12832EC-6.5TQLI
IS61LF12832EC-6.5B3LI
IS61LF12832EC-6.5B2LI
IS61LF12832EC-7.5TQI
IS61LF12832EC-7.5B3I
IS61LF12832EC-7.5B2I
IS61LF12832EC-7.5TQLI
IS61LF12832EC-7.5B3LI
IS61LF12832EC-7.5B2LI
IS61VF12832EC-6.5TQI
IS61VF12832EC-6.5B3I
IS61VF12832EC-6.5B2I
IS61VF12832EC-6.5TQLI
IS61VF12832EC-6.5B3LI
IS61VF12832EC-6.5B2LI
IS61VF12832EC-7.5TQI
IS61VF12832EC-7.5B3I
IS61VF12832EC-7.5B2I
IS61VF12832EC-7.5TQLI
IS61VF12832EC-7.5B3LI
IS61VF12832EC-7.5B2LI
IS61LF25618EC-6.5TQI
IS61LF25618EC-6.5B3I
IS61LF25618EC-6.5B2I
IS61LF25618EC-6.5TQLI
IS61LF25618EC-6.5B3LI
IS61LF25618EC-6.5B2LI
IS61LF25618EC-7.5TQI
IS61LF25618EC-7.5B3I
IS61LF25618EC-7.5B2I
IS61LF25618EC-7.5TQLI
IS61LF25618EC-7.5B3LI
IS61LF25618EC-7.5B2LI
IS61VF25618EC-6.5TQI
IS61VF25618EC-6.5B3I
IS61VF25618EC-6.5B2I
IS61VF25618EC-6.5TQLI
IS61VF25618EC-6.5B3LI
IS61VF25618EC-6.5B2LI
IS61VF25618EC-7.5TQI
IS61VF25618EC-7.5B3I
IS61VF25618EC-7.5B2I
IS61VF25618EC-7.5TQLI
IS61VF25618EC-7.5B3LI
IS61VF25618EC-7.5B2LI
VDD =3.3V
VDDQ=2.5V
or
6.5ns
165 BGA
119 BGA
VDDQ=3.3V
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
7.5ns
6.5ns
7.5ns
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
VDD =2.5V
VDDQ=2.5V
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
32
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Automotive(A3) Range: -40°C to 125°C
VDD
SPEED
X36
X32
X18
Package
100 QFP
IS64LF12836EC-6.5TQA3
IS64LF12836EC-6.5B3A3
IS64LF12836EC-6.5B2A3
IS64LF12832EC-6.5TQA3
IS64LF12832EC-6.5B3A3
IS64LF12832EC-6.5B2A3
IS64LF25618EC-6.5TQA3
IS64LF25618EC-6.5B3A3
IS64LF25618EC-6.5B2A3
VDD
=3.3V
VDDQ=2.5V
or
VDDQ=3.3V
6.5ns
165 BGA
119 BGA
IS64LF12836EC-6.5TQLA3 IS64LF12832EC-6.5TQLA3 IS64LF25618EC-6.5TQLA3 100 QFP, Lead-free
IS64LF12836EC-6.5B3LA3
IS64LF12836EC-6.5B2LA3
IS64LF12836EC-7.5TQA3
IS64LF12836EC-7.5B3A3
IS64LF12836EC-7.5B2A3
IS64LF12832EC-6.5B3LA3
IS64LF12832EC-6.5B2LA3
IS64LF12832EC-7.5TQA3
IS64LF12832EC-7.5B3A3
IS64LF12832EC-7.5B2A3
IS64LF25618EC-6.5B3LA3
IS64LF25618EC-6.5B2LA3
IS64LF25618EC-7.5TQA3
IS64LF25618EC-7.5B3A3
IS64LF25618EC-7.5B2A3
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
7.5ns
6.5ns
7.5ns
165 BGA
119 BGA
IS64LF12836EC-7.5TQLA3 IS64LF12832EC-7.5TQLA3 IS64LF25618EC-7.5TQLA3 100 QFP, Lead-free
IS64LF12836EC-7.5B3LA3
IS64LF12836EC-7.5B2LA3
IS64VF12836EC-6.5TQA3
IS64VF12836EC-6.5B3A3
IS64VF12836EC-6.5B2A3
IS64LF12832EC-7.5B3LA3
IS64LF12832EC-7.5B2LA3
IS64VF12832EC-6.5TQA3
IS64VF12832EC-6.5B3A3
IS64VF12832EC-6.5B2A3
IS64LF25618EC-7.5B3LA3
IS64LF25618EC-7.5B2LA3
IS64VF25618EC-6.5TQA3
IS64VF25618EC-6.5B3A3
IS64VF25618EC-6.5B2A3
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
VDD =2.5V
VDDQ=2.5V
165 BGA
119 BGA
IS64VF12836EC-6.5TQLA3 IS64VF12832EC-6.5TQLA3 IS64VF25618EC-6.5TQLA3 100 QFP, Lead-free
IS64VF12836EC-6.5B3LA3 IS64VF12832EC-6.5B3LA3 IS64VF25618EC-6.5B3LA3 165 BGA, Lead-free
IS64VF12836EC-6.5B2LA3 IS64VF12832EC-6.5B2LA3 IS64VF25618EC-6.5B2LA3 119 BGA, Lead-free
IS64VF12836EC-7.5TQA3
IS64VF12836EC-7.5B3A3
IS64VF12836EC-7.5B2A3
IS64VF12832EC-7.5TQA3
IS64VF12832EC-7.5B3A3
IS64VF12832EC-7.5B2A3
IS64VF25618EC-7.5TQA3
IS64VF25618EC-7.5B3A3
IS64VF25618EC-7.5B2A3
100 QFP
165 BGA
119 BGA
IS64VF12836EC-7.5TQLA3 IS64VF12832EC-7.5TQLA3 IS64VF25618EC-7.5TQLA3 100 QFP, Lead-free
IS64VF12836EC-7.5B3LA3 IS64VF12832EC-7.5B3LA3 IS64VF25618EC-7.5B3LA3 165 BGA, Lead-free
IS64VF12836EC-7.5B2LA3 IS64VF12832EC-7.5B2LA3 IS64VF25618EC-7.5B2LA3 119 BGA, Lead-free
Note : Not all automotive options listed are currently available. Please contact ISSI for parts
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
33
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
PACKAGE OUTLINE DRAWING
100 QFP (14x20x1.4mm)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
34
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
119 BGA (14x22x2.15mm)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
35
09/30/2015
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
165 BGA (13x15x1.2mm)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
36
09/30/2015
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