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IS61LF51218A-6.5TQL [ISSI]

Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100;
IS61LF51218A-6.5TQL
型号： IS61LF51218A-6.5TQL
厂家： INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述：

Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100

静态存储器 内存集成电路
文件： 总32页 (文件大小：630K)
中文：  中文翻译
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IS61LF25636A IS61VF25636A IS64LF25636A  
IS61LF51218A IS61VF51218A  
256K x 36, 512K x 18  
9 Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
AUGUST 2009  
FEATURES  
DESCRIPTION  
The ISSIꢀ IS61LF/VF25636A,ꢀIS64LF25636AꢀandꢀIS61LF/  
VF51218Aꢀ are high-speed, low-power synchronous  
staticRAMsdesignedtoprovideburstable,high-performance  
memory for communication and networking applications.  
TheIS61LF/VF25636AꢀandꢀIS64LF25636Aꢀareꢀorganizedꢀ  
asꢀ262,144ꢀwordsꢀbyꢀ36ꢀbits.ꢀTheꢀIS61LF/VF51218A is  
organizedꢀasꢀ524,288ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀ  
ISSI'sꢀadvancedꢀCMOSꢀtechnology,ꢀtheꢀdeviceꢀintegratesꢀ  
aꢀ2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-  
drive capability outputs into a single monolithic circuit. All  
synchronous inputs pass through registers controlled by  
a positive-edge-triggered single clock input.  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ  
control  
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ  
•ꢀ Three chip enable option for simple depth expan-  
sion and address pipelining  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ AutoꢀPower-downꢀduringꢀdeselect  
•ꢀ Singleꢀcycleꢀdeselect  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀtheꢀ  
risingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀoneꢀtoꢀ  
four bytes wide as controlled by the write control inputs.  
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackage  
•ꢀ PowerꢀSupply  
Separate byte enables allow individual bytes to be written.  
Byteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀbyteꢀwriteꢀen-  
able (BWE) input combined with one or more individual  
byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀWriteꢀ(GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
LF: Vd d 3.3V + 5%, Vd d q 3.3V/2.5V + 5%  
VF: Vd d 2.5V + 5%, Vd d q 2.5V + 5%  
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status  
Processor)ꢀorꢀADSC (Address Status Cache Controller)  
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-  
ated internally and controlled by the ADV (burst address  
advance) input pin.  
•ꢀ JEDECꢀ100-PinꢀTQFP,ꢀ119-pinꢀPBGA,ꢀandꢀ165-  
pinꢀPBGAꢀpackages  
•ꢀ Lead-freeꢀavailable  
•ꢀ Automotiveꢀtemperatureꢀavailable  
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀorder,ꢀ  
LinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀInter-  
leaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀorꢀleftꢀ  
floating.  
FAST ACCESS TIME  
Symbol  
Parameter  
-6.5  
6.5ꢀ  
7.5ꢀ  
133ꢀ  
-7.5  
7.5ꢀ  
8.5ꢀ  
117ꢀ  
Units  
ns  
tk q  
tk c  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
ꢀ
Frequencyꢀ  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc.  
1
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
BLOCK DIAGRAM  
MODE  
A0'  
Q0  
A0  
CLK  
CLK  
BINARY  
COUNTER  
Q1  
CE  
A1'  
ADV  
A1  
256Kx36;  
512Kx18;  
MEMORY ARRAY  
ADSC  
ADSP  
CLR  
18/19  
16/17  
18/19  
D
Q
A
ADDRESS  
REGISTER  
CE  
CLK  
36,  
or 18  
36,  
or 18  
D
Q
GW  
BWE  
DQ(a-d)  
BYTE WRITE  
REGISTERS  
BW(a-d)  
x18: a,b  
x36: a-d  
CLK  
36,  
or 18  
CE  
CE2  
CE2  
2/4/8  
INPUT  
D
Q
DQa - DQd  
REGISTERS  
ENABLE  
OE  
REGISTER  
CLK  
CE  
CLK  
POWER  
DOWN  
ZZ  
OE  
2
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
119-PIN BGA  
119-Ball,ꢀ14x22ꢀmmꢀBGA  
165-PIN BGA  
165-Ball,ꢀ13x15ꢀmmꢀBGA  
BOTTOMꢀVIEW  
BOTTOMꢀVIEW  
Integrated Silicon Solution, Inc.ꢀ  
3
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
119 BGA PACKAGE PIN CONFIGURATION-256k x 36 (TOP VIEW)  
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ  
NC  
A
A
A
ADSP  
ADSC  
VDD  
NC  
A
A
A
A
VDDQ  
NC  
CE2  
A
NC  
A
A
A
NC  
DQc  
DQc  
VDDQ  
DQc  
DQc  
VDDQ  
DQd  
DQd  
VDDQ  
DQd  
DQd  
NC  
DQPc  
DQc  
DQc  
DQc  
DQc  
VDD  
Vss  
Vss  
Vss  
BWc  
Vss  
NC  
Vss  
Vss  
Vss  
BWb  
Vss  
NC  
Vss  
BWa  
Vss  
Vss  
Vss  
NC  
A
DQPb  
DQb  
DQb  
DQb  
DQb  
VDD  
DQa  
DQa  
DQa  
DQa  
DQPa  
A
DQbꢀꢀꢀ  
DQb  
VDDQ  
DQb  
DQb  
VDDQ  
DQa  
DQa  
VDDQ  
DQa  
DQa  
NC  
CE  
OE  
G
H
J
ADV  
GW  
VDD  
CLK  
NC  
K
L
DQd  
DQd  
DQd  
DQd  
DQPd  
A
Vss  
BWd  
Vss  
Vss  
Vss  
MODE  
A
M
N
P
R
T
BWE  
A1*  
A0*  
VDD  
A
NC  
NC  
NC  
ZZ  
U
VDDQ  
TMS  
TDI  
TCK  
TDO  
NC  
VDDQ  
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ  
PIN DESCRIPTIONS  
Symbol  
OE  
Pin Name  
Symbol  
A
Pin Name  
OutputꢀEnable  
Address Inputs  
ZZꢀ  
PowerꢀSleepꢀModeꢀ  
BurstꢀSequenceꢀSelection  
JTAGꢀPins  
A0,ꢀA1ꢀ  
ADVꢀ  
SynchronousꢀBurstꢀAddressꢀInputsꢀ  
MODE  
TCK,ꢀTDO  
ꢀꢀTMS,ꢀTDI  
NC  
SynchronousꢀBurstꢀAddressꢀ  
Advance  
ADSP  
ADSC  
GWꢀ  
AddressꢀStatusꢀProcessor  
Address Status Controller  
GlobalꢀWriteꢀEnable  
No Connect  
DQa-DQd  
DQPa-Pdꢀ  
Vd d  
DataꢀInputs/Outputs  
OutputꢀPowerꢀSupply  
PowerꢀSupply  
CLK  
Synchronous Clock  
CE,ꢀCE2  
Synchronous Chip Select  
BWxꢀ(x=a-d)ꢀ SynchronousꢀByteꢀWriteꢀControls  
BWE ByteꢀWriteꢀEnable  
Vd d q  
OutputꢀPowerꢀSupply  
Ground  
Vss  
4ꢀ  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
119 BGA PACKAGE PIN CONFIGURATION  
512kx18 (TOP VIEW)  
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ  
NC  
A
CE2  
A
A
A
ADSP  
ADSC  
VDD  
NC  
A
A
A
A
VDDQ  
NC  
NC  
A
A
A
NC  
DQb  
NC  
NC  
Vss  
Vss  
Vss  
BWb  
Vss  
NC  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
Vss  
BWa  
Vss  
Vss  
Vss  
NC  
A
DQPa  
NC  
DQa  
NC  
DQa  
VDD  
NC  
DQa  
NC  
DQa  
NC  
A
NC  
DQb  
NC  
CE  
DQa  
VDDQ  
DQa  
NC  
VDDQ  
NC  
OE  
G
H
J
DQb  
NC  
ADV  
GW  
VDD  
CLK  
NC  
DQb  
VDDQ  
NC  
VDD  
DQb  
NC  
VDDQ  
DQa  
NC  
K
L
Vss  
Vss  
Vss  
Vss  
Vss  
MODE  
A
DQb  
VDDQ  
DQb  
NC  
M
N
P
R
T
DQb  
NC  
BWE  
A1*  
VDDQ  
NC  
DQPb  
A
A0*  
DQa  
NC  
NC  
VDD  
NC  
NC  
A
A
ZZ  
U
VDDQ  
TMS  
TDI  
TCK  
TDO  
NC  
VDDQ  
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ  
PIN DESCRIPTIONS  
Symbol  
OE  
Pin Name  
Symbol  
A
Pin Name  
Address Inputs  
OutputꢀEnable  
A0, A1  
SynchronousꢀBurstꢀAddressꢀInputsꢀ  
ZZꢀ  
PowerꢀSleepꢀModeꢀ  
BurstꢀSequenceꢀSelection  
JTAGꢀPins  
ADVꢀ  
SynchronousꢀBurstꢀAddressꢀ  
Advance  
MODE  
TCK,ꢀTDO  
TMS,ꢀTDI  
NC  
ADSP  
ADSC  
GWꢀ  
AddressꢀStatusꢀProcessor  
Address Status Controller  
GlobalꢀWriteꢀEnable  
No Connect  
DQa-DQb  
DQPa-Pbꢀ  
Vd d  
DataꢀInputs/Outputs  
OutputꢀPowerꢀSupply  
PowerꢀSupply  
CLK  
Synchronous Clock  
CE,ꢀCE2  
Synchronous Chip Select  
BWxꢀ(x=a,b)ꢀ SynchronousꢀByteꢀWriteꢀControls  
BWE ByteꢀWriteꢀEnable  
Vd d q  
OutputꢀPowerꢀSupply  
Ground  
Vss  
Integrated Silicon Solution, Inc.ꢀ  
5
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
165 PBGA PACKAGE PIN CONFIGURATION  
256k x 36 (TOP VIEW)  
1
2
3
4
5
6
7
8
ADSC  
OE  
9
10  
A
11  
NC  
A
B
C
D
E
F
NC  
A
CE  
BWc  
BWd  
Vss  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vss  
A
BWb  
BWa  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
CE2  
CLK  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
BWE  
GW  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
ADV  
ADSP  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Nc  
NC  
A
CE2  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
NC  
A
NC  
DQPb  
DQb  
DQb  
DQb  
DQb  
ZZ  
DQPc  
DQc  
DQc  
DQc  
DQc  
NC  
NC  
Vss  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vss  
A
Nc  
DQb  
DQb  
DQb  
DQb  
Nc  
dqa  
dqa  
dqa  
dqa  
NC  
A
DQc  
DQc  
DQc  
DQc  
Vss  
DQd  
DQd  
DQd  
DQd  
NC  
G
H
J
DQd  
DQd  
DQd  
DQd  
DQPd  
NC  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
A
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
A
dqa  
dqa  
dqa  
dqa  
DQPa  
A
K
L
M
N
P
R
NC  
TDI  
TMS  
A1*  
A0*  
TDO  
TCK  
MODE  
NC  
A
A
A
A
A
A
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ  
PIN DESCRIPTIONS  
Symbol  
BWE  
OE  
Pin Name  
Symbol  
A
Pin Name  
Address Inputs  
ByteꢀWriteꢀEnable  
OutputꢀEnable  
PowerꢀSleepꢀModeꢀ  
A0, A1  
SynchronousꢀBurstꢀAddressꢀInputsꢀ  
ADVꢀ  
SynchronousꢀBurstꢀAddressꢀ  
Advance  
ZZꢀ  
MODE  
BurstꢀSequenceꢀSelection  
JTAGꢀPins  
ADSP  
AddressꢀStatusꢀProcessor  
Address Status Controller  
GlobalꢀWriteꢀEnable  
TCK,ꢀTDO  
TMS,ꢀTDI  
ADSC  
GW  
NC  
No Connect  
CLK  
Synchronous Clock  
DQx  
DQPxꢀ  
Vd d  
DataꢀInputs/Outputs  
DataꢀInputs/Outputs  
3.3V/2.5VꢀPowerꢀSupply  
CE, CE2, CE2  
Synchronous Chip Select  
BWxꢀ(x=a,b,c,d)ꢀ SynchronousꢀByteꢀWriteꢀꢀ  
ꢀ
Controls  
Vd d q  
ꢀ
IsolatedꢀOutputꢀPowerꢀSupplyꢀꢀꢀꢀꢀ ꢀ  
3.3V/2.5V  
Vssꢀ  
Ground  
6
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
165 PBGA PACKAGE PIN CONFIGURATION  
512k x 18 (TOP VIEW)  
1
NC  
2
3
4
5
6
7
8
ADSC  
OE  
9
10  
A
11  
A
A
B
C
D
E
F
A
CE  
BWb  
NC  
Vss  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vss  
A
NC  
CE2  
CLK  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
BWE  
GW  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
ADV  
ADSP  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Nc  
NC  
A
CE2  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
NC  
BWa  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
NC  
A
NC  
DQPa  
DQa  
DQa  
DQa  
DQa  
ZZ  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
Vss  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
Vss  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vd d  
Vss  
A
Nc  
NC  
NC  
NC  
NC  
Nc  
dqa  
dqa  
dqa  
dqa  
NC  
A
NC  
NC  
NC  
G
H
J
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQPb  
NC  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
A
Vd d q  
Vd d q  
Vd d q  
Vd d q  
Vd d q  
A
Nc  
Nc  
Nc  
Nc  
NC  
A
K
L
M
N
P
R
TDI  
TMS  
A1*  
A0*  
TDO  
TCK  
MODE  
A
A
A
A
A
A
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ  
PIN DESCRIPTIONS  
Symbol  
A
Pin Name  
Address Inputs  
Symbol  
BWE  
OE  
Pin Name  
ByteꢀWriteꢀEnable  
OutputꢀEnable  
A0, A1  
SynchronousꢀBurstꢀAddressꢀInputsꢀ  
ADVꢀ  
SynchronousꢀBurstꢀAddressꢀ  
ZZꢀ  
PowerꢀSleepꢀModeꢀ  
BurstꢀSequenceꢀSelection  
JTAGꢀPins  
Advance  
MODE  
ADSP  
ADSC  
GW  
AddressꢀStatusꢀProcessor  
Address Status Controller  
GlobalꢀWriteꢀEnableꢀ  
TCK,ꢀTDO  
TMS,ꢀTDI  
NC  
No Connect  
CLK  
Synchronous Clock  
DQx  
DQPxꢀ  
Vd d  
DataꢀInputs/Outputs  
DataꢀInputs/Outputs  
3.3V/2.5VꢀPowerꢀSupply  
CE, CE2, CE2 Synchronous Chip Select  
BWxꢀ(x=a,b)ꢀ  
SynchronousꢀByteꢀWriteꢀꢀ  
Controls  
ꢀ
Vd d q  
ꢀ
IsolatedꢀOutputꢀPowerꢀSupplyꢀꢀꢀꢀꢀ ꢀ  
3.3V/2.5V  
Vssꢀ  
Ground  
Integrated Silicon Solution, Inc.  
7
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
PIN CONFIGURATION  
100-PIN TQFP (256K ꢀ 36)  
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
100  
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
100  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQPb  
DQb  
DQb  
VDDQ  
VSS  
DQb  
DQb  
DQb  
DQb  
VSS  
VDDQ  
DQb  
DQb  
VSS  
NC  
DQPc  
DQc  
DQc  
VDDQ  
VSS  
DQc  
DQc  
DQc  
DQc  
VSS  
VDDQ  
DQc  
DQc  
NC  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQPb  
DQb  
DQb  
DQPc  
DQc  
DQc  
VDDQ  
V
DDQ  
VSS  
DQb  
DQb  
DQb  
DQb  
VSS  
VSS  
DQc  
DQc  
DQc  
DQc  
VSS  
V
DDQ  
V
DDQ  
DQb  
DQb  
VSS  
NC  
DQc  
DQc  
NC  
VDD  
NC  
V
DD  
NC  
VDD  
ZZ  
V
DD  
VSS  
DQd  
DQd  
VDDQ  
VSS  
DQd  
DQd  
DQd  
DQd  
VSS  
VDDQ  
DQd  
DQd  
DQPd  
ZZ  
DQa  
DQa  
VSS  
DQd  
DQd  
DQa  
DQa  
VDDQ  
VSS  
DQa  
DQa  
DQa  
DQa  
VSS  
VDDQ  
DQa  
DQa  
DQPa  
VDDQ  
V
V
DDQ  
VSS  
DQa  
DQa  
DQa  
DQa  
VSS  
VSS  
DQd  
DQd  
DQd  
DQd  
VSS  
V
DDQ  
DDQ  
DQa  
DQa  
DQPa  
DQd  
DQd  
DQPd  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
(2 Chip-Enable option)  
(3 Chip-Enable option)  
PIN DESCRIPTIONS  
DQa-DQdꢀ  
DQPa-DQPdꢀ ParityꢀDataꢀInput/Output  
GWꢀ SynchronousꢀGlobalꢀWriteꢀEnable  
MODEꢀꢀ ꢀ  
SynchronousꢀDataꢀInput/Output  
A0, A1  
Synchronous Address Inputs. These  
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ  
address bus.  
ꢀ
A
Synchronous Address Inputs  
BurstꢀSequenceꢀModeꢀSelection  
OutputꢀEnable  
ADSC  
ADSP  
ADV  
Synchronous Controller Address Status  
SynchronousꢀProcessorꢀAddressꢀStatus  
SynchronousꢀBurstꢀAddressꢀAdvance  
SynchronousꢀByteꢀWriteꢀEnable  
SynchronousꢀByteꢀWriteꢀEnable  
OEꢀ  
ꢀ
ꢀ
Vd d ꢀ  
Vd d q ꢀ  
3.3V/2.5VꢀPowerꢀSupply  
ꢀ
ꢀ
IsolatedꢀOutputꢀBufferꢀSupply:  
3.3V/2.5V  
BWa-BWdꢀ  
BWEꢀ  
Vssꢀ  
ZZꢀ  
ꢀ
ꢀ
Ground  
CE, CE2, CE2ꢀ SynchronousꢀChipꢀEnable  
CLK Synchronous Clock  
SnoozeꢀEnable  
8ꢀ  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
PIN CONFIGURATION  
100-PIN TQFP (512K ꢀ 18)  
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
100  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
A
NC  
NC  
VDDQ  
VSS  
NC  
DQPa  
DQa  
DQa  
VSS  
VDDQ  
DQa  
DQa  
VSS  
NC  
NC  
NC  
NC  
VDDQ  
VSS  
NC  
1
2
3
4
5
6
7
8
9
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A
NC  
NC  
NC  
NC  
NC  
DDQ  
VDDQ  
V
VSS  
NC  
DQPa  
DQa  
DQa  
VSS  
VSS  
NC  
NC  
DQb  
DQb  
VSS  
NC  
DQb  
DQb  
VSS  
VDDQ  
DQb  
DQb  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
V
DDQ  
DQb  
DQb  
NC  
DQa  
DQa  
VSS  
NC  
VDD  
NC  
V
DD  
VDD  
ZZ  
VDD  
NC  
VSS  
DQb  
DQb  
VSS  
DQb  
DQb  
VDDQ  
VSS  
DQb  
DQb  
DQPb  
NC  
VSS  
VDDQ  
NC  
NC  
NC  
ZZ  
DQa  
DQa  
DQa  
DQa  
VDDQ  
VSS  
DQa  
DQa  
NC  
VDDQ  
V
DDQ  
VSS  
DQb  
DQb  
DQPb  
NC  
VSS  
DQa  
DQa  
NC  
NC  
VSS  
NC  
VSS  
VDDQ  
NC  
NC  
NC  
VSS  
VDDQ  
V
DDQ  
NC  
NC  
NC  
NC  
NC  
NC  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
(3 Chip-Enable Option)  
(2 Chip-Enable Option)  
PIN DESCRIPTIONS  
DQPa-DQPbꢀ ParityꢀDataꢀI/O;ꢀDQPaꢀisꢀparityꢀforꢀꢀ  
A0, A1  
Synchronous Address Inputs. These  
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ  
address bus.  
ꢀ
DQa1-8;ꢀDQPbꢀisꢀparityꢀforꢀDQb1-8  
GWꢀ  
ꢀ
SynchronousꢀGlobalꢀWriteꢀEnable  
BurstꢀSequenceꢀModeꢀSelection  
OutputꢀEnable  
A
Synchronous Address Inputs  
MODEꢀꢀ ꢀ  
ADSC  
ADSP  
ADV  
Synchronous Controller Address Status  
SynchronousꢀProcessorꢀAddressꢀStatus  
SynchronousꢀBurstꢀAddressꢀAdvance  
SynchronousꢀByteꢀWriteꢀEnable  
SynchronousꢀByteꢀWriteꢀEnable  
OEꢀ  
ꢀ
ꢀ
Vd d ꢀ  
Vd d q ꢀ  
3.3V/2.5VꢀPowerꢀSupply  
ꢀ
ꢀ
IsolatedꢀOutputꢀBufferꢀSupply:  
3.3V/2.5V  
BWa-BWbꢀ  
BWEꢀ  
Vssꢀ  
ZZꢀ  
ꢀ
ꢀ
Ground  
CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable  
SnoozeꢀEnable  
CLK  
Synchronous Clock  
DQa-DQbꢀ  
SynchronousꢀDataꢀInput/Output  
Integrated Silicon Solution, Inc.  
9
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
TRUTH TABLE(1-8)  
OPERATION  
ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Q
DeselectꢀCycle,ꢀPower-Downꢀ  
DeselectꢀCycle,ꢀPower-Downꢀ  
DeselectꢀCycle,ꢀPower-Downꢀ  
DeselectꢀCycle,ꢀPower-Downꢀ  
DeselectꢀCycle,ꢀPower-Downꢀ  
SnoozeꢀꢀMode,ꢀPower-Downꢀ  
ReadꢀCycle,ꢀBeginꢀBurstꢀ  
ReadꢀCycle,ꢀBeginꢀBurstꢀ  
WriteꢀCycle,ꢀBeginꢀBurstꢀ  
ReadꢀCycle,ꢀBeginꢀBurstꢀ  
ReadꢀCycle,ꢀBeginꢀBurstꢀ  
ReadꢀCycle,ꢀContinueꢀBurstꢀ  
ReadꢀCycle,ꢀContinueꢀBurstꢀ  
ReadꢀCycle,ꢀContinueꢀBurstꢀ  
ReadꢀCycle,ꢀContinueꢀBurstꢀ  
WriteꢀCycle,ꢀContinueꢀBurstꢀ  
WriteꢀCycle,ꢀContinueꢀBurstꢀ  
ReadꢀCycle,ꢀSuspendꢀBurstꢀ  
ReadꢀCycle,ꢀSuspendꢀBurstꢀ  
ReadꢀCycle,ꢀSuspendꢀBurstꢀ  
ReadꢀCycle,ꢀSuspendꢀBurstꢀ  
WriteꢀCycle,ꢀSuspendꢀBurstꢀ  
WriteꢀCycle,ꢀSuspendꢀBurstꢀ  
NOTE:  
Noneꢀ  
Noneꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Lꢀ  
Xꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Hꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
Xꢀ  
Noneꢀ  
Lꢀ  
Xꢀ  
Lꢀ  
Lꢀ  
Noneꢀ  
Lꢀ  
Hꢀ  
Hꢀ  
Xꢀ  
Lꢀ  
Noneꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
Noneꢀ  
Xꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
Externalꢀ  
Externalꢀ  
Externalꢀ  
Externalꢀ  
Externalꢀ  
Nextꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
L-Hꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Hꢀ  
Xꢀ  
Lꢀ  
High-Z  
D
Lꢀ  
Lꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Xꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Xꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
ꢀQ  
Lꢀ  
Lꢀ  
Lꢀ  
Hꢀ  
Lꢀ  
High-Z  
Q
Xꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Nextꢀ  
Lꢀ  
Hꢀ  
Lꢀ  
High-Z  
Q
Nextꢀ  
Lꢀ  
Nextꢀ  
Lꢀ  
Hꢀ  
Xꢀ  
Xꢀ  
Lꢀ  
High-Z  
D
Nextꢀ  
Lꢀ  
Nextꢀ  
Lꢀ  
Lꢀ  
D
Currentꢀ  
Currentꢀ  
Currentꢀ  
Currentꢀ  
Currentꢀ  
Currentꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
Q
Hꢀ  
Lꢀ  
High-Z  
Q
Hꢀ  
Xꢀ  
Xꢀ  
High-Z  
D
Lꢀ  
D
1.ꢀ Xꢀmeansꢀ“Don’tꢀCare.”ꢀHꢀmeansꢀlogicꢀHIGH.ꢀLꢀmeansꢀlogicꢀLOW.  
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWEꢀareꢀLOWꢀorꢀGWꢀisꢀLOW.ꢀWRITE = H for all  
BWx, BWE, GWꢀHIGH.  
3.ꢀ BWaꢀenablesꢀWRITEsꢀtoꢀDQa’sꢀandꢀDQPa.ꢀBWbꢀenablesꢀWRITEsꢀtoꢀDQb’sꢀandꢀDQPb.ꢀBWcꢀenablesꢀWRITEsꢀtoꢀDQc’sꢀ andꢀ  
DQPc.ꢀBWdꢀenablesꢀWRITEsꢀtoꢀDQd’sꢀandꢀDQPd.ꢀDQPaꢀandꢀDQPbꢀareꢀavailableꢀonꢀtheꢀx18ꢀversion.ꢀ DQPa-DQPdꢀareꢀavail-  
ableꢀonꢀtheꢀx36ꢀversion.  
4.ꢀ AllꢀinputsꢀexceptꢀOEꢀandꢀZZꢀmustꢀmeetꢀsetupꢀandꢀholdꢀtimesꢀaroundꢀtheꢀrisingꢀedgeꢀ(LOWꢀtoꢀHIGH)ꢀofꢀCLK.  
5.ꢀ Waitꢀstatesꢀareꢀinsertedꢀbyꢀsuspendingꢀburst.  
6.ꢀ ForꢀaꢀWRITEꢀoperationꢀfollowingꢀaꢀREADꢀoperation,ꢀOEꢀmustꢀbeꢀHIGHꢀbeforeꢀtheꢀinputꢀdataꢀsetupꢀtimeꢀandꢀheldꢀHIGHꢀduringꢀ  
the input data hold time.  
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.  
8.ꢀ ADSPꢀLOWꢀalwaysꢀinitiatesꢀanꢀinternalꢀREADꢀatꢀtheꢀL-HꢀedgeꢀofꢀCLK.ꢀAꢀWRITEꢀisꢀperformedꢀbyꢀsettingꢀoneꢀorꢀmoreꢀbyteꢀwriteꢀ  
enable signals and BWEꢀLOWꢀorꢀGWꢀLOWꢀforꢀtheꢀsubsequentꢀL-HꢀedgeꢀofꢀCLK.ꢀSeeꢀWRITEꢀtimingꢀdiagramꢀforꢀclarification.  
PARTIAL TRUTH TABLE  
Function  
Read  
GW  
BWE  
H
BWa  
X
BWb  
X
BWc  
X
BWd  
X
H
Read  
H
L
H
H
H
H
WriteꢀByteꢀ1ꢀ  
WriteꢀAllꢀBytesꢀ  
WriteꢀAllꢀBytesꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
10  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
INTERLEAVED BURST ADDRESS TABLE (MODE = VD D or No Connect)  
External Address  
A1 A0  
1st Burst Address  
A1 A0  
2nd Burst Address  
A1 A0  
3rd Burst Address  
A1 A0  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
LINEAR BURST ADDRESS TABLE (MODE = VSS)  
0,0  
A1', A0' = 1,1  
0,1  
1,0  
ABSOLUTE MAꢀIMUM RATINGS(1)  
Symbol Parameter  
Value  
–55ꢀtoꢀ+150ꢀ  
1.6ꢀ  
Unit  
°C  
W
Ts T g  
Pd  
StorageꢀTemperatureꢀ  
PowerꢀDissipationꢀ  
IO u T ꢀ  
OutputꢀCurrentꢀ(perꢀI/O)ꢀ  
100ꢀ  
mA  
V
V
VIN, VO u T ꢀ VoltageꢀRelativeꢀtoꢀVssꢀforꢀI/OꢀPinsꢀ  
–0.5ꢀtoꢀVd d q + 0.5  
–0.5ꢀtoꢀVd d + 0.5  
VINꢀ  
VoltageꢀRelativeꢀtoꢀVssꢀforꢀꢀ  
for Address and Control Inputs  
Vd d  
Voltage on Vd d ꢀSupplyꢀRelativeꢀtoꢀVssꢀ  
–0.5ꢀtoꢀ4.6  
V
Notes:  
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀperma-  
nent damage to the device.This is a stress rating only and functional operation of the device  
at these or any other conditions above those indicated in the operational sections of this  
specificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀ  
periods may affect reliability.  
2.This device contains circuity to protect the inputs against damage due to high static voltages  
orꢀelectricꢀfields;ꢀhowever,ꢀprecautionsꢀmayꢀbeꢀtakenꢀtoꢀavoidꢀapplicationꢀofꢀanyꢀvoltageꢀ  
higher than maximum rated voltages to this high-impedance circuit.  
3.ꢀThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputꢀdevicesꢀareꢀinꢀHigh-Zꢀatꢀpowerꢀup.  
Integrated Silicon Solution, Inc.  
11  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
OPERATING RANGE (IS61LFxxxxx)  
Range  
Commercialꢀ  
Industrialꢀ  
Ambient Temperature  
0°Cꢀtoꢀ+70°Cꢀ  
VD D  
3.3Vꢀ±ꢀ5%ꢀ  
3.3Vꢀ±ꢀ5%ꢀ  
VD D q  
ꢀ3.3V/2.5Vꢀ±ꢀ5%  
3.3V/2.5Vꢀ±ꢀ5%  
ꢀ
ꢀ
-40°Cꢀtoꢀ+85°Cꢀ  
OPERATING RANGE (IS64LFxxxxx)  
Range  
Ambient Temperature  
VD D  
VD D q  
ꢀ
Automotiveꢀ  
-40°Cꢀtoꢀ+125°Cꢀ  
3.3Vꢀ±ꢀ5%ꢀ  
3.3V/2.5Vꢀ±ꢀ5%  
OPERATING RANGE (IS61VFxxxxx)  
Range  
Commercialꢀ  
Industrialꢀ  
Ambient Temperature  
0°Cꢀtoꢀ+70°Cꢀ  
VD D  
2.5Vꢀ±ꢀ5%ꢀ  
2.5Vꢀ±ꢀ5%ꢀ  
VD D q  
ꢀ2.5Vꢀ±ꢀ5%  
2.5Vꢀ±ꢀ5%  
ꢀ
ꢀ
-40°Cꢀtoꢀ+85°Cꢀ  
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)  
3.3V  
2.5V  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
Min.  
Max.  
Unit  
VO h  
OutputꢀHIGHꢀVoltageꢀ  
IO h = –4.0ꢀmAꢀ (3.3V)ꢀ  
IO h = –1.0 mA (2.5V)  
2.4ꢀ  
—ꢀ  
2.0ꢀ  
—ꢀ  
V
VO l  
OutputꢀLOWꢀVoltageꢀ  
IO l = 8.0ꢀmA (3.3V)ꢀ  
IO l = 1.0 mA (2.5V)  
—ꢀ  
0.4ꢀ  
—ꢀ  
0.4ꢀ  
V
VIh  
VIl  
Il I  
InputꢀHIGHꢀVoltageꢀꢀ  
InputꢀLOWꢀVoltage  
ꢀ
2.0ꢀ  
–0.3ꢀ  
–5ꢀ  
Vd d + 0.3  
1.7  
–0.3ꢀ  
–5ꢀ  
Vd d + 0.3  
V
V
ꢀ
0.8ꢀ  
5ꢀ  
0.7ꢀ  
5ꢀ  
Input Leakage Current  
OutputꢀLeakageꢀCurrent  
Vs s ≤ VIN ≤ Vd d (1)ꢀ  
µA  
µA  
Il O  
Vs s ≤ VO u T ≤ Vd d q , OE = VIhꢀ  
–5ꢀ  
5ꢀ  
–5ꢀ  
5ꢀ  
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)  
6.5  
7.5  
MAꢀ  
MAꢀ  
Symbol Parameter  
Test Conditions  
Temp. range  
x18  
x36  
x18  
x36  
Unit  
Ic c  
ACꢀOperatingꢀ  
Supply Current  
DeviceꢀSelected,ꢀꢀ  
OE = VIh, ZZ ≤ VIl,  
Com.ꢀ  
Ind.  
185ꢀ 185ꢀ  
190ꢀ 190ꢀ  
ꢀ
ꢀ
175ꢀ 175ꢀ  
185ꢀ 185ꢀ  
mA  
All Inputs ≤ 0.2V or ≥ Vd d – 0.2V, Au T O .  
Cycle Time ≥ tk c min.  
225  
225  
Is b  
StandbyꢀCurrentꢀ  
TTL Input  
DeviceꢀDeselected,ꢀꢀ  
Vd d = Max.,ꢀ  
All Inputs ≤ VIl or ≥ VIh,  
ZZ ≤ VIl, fꢀ=ꢀMax.  
Com.  
Ind.ꢀ  
Au T O .  
140  
150ꢀ 150ꢀ  
140  
140  
150ꢀ 150ꢀ  
150  
140  
mA  
ꢀ
ꢀ
150  
Is b Iꢀ  
StandbyꢀCurrentꢀ  
cMOs Input  
DeviceꢀDeselected,ꢀ  
Vd d = Max.,ꢀ  
Com.ꢀ  
Ind.ꢀ  
Auto.  
80  
85ꢀ  
80  
85ꢀ  
80  
85ꢀ  
90  
80  
85ꢀ  
90  
mA  
VIN  
≤
Vs s +ꢀ0.2Vꢀorꢀ≥Vd d – 0.2V  
f = 0  
Note:  
1.ꢀ MODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀVd d or Vs s . It exhibits 100 ꢀA maximum leakage current when tied to ≤ Vs s ꢀ+ꢀ0.2Vꢀorꢀ≥ Vd d – 0.2V.  
12  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
CAPACITANCE(1,2)  
Symbol  
cIN  
Parameter  
Conditions  
VIN = 0V  
Max.  
Unit  
pF  
Input Capacitance  
Input/OutputꢀCapacitanceꢀ  
6
8
cO u T ꢀ  
VO u T = 0V  
pF  
Notes:  
1. Tested initially and after any design or process changes that may affect these parameters.  
2. Test conditions: TA = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVd d ꢀ=ꢀ3.3V.  
3.3V I/O AC TEST CONDITIONS  
Parameter  
InputꢀPulseꢀLevelꢀ  
InputꢀRiseꢀandꢀFallꢀTimesꢀ  
Unit  
0Vꢀtoꢀ3.0V  
1.5ꢀns  
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ  
1.5V  
and Reference Level  
ꢀ
OutputꢀLoadꢀ  
SeeꢀFiguresꢀ1ꢀandꢀ2  
AC TEST LOADS  
317 Ω  
3.3V  
ZO = 50Ω  
OUTPUT  
OUTPUT  
50Ω  
351 Ω  
5 pF  
Including  
jig and  
1.5V  
scope  
Figure 1  
Figure 2  
Integrated Silicon Solution, Inc.ꢀ  
13  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
2.5V I/O AC TEST CONDITIONS  
Parameter  
InputꢀPulseꢀLevelꢀ  
InputꢀRiseꢀandꢀFallꢀTimesꢀ  
Unit  
0Vꢀtoꢀ2.5V  
1.5ꢀns  
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ  
1.25V  
and Reference Level  
ꢀ
OutputꢀLoadꢀ  
SeeꢀFiguresꢀ3ꢀandꢀ4  
2.5V I/O OUTPUT LOAD EQUIVALENT  
1,667 Ω  
+2.5V  
ZO = 50Ω  
OUTPUT  
OUTPUT  
50Ω  
5 pF  
Including  
jig and  
scope  
1,538 Ω  
1.25V  
Figure 3  
Figure 4  
14  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)  
6.5  
Min.  
7.5  
Min. Max.  
Symbol  
ꢀ fmaxꢀ  
Parameter  
Max.  
133ꢀ  
—ꢀ  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ClockꢀFrequencyꢀ  
—ꢀ  
7.5ꢀ  
2.2ꢀ  
2.2ꢀ  
—ꢀ  
—ꢀ 117ꢀ  
8.5ꢀ —ꢀ  
2.5ꢀ —ꢀ  
2.5ꢀ —ꢀ  
—ꢀ 7.5ꢀ  
2.5ꢀ —ꢀ  
2.5ꢀ —ꢀ  
—ꢀ 4.0ꢀ  
—ꢀ 3.4ꢀ  
tk c ꢀ  
tk h ꢀ  
tk l ꢀ  
tk q ꢀ  
CycleꢀTimeꢀ  
ClockꢀHighꢀTimeꢀ  
—ꢀ  
ClockꢀLowꢀTimeꢀ  
—ꢀ  
ClockꢀAccessꢀTimeꢀꢀ  
6.5ꢀ  
—ꢀ  
(2)  
tk q x ꢀ  
tk q l Z (2,3)ꢀ  
tk q h Z (2,3)ꢀ  
tO E q ꢀ  
tO E l Z (2,3)ꢀ  
tO E h Z (2,3)ꢀ  
tA s ꢀ  
ClockꢀHighꢀtoꢀOutputꢀInvalidꢀ  
ClockꢀHighꢀtoꢀOutputꢀLow-Zꢀ  
ClockꢀHighꢀtoꢀOutputꢀHigh-Zꢀꢀ  
OutputꢀEnableꢀtoꢀOutputꢀValidꢀꢀ  
OutputꢀEnableꢀtoꢀOutputꢀLow-Zꢀ  
OutputꢀDisableꢀtoꢀOutputꢀHigh-Zꢀꢀ  
AddressꢀSetupꢀTimeꢀꢀ  
AddressꢀStatusꢀSetupꢀTimeꢀꢀ  
Read/WriteꢀSetupꢀTimeꢀꢀ  
ChipꢀEnableꢀSetupꢀTimeꢀꢀ  
AddressꢀAdvanceꢀSetupꢀTimeꢀꢀ  
DataꢀSetupꢀTimeꢀ  
2.5ꢀ  
2.5ꢀ  
—ꢀ  
—ꢀ  
3.8ꢀ  
3.2ꢀ  
—ꢀꢀ  
3.5ꢀ  
—ꢀ  
—ꢀ  
0ꢀ  
0ꢀꢀ  
—ꢀ  
—ꢀ  
—ꢀ 3.5ꢀ  
1.5ꢀ —ꢀ  
1.5ꢀ —ꢀ  
1.5ꢀ —ꢀ  
1.5ꢀ —ꢀ  
1.5ꢀ —ꢀ  
1.5ꢀ —ꢀ  
0.5ꢀ —ꢀ  
0.5ꢀ —ꢀ  
0.5ꢀꢀ —ꢀ  
0.5ꢀꢀ —ꢀ  
0.5ꢀꢀ —ꢀ  
0.5ꢀ —ꢀ  
1.5ꢀ  
1.5ꢀ  
1.5ꢀ  
1.5ꢀ  
1.5ꢀ  
1.5ꢀ  
0.5ꢀ  
0.5ꢀ  
0.5ꢀ  
0.5ꢀ  
0.5ꢀ  
0.5ꢀ  
ts s ꢀ  
—ꢀ  
tW s ꢀ  
—ꢀ  
tc E s ꢀ  
tA V s ꢀ  
—ꢀ  
—ꢀ  
td s ꢀ  
—ꢀ  
tA h  
Address Hold Time  
—ꢀ  
ts h  
Address Status Hold Time  
WriteꢀHoldꢀTimeꢀꢀ  
—ꢀ  
tW h ꢀ  
—ꢀ  
tc E h ꢀ  
tA V h ꢀ  
ChipꢀEnableꢀHoldꢀTimeꢀꢀ  
AddressꢀAdvanceꢀHoldꢀTimeꢀꢀ  
DataꢀHoldꢀTimeꢀ  
—ꢀ  
—ꢀ  
td h ꢀ  
—ꢀ  
Notes:  
1.ꢀ ConfigurationꢀsignalꢀMODEꢀisꢀstaticꢀandꢀmustꢀnotꢀchangeꢀduringꢀnormalꢀoperation.  
2.ꢀ Guaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled.  
3.ꢀ TestedꢀwithꢀloadꢀinꢀFigureꢀ2.  
Integrated Silicon Solution, Inc.ꢀ  
15  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
READ/WRITE CYCLE TIMING  
tKC  
CLK  
ADSP  
ADSC  
t
KH  
tKL  
ADSP is blocked by CE inactive  
t
SS  
tSH  
t
SS  
tSH  
ADV  
t
AS  
tAH  
Address  
RD1  
WR1  
RD2  
RD3  
t
t
WS  
WS  
t
t
WH  
GW  
BWE  
WH  
tWS  
tWH  
WR1  
BWd-BWa  
t
CES  
tCEH  
CE Masks ADSP  
CE  
CE2  
CE2  
t
t
CES  
CES  
t
t
CEH  
CEH  
CE2 and CE2 only sampled with ADSP or ADSC  
Unselected with CE2  
t
OELZ  
OEQ  
tOEHZ  
t
OE  
t
KQX  
High-Z  
KQLZ  
KQ  
High-Z  
DATAOUT  
2a  
2b  
2c  
2d  
1a  
t
tKQLZ  
t
KQHZ  
t
KQX  
t
tKQ  
High-Z  
1a  
DATAIN  
tDS  
tDH  
Single Write  
Burst Read  
Single Read  
Flow-through  
Unselected  
16  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
WRITE CYCLE TIMING  
tKC  
CLK  
ADSP  
ADSC  
t
KH  
tKL  
ADSP is blocked by CE1 inactive  
ADSC initiate Write  
tSS  
tSH  
t
AVH  
t
AVS  
ADV must be inactive for ADSP Write  
ADV  
tAS  
tAH  
Address  
WR1  
WR2  
WR3  
t
t
WS  
WS  
t
t
WH  
WH  
GW  
BWE  
tWS  
tWH  
tWS  
tWH  
BWd-BWa  
WR1  
WR2  
CE1 Masks ADSP  
WR3  
t
CES  
tCEH  
CE  
CE2  
CE2  
t
CES  
CES  
t
CEH  
CEH  
Unselected with CE2  
CE2 and CE3 only sampled with ADSP or ADSC  
t
t
OE  
DATAOUT  
DATAIN  
High-Z  
tDS  
tDH  
BW4-BW1 only are applied to first cycle of WR2  
2a 2b 2c 2d  
High-Z  
3a  
1a  
Burst Write  
Single Write  
Write  
Unselected  
Integrated Silicon Solution, Inc.  
17  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
SNOOZE MODE ELECTRICAL CHARACTERISTICS  
Symbol Parameter  
Conditions  
Temp. Range  
Min. Max.  
Unit  
Is b 2ꢀ  
ꢀ
ꢀ
CurrentꢀduringꢀSNOOZEꢀMODEꢀ  
ꢀ
ꢀ
ZZꢀ≥ꢀVihꢀ  
Com.ꢀ  
Ind.ꢀ  
Auto.ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
55ꢀ  
60ꢀ  
75  
mAꢀ ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tP d s ꢀ  
tP u s ꢀ  
tZ Z I ꢀ  
ZZꢀactiveꢀtoꢀinputꢀignoredꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ  
2ꢀ  
2ꢀ  
—ꢀ  
2ꢀ  
cycle  
cycle  
cycle  
ns  
ZZꢀinactiveꢀtoꢀinputꢀsampledꢀ  
ZZꢀactiveꢀtoꢀSNOOZEꢀcurrentꢀ  
ZZꢀinactiveꢀtoꢀexitꢀSNOOZEꢀcurrentꢀ  
—ꢀ  
0ꢀ  
tr Z Z I ꢀ  
—ꢀ  
SNOOZE MODE TIMING  
CLK  
t
PDS  
t
ZZ setup cycle  
ZZ recovPeUryS cycle  
ZZ  
t
ZZI  
Isupply  
ISB2  
tRZZI  
All Inputs  
Deselect or Read Only  
Deselect or Read Only  
(except ZZ)  
Normal  
operation  
cycle  
Outputs  
(Q)  
High-Z  
Don't Care  
18  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)  
TEST ACCESS PORT (TAP) - TEST CLOCK  
Theꢀ IS61LF/VF25636Aꢀ andꢀ IS61LF/VF51218Aꢀ haveꢀ aꢀ  
serialꢀboundaryꢀscanꢀTestꢀAccessꢀPortꢀ(TAP)ꢀinꢀtheꢀPBGAꢀ  
package only.This port operates in accordance with IEEE  
Standardꢀ1149.1-1900,ꢀbutꢀdoesꢀnotꢀincludeꢀallꢀfunctionsꢀ  
requiredꢀforꢀfullꢀ1149.1ꢀcompliance.ꢀTheseꢀfunctionsꢀfromꢀ  
the IEEEꢀ specification are excluded because they place  
addedꢀdelayꢀinꢀtheꢀcriticalꢀspeedꢀpathꢀofꢀtheꢀSRAM.ꢀTheꢀ  
TAPꢀcontrollerꢀoperatesꢀinꢀaꢀmannerꢀthatꢀdoesꢀnotꢀconflictꢀ  
withꢀtheꢀperformanceꢀofꢀotherꢀdevicesꢀusingꢀ1149.1ꢀfullyꢀ  
compliantꢀTAPs.ꢀTheꢀTAPꢀoperatesꢀusingꢀJEDECꢀstandardꢀ  
2.5VꢀI/Oꢀlogicꢀlevels.  
TheꢀtestꢀclockꢀisꢀonlyꢀusedꢀwithꢀtheTAPꢀcontroller.ꢀAllꢀinputsꢀ  
are captured on the rising edge of TCK and outputs are  
driven from the falling edge of TCK.  
                                                                               
TEST MODE SELECT (TMS)  
TheꢀTMSꢀinputꢀisꢀusedꢀtoꢀsendꢀcommandsꢀtoꢀtheꢀTAPꢀ  
controller and is sampled on the rising edge of TCK. This  
pinꢀmayꢀbeꢀleftꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀnotꢀused.ꢀTheꢀpinꢀ  
isꢀinternallyꢀpulledꢀup,ꢀresultingꢀinꢀaꢀlogicꢀHIGHꢀlevel.  
TEST DATA-IN (TDI)  
TheꢀTDIꢀpinꢀisꢀusedꢀtoꢀseriallyꢀinputꢀinformationꢀtoꢀtheꢀ  
registers and can be connected to the input of any regis-  
ter.ꢀTheꢀregisterꢀbetweenꢀTDIꢀandꢀTDOꢀisꢀchosenꢀbyꢀtheꢀ  
instructionꢀ loadedꢀ intoꢀ theꢀTAPꢀ instructionꢀ register.ꢀ Forꢀ  
informationꢀonꢀinstructionꢀregisterꢀloading,ꢀseeꢀtheꢀTAPꢀ  
ControllerꢀStateꢀDiagram.ꢀTDIꢀisꢀinternallyꢀpulledꢀupꢀandꢀ  
canꢀbeꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀunusedꢀinꢀanꢀapplica-  
tion.ꢀTDIꢀisꢀconnectedꢀtoꢀtheꢀMostꢀSignificantꢀBitꢀ(MSB)ꢀ  
on any register.  
DISABLING THE JTAG FEATURE  
TheꢀSRAMꢀcanꢀoperateꢀwithoutꢀusingꢀtheꢀJTAGꢀfeature.ꢀ  
Toꢀ disableꢀ theꢀTAPꢀ controller,ꢀTCKꢀ mustꢀ beꢀ tiedꢀ LOWꢀ  
(Vss)ꢀtoꢀpreventꢀclockingꢀofꢀtheꢀdevice.ꢀTDIꢀandꢀTMSꢀareꢀ  
internally pulled up and may be disconnected. They may  
alternately be connected toVd d through a pull-up resistor.  
TDOꢀshouldꢀbeꢀleftꢀdisconnected.ꢀOnꢀpower-up,ꢀtheꢀdeviceꢀ  
will start in a reset state which will not interfere with the  
device operation.  
TAP CONTROLLER BLOCK DIAGRAM  
0
Bypass Register  
2
1
0
Instruction Register  
TDI  
Selection Circuitry  
Selection Circuitry  
TDO  
31 30 29 . . .  
2
2
1
1
0
0
Identification Register  
x
. . . . .  
Boundary Scan Register*  
TCK  
TMS  
TAP CONTROLLER  
Integrated Silicon Solution, Inc.  
19  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
TEST DATA OUT (TDO)  
Boundary Scan Register  
TheꢀTDOꢀoutputꢀpinꢀisꢀusedꢀtoꢀseriallyꢀclockꢀdata-outꢀfromꢀ  
The boundary scan register is connected to all input and  
theregisters.Theoutputisactivedependingonthecurrent  
state of the TAP state machine (see TAP Controller State  
Diagram).ꢀTheꢀoutputꢀchangesꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCKꢀ  
andꢀTDOꢀisꢀconnectedꢀtoꢀtheꢀLeastꢀSignificantꢀBitꢀ(LSB)ꢀ  
of any register.  
output pins on the SRAM.Several no connect (NC) pins are  
also included in the scan register to reserve pins for higher  
densityꢀdevices.ꢀTheꢀx36ꢀconfigurationꢀhasꢀaꢀ75-bit-longꢀ  
registerꢀandꢀtheꢀx18ꢀconfigurationꢀalsoꢀhasꢀaꢀ75-bit-longꢀ  
register. The boundary scan register is loaded with the  
contentsꢀofꢀtheꢀRAMꢀInputꢀandꢀOutputꢀringꢀwhenꢀtheꢀTAPꢀ  
controllerꢀisꢀinꢀtheꢀCapture-DRꢀstateꢀandꢀthenꢀplacedꢀbe-  
tween the TDI and TDO pins when the controller is moved  
to the Shift-DRꢀstate.ꢀTheꢀEXTEST,ꢀSAMPLE/PRELOADꢀ  
andꢀSAMPLE-Zꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀcaptureꢀtheꢀ  
contentsꢀofꢀtheꢀInputꢀandꢀOutputꢀring.  
PERFORMING A TAP RESET  
AꢀResetꢀisꢀperformedꢀbyꢀforcingꢀTMSꢀHIGHꢀ(Vd d ) for five  
risingꢀedgesꢀofꢀTCK.ꢀRESETꢀmayꢀbeꢀperformedꢀwhileꢀtheꢀ  
SRAMꢀisꢀoperatingꢀandꢀdoesꢀnotꢀaffectꢀitsꢀoperation.ꢀAtꢀ  
power-up,ꢀtheꢀTAPꢀisꢀinternallyꢀresetꢀtoꢀensureꢀthatꢀTDOꢀ  
comes up in a high-Z state.  
TheꢀBoundaryꢀScanꢀOrderꢀtablesꢀshowꢀtheꢀorderꢀinꢀwhichꢀ  
theꢀbitsꢀareꢀconnected.ꢀEachꢀbitꢀcorrespondsꢀtoꢀoneꢀofꢀtheꢀ  
bumpsꢀonꢀtheꢀSRAMꢀpackage.ꢀTheꢀMSBꢀofꢀtheꢀregisterꢀisꢀ  
connectedꢀtoꢀTDI,ꢀandꢀtheꢀLSBꢀisꢀconnectedꢀtoꢀTDO.  
TAP REGISTERS  
RegistersꢀareꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ  
andꢀallowꢀdataꢀtoꢀbeꢀscannedꢀintoꢀandꢀoutꢀofꢀtheꢀSRAMꢀ  
test circuitry. Onlyꢀoneꢀregisterꢀcanꢀbeꢀselectedꢀatꢀaꢀtimeꢀ  
throughꢀtheꢀinstructionꢀregisters.ꢀDataꢀisꢀseriallyꢀloadedꢀ  
intoꢀtheꢀTDIꢀpinꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputꢀonꢀ  
theꢀTDOꢀpinꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCK.  
Scan Register Sizes  
Register Name  
Bit Size Bit Size  
(x18)  
(x36)  
Instruction Register  
Instructionꢀ  
Bypassꢀ  
3ꢀ  
3ꢀ  
Three-bit instructions can be serially loaded into the in-  
struction register.This register is loaded when it is placed  
between the TDI and TDO pins. (See TAPꢀControllerꢀBlockꢀ  
Diagram)ꢀ Atꢀpower-up,ꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀ  
withꢀtheꢀIDCODEꢀinstruction.ꢀItꢀisꢀalsoꢀloadedꢀwithꢀtheꢀ  
IDCODEꢀinstructionꢀifꢀtheꢀcontrollerꢀisꢀplacedꢀinꢀaꢀresetꢀ  
state as previously described.  
1ꢀ  
1ꢀ  
IDꢀ  
32ꢀ  
75ꢀ  
32ꢀ  
75ꢀ  
BoundaryꢀScanꢀ  
Identification (ID) Register  
WhenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCaptureIRꢀstate,ꢀtheꢀtwoꢀ  
leastꢀsignificantꢀbitsꢀareꢀloadedꢀwithꢀaꢀbinaryꢀ“01”ꢀpatternꢀtoꢀ  
allow for fault isolation of the board level serial test path.  
TheꢀIDꢀregisterꢀisꢀloadedꢀwithꢀaꢀvendor-specific,ꢀ32-bitꢀ  
codeꢀduringꢀtheꢀCapture-DRꢀstateꢀwhenꢀtheꢀIDCODEꢀcom-  
mandꢀisꢀloadedꢀtoꢀtheꢀinstructionꢀregister.ꢀTheꢀIDCODEꢀ  
isꢀhardwiredꢀintoꢀtheꢀSRAMꢀandꢀcanꢀbeꢀshiftedꢀoutꢀwhenꢀ  
theꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀShift-DRꢀstate.ꢀTheꢀIDꢀregisterꢀ  
has vendor code and other information described in the  
IdentificationꢀRegisterꢀDefinitionsꢀtable.  
Bypass Register  
To save time when serially shifting data through registers,  
it is sometimes advantageous to skip certain states. The  
bypass register is a single-bit register that can be placed  
betweenꢀTDIꢀandꢀTDOꢀpins.ꢀThisꢀallowsꢀdataꢀtoꢀbeꢀshiftedꢀ  
through the SRAM with minimal delay. The bypass reg-  
isterꢀisꢀsetꢀLOWꢀ(Vss)ꢀwhenꢀtheꢀBYPASSꢀinstructionꢀisꢀ  
executed.  
IDENTIFICATION REGISTER DEFINITIONS  
Instruction Field  
Description  
256K x 36  
xxxxꢀ  
512K x 18  
xxxxꢀ  
RevisionꢀNumberꢀ (31:28)ꢀꢀ Reservedꢀforꢀversionꢀnumber.ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DeviceꢀDepthꢀ (27:23)ꢀ  
DeviceꢀWidthꢀ (22:18)ꢀ  
ISSIꢀDeviceꢀIDꢀ (17:12)ꢀ  
ISSIꢀJEDECꢀIDꢀ (11:1)ꢀ  
IDꢀRegisterꢀPresenceꢀ (0)ꢀ  
DefinesꢀdepthꢀofꢀSRAM.ꢀ256Kꢀorꢀ512Kꢀ  
DefinesꢀwithꢀofꢀtheꢀSRAM.ꢀx36ꢀorꢀx18ꢀ  
Reservedꢀforꢀfutureꢀuse.ꢀ  
00111ꢀ  
01000ꢀ  
00011ꢀ  
xxxxxꢀ  
00100ꢀ  
xxxxxꢀ  
AllowsꢀuniqueꢀidentificationꢀofꢀSRAMꢀvendor.ꢀ  
IndicateꢀtheꢀpresenceꢀofꢀanꢀIDꢀregister.ꢀ  
00011010101ꢀ  
1ꢀ  
00011010101  
1ꢀ  
20  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
The  
            
TAPꢀcontrollerꢀrecognizesꢀanꢀall-0ꢀinstruction.Whenꢀanꢀ  
                                            
Eightꢀinstructionsꢀareꢀpossibleꢀwithꢀtheꢀthree-bitꢀinstructionꢀ  
register and all combinations are listed in the Instruction  
Code table. Three instructions are listed as RESERVED  
and should not be used and the other five instructions are  
describedꢀbelow.ꢀTheꢀTAPꢀcontrollerꢀusedꢀinꢀthisꢀSRAMꢀ  
isꢀnotꢀfullyꢀcompliantꢀwithꢀtheꢀ1149.1ꢀconventionꢀbecauseꢀ  
some mandatory instructions are not fully implemented.  
TheꢀTAPꢀcontrollerꢀcannotꢀbeꢀusedꢀtoꢀloadꢀaddress,ꢀdataꢀorꢀ  
control signals and cannot preload the Input or Output buf-  
fers.The SRAM does not implement the 1149.1 commands  
EXTEST or INTEST or the PRELOAD portion of SAMPLE/  
PRELOAD;ꢀinsteadꢀitꢀperformsꢀaꢀcaptureꢀofꢀtheꢀInputs and  
Output ring when these instructions are executed. Instruc-  
tionsꢀareꢀloadedꢀintoꢀtheꢀTAPꢀcontrollerꢀduringꢀtheꢀShift-IRꢀ  
stateꢀwhenꢀtheꢀinstructionꢀregisterꢀisꢀplacedꢀbetweenꢀTDIꢀ  
andꢀTDO.ꢀDuringꢀthisꢀstate,ꢀinstructionsꢀareꢀshiftedꢀfromꢀ  
theꢀinstructionꢀregisterꢀthroughꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀToꢀ  
executeꢀanꢀinstructionꢀonceꢀitꢀisꢀshiftedꢀin,ꢀtheꢀTAPꢀcontrol-  
lerꢀmustꢀbeꢀmovedꢀintoꢀtheꢀUpdate-IRꢀstate.  
SAMPLE/PRELOADꢀisꢀaꢀ1149.1ꢀmandatoryꢀinstruction.Theꢀ  
                                                                                             
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
TAP INSTRUCTION SET  
SAMPLE/PRELOAD  
PRELOADꢀportionꢀofꢀthisꢀinstructionꢀisꢀnotꢀimplemented,ꢀsoꢀ  
theꢀTAPꢀcontrollerꢀisꢀnotꢀfullyꢀ1149.1ꢀcompliant.ꢀWhenꢀtheꢀ  
SAMPLE/PRELOADꢀinstructionꢀisꢀloadedꢀtoꢀtheꢀinstruc-  
tionꢀregisterꢀandꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCapture-DRꢀ  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
ItꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀtheꢀTAPꢀcontrollerꢀclockꢀoper-  
atesꢀatꢀaꢀfrequencyꢀupꢀtoꢀ10ꢀMHz,ꢀwhileꢀtheꢀSRAMꢀclockꢀ  
runsꢀmoreꢀthanꢀanꢀorderꢀofꢀmagnitudeꢀfaster.ꢀBecauseꢀofꢀ  
theꢀclockꢀfrequencyꢀdifferences,ꢀitꢀisꢀpossibleꢀthatꢀduringꢀ  
theꢀCapture-DRꢀstate,ꢀanꢀinputꢀorꢀoutputꢀwillꢀunder-goꢀaꢀ  
transition.ꢀTheꢀTAPꢀmayꢀattemptꢀaꢀsignalꢀcaptureꢀwhileꢀinꢀ  
transition(metastablestate).Thedevicewillnotbeharmed,  
but there is no guarantee of the value that will be captured  
or repeatable results.  
To guarantee that the boundary scan register will capture  
theꢀcorrectꢀsignalꢀvalue,ꢀtheꢀSRAMꢀsignalꢀmustꢀbeꢀstabilizedꢀ  
longꢀenoughꢀtoꢀmeetꢀtheꢀTAPꢀcontroller’sꢀcaptureꢀset-upꢀ  
plusholdtimes(tc s andtc h ).ꢀToꢀinsureꢀthatꢀtheꢀSRAMꢀclockꢀ  
input is captured correctly, designs need a way to stop (or  
slow)ꢀtheꢀclockꢀduringꢀaꢀSAMPLE/PRELOADꢀinstruction.ꢀ  
If this is not an issue, it is possible to capture all other  
signals and simply ignore the value of the CLK and CLK  
captured in the boundary scan register.  
EꢀTEST  
EXTESTꢀisꢀaꢀmandatoryꢀ1149.1ꢀinstructionꢀwhichꢀisꢀtoꢀbeꢀ  
executed whenever the instruction register is loaded with  
allꢀ0s.ꢀBecauseꢀEXTESTꢀisꢀnotꢀimplementedꢀinꢀtheꢀTAPꢀ  
controller,ꢀthisꢀdeviceꢀisꢀnotꢀ1149.1ꢀstandardꢀcompliant.ꢀ  
Onceꢀtheꢀdataꢀisꢀcaptured,ꢀitꢀisꢀpossibleꢀtoꢀshiftꢀoutꢀtheꢀdataꢀ  
byꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀShift-DRꢀstate.ꢀThisꢀplacesꢀtheꢀ  
boundaryꢀscanꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpins.  
EXTESTꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregister,ꢀ  
theꢀSRAMꢀrespondsꢀasꢀifꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ  
hasbeenloaded.Thereisadifferencebetweenthe instruc-  
tions, unlike the SAMPLE/PRELOADꢀinstruction,ꢀEXTESTꢀ  
placesꢀtheꢀSRAMꢀoutputsꢀinꢀaꢀHigh-Zꢀstate.  
Note that since the PRELOAD part of the command is not  
implemented, putting the TAP into the Update to the Update-  
DR state while performing a SAMPLE/PRELOAD instruction  
willꢀhaveꢀtheꢀsameꢀeffectꢀasꢀtheꢀPause-DRꢀcommand.  
IDCODE  
Theꢀ IDCODEꢀ instructionꢀ causesꢀ aꢀ vendor-specific,ꢀ 32-  
bit code to be loaded into the instruction register. It also  
placesꢀtheꢀinstructionꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ  
pinsꢀandꢀallowsꢀtheꢀIDCODEꢀtoꢀbeꢀshiftedꢀoutꢀofꢀtheꢀdeviceꢀ  
whenꢀtheꢀTAPꢀcontrollerꢀentersꢀtheꢀShift-DRꢀstate.ꢀTheꢀ  
IDCODEꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregisterꢀ  
uponꢀpower-upꢀorꢀwheneverꢀtheꢀTAPꢀcontrollerꢀisꢀgivenꢀaꢀ  
test logic reset state.  
BYPASS  
WhenꢀtheꢀBYPASSꢀinstructionꢀisꢀloadedꢀinꢀtheꢀinstruc-  
tionꢀregisterꢀandꢀtheꢀTAPꢀisꢀplacedꢀinꢀaꢀShift-DRꢀstate,ꢀ  
theꢀbypassꢀregisterꢀisꢀplacedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ  
pins.ꢀTheꢀadvantageꢀofꢀtheꢀBYPASSꢀinstructionꢀisꢀthatꢀitꢀ  
shortens the boundary scan path when multiple devices  
are connected together on a board.  
SAMPLE-Z  
RESERVED  
Theꢀ SAMPLE-Zꢀ instructionꢀ causesꢀ theꢀ boundaryꢀ scanꢀ  
registerꢀtoꢀbeꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ  
whenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀaꢀShift-DRꢀstate.ꢀItꢀalsoꢀplacesꢀ  
allꢀSRAMꢀoutputsꢀintoꢀaꢀHigh-Zꢀstate.  
These instructions are not implemented but are reserved  
forꢀfutureꢀuse.ꢀDoꢀnotꢀuseꢀtheseꢀinstructions.  
Integrated Silicon Solution, Inc.  
21  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
INSTRUCTION CODES  
Code  
Instruction  
Description  
000ꢀ  
EXTESTꢀ  
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbe-  
tweenꢀtheꢀTDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputsꢀtoꢀHigh-Zꢀstate.ꢀThisꢀ  
instructionꢀisꢀnotꢀ1149.1ꢀcompliant.  
001ꢀ  
010ꢀ  
IDCODEꢀ  
LoadsꢀtheꢀIDꢀregisterꢀwithꢀtheꢀvendorꢀIDꢀcodeꢀandꢀplacesꢀtheꢀregisterꢀbetweenꢀTDIꢀ  
andꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀaffectꢀSRAMꢀoperation.  
SAMPLE-Zꢀ  
CapturesꢀtheꢀInput/Outputꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbetweenꢀ  
TDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputꢀdriversꢀtoꢀaꢀHigh-Zꢀstate.  
011ꢀ  
RESERVEDꢀ  
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.  
100  
SAMPLE/PRELOAD  
ꢀ
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀ  
between TDIꢀandꢀTDO.ꢀDoesꢀnotꢀaffectꢀtheꢀSRAMꢀoperation.ꢀThisꢀinstructionꢀdoesꢀnotꢀ  
implementꢀ1149.1ꢀpreloadꢀfunctionꢀandꢀisꢀthereforeꢀnotꢀ1149.1ꢀcompliant.  
101ꢀ  
110ꢀꢀ  
111ꢀ  
RESERVEDꢀ  
RESERVEDꢀ  
BYPASSꢀ  
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.ꢀꢀ  
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.  
PlacesꢀtheꢀbypassꢀregisterꢀbetweenꢀTDIꢀandꢀTDO.ꢀThisꢀoperationꢀdoesꢀnot  
affectꢀSRAMꢀoperation.  
TAP CONTROLLER STATE DIAGRAM  
Test Logic Reset  
1
0
1
1
1
Run Test/Idle  
Select DR  
0
Select IR  
0
0
1
1
Capture DR  
0
Capture IR  
0
Shift DR  
1
Shift IR  
1
0
0
1
1
Exit1 DR  
0
Exit1 IR  
0
Pause DR  
1
Pause IR  
1
0
0
Exit2 DR  
1
Exit2 IR  
1
0
1
0
1
Update DR  
0
Update IR  
0
22  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
TAP Electrical Characteristics OverꢀtheꢀOperatingꢀRange(1,2)  
Symbol  
VO h 1  
VO h 2  
VO l 1  
VO l 2  
VIh  
Parameter  
Test Conditions  
IO h = –2.0 mAꢀ  
IO h = –100 µA  
IO l = 2.0 mAꢀ  
IO l = 100 µAꢀ  
Min.  
1.7ꢀ  
2.1ꢀ  
—ꢀ  
Max.  
—ꢀ  
Units  
V
OutputꢀHIGHꢀVoltage  
OutputꢀHIGHꢀVoltage  
OutputꢀLOWꢀVoltage  
OutputꢀLOWꢀVoltage  
InputꢀHIGHꢀVoltage  
InputꢀLOWꢀVoltage  
Input Load Current  
—ꢀ  
V
0.7  
V
—ꢀ  
0.2  
V
1.7  
Vd d ꢀ+0.3  
0.7  
V
VIl  
IO l T = 2mA  
–0.3ꢀ  
–5ꢀ  
V
Ix  
Vss ≤ V I ≤ Vd d q  
5ꢀ  
mA  
Notes:  
1.ꢀ AllꢀVoltageꢀreferencedꢀtoꢀGround.  
2.ꢀ Overshoot:ꢀVIh (AC) ≤ Vd d ꢀ+1.5Vꢀforꢀtꢀ≤ tT c y c /2,  
ꢀ
ꢀ
Undershoot:ꢀVilꢀ(AC)ꢀ≤ꢀ0.5Vꢀforꢀtꢀ≤ tT c y c /2,  
Power-up:ꢀVIh < 2.6V and Vd d ꢀ<ꢀ2.4VꢀandꢀVd d q ꢀ<ꢀ1.4Vꢀforꢀtꢀ<ꢀ200ꢀms.  
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)  
Symbol Parameter  
Min.  
100ꢀ  
—ꢀ  
Max.  
—ꢀ  
10ꢀ  
—
Unit  
ns  
tT c y c  
fT f  
TCK Clock cycle time  
TCKꢀClockꢀfrequencyꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
MHz  
ns  
tT h  
TCKꢀClockꢀHIGH  
40ꢀ  
40ꢀ  
10ꢀ  
10ꢀ  
10ꢀ  
10ꢀ  
10ꢀ  
10ꢀ  
—ꢀ  
tT l  
TCKꢀClockꢀLOWꢀ  
—
ns  
tT M s s  
tT d Is  
tc s  
TMSꢀsetupꢀtoꢀTCKꢀClockꢀRise  
TDIꢀsetupꢀtoꢀTCKꢀClockꢀRise  
Capture setup to TCK Rise  
TMSꢀholdꢀafterꢀTCKꢀClockꢀRise  
TDIꢀHoldꢀafterꢀClockꢀRise  
Capture hold after Clock Rise  
TCKꢀLOWꢀtoꢀTDOꢀvalidꢀ  
TCKꢀLOWꢀtoꢀTDOꢀinvalid  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
20  
ns  
ns  
ns  
tT M s h  
tT d Ih  
tc h  
ns  
ns  
ns  
tT d O V  
ꢀ
ꢀ
ns  
tT d O x  
0ꢀ  
—ꢀ  
ns  
Notes:  
1. Both tc s and tc h refer to the set-up and hold time requirements of latching data from the boundary scan register.  
2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.  
Integrated Silicon Solution, Inc.ꢀ  
23  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
TAP Output Load Equivalent  
TAP AC TEST CONDITIONS  
Inputꢀpulseꢀlevelsꢀ  
0ꢀtoꢀ2.5V/0ꢀtoꢀ3.0V  
1ns  
Input rise and fall times  
Inputꢀtimingꢀreferenceꢀlevelsꢀ  
Outputꢀreferenceꢀlevelsꢀ  
1.25V/1.5V  
1.25V/1.5V  
50Ω  
Testꢀloadꢀterminationꢀsupplyꢀvoltageꢀ  
1.25V/1.5V  
1.25V/1.5V  
TDO  
20 pF  
GND  
Z0 = 50Ω  
TAP TIMING  
1
2
3
4
5
6
tTHTH  
t
TLTH  
TCK  
TMS  
t
THTL  
t
MVTH  
DVTH  
t
THMX  
t
t
THDX  
TDI  
tTLOV  
TDO  
t
TLOX  
DON'T CARE  
UNDEFINED  
24  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
119 BGA BOUNDARY SCAN ORDER (256K ꢀ 36)  
Signal Bump  
Signal Bump  
Signal Bump  
Signal Bump  
Bit # Name  
ID  
Bit # Name  
ID  
Bit # Name  
ID  
Bit # Name  
ID  
2K  
1L  
ꢀ 1ꢀ  
ꢀ 2ꢀ  
ꢀ 3ꢀ  
ꢀ 4ꢀ  
ꢀ 5ꢀ  
ꢀ 6ꢀ  
ꢀ 7ꢀ  
ꢀ 8ꢀ  
ꢀ 9ꢀ  
ꢀ10ꢀ  
ꢀ11ꢀ  
ꢀ12ꢀ  
ꢀ13ꢀ  
ꢀ14ꢀ  
ꢀ15ꢀ  
ꢀ16ꢀ  
ꢀ17ꢀ  
ꢀ18ꢀ  
Aꢀ  
Aꢀ  
2Rꢀ  
3Tꢀ  
4Tꢀ  
5Tꢀ  
6Rꢀ  
3Bꢀ  
5Bꢀ  
6Pꢀ  
7Nꢀ  
6Mꢀ  
7Lꢀ  
6Kꢀ  
7Pꢀ  
6Nꢀ  
6Lꢀ  
7Kꢀ  
7Tꢀ  
6Hꢀ  
19ꢀ  
20ꢀ  
21ꢀ  
22ꢀ  
23ꢀ  
24ꢀ  
25ꢀ  
26ꢀ  
27ꢀ  
28ꢀ  
29ꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
Aꢀ  
7Gꢀ  
6Fꢀ  
7Eꢀ  
7Dꢀ  
7Hꢀ  
6Gꢀ  
6Eꢀ  
6Dꢀ  
6Aꢀ  
5Aꢀ  
4Gꢀ  
37ꢀ  
38ꢀ  
39ꢀ  
40ꢀ  
41ꢀ  
42ꢀ  
43ꢀ  
44ꢀ  
45ꢀ  
46ꢀ  
47ꢀ  
48ꢀ  
49ꢀ  
50ꢀ  
51ꢀ  
52ꢀ  
53ꢀ  
54ꢀ  
BWaꢀ  
BWbꢀ  
BWcꢀ  
BWdꢀ  
CE2ꢀ  
CEꢀ  
5Lꢀ  
5Gꢀ  
3Gꢀ  
3Lꢀ  
2Bꢀ  
4Eꢀ  
3Aꢀ  
2Aꢀ  
2Dꢀ  
1Eꢀ  
2Fꢀ  
1Gꢀ  
2Hꢀ  
1Dꢀ  
2Eꢀ  
2Gꢀ  
1H  
55ꢀ  
56ꢀ  
57ꢀ  
58ꢀ  
59ꢀ  
60ꢀ  
61ꢀ  
62ꢀ  
63ꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
Aꢀ  
2M  
1N  
1P  
1K  
2L  
Aꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
ZZꢀ  
Aꢀ  
2N  
2P  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
NCꢀ  
Aꢀ  
64ꢀ MODEꢀ 3R  
ADVꢀ  
65ꢀ  
66ꢀ  
67ꢀ  
68ꢀ  
69ꢀ  
70ꢀ  
Aꢀ  
Aꢀ  
2C  
3C  
5C  
6C  
4N  
4P  
30ꢀ ADSPꢀ 4Aꢀ  
31ꢀ ADSCꢀ 4Bꢀ  
Aꢀ  
32ꢀ  
33ꢀ  
34ꢀ  
35ꢀ  
36ꢀ  
OEꢀ  
4Fꢀ  
Aꢀ  
BWEꢀ 4Mꢀ  
A1ꢀ  
A0ꢀ  
GWꢀ  
CLKꢀ  
Aꢀ  
4Hꢀ  
4Kꢀ  
6Bꢀ  
DQbꢀ  
5R  
119 BGA BOUNDARY SCAN ORDER (512K ꢀ 18)  
Signal Bump  
Signal Bump  
Signal Bump  
Signal Bump  
Bit # Name  
ID  
Bit # Name  
ID  
Bit # Name  
ID  
Bit # Name  
ID  
2K  
1L  
ꢀ 1ꢀ  
ꢀ 2ꢀ  
ꢀ 3ꢀ  
ꢀ 4ꢀ  
ꢀ 5ꢀ  
ꢀ 6ꢀ  
ꢀ 7ꢀ  
ꢀ 8ꢀ  
ꢀ 9ꢀ  
ꢀ10ꢀ  
ꢀ11ꢀ  
ꢀ12ꢀ  
ꢀ13ꢀ  
Aꢀ  
Aꢀ  
2Rꢀ  
2Tꢀ  
3Tꢀ  
5Tꢀ  
6Rꢀ  
3Bꢀ  
5Bꢀ  
7Pꢀ  
6Nꢀ  
6Lꢀ  
7Kꢀ  
7Tꢀ  
6Hꢀ  
14ꢀ  
15ꢀ  
16ꢀ  
17ꢀ  
18ꢀ  
19ꢀ  
20ꢀ  
21ꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
Aꢀ  
7Gꢀ  
6Fꢀ  
7Eꢀ  
6Dꢀ  
6Tꢀ  
6Aꢀ  
5Aꢀ  
4Gꢀ  
27ꢀ  
28ꢀ  
29ꢀ  
30ꢀ  
31ꢀ  
32ꢀ  
33ꢀ  
34ꢀ  
35ꢀ  
36ꢀ  
37ꢀ  
38ꢀ  
39ꢀ  
CLKꢀ  
Aꢀ  
4Kꢀ  
6Bꢀ  
5Lꢀ  
3Gꢀ  
2Bꢀ  
4Eꢀ  
3Aꢀ  
2Aꢀ  
1Dꢀ  
2Eꢀ  
2Gꢀ  
1Hꢀ  
5R  
40ꢀ  
41ꢀ  
42ꢀ  
43ꢀ  
44ꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
Aꢀ  
BWaꢀ  
BWbꢀ  
CE2ꢀ  
CEꢀ  
2M  
1N  
2P  
Aꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
45ꢀ MODEꢀ 3R  
Aꢀ  
Aꢀ  
Aꢀ  
46ꢀ  
47ꢀ  
48ꢀ  
49ꢀ  
50ꢀ  
51ꢀ  
Aꢀ  
Aꢀ  
2C  
3C  
5C  
6C  
4N  
4P  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
ZZꢀ  
DQaꢀ  
ADVꢀ  
Aꢀ  
22ꢀ ADSPꢀ 4Aꢀ  
23ꢀ ADSCꢀ 4Bꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
NCꢀ  
Aꢀ  
Aꢀ  
24ꢀ  
25ꢀ  
26ꢀ  
OEꢀ  
BWEꢀ 4Mꢀ  
GWꢀ 4Hꢀ  
4Fꢀ  
A1ꢀ  
A0ꢀ  
Integrated Silicon Solution, Inc.ꢀ  
25  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
165 PBGA BOUNDARY SCAN ORDER (x 36)  
Signal Bump  
Signal Bump  
Signal  
Name  
Bump  
ID  
Signal Bump  
Bit # Name  
ID  
Bit # Name  
ID  
Bit #  
41ꢀ  
42ꢀ  
43ꢀ  
44ꢀ  
45ꢀ  
46ꢀ  
47ꢀ  
48ꢀ  
49ꢀ  
50ꢀ  
51ꢀ  
52ꢀ  
53ꢀ  
54ꢀ  
55ꢀ  
56ꢀ  
57ꢀ  
58ꢀ  
59ꢀ  
60ꢀ  
Bit #  
61ꢀ  
62ꢀ  
63ꢀ  
64ꢀ  
65ꢀ  
66ꢀ  
67ꢀ  
68ꢀ  
69ꢀ  
70ꢀ  
71ꢀ  
72ꢀ  
73ꢀ  
74ꢀ  
75ꢀ  
ꢀ
Name  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
DQdꢀ  
Aꢀ  
ID  
ꢀ 1ꢀ  
ꢀ 2ꢀ  
ꢀ 3ꢀ  
ꢀ 4ꢀ  
ꢀ 5ꢀ  
ꢀ 6ꢀ  
ꢀ 7ꢀ  
ꢀ 8ꢀ  
ꢀ 9ꢀ  
ꢀ10ꢀ  
ꢀ11ꢀ  
ꢀ12ꢀ  
ꢀ13ꢀ  
ꢀ14ꢀ  
ꢀ15ꢀ  
ꢀ16ꢀ  
ꢀ17ꢀ  
ꢀ18ꢀ  
ꢀ19ꢀ  
ꢀ20ꢀ  
MODEꢀ 1Rꢀ  
21ꢀ  
22ꢀ  
23ꢀ  
24ꢀ  
25ꢀ  
26ꢀ  
27ꢀ  
28ꢀ  
29ꢀ  
30ꢀ  
31ꢀ  
32ꢀ  
33ꢀ  
34ꢀ  
35ꢀ  
36ꢀ  
37ꢀ  
38ꢀ  
39ꢀ  
40ꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
NCꢀ  
11Gꢀ  
11Fꢀ  
11Eꢀ  
11Dꢀ  
10Gꢀ  
10Fꢀ  
10Eꢀ  
10Dꢀ  
11Cꢀ  
11Aꢀ  
10Aꢀ  
10Bꢀ  
9Aꢀ  
NCꢀ  
CE2ꢀ  
BWaꢀ  
BWbꢀ  
BWcꢀ  
BWdꢀ  
CE2ꢀ  
CEꢀ  
1Aꢀ  
6Aꢀ  
5Bꢀ  
5Aꢀ  
4Aꢀ  
4Bꢀ  
3Bꢀ  
3Aꢀ  
2Aꢀ  
2Bꢀ  
1Bꢀ  
1Cꢀ  
1Dꢀ  
1Eꢀ  
1Fꢀ  
1Gꢀ  
2D  
1J  
NCꢀ  
Aꢀ  
6Nꢀ  
11Pꢀ  
8Pꢀ  
1K  
1L  
1M  
2J  
Aꢀ  
Aꢀ  
8Rꢀ  
Aꢀ  
9Rꢀ  
2K  
2L  
2M  
1N  
3P  
3R  
4R  
4P  
6P  
6R  
Aꢀ  
9Pꢀ  
Aꢀ  
10Pꢀ  
10Rꢀ  
11Rꢀ  
11Hꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
ZZꢀ  
Aꢀ  
NCꢀ  
Aꢀ  
DQaꢀ 11Nꢀ  
DQaꢀ 11Mꢀ  
DQaꢀ 11Lꢀ  
DQaꢀ 11Kꢀ  
DQaꢀ 11Jꢀ  
DQaꢀ 10Mꢀ  
DQaꢀ 10Lꢀ  
DQaꢀ 10Kꢀ  
DQaꢀ 10Jꢀ  
Aꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
DQcꢀ  
Aꢀ  
ADVꢀ  
ADSPꢀ  
ADSCꢀ  
OEꢀ  
Aꢀ  
9Bꢀ  
A1ꢀ  
8Aꢀ  
A0ꢀ  
8Bꢀ  
BWEꢀ  
GWꢀ  
CLKꢀ  
NCꢀ  
7Aꢀ  
7Bꢀ  
2E  
6Bꢀ  
2F  
11Bꢀ  
2G  
26  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
165 PBGA BOUNDARY SCAN ORDER (x 18)  
Signal Bump  
Signal Bump  
Signal  
Name  
Bump  
ID  
Signal Bump  
Bit # Name  
ID  
Bit # Name  
ID  
Bit #  
41ꢀ  
42ꢀ  
43ꢀ  
44ꢀ  
45ꢀ  
46ꢀ  
47ꢀ  
48ꢀ  
49ꢀ  
50ꢀ  
51ꢀ  
52ꢀ  
53ꢀ  
54ꢀ  
55ꢀ  
56ꢀ  
57ꢀ  
58ꢀ  
59ꢀ  
60ꢀ  
Bit #  
61ꢀ  
62ꢀ  
63ꢀ  
64ꢀ  
65ꢀ  
66ꢀ  
67ꢀ  
68ꢀ  
69ꢀ  
70ꢀ  
71ꢀ  
72ꢀ  
73ꢀ  
74ꢀ  
75ꢀ  
ꢀ
Name  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
NCꢀ  
NCꢀ  
NCꢀ  
NCꢀ  
Aꢀ  
ID  
ꢀ 1ꢀ  
ꢀ 2ꢀ  
ꢀ 3ꢀ  
ꢀ 4ꢀ  
ꢀ 5ꢀ  
ꢀ 6ꢀ  
ꢀ 7ꢀ  
ꢀ 8ꢀ  
ꢀ 9ꢀ  
ꢀ10ꢀ  
ꢀ11ꢀ  
ꢀ12ꢀ  
ꢀ13ꢀ  
ꢀ14ꢀ  
ꢀ15ꢀ  
ꢀ16ꢀ  
ꢀ17ꢀ  
ꢀ18ꢀ  
ꢀ19ꢀ  
ꢀ20ꢀ  
MODEꢀ 1Rꢀ  
21ꢀ  
22ꢀ  
23ꢀ  
24ꢀ  
25ꢀ  
26ꢀ  
27ꢀ  
28ꢀ  
29ꢀ  
30ꢀ  
31ꢀ  
32ꢀ  
33ꢀ  
34ꢀ  
35ꢀ  
36ꢀ  
37ꢀ  
38ꢀ  
39ꢀ  
40ꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
DQaꢀ  
NCꢀ  
11Gꢀ  
11Fꢀ  
11Eꢀ  
11Dꢀ  
11Cꢀ  
10Fꢀ  
10Eꢀ  
10Dꢀ  
10Gꢀ  
11Aꢀ  
10Aꢀ  
10Bꢀ  
9Aꢀ  
NCꢀ  
CE2ꢀ  
BWaꢀ  
NCꢀ  
1Aꢀ  
6Aꢀ  
5Bꢀ  
5Aꢀ  
4Aꢀ  
4Bꢀ  
3Bꢀ  
3Aꢀ  
2Aꢀ  
2Bꢀ  
1Bꢀ  
1Cꢀ  
1Dꢀ  
1Eꢀ  
1Fꢀ  
1Gꢀ  
2D  
1J  
NCꢀ  
Aꢀ  
6Nꢀ  
11Pꢀ  
8Pꢀ  
1K  
1L  
1M  
1N  
2K  
2L  
2M  
2J  
Aꢀ  
Aꢀ  
8Rꢀ  
BWbꢀ  
NCꢀ  
Aꢀ  
9Rꢀ  
Aꢀ  
9Pꢀ  
NCꢀ  
CE2ꢀ  
CEꢀ  
Aꢀ  
10Pꢀ  
10Rꢀ  
11Rꢀ  
11Hꢀ  
11Nꢀ  
11Mꢀ  
11Lꢀ  
11Kꢀ  
11Jꢀ  
NCꢀ  
Aꢀ  
NCꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
Aꢀ  
3P  
3R  
4R  
4P  
6P  
6R  
ZZꢀ  
NCꢀ  
NCꢀ  
NCꢀ  
NCꢀ  
NCꢀ  
Aꢀ  
NCꢀ  
Aꢀ  
Aꢀ  
NCꢀ  
Aꢀ  
ADVꢀ  
ADSPꢀ  
ADSCꢀ  
OEꢀ  
NCꢀ  
Aꢀ  
9Bꢀ  
NCꢀ  
A1ꢀ  
8Aꢀ  
NCꢀ  
A0ꢀ  
8Bꢀ  
NCꢀ  
DQaꢀ 10Mꢀ  
DQaꢀ 10Lꢀ  
DQaꢀ 10Kꢀ  
DQaꢀ 10Jꢀ  
BWEꢀ  
GWꢀ  
CLKꢀ  
NCꢀ  
7Aꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
DQbꢀ  
7Bꢀ  
2E  
6Bꢀ  
2F  
11Bꢀ  
2G  
Integrated Silicon Solution, Inc.  
27  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
ORDERING INFORMATION (VD D = 3.3V/VD D q = 2.5V/3.3V)  
Commercial Range: 0°C to +70°C  
Configuration  
Access Time  
Order Part Number  
Package(1)  
256Kx36ꢀ  
6.5ꢀ  
ꢀ
IS61LF25636A-6.5TQꢀ  
IS61LF25636A-6.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
256Kx36ꢀ  
ꢀ
IS61LF25636A-6.5B3ꢀ  
165ꢀPBGA  
7.5ꢀ  
ꢀ
IS61LF25636A-7.5TQꢀ  
IS61LF25636A-7.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
ꢀ
IS61LF25636A-7.5B3ꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
ꢀ ꢀ  
6.5ꢀ  
ꢀ
ꢀ
IS61LF51218A-6.5TQꢀ  
IS61LF51218A-6.5TQLꢀ  
IS61LF51218A-6.5B2ꢀ  
100ꢀTQFP,ꢀ3CEꢀ  
100ꢀTQFP,ꢀ3CE,ꢀLead-free  
119ꢀPBGA  
ꢀ
ꢀ
ꢀ ꢀ  
ꢀ
IS61LF51218A-6.5B3ꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
7.5ꢀ  
ꢀ
IS61LF51218A-7.5TQꢀ  
IS61LF51218A-7.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ
IS61LF51218A-7.5B3ꢀ  
165ꢀPBGA  
Industrial Range: -40°C to +85°C  
Configuration  
Access Time  
Order Part Number  
Package(1)  
256Kx36ꢀ  
6.5ꢀ  
ꢀ
IS61LF25636A-6.5TQIꢀ  
IS61LF25636A-6.5B2Iꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
256Kx36ꢀ  
ꢀ ꢀ  
ꢀ ꢀ  
ꢀ
IS61LF25636A-6.5B3Iꢀ  
165ꢀPBGA  
7.5ꢀ  
ꢀ
ꢀ
IS61LF25636A-7.5TQIꢀ  
IS61LF25636A-7.5TQLIꢀ  
IS61LF25636A-7.5B2Iꢀ  
100ꢀTQFP,ꢀ3CEꢀ  
100ꢀTQFP,ꢀ3CE,ꢀLead-free  
119ꢀPBGA  
ꢀ
ꢀ
ꢀ
ꢀ ꢀ  
ꢀ
IS61LF25636A-7.5B3Iꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
6.5ꢀ  
ꢀ
IS61LF51218A-6.5TQIꢀ  
IS61LF51218A-6.5B2Iꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ
IS61LF51218A-6.5B3Iꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
ꢀ ꢀ  
7.5ꢀ  
ꢀ
ꢀ
IS61LF51218A-7.5TQIꢀ  
IS61LF51218A-7.5TQLIꢀ  
IS61LF51218A-7.5B2Iꢀ  
100ꢀTQFP,ꢀ3CEꢀ  
100ꢀTQFP,ꢀ3CE,ꢀLead-free  
119ꢀPBGA  
ꢀ
ꢀ ꢀ  
ꢀ
IS61LF51218A-7.5B3Iꢀ  
165ꢀPBGA  
Note:  
1.ꢀꢀForꢀ100ꢀTQFP,ꢀ2CEꢀoptionꢀcontactꢀSRAMꢀMarketingꢀatꢀsram@issi.com  
Automotive Range: -40°C to +125°C  
Configuration  
Access Time  
Order Part Number  
Package(1)  
256Kx36ꢀ  
ꢀ ꢀ  
7.5ꢀ  
ꢀ
IS64LF25636A-7.5TQLA3ꢀ  
IS64LF25636A-7.5BLA3ꢀ  
100ꢀTQFP,ꢀ3CE,ꢀLead-freeꢀ  
165ꢀPBGA,ꢀLead-free  
ꢀ
28  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
ORDERING INFORMATION (VD D = 2.5V /VD D q = 2.5V)  
Commercial Range: 0°C to +70°C  
Configuration  
Access Time  
Order Part Number  
Package(1)  
256Kx36ꢀ  
6.5ꢀ  
ꢀ
IS61VF25636A-6.5TQꢀ  
IS61VF25636A-6.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
256Kx36ꢀ  
ꢀ
IS61VF25636A-6.5B3ꢀ  
165ꢀPBGA  
7.5ꢀ  
ꢀ
IS61VF25636A-7.5TQꢀ  
IS61VF25636A-7.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
ꢀ
IS61VF25636A-7.5B3ꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
6.5ꢀ  
ꢀ
IS61VF51218A-6.5TQꢀ  
IS61VF51218A-6.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ
IS61VF51218A-6.5B3ꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
7.5ꢀ  
ꢀ
IS61VF51218A-7.5TQꢀ  
IS61VF51218A-7.5B2ꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ
IS61VF51218A-7.5B3ꢀ  
165ꢀPBGA  
Industrial Range: -40°C to +85°C  
Configuration  
Access Time  
Order Part Number  
Package(1)  
256Kx36ꢀ  
6.5ꢀ  
ꢀ
IS61VF25636A-6.5TQIꢀ  
IS61VF25636A-6.5B2Iꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
256Kx36ꢀ  
ꢀ
IS61VF25636A-6.5B3Iꢀ  
165ꢀPBGA  
7.5ꢀ  
ꢀ
IS61VF25636A-7.5TQIꢀ  
IS61VF25636A-7.5B2Iꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ ꢀ  
ꢀ
IS61VF25636A-7.5B3Iꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
6.5ꢀ  
ꢀ
IS61VF51218A-6.5TQIꢀ  
IS61VF51218A-6.5B2Iꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ
IS61VF51218A-6.5B3Iꢀ  
165ꢀPBGA  
512Kx18ꢀ  
ꢀ ꢀ  
7.5ꢀ  
ꢀ
IS61VF51218A-7.5TQIꢀ  
IS61VF51218A-7.5B2Iꢀ  
100ꢀTQFP,ꢀ3CE  
119ꢀPBGA  
ꢀ ꢀ  
ꢀ
IS61VF51218A-7.5B3Iꢀ  
165ꢀPBGA  
Note:  
1.ꢀꢀForꢀ100ꢀTQFP,ꢀ2CEꢀoptionꢀcontactꢀSRAMꢀMarketingꢀatꢀsram@issi.com  
Integrated Silicon Solution, Inc.  
29  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
30  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
Integrated Silicon Solution, Inc.ꢀ  
31  
Rev. F  
07/22/09  
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A  
32  
Integrated Silicon Solution, Inc.  
Rev. F  
07/22/09  

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