IS61LPS25618A-250TQI [ISSI]
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM; 128K ×32 ， 128K ×36 ， 256K ×18 4 Mb的同步PIPELINED ，单曲循环DESELECT静态RAM
| 型号： | IS61LPS25618A-250TQI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 文件： | 总26页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
FEBRUARY 2005
DESCRIPTION
FEATURES
The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A
andIS61(64)LPS/VPS25618Aarehigh-speed,low-power
synchronous static RAMs designed to provide burstable,
high-performancememoryforcommunicationandnetwork-
ingapplications.TheIS61(64)LPS12832Aisorganizedas
131,072wordsby32bits.TheIS61(64)LPS/VPS12836A
isorganizedas131,072wordsby36bits.TheIS61(64)LPS/
VPS25618A is organized as 262,144 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology, the
deviceintegratesa2-bitburstcounter,high-speedSRAM
core,andhigh-drivecapabilityoutputsintoasinglemono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
Write cycles are internally self-timed and are initiated by
therisingedgeoftheclockinput. Writecyclescanbeone
tofourbyteswideascontrolledbythewritecontrolinputs.
• Snooze MODE for reduced-power standby
• Power Supply
Separatebyteenablesallowindividualbytestobewritten.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, and
165-ball PBGA packages
• Automotive temperature available
• Lead Free available
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
inputpins.Subsequentburstaddressescanbegenerated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
250
2.6
4
200
3.1
5
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
250
200
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
1
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
BLOCK DIAGRAM
MODE
Q0
A0'
A1'
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
ADV
A1
128Kx32;
128Kx36;
ADSC
ADSP
CLR
256Kx18
MEMORY ARRAY
17/18
15/16
17/18
D
Q
A
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
DQ(a-d)
BYTE WRITE
REGISTERS
BW(a-d)
x18: a,b
x32/x36: a-d
CLK
32, 36,
or 18
CE
CE2
CE2
2/4/8
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DQa - DQd
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
165-PIN BGA
119-PIN BGA
119-Ball, 14x22 mm BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 7x17 Ball Array
1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
3
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
119 BGA PACKAGE PIN CONFIGURATION
128K X 36 (TOP VIEW)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
CE2
A
A
A
CE2
A
NC
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CE
OE
G
H
J
ADV
GW
VDD
CLK
NC
K
L
Vss
BWd
Vss
Vss
Vss
MODE
A
M
N
P
R
T
BWE
A1*
A0*
VDD
A
NC
NC
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
OE
Pin Name
Address Inputs
Output Enable
PowerSleepMode
A0, A1
ADV
Synchronous Burst Address Inputs
ZZ
Synchronous Burst Address
Advance
MODE
NC
Burst Sequence Selection
NoConnect
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
GlobalWriteEnable
DQa-DQd
DQPa-Pd
VDD
Data Inputs/Outputs
Output Power Supply
Power Supply
CLK
SynchronousClock
VDDQ
Output Power Supply
CE, CE2, CE2 Synchronous Chip Select
Vss
Ground
BWx (x=a-d)
Synchronous Byte Write Controls
Byte Write Enable
BWE
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
119 BGA PACKAGE PIN CONFIGURATION
256KX18 (TOP VIEW)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
VDDQ
NC
A
B
C
D
E
F
VDDQ
NC
CE2
A
A
A
CE2
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CE
DQa
VDDQ
DQa
NC
VDDQ
NC
OE
G
H
J
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDDQ
DQa
NC
K
L
Vss
Vss
Vss
Vss
Vss
MODE
A
DQb
VDDQ
DQb
NC
M
N
P
R
T
BWE
A1*
VDDQ
NC
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
OE
Pin Name
Symbol
A
Pin Name
Address Inputs
OutputEnable
PowerSleepMode
A0, A1
ADV
Synchronous Burst Address Inputs
ZZ
Synchronous Burst Address
Advance
MODE
NC
Burst Sequence Selection
NoConnect
ADSP
Address Status Processor
Address Status Controller
GlobalWriteEnable
DQa-DQb
DQPa-Pb
VDD
DataInputs/Outputs
Output Power Supply
PowerSupply
ADSC
GW
CLK
SynchronousClock
VDDQ
Output Power Supply
CE, CE2, CE2
BWx (x=a,b)
BWE
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Vss
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
5
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
165 PBGA PACKAGE PIN CONFIGURATION
128K X 36 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWc
BWd
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A1*
A0*
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
NC
NC
A
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
DQPc
DQc
DQc
DQc
DQc
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
DQPd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
NC
K
L
M
N
P
R
MODE
A
A
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
Pin Name
Address Inputs
BWE
Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
OE
OutputEnable
Synchronous Burst Address
Advance
ZZ
PowerSleepMode
Burst Sequence Selection
NoConnect
MODE
NC
ADSP
Address Status Processor
Address Status Controller
GlobalWriteEnable
ADSC
DQx
DQPx
VDD
DataInputs/Outputs
DataInputs/Outputs
3.3V/2.5V Power Supply
GW
CLK
SynchronousClock
CE, CE2, CE2
Synchronous Chip Select
VDDQ
Isolated Output Power Supply
3.3V/2.5V
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
Vss
Ground
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
165 PBGA PACKAGE PIN CONFIGURATION
256K X 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWb
NC
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A1*
A0*
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
ADSC
OE
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
A
NC
A
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
NC
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
NC
A
K
L
M
N
P
R
MODE
A
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
Pin Name
Address Inputs
BWE
Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
OE
OutputEnable
Synchronous Burst Address
Advance
ZZ
PowerSleepMode
MODE
NC
Burst Sequence Selection
NoConnect
ADSP
Address Status Processor
Address Status Controller
GlobalWriteEnable
ADSC
DQx
DQPx
VDD
DataInputs/Outputs
DataInputs/Outputs
3.3V/2.5V Power Supply
GW
CLK
SynchronousClock
CE, CE2, CE2
BWx (x=a,b)
Synchronous Chip Select
VDDQ
Isolated Output Power Supply
3.3V/2.5V
Synchronous Byte Write
Controls
Vss
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
7
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
PIN CONFIGURATION
100-PIN TQFP (128K X 36)
100-PIN TQFP (128K X 32)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
NC
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
NC
VDD
NC
VDD
ZZ
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable option)
(3 Chip-Enable option)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQa-DQd
DQPa-DQPd
GW
Synchronous Data Input/Output
Parity Data Input/Output
SynchronousGlobalWriteEnable
Burst Sequence Mode Selection
OutputEnable
A
Synchronous Address Inputs
MODE
OE
ADSC
Synchronous Controller Address
Status
ADSP
Synchronous Processor Address
Status
VDD
3.3V/2.5V Power Supply
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
BWa-BWd
BWE
Vss
ZZ
Ground
Snooze Enable
CE, CE2, CE2 SynchronousChipEnable
CLK SynchronousClock
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
PIN CONFIGURATION
100-PIN TQFP (256K X 18)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VDD
ZZ
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQPa-DQPb Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GW
Synchronous Global Write Enable
Burst Sequence Mode Selection
OutputEnable
A
Synchronous Address Inputs
MODE
OE
ADSC
ADSP
ADV
SynchronousControllerAddressStatus
SynchronousProcessorAddressStatus
SynchronousBurstAddressAdvance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
VDD
3.3V/2.5V Power Supply
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
BWa-BWb
BWE
Vss
ZZ
Ground
CE, CE2, CE2 Synchronous Chip Enable
Snooze Enable
CLK
Synchronous Clock
DQa-DQb
SynchronousDataInput/Output
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
9
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
TRUTH TABLE(1-8)
OPERATION
ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE
CLK
L-H
L-H
L-H
L-H
L-H
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
High-Z
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
Write Cycle, Suspend Burst
L
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are
available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
inputdataholdtime.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Read
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
°C
W
TSTG
PD
Storage Temperature
Power Dissipation
–55 to +150
1.6
IOUT
Output Current (per I/O)
100
mA
V
VIN, VOUT Voltage Relative to Vss for I/O Pins
–0.5 to VDDQ + 0.5
–0.5 to VDD + 0.5
VIN
Voltage Relative to Vss for
V
for Address and Control Inputs
VDD
Voltage on VDD Supply Relative to Vss
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceat
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periodsmayaffectreliability.
2. Thisdevicecontainscircuitytoprotecttheinputsagainstdamageduetohighstaticvoltagesor
electricfields;however,precautionsmaybetakentoavoidapplicationofanyvoltagehigherthan
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
11
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
OPERATING RANGE (IS61/64LPSXXXXX)
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V + 5%
3.3V / 2.5V + 5%
Industrial
–40°Cto+85°C
–40°Cto+125°C
3.3V + 5%
3.3V + 5%
3.3V / 2.5V + 5%
3.3V / 2.5V + 5%
Automotive
OPERATING RANGE (IS61/64VPSXXXXX)
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
2.5V + 5%
2.5V + 5%
Industrial
–40°Cto+85°C
–40°Cto+125°C
2.5V + 5%
2.5V + 5%
2.5V + 5%
2.5V + 5%
Automotive
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
2.5V
Max.
Symbol Parameter
Test Conditions
Min.
Max.
Min.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
2.0
-0.3
-5
VDD + 0.3
1.7 VDD + 0.3
V
V
0.8
5
-0.3
-5
0.7
5
(1)
Vss ≤ VIN ≤ VDD
µA
µA
ILO
Output Leakage Current Vss ≤ VOUT ≤ VDDQ,
OE = VIH
-5
5
-5
5
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250
-200
MAX
MAX
Symbol Parameter
Test Conditions
Temp.range
x18
x32/x36
x18
x32/x36
Unit
ICC
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or
≥ VDD – 0.2V,
Com.
Ind.
Auto.
225
250
275
225
250
275
200
210
225
200
210
225
mA
Cycle Time ≥ tKC min.
ISB
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
Auto.
90
100
120
90
100
120
90
100
120
90
100
120
mA
mA
ISBI
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
70
75
90
70
75
90
70
75
90
70
75
90
VIN
≤
VSS + 0.2V or
Auto.
≥VDD – 0.2V
typ.(2)
40
40
25
f = 0
ISB2
Sleep Mode
ZZ>VIH
Com.
Ind.
30
35
45
30
35
45
30
35
45
30
35
45
mA
Auto.
typ.(2)
25
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
13
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
Z
O
= 50Ω
OUTPUT
Output
50Ω
351 Ω
5 pF
Including
jig and
1.5V
scope
Figure 1
Figure 2
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
2.5V
Z
O
= 50Ω
OUTPUT
Output
50Ω
1,538 Ω
5 pF
Including
jig and
scope
1.25V
Figure 3
Figure 4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
15
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-250
-200
Min.
Symbol
fMAX
tKC
Parameter
Min.
Max.
250
Max.
200
—
Unit
MHz
ns
ClockFrequency
—
—
5
Cycle Time
4.0
1.7
1.7
—
—
—
—
2.6
—
—
2.6
2.8
—
2.6
—
—
—
—
—
—
—
—
—
—
2
tKH
Clock High Time
2
—
ns
tKL
Clock Low Time
2
—
ns
tKQ
Clock Access Time
—
3.1
—
ns
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup Time
0.8
0.8
—
1.5
1
ns
(2,3)
tKQLZ
tKQHZ
tOEQ
—
ns
(2,3)
—
3.0
3.1
—
ns
—
—
ns
(2,3)
tOELZ
0
0
ns
(2,3)
tOEHZ
tAS
—
—
3.0
—
ns
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
—
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
—
ns
tWS
—
ns
tCES
tAVS
tDS
—
ns
—
ns
—
ns
tAH
Address Hold Time
—
ns
tWH
Write Hold Time
—
ns
tCEH
tAVH
tDH
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
—
ns
—
ns
—
ns
tPDS
tPUS
Note:
ZZ High to Power Down
ZZ Low to Power Down
2
cyc
cyc
—
2
—
2
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
BWx
WH
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
17
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Unselected
Single Write
Write
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
ISB2
Parameter
Conditions
Min.
—
—
2
Max.
60
2
Unit
mA
CurrentduringSNOOZEMODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
ZZ ≥ Vih
tPDS
cycle
cycle
cycle
ns
tPUS
—
2
tZZI
—
0
tRZZI
—
SNOOZE MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
19
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration
128Kx32
Frequency
OrderPartNumber
Package
250
IS61LPS12832A-250TQ
IS61LPS12832A-250B2
100 TQFP
119 PBGA
IS61LPS12832A-250B3
165 PBGA
200
IS61LPS12832A-200TQ
IS61LPS12832A-200B2
IS61LPS12832A-200B3
100 TQFP
119 PBGA
165 PBGA
128Kx36
250
200
IS61LPS12836A-250TQ
IS61LPS12836A-250B2
100 TQFP
119 PBGA
IS61LPS12836A-250B3
165 PBGA
IS61LPS12836A-200TQ
IS61LPS12836A-200B2
IS61LPS12836A-200B3
100 TQFP
119 PBGA
165 PBGA
256Kx18
250
200
IS61LPS25618A-250TQ
IS61LPS25618A-250B2
100 TQFP
119 PBGA
IS61LPS25618A-250B3
165 PBGA
IS61LPS25618A-200TQ
IS61LPS25618A-200B2
IS61LPS25618A-200B3
100 TQFP
119 PBGA
165 PBGA
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Industrial Range: -40°C to +85°C
Configuration
128Kx32
Frequency
OrderPartNumber
Package
250
IS61LPS12832A-250TQI
IS61LPS12832A-250B2I
100 TQFP
119 PBGA
IS61LPS12832A-250B3I
165 PBGA
200
IS61LPS12832A-200TQI
IS61LPS12832A-200TQLI
IS61LPS12832A-200B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61LPS12832A-200B3I
165 PBGA
128Kx36
250
200
IS61LPS12836A-250TQI
IS61LPS12836A-250B2I
100 TQFP
119 PBGA
IS61LPS12836A-250B3I
165 PBGA
IS61LPS12836A-200TQI
IS61LPS12836A-200TQLI
IS61LPS12836A-200B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61LPS12836A-200B3I
165 PBGA
256Kx18
250
200
IS61LPS25618A-250TQI
IS61LPS25618A-250B2I
100 TQFP
119 PBGA
IS61LPS25618A-250B3I
165 PBGA
IS61LPS25618A-200TQI
IS61LPS25618A-200TQLI
IS61LPS25618A-200B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61LPS25618A-200B3I
165 PBGA
Automotive Range: -40°C to +125°C
Configuration
128Kx32
Frequency
OrderPartNumber
Package
200
IS64LPS12832A-200TQA3
IS64LPS12836A-200TQA3
IS64LPS25618A-200TQA3
100 TQFP
100 TQFP
100 TQFP
128Kx36
256Kx18
200
200
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
21
10/07/04
IS61(64)LPS12832A
®
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration
128Kx36
Frequency
OrderPartNumber
Package
250
IS61VPS12836A-250TQ
IS61VPS12836A-250B2
100 TQFP
119 PBGA
IS61VPS12836A-250B3
165 PBGA
200
IS61VPS12836A-200TQ
IS61VPS12836A-200B2
100 TQFP
119 PBGA
IS61VPS12836A-200B3
165 PBGA
256Kx18
250
200
IS61VPS25618A-250TQ
IS61VPS25618A-250B2
100 TQFP
119 PBGA
IS61VPS25618A-250B3
165 PBGA
IS61VPS25618A-200TQ
IS61VPS25618A-200B2
100 TQFP
119 PBGA
IS61VPS25618A-200B3
165 PBGA
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
Industrial Range: -40°C to +85°C
Configuration
128Kx36
Frequency
Order Part Number
Package
250
IS61VPS12836A-250TQI
IS61VPS12836A-250B2I
100 TQFP
119 PBGA
IS61VPS12836A-250B3I
165 PBGA
200
IS61VPS12836A-200TQI
IS61VPS12836A-200B2I
100 TQFP
119 PBGA
IS61VPS12836A-200B3I
165 PBGA
256Kx18
250
200
IS61VPS25618A-250TQI
IS61VPS25618A-250B2I
100 TQFP
119 PBGA
IS61VPS25618A-250B3I
165 PBGA
IS61VPS25618A-200TQI
IS61VPS25618A-200B2I
100 TQFP
119 PBGA
IS61VPS25618A-200B3I
165 PBGA
Automotive Range: -40°C to +125°C
Configuration
128Kx32
Frequency
OrderPartNumber
Package
200
IS64VPS12832A-200TQA3
IS64VPS12836A-200TQA3
IS64VPS25618A-200TQA3
100 TQFP
100 TQFP
100 TQFP
128Kx36
256Kx18
200
200
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
23
10/07/04
®
PACKAGING INFORMATION
ISSI
Plastic Ball Grid Array
Package Code: B (119-pin)
φ
b (119X)
E
A
7
6
5
4
3
2
1
A
B
C
D
E
F
30ϒ
G
H
J
D
D2
D1
K
L
M
N
P
R
T
e
U
A2
E1
A1
A3
E2
SEATING PLANE
A4
MILLIMETERS
INCHES
Min.
Sym. Min.
Max.
Max.
N0.
Leads
Notes:
119
1.Controllingdimension:millimeters,unlessotherwisespecified.
2.BSC=Basicleadspacingbetweencenters.
3.DimensionsD1andEdonotincludemoldflashprotrusionand
shouldbemeasuredfromthebottomofthepackage.
4.Formedleadsshallbeplanarwithrespecttooneanotherwithin
0.004inchesattheseatingplane.
A
—
2.41
0.70
1.00
1.70
—
0.095
0.028
0.039
0.067
A1
A2
A3
A4
b
0.50
0.80
1.30
0.020
0.032
0.051
0.56 BSC
0.022 BSC
0.60
0.90
0.024
0.858
0.035
0.874
D
21.80
22.20
D1
D2
E
20.32 BSC
0.800 BSC
19.40
13.80
19.60
14.20
0.764
0.543
0.772
0.559
E1
E2
e
7.62 BSC
0.300 BSC
11.90
12.10
0.469
0.476
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
02/12/03
®
PACKAGING INFORMATION
Ball Grid Array
ISSI
Package Code: B (165-pin)
BOTTOM VIEW
A1 CORNER
TOP VIEW
A1 CORNER
φ b (165X)
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D
D1
K
L
K
L
M
N
P
R
M
N
P
R
e
E1
E
A2
A
A1
BGA - 13mm x 15mm
Notes:
MILLIMETERS
INCHES
1. Controlling dimensions are in millimeters.
Sym. Min. Nom. Max.
Min. Nom. Max.
165
N0.
Leads
165
A
—
0.25
—
—
1.20
0.40
—
—
—
0.047
0.010 0.013 0.016
0.031
A1
A2
D
0.33
0.79
—
—
14.90 15.00 15.10
13.90 14.00 14.10
12.90 13.00 13.10
9.90 10.00 10.10
0.587 0.591 0.594
0.547 0.551 0.555
0.508 0.512 0.516
0.390 0.394 0.398
D1
E
E1
e
—
1.00
0.45
—
—
0.039
—
b
0.40
0.50
0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03
®
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
Inches Millimeters
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
Millimeters
Min Max
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
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