IS61LV25616AL-12TI-TR [ISSI]
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44,;
| 型号： | IS61LV25616AL-12TI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LV25616AL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
DECEMBER 2011
DESCRIPTION
FEATURES
TheꢀISSIꢀIS61LV25616ALꢀisꢀaꢀhigh-speed,ꢀ4,194,304-bitꢀ
staticꢀRAMꢀorganizedꢀasꢀ262,144ꢀwordsꢀbyꢀ16ꢀbits.ꢀItꢀisꢀ
fabricatedꢀusingꢀISSI'sꢀhigh-performanceꢀCMOSꢀtechnol-
ogy.ꢀThisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀinnovativeꢀ
circuitꢀdesignꢀtechniques,ꢀyieldsꢀhigh-performanceꢀandꢀlowꢀ
powerꢀconsumptionꢀdevices.
•ꢀ High-speedꢀaccessꢀtime:ꢀ
—ꢀ10,ꢀ12ꢀnsꢀ
•ꢀ CMOSꢀlowꢀpowerꢀoperation
•ꢀ Lowꢀstand-byꢀpower:ꢀ
—ꢀꢀLessꢀthanꢀ5ꢀmAꢀ(typ.)ꢀCMOSꢀstand-by
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels
•ꢀ Singleꢀ3.3Vꢀpowerꢀsupply
WhenꢀCEꢀisꢀHIGHꢀ(deselected),ꢀtheꢀdeviceꢀassumesꢀaꢀ
standbyꢀmodeꢀatꢀwhichꢀtheꢀpowerꢀdissipationꢀcanꢀbeꢀre-
ducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀꢀ
required
EasyꢀmemoryꢀexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ
andꢀOutputꢀEnableꢀinputs,ꢀCEꢀandꢀOE.ꢀTheꢀactiveꢀLOWꢀ
WriteꢀEnableꢀ(WE)ꢀcontrolsꢀbothꢀwritingꢀandꢀreadingꢀofꢀtheꢀ
memory.ꢀꢀAꢀdataꢀbyteꢀallowsꢀUpperꢀByteꢀ(UB)ꢀandꢀLowerꢀ
Byteꢀ(LB)ꢀaccess.
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes
•ꢀ Industrialꢀtemperatureꢀavailable
•ꢀ Lead-freeꢀavailable
TheꢀIS61LV25616ALꢀisꢀpackagedꢀinꢀtheꢀJEDECꢀstandardꢀ
44-pinꢀ400-milꢀSOJ,ꢀ44-pinꢀTSOPꢀTypeꢀII,ꢀ44-pinꢀLQFPꢀ
andꢀ48-pinꢀMiniꢀBGAꢀ(8mmꢀxꢀ10mm).
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstancesꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
1
Rev. F
12/15/2011
IS61LV25616AL
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LBꢀ
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Isb1, Isb2
Iccꢀ
NotꢀSelectedꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
High-Zꢀ
High-Zꢀ
OutputꢀDisabledꢀ
ꢀ
Hꢀ
Xꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Z
ꢀ
ꢀ
ꢀ
Readꢀ
ꢀ
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
Doutꢀ
High-Zꢀ
Dout
High-Z
Dout
Dout
Iccꢀ
Iccꢀ
ꢀ
ꢀ
Writeꢀ
ꢀ
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Xꢀ
Xꢀ
X
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
DInꢀ
High-Zꢀ
DIn
High-Z
DIn
DIn
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
PIN DESCRIPTIONS
A0-A17ꢀ
I/O0-I/O15ꢀ
CEꢀꢀ
AddressꢀInputs
DataꢀInputs/Outputs
ChipꢀEnableꢀInput
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
OEꢀꢀ
A0
A1
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
WEꢀꢀ
A2
3
LBꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
NoꢀConnection
A3
4
UBꢀ
A4
5
CE
6
NCꢀ
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
8
9
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
VDDꢀ
Power
GNDꢀ
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
A6
A7
A8
A9
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
PIN CONFIGURATIONS
44-Pin LQFP
48-Pin mini BGA
1
2
3
4
5
6
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
A0
A3
A1
A4
A2
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
CE
I/O
0
8
I/O
I/O
I/O
A5
A6
I/O
I/O
I/O
2
9
10
1
TOP VIEW
GND
A7
A17
NC
A14
A12
VDD
11
3
4
5
I/O
I/O
GND
V
DD
I/O
I/O
A16
A15
A13
A10
12
I/O
I/O
I/O
6
14
13
9
NC
A8
WE
I/O
7
15
G
H
10
11
I/O8
NC
NC
A9
A11
NC
12 13 14 15 16 17 18 19 20 21 22
PIN DESCRIPTIONS
A0-A17ꢀ
I/O0-I/O15ꢀ
CEꢀꢀ
AddressꢀInputs
DataꢀInputs/Outputs
ChipꢀEnableꢀInput
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
OEꢀꢀ
WEꢀꢀ
LBꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
NoꢀConnection
UBꢀ
NCꢀ
VDDꢀ
Power
GNDꢀ
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
3
Rev. F
12/15/2011
IS61LV25616AL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
Vterm
ꢀ tstg
ꢀ Pt
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ –0.5ꢀtoꢀVDD+0.5ꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
°C
W
Note:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀ
permanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀ
ofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀ
sectionsꢀ ofꢀ thisꢀ specificationꢀ isꢀ notꢀ implied.ꢀ Exposureꢀ toꢀ absoluteꢀ maximumꢀ ratingꢀ
conditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.ꢀ
OPERATING RANGE
VDD
Range
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
10ns
12ns
Commercialꢀ
Industrialꢀ
3.3Vꢀ+10%,ꢀ-5%ꢀ
3.3Vꢀ+10%,ꢀ-5%ꢀ
3.3Vꢀ+ꢀ10%ꢀ
3.3Vꢀ+ꢀ10%ꢀ
–40°Cꢀtoꢀ+85°Cꢀ
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Min.
Max.
—ꢀ
Unit
V
VoH
ꢀ VoL
ꢀ VIH
ꢀ VIL
ꢀ ILI
OutputꢀHIGHꢀVoltageꢀ
VDD = Min.,ꢀIoH = –4.0ꢀmAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2.4ꢀ
—ꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
VDD = Min.,ꢀIoL = 8.0ꢀmAꢀ
0.4ꢀ
V
ꢀ
ꢀ
2.0ꢀ
–0.3ꢀ
VDD + 0.3
0.8ꢀ
V
V
ꢀ
InputꢀLeakageꢀ
ꢀ
GNDꢀ≤ꢀVIn ≤ VDD
ꢀ
Com.ꢀꢀꢀ
Ind.ꢀ
–2ꢀ
–5ꢀ
2ꢀ
5ꢀ
µAꢀ
ꢀ
ꢀ
ꢀ ILo
OutputꢀLeakageꢀ
ꢀ
GNDꢀ≤ꢀVout ≤ VDDꢀ
OutputsꢀDisabledꢀ
Com.ꢀ
Ind.ꢀ
–2ꢀ
–5ꢀ
2ꢀ
5ꢀ
µAꢀ
ꢀ
ꢀ
Notes:
1.ꢀ VIL (min.)ꢀ= –2.0Vꢀforꢀpulseꢀwidthꢀlessꢀthanꢀ10ꢀns.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-10
-12
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
ꢀ Icc
ꢀ ꢀ
VDDꢀDynamicꢀOperatingꢀ
SupplyꢀCurrentꢀ
VDD = Max.,ꢀꢀ
Iout = 0 mA,ꢀfꢀ=ꢀfmaX
Com.ꢀ
Ind.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ 100ꢀ
—ꢀ 110ꢀ
—ꢀ
—ꢀ 100ꢀ
90ꢀ
mA
ꢀ Isb
ꢀ ꢀ
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
VDD = Max.,ꢀ
VIn = VIH orꢀVIL
CEꢀ≥ꢀVIH,ꢀfꢀ=ꢀꢀfmaX.ꢀ
Com.
Ind.ꢀ
—
—ꢀ
50
55ꢀ
—
—ꢀ
45
50ꢀ
mA
mA
mA
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ Isb1
ꢀ ꢀ
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
VDD = Max.,ꢀ
VIn = VIH orꢀVIL
CEꢀ≥ꢀVIH,ꢀfꢀ=ꢀ0ꢀ
Com.
Ind.ꢀ
—
—ꢀ
20
25ꢀ
—
—ꢀ
20
25ꢀ
ꢀ Isb2ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ
VDD = Max.,ꢀ
Com.
Ind.
—
—
15
20
—
—
15
20
CEꢀ≥ꢀVDD – 0.2V,
VIn ≥ VDD – 0.2V, or
VIn ≤ 0.2V, fꢀ=ꢀ0
ꢀ ꢀ
ꢀ
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmaX,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
Shadedꢀareaꢀproductꢀinꢀdevelopment
CAPACITANCE(1)
Symbol
Parameter
Conditions
VIn = 0V
Max.
6ꢀ
Unit
pF
cIn
InputꢀCapacitanceꢀ
Input/OutputꢀCapacitanceꢀ
ꢀ coutꢀ
Vout = 0V
8ꢀ
pF
Note:
1.ꢀ Testedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
5
Rev. F
12/15/2011
IS61LV25616AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-10
-12
Symbol
ꢀ ꢀ trc
ꢀ ꢀ taa
ꢀ ꢀ toHa
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ꢀ
ReadꢀCycleꢀTimeꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
CEꢀAccessꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
—ꢀ
2ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
0ꢀ
3ꢀ
—ꢀ
0ꢀ
0ꢀ
—ꢀ
10ꢀ
—ꢀ
10ꢀ
4ꢀ
4ꢀ
—ꢀ
4ꢀ
—ꢀ
4ꢀ
3ꢀ
—ꢀ
—ꢀ
10ꢀ
12ꢀ
—ꢀ
2ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
0ꢀ
3ꢀ
—ꢀ
0ꢀ
0ꢀ
—ꢀ
12ꢀ
—ꢀ
12ꢀ
5ꢀ
5ꢀ
—ꢀ
6ꢀ
—ꢀ
5ꢀ
4ꢀ
—ꢀ
—ꢀ
12ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ tace
ꢀ
ꢀ ꢀ tDoe
OEꢀAccessꢀTimeꢀ
ꢀ ꢀ tHzoe(2)ꢀ
ꢀ ꢀ tLzoe(2)ꢀ
ꢀ ꢀ tHzce(2ꢀ
ꢀ ꢀ tLzce(2)ꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CEꢀtoꢀHigh-ZꢀOutputꢀ
CEꢀtoꢀLow-ZꢀOutputꢀ
LB,ꢀUBꢀAccessꢀTimeꢀ
LB,ꢀUBꢀtoꢀHigh-ZꢀOutputꢀ
LB,ꢀUBꢀtoꢀLow-ZꢀOutputꢀ
PowerꢀUpꢀTimeꢀ
ꢀ ꢀ tba
ꢀ
ꢀ ꢀ tHzb(2)ꢀ
ꢀ ꢀ tLzb(2)ꢀ
ꢀ ꢀ tPu
ꢀ ꢀ tPD
ꢀ
ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
PowerꢀDownꢀTimeꢀ
Notes:ꢀ
ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ3ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ
0Vꢀtoꢀ3.0VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
5 pF
Including
jig and
353 Ω
30 pF
Including
jig and
scope
scope
Figure 1
Figure 2
AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ3.0V
3ꢀns
ꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀandꢀReferenceꢀLevelꢀ
OutputꢀLoadꢀ
1.5V
SeeꢀFiguresꢀ1ꢀandꢀ2
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
AC WAVEFORMS
READ CYCLE NO. 1(1,2)ꢀ(AddressꢀControlled)ꢀ(CEꢀ=ꢀOEꢀ=ꢀVIL, UB orꢀLB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
tHZOE
t
DOE
LZOE
ACE
t
CE
t
tHZCE
tLZCE
LB, UB
t
BA
t
HZB
tRC
tLZB
HIGH-Z
DOUT
DATA VALID
I
CC
V
DD
Supply
Current
50%
50%
t
PD
tPU
I
SB
UB_CEDR2.eps
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCE,ꢀUB,ꢀorꢀLBꢀ=ꢀVIL.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCEꢀLOWꢀtransition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
7
Rev. F
12/15/2011
IS61LV25616AL
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
tHZCE
tLZCE
LB, UB
t
BA
t
HZB
t
RC
tLZB
HIGH-Z
DOUT
DATA VALID
I
CC
SB
V
DD
Supply
Current
50%
50%
t
PD
tPU
I
UB_CEDR2.eps
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCE,ꢀUB,ꢀorꢀLBꢀ=ꢀVIL.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCEꢀLOWꢀtransition.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (OverꢀOperatingꢀRange)
-10
-12
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
nꢀ s
ns
ns
ꢀ ꢀ twc
ꢀ
WriteꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ —ꢀ
12ꢀ —ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ tsce
CEꢀtoꢀWriteꢀEndꢀ
8ꢀ
8ꢀ
0ꢀ
0ꢀ
8ꢀ
8ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
8ꢀ
8ꢀ
0ꢀ
0ꢀ
8ꢀ
8ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ ꢀ taw
ꢀ ꢀ tHa
ꢀ ꢀ tsa
ꢀ ꢀ tPwb
ꢀ
AddressꢀSetupꢀTimeꢀtoꢀWriteꢀEndꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
LB,ꢀUBꢀValidꢀtoꢀEndꢀofꢀWriteꢀ
WEꢀPulseꢀWidthꢀ
ꢀ ꢀ tPwe1ꢀ
ꢀ ꢀ tPwe2ꢀ
WEꢀPulseꢀWidthꢀꢀ(OEꢀ=ꢀLOW)ꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
10ꢀ —ꢀ
12ꢀ —ꢀ
ꢀ ꢀ tsD
ꢀ
6ꢀ
0ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
0ꢀ
—ꢀ
—ꢀ
6ꢀ
ꢀ ꢀ tHD
ꢀ
ꢀ ꢀ tHzwe(2)ꢀ
ꢀ ꢀ tLzwe(2)ꢀ
Notes:ꢀ
—ꢀ
2ꢀ
—ꢀ
2ꢀ
—ꢀ
—ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ3ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0Vꢀ
toꢀ3.0VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀUBꢀorꢀLBꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀ
statesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀ
areꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
AC WAVEFORMS
WRITE CYCLE NO. 1ꢀ(CEꢀControlled,ꢀOEꢀisꢀHIGHꢀorꢀLOW)ꢀ(1ꢀ)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPWE12
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
Notes:ꢀ
1.ꢀ WRITEꢀisꢀanꢀinternallyꢀgeneratedꢀsignalꢀassertedꢀduringꢀanꢀoverlapꢀofꢀtheꢀLOWꢀstatesꢀonꢀtheꢀCEꢀandꢀWEꢀinputsꢀandꢀatꢀleastꢀ
oneꢀofꢀtheꢀLBꢀandꢀUBꢀinputsꢀbeingꢀinꢀtheꢀLOWꢀstate.
2.ꢀ WRITEꢀ=ꢀ(CE)ꢀ[ꢀ(LB)ꢀ=ꢀ(UB)ꢀ]ꢀ(WE).
WRITE CYCLE NO. 2ꢀ(WE Controlled.ꢀ OE isꢀHIGHꢀDuringꢀWriteꢀCycle)ꢀ(1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
UB, LB
DOUT
t
SA
t
PBW
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
9
Rev. F
12/15/2011
IS61LV25616AL
AC WAVEFORMS
WRITE CYCLE NO. 3ꢀ(WE Controlled.ꢀ OE isꢀLOWꢀDuringꢀWriteꢀCycle)ꢀ(1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
WRITE CYCLE NO. 4ꢀ(LB, UB Controlled,ꢀBack-to-BackꢀWrite)ꢀ(1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:ꢀ
1.ꢀ TheꢀꢀinternalꢀWriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀ=ꢀLow, UBꢀand/orꢀLBꢀ=ꢀLow,ꢀandꢀWEꢀ=ꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀ
validꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀcanꢀbeꢀdeassertedꢀtoꢀterminateꢀtheꢀWrite.ꢀTheꢀtsa,ꢀtHa, tsD,ꢀandꢀtHDꢀtimingꢀisꢀreferencedꢀ
toꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀWrite.
2.ꢀ TestedꢀwithꢀOEꢀHIGHꢀforꢀaꢀminimumꢀofꢀ4ꢀnsꢀbeforeꢀWEꢀ=ꢀLOWꢀtoꢀplaceꢀtheꢀI/OꢀinꢀaꢀHIGH-Zꢀstate.
3.ꢀ WEꢀmayꢀbeꢀheldꢀLOWꢀacrossꢀmanyꢀaddressꢀcyclesꢀandꢀtheꢀLB,ꢀUBꢀpinsꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀWriteꢀfunction.
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
DATA RETENTION SWITCHING CHARACTERISTICS (LL)
Symbol
ꢀ ꢀ VDrꢀ
Parameter
Test Condition
Options
Min.
2.0ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
10ꢀ
15
Unit
V
VDDꢀforꢀDataꢀRetentionꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
VDDꢀ=ꢀ2.0V,ꢀCEꢀ≥ꢀVDDꢀ–ꢀ0.2Vꢀ
ꢀ
ꢀ
ꢀ ꢀ IDrꢀ
ꢀ ꢀ ꢀ
DataꢀRetentionꢀCurrentꢀ
ꢀ
Com.ꢀ
5ꢀ
mA
Ind.ꢀ
—ꢀ
—ꢀ
ꢀ ꢀ tsDr
ꢀ ꢀ trDr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
ns
ns
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trcꢀ
—ꢀ
—ꢀ
o
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVDDꢀ=ꢀ3.0V,ꢀTa = 25 c andꢀnotꢀ100%ꢀtested.
DATA RETENTION WAVEFORM (CEꢀControlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
11
Rev. F
12/15/2011
IS61LV25616AL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
10ꢀ
ꢀ
ꢀ
IS61LV25616AL-10Tꢀ
IS61LV25616AL-10TLꢀ
IS61LV25616AL-10Kꢀ
TSOPꢀ(TypeꢀII)ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
400-milꢀSOJ
ꢀ
ꢀ
ꢀ
ꢀ
12ꢀ
IS61LV25616AL-12Tꢀ
TSOPꢀ(TypeꢀII)
ꢀ
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
10ꢀ
IS61LV25616AL-10TIꢀ
IS61LV25616AL-10TLIꢀ
IS61LV25616AL-10KIꢀ
IS61LV25616AL-10KLIꢀ
IS61LV25616AL-10LQIꢀꢀ
IS61LV25616AL-10LQLIꢀꢀ
IS61LV25616AL-10BIꢀ
IS61LV25616AL-10BLIꢀ
TSOPꢀ(TypeꢀII)ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
400-milꢀSOJꢀ
400-milꢀSOJ,ꢀLead-freeꢀ
LQFPꢀ
LQFP,ꢀLead-freeꢀ
MiniꢀBGAꢀ(8mmꢀxꢀ10mm)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MiniꢀBGAꢀ(8mmꢀxꢀ10mm),ꢀLead-free
ꢀ
12ꢀ
IS61LV25616AL-12TIꢀ
TSOPꢀ(TypeꢀII)
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
13
Rev. F
12/15/2011
IS61LV25616AL
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
15
Rev. F
12/15/2011
IS61LV25616AL
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
相关型号：
©2020 ICPDF网 联系我们和版权申明