IS61LV2568LL-15T [ISSI]
Standard SRAM, 256KX8, 15ns, CMOS, PDSO44, TSOP2-44;
| 型号： | IS61LV2568LL-15T |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 256KX8, 15ns, CMOS, PDSO44, TSOP2-44 静态存储器 光电二极管 |
| 文件： | 总11页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV2568L
IS61LV2568LL
ISSI
256K x 8 HIGH-SPEED CMOS STATIC RAM
PRELIMINARYINFORMATION
SEPTEMBER2002
FEATURES
• High-speed access time:
IS61LV2568L: 8, 10 ns
IS61LV2568LL: 12, 15 ns
• Operating Current:
• Packages available:
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)
– 36-ball mini BGA (6mm x 8mm)
IS61LV2568L: 50mA (typ.)
IS61LV2568LL: 25mA (typ.)
• Standby Current:
DESCRIPTION
The ISSI IS61LV2568L/IS61LV2568LL is a very high-
speed, low power, 262,144-word by 8-bit CMOS static
RAM. The IS61LV2568L/IS61LV2568LL is fabricated us-
ingISSI'shigh-performanceCMOStechnology.Thishighly
reliable process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
IS61LV2568L: 500µA (typ.)
IS61LV2568LL: 250µA(typ.)
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
options
• CE power-down
• TTL compatible inputs and outputs
• Single 3.3V power supply
The S61LV2568L/IS61LV2568LL operates from a single
3.3V power supply and all inputs are TTL-compatible.
TheS61LV2568L/IS61LV2568LL isavailablein36-pin400-
milSOJ,44-pinTSOP(TypeII),and36-ballminiBGA(6mm
x 8mm) packages.
FUNCTIONAL BLOCK DIAGRAM
256K X 8
MEMORY ARRAY
A0-A17
DECODER
V
DD
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
1
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
PIN CONFIGURATION
36-Pin SOJ
44-Pin TSOP (Type II)
A4
A3
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A5
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A5
A6
A7
2
A2
3
A6
A1
4
A7
A0
5
A8
CE
I/O0
I/O1
6
OE
I/O7
I/O6
GND
A8
7
OE
I/O7
I/O6
GND
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD
9
VDD
GND
I/O2
I/O3
WE
10
11
12
13
14
15
16
17
18
VDD
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
VDD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
I/O5
I/O4
A9
A17
A16
A15
A14
A13
A10
A11
A12
NC
NC
NC
PIN DESCRIPTIONS
36 Ball mini BGA (6mm x 8mm)
A0-A17
CE
Address Inputs
1
2
3
4
5
6
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
OE
NC
WE
NC
A3
A4
A5
A6
WE
A0
A1
A2
A8
I/O
A
B
C
D
E
F
I/O4
I/O5
GND
A7
0
I/O0-I/O7
VDD
I/O
1
V
DD
GND
NC
Ground
GND
V
DD
I/O6
I/O7
A9
NC
CE
NoConnection
A17
A16
A12
I/O
2
OE
A15
A13
I/O
3
G
H
A10
A11
A14
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
TRUTH TABLE
Mode
WE
CE
OE
I/OOperation
VDD Current
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD
Parameter
Value
Unit
V
Supply voltage with Respect to GND
Terminal Voltage with Respect to GND
StorageTemperature
–0.5 to +4.0
–0.5 to VDD + 0.5
–65 to +150
1.0
VTERM
TSTG
PD
V
°C
W
PowerDissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
OPERATING RANGE
Range
AmbientTemperature
0°C to +70°C
VDD (8ns)
VDD (10 ns, 12 ns, 15 ns)
3.3V + 10%
Commercial
Industrial
3.3V +10%,-5%
3.3V +10%,-5%
–40°Cto+85°C
3.3V + 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
OutputLOWVoltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
InputLeakage
—
0.4
V
2.0
VDD + 0.3
0.8
V
–0.3
V
GND - VIN - VDD
Com.
Ind.
–1
–5
1
5
µA
ILO
OutputLeakage
GND - VOUT - VDD, Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Note:
1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns).
VIH(max) = VDD + 0.3V (DC); VIH(max) = VDD + 2.0V (pulse width - 2.0 ns).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
3
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV2568L
-8 ns
Min. Max.
-10 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
65
70
—
—
60
65
mA
ISB1
ISB2
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE • VIH, f = max
Com.
Ind.
—
—
30
35
—
—
25
30
mA
CMOS Standby
Current
(CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
3
4
—
—
3
4
mA
mA
CE - VDD – 0.2V,
VIN > VDD – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV2568LL
-12 ns
-15 ns
Symbol
Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
ICC
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
50
60
—
—
45
50
mA
ISB1
ISB2
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE • VIH, f = max
Com.
Ind.
—
—
15
20
—
—
15
20
mA
CMOS Standby
Current
(CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
200
300
—
—
200
300
µA
µA
CE - VDD – 0.2V,
VIN > VDD – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Levels
OutputLoad
1.5V
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 2
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
5
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
IS61LV2568L
- 8 ns
-10 ns
Min.
Symbol Parameter
Min.
Max
—
Max.
—
10
—
10
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
—
2.5
—
—
0
10
—
2.5
—
—
0
tAA
Address Access Time
Output Hold Time
8
tOHA
tACE
tDOE
tLZOE
—
CE Access Time
8
OE Access Time
3.5
—
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
—
4
tHZOE
0
3.5
—
0
(2)
tLZCE
tHZCE
3.5
0
3
—
4
(2)
3.5
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
IS61LV2568LL
- 12 ns
Min.
-15 ns
Min.
Symbol Parameter
Max
—
12
—
12
5
Max.
—
15
—
15
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
12
—
3
15
—
3
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
tDOE
tLZOE
—
—
0
—
—
0
OE Access Time
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
—
5
—
6
tHZOE
0
0
(2)
tLZCE
tHZCE
3
—
5
3
—
6
(2)
0
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
CE
t
HZOE
t
DOE
t
t
LZOE
ACE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
7
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
IS61LV2568L
- 8 ns
Min.
-10 ns
Min.
Symbol Parameter
Max
—
—
—
—
—
—
—
—
—
3
Max.
—
—
—
—
—
—
—
—
—
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
8
7
10
8
tSCE
tAW
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
7
8
tHA
0
0
tSA
0
0
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6
7
6.5
4
8
5
tHD
0
0
(3)
tHZWE
—
0
—
0
(3)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
IS61LV2568LL
- 12ns
Min.
-15 ns
Min.
Symbol Parameter
Max
—
—
—
—
—
—
—
—
—
5
Max.
—
—
—
—
—
—
—
—
—
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
12
8
15
10
10
0
tSCE
tAW
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
8
tHA
0
tSA
0
0
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
10
11
7
10
6
tHD
0
0
(3)
tHZWE
—
0
—
0
(3)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
PWE1
PWE2
t
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a
Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or
falling edge of the signal that terminates the Write.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
9
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
09/12/02
®
IS61LV2568L, IS61LV2568LL
ISSI
ORDERING INFORMATION
IS61LV2568L
Industrial Range: –40°C to +85°C
IS61LV2568L
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IS61LV2568L-8BI
IS61LV2568L-8KI
IS61LV2568L-8TI
mini BGA (6mm x 8mm)
400-mil SOJ
TSOP (Type II)
8
IS61LV2568L-8B
IS61LV2568L-8K
IS61LV2568L-8T
mini BGA (6mm x 8mm)
400-mil SOJ
TSOP (Type II)
10
IS61LV2568L-10BI
IS61LV2568L-10KI
IS61LV2568L-10TI
mini BGA (6mm x 8mm)
400-mil SOJ
TSOP (Type II)
10
IS61LV2568L-10B
IS61LV2568L-10K
IS61LV2568L-10T
mini BGA (6mm x 8mm)
400-mil SOJ
TSOP (Type II)
IS61LV2568LL
Commercial Range: 0°C to +70°C
IS61LV2568LL
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
12
IS61LV2568LL-12B mini BGA (6mm x 8mm)
IS61LV2568LL-12K 400-mil SOJ
IS61LV2568LL-12T TSOP (Type II)
12
IS61LV2568LL-12BI mini BGA (6mm x 8mm)
IS61LV2568LL-12KI 400-mil SOJ
IS61LV2568LL-12TI
TSOP (Type II)
15
IS61LV2568LL-15B mini BGA (6mm x 8mm)
IS61LV2568LL-15K 400-mil SOJ
IS61LV2568LL-15T TSOP (Type II)
15
IS61LV2568LL-15BI mini BGA (6mm x 8mm)
IS61LV2568LL-15KI 400-mil SOJ
IS61LV2568LL-15TI
TSOP (Type II)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00D
11
09/12/02
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