IS61LV5128-12BI [ISSI]
512K x 8 HIGH-SPEED CMOS STATIC RAM; 512K ×8高速CMOS静态RAM
| 型号： | IS61LV5128-12BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 512K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总9页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV5128
ISSI
512K x 8 HIGH-SPEED CMOS STATIC RAM
JULY 2001
FEATURES
DESCRIPTION
• High-speed access times:
10, 12 and 15 ns
The ISSI IS61LV5128 is a very high-speed, low power,
524,288-wordby8-bitCMOSstaticRAM.TheIS61LV5128
is fabricated using ISSI's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
options
• CE power-down
• Fully static operation: no clock or refresh
required
The IS61LV5128 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
• TTL compatible inputs and outputs
• Single 3.3V power supply
The IS61LV5128 is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.
• Packagesavailable:
– 36-pin 400-mil SOJ
– 36-pin miniBGA
– 44-pin TSOP (Type II)
FUNCTIONAL BLOCK DIAGRAM
512K X 8
MEMORY ARRAY
A0-A18
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
07/16/01
®
IS61LV5128
ISSI
PIN CONFIGURATION
36 mini BGA
44-Pin TSOP (Type II)
1
2
3
4
5
6
NC
NC
A0
A1
A2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
2
3
4
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
5
A3
A4
6
A
B
C
D
E
F
A0
I/O4
I/O5
GND
Vcc
I/O6
I/O7
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O0
I/O1
Vcc
7
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
I/O2
I/O3
A14
A18
CE
A17
A16
A12
OE
A15
A13
G
H
A10
A11
NC
NC
NC
NC
36-Pin SOJ
PIN DESCRIPTIONS
A0-A18
CE
Address Inputs
A0
A1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
2
A18
A17
A16
A15
OE
A2
3
OE
A3
4
WE
A4
5
CE
6
I/O0-I/O7
Vcc
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
7
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
8
GND
NC
Ground
9
10
11
12
13
14
15
16
17
18
No Connection
TRUTH TABLE
A6
A7
Mode
WE
CE OE I/O Operation Vcc Current
A8
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
A9
Output Disabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Read
Write
H
L
X
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
®
IS61LV5128
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
1.0
Unit
V
°C
°C
W
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceat
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periodsmayaffectreliability.
OPERATING RANGE
10 ns
12 ns, 15 ns
Range
Ambient Temperature
0°C to +70°C
VCC
VCC
Commercial
Industrial
3.3V +10%, -5%
3.3V +10%, -5%
3.3V 10%
3.3V 10%
–40°C to +85°C
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
Max.
Unit
Input Capacitance
VIN = 0V
6
8
pF
pF
CI/O
Input/Output Capacitance
VOUT = 0V
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
07/16/01
®
IS61LV5128
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.0
VCC + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled Com.
–1
–5
1
5
µA
Ind.
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10ns
Min.
-12ns
Min.
-15ns
Min.
Symbol Parameter
TestConditions
Max.
Max.
Max.
Unit
ICC
VccOperating
SupplyCurrent
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX.
Com.
Ind.
—
—
145
155
—
—
135
145
—
—
125
135
mA
ISB
TTL Standby
Current
(TTLInputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
Com.
Ind.
—
—
70
80
—
—
60
70
—
—
50
60
mA
ISB1
ISB2
TTL Standby
Current
(TTLInputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
—
—
20
25
mA
mA
CMOSStandby
Current
(CMOSInputs)
VCC = Max.,
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
CE
VIN ≥ VCC – 0.2V, or
VIN 0.2V, f = 0
≤ VCC – 0.2V,
≤
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
®
IS61LV5128
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns
Min.
-12 ns
Min.
-15 ns
Min. Max.
Symbol
tRC
Parameter
Max.
—
10
—
10
4
Max.
—
12
—
12
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
Power Up Time
10
—
3
12
—
3
15
—
3
—
15
—
15
7
tAA
tOHA
tACE
tDOE
—
—
0
—
—
0
—
—
0
(2)
tLZOE
—
4
—
5
—
6
(2)
tHZOE
0
0
0
(2)
tLZCE
3
—
4
3
—
6
3
—
8
(2)
tHZCE
0
0
0
tPU
tPD
0
—
10
0
—
12
0
—
15
Power Down Time
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
07/16/01
®
IS61LV5128
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
tRC
ADDRESS
tAA
tOHA
tOHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
D
OUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
®
IS61LV5128
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 ns
Min.
-12 ns
Min.
-15 ns
Min. Max.
Symbol
tWC
Parameter
Max.
—
Max.
—
Unit
ns
Write Cycle Time
CE to Write End
Address Setup Time to
10
8
12
9
15
10
10
—
—
—
tSCE
—
—
ns
tAW
8
—
9
—
ns
Write End
tHA
Address Hold from
0
—
0
—
0
—
ns
Write End
tSA
Address Setup Time
0
8
—
—
—
—
—
5
0
8
—
—
—
—
—
6
0
10
12
7
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
tPWE1(4)
tPWE2
tSD
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
10
6
12
6
tHD
0
0
0
(2)
tHZWE
0
0
0
(2)
tLZWE
0
—
0
—
0
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
07/16/01
®
IS61LV5128
ISSI
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
®
IS61LV5128
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
Speed (ns)
Order Part No.
Package
10
10
10
IS61LV5128-10K
IS61LV5128-10T
IS61LV5128-10B
400-milPlasticSOJ
TSOP (Type II)
miniBGA(8mmx10mm)
10
10
10
IS61LV5128-10KI
IS61LV5128-10TI
IS61LV5128-10BI
400-milPlasticSOJ
TSOP (Type II)
miniBGA(8mmx10mm)
12
12
12
IS61LV5128-12K
IS61LV5128-12T
IS61LV5128-12B
400-milPlasticSOJ
TSOP (Type II)
miniBGA(8mmx10mm)
12
12
12
IS61LV5128-12KI
IS61LV5128-12TI
IS61LV5128-12BI
400-milPlasticSOJ
TSOP (Type II)
miniBGA(8mmx10mm)
15
15
15
IS61LV5128-15K
IS61LV5128-15T
IS61LV5128-15B
400-milPlasticSOJ
TSOP (Type II)
miniBGA(8mmx10mm)
15
15
15
IS61LV5128-15KI
IS61LV5128-15TI
IS61LV5128-15BI
400-milPlasticSOJ
TSOP (Type II)
miniBGA(8mmx10mm)
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
07/16/01
相关型号：
©2020 ICPDF网 联系我们和版权申明