IS61NLP6432A [ISSI]
64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM; 64K ×32 ， 64K ×36 ，和128K ×18的2Mb ，管道（不等待）态总线SRAM
| 型号： | IS61NLP6432A |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM |
| 文件： | 总21页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
64K x 32, 64K x 36, and 128K x 18
2Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
®
ISSI
PRELIMINARYINFORMATION
SEPTEMBER 2005
FEATURES
DESCRIPTION
The 2 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 64K words by 32 bits, 64K words by 36 bits,
and128K wordsby18bits,fabricatedwithISSI'sadvanced
CMOS technology.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP package
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
• Power supply:
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
• Industrial temperature available
• Lead-free available
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-250
2.6
4
-200
3.1
5
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
250
200
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
1
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
BLOCK DIAGRAM
64Kx32;
64Kx36;
128Kx18
A2-A15 or A2-A16
x 32/x 36: A [0:15] or
x 18: A [0:16]
ADDRESS
REGISTER
MEMORY ARRAY
MODE
BURST
ADDRESS
COUNTER
K
K
DATA-IN
REGISTER
A0-A1
A'0-A'1
DATA-IN
REGISTER
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CONTROL
LOGIC
K
CKE
CE
CE2
CE2
CONTROL
REGISTER
ADV
WE
K
CONTROL
LOGIC
OUTPUT
REGISTER
}
BW
X
(X=a,b,c,d or a,b)
BUFFER
OE
ZZ
32, 36 or 18
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
100
DQPc
DQc
NC
DQc
DQc
VDDQ
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
NC
DQb
DQb
VDDQ
Vss
DQc
DQb
V
DDQ
Vss
V
DDQ
Vss
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
DQc
DQc
Vss
DQc
DQc
Vss
DQb
DQb
Vss
DQb
DQb
Vss
V
DDQ
VDDQ
DQc
V
DDQ
VDDQ
DQb
DQc
DQb
DQc
NC
DQc
NC
DQb
Vss
NC
DQb
Vss
NC
V
DD
VDD
NC
Vss
V
DD
NC
Vss
VDD
ZZ
ZZ
DQa
DQa
DQa
DQa
VDDQ
Vss
DQd
DQd
DQd
DQd
VDDQ
V
DDQ
V
DDQ
Vss
Vss
Vss
DQd
DQa
DQa
DQd
DQa
DQa
DQd
DQd
DQd
DQd
Vss
DQa
DQa
Vss
DQd
DQd
Vss
DQa
DQa
Vss
V
DDQ
V
DDQ
VDDQ
VDDQ
DQd
DQd
DQa
DQd
DQd
NC
DQa
DQa
NC
DQa
DQPd
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
64K x 32
64K x 36
PIN DESCRIPTIONS
CE, CE2, CE2 SynchronousChipEnable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
OE
OutputEnable
DQa-DQd
DQPa-DQPd
MODE
VDD
SynchronousDataInput/Output
Parity Data I/O
A
Synchronous Address Inputs
SynchronousClock
CLK
ADV
BWa-BWd
WE
Burst Sequence Selection
+3.3V/2.5V Power Supply
Ground for output Buffer
Synchronous Burst Address Advance
Synchronous Byte Write Enable
WriteEnable
VSS
VDDQ
Isolated Output Buffer Supply: +3.3V/2.5V
SnoozeEnable
CKE
Vss
Clock Enable
ZZ
GroundforCore
NC
NotConnected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
3
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
V
DDQ
V
DDQ
Vss
Vss
NC
NC
NC
DQPa
DQb
DQb
Vss
DQa
DQa
Vss
V
DDQ
V
DDQ
DQb
DQa
DQb
NC
DQa
Vss
NC
V
DD
NC
VDD
Vss
ZZ
DQb
DQb
DQa
DQa
V
DDQ
VDDQ
Vss
Vss
DQb
DQa
DQa
DQb
DQPb
NC
NC
NC
Vss
Vss
V
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
128K x 18
PIN DESCRIPTIONS
CE, CE2, CE2 Synchronous Chip Enable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
OE
Output Enable
DQa-DQd
DQPa-DQPd
MODE
VDD
Synchronous Data Input/Output
Parity Data I/O
A
Synchronous Address Inputs
SynchronousClock
CLK
ADV
BWa-BWd
WE
Burst Sequence Selection
+3.3V/2.5V Power Supply
Ground for output Buffer
Synchronous Burst Address Advance
Synchronous Byte Write Enable
WriteEnable
VSS
VDDQ
Isolated Output Buffer Supply: +3.3V/2.5V
SnoozeEnable
CKE
Vss
Clock Enable
ZZ
GroundforCore
NC
NotConnected
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
STATE DIAGRAM
READ
WRITE
BEGIN
BEGIN
WRITE
WRITE
READ
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
BURST
WRITE
BURST
DS
DS
DS
WRITE
BURST
READ
BURST
BURST
BURST
WRITE
READ
SYNCHRONOUSTRUTHTABLE(1)
Address
Operation
Used
CE
CE2 CE2 ADV
WE
BWx
OE
CKE CLK
Not Selected
N/A
N/A
H
X
X
X
L
X
L
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Not Selected
Not Selected
N/A
X
X
H
X
H
X
H
X
H
X
X
L
NotSelectedContinue
Begin Burst Read
ContinueBurstRead
NOP/DummyRead
DummyRead
N/A
H
L
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write
ContinueBurstWrite
NOP/WriteAbort
WriteAbort
X
L
X
L
H
L
X
L
L
H
H
X
Next Address
CurrentAddress
X
X
X
X
H
X
X
X
IgnoreClock
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
5
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
ASYNCHRONOUSTRUTHTABLE(1)
Operation
ZZ
OE
I/O STATUS
SleepMode
H
X
High-Z
L
L
L
H
DQ
High-Z
Read
Write
L
L
X
X
Din,High-Z
High-Z
Deselected
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BWa
BWb
READ
H
L
L
L
L
X
L
X
H
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITEABORT/NOP
H
L
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
WRITE TRUTH TABLE (x32/x36)
Operation
WE
BWa
BWb
BWc
BWd
READ
H
L
L
L
L
L
L
X
L
X
H
L
X
H
H
L
X
H
H
H
L
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITEABORT/NOP
H
H
H
L
H
H
L
H
L
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
7
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
Parameter
Value
–65 to +150
1.6
Unit
°C
W
StorageTemperature
PowerDissipation
OutputCurrent(perI/O)
PD
IOUT
100
mA
V
VIN, VOUT
VIN
Voltage Relative to VSS for I/O Pins
–0.5 to VDDQ + 0.3
–0.3 to 4.6
Voltage Relative to VSS for
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,
precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLPx)
Range
AmbientTemperature
0°C to +70°C
VDD
VDDQ
Commercial
Industrial
3.3V ± 5%
3.3V ± 5%
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
-40°Cto+85°C
OPERATING RANGE (IS61NVPx)
Range
AmbientTemperature
0°C to +70°C
VDD
VDDQ
Commercial
Industrial
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
-40°Cto+85°C
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
2.0
–0.3
–5
VDD + 0.3
1.7
–0.3
–5
VDD + 0.3
V
V
0.8
5
0.7
5
(1)
Input Leakage Current
Output Leakage Current
VSS ≤ VIN ≤ VDD
µA
µA
ILO
VSS ≤ VOUT ≤ VDDQ, OE = VIH
–5
5
–5
5
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250
-200
MAX
MAX
Symbol Parameter
Test Conditions
Temp.range
x18
x32/x36
x18 x32/x36
Unit
ICC
ISB
ISBI
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Com.
Ind.
225
250
225
250
200
210
200
210
mA
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
90
100
90
100
90
100
90
100
mA
mA
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
70
75
70
75
70
75
70
75
VIN
≤
VSS + 0.2V or ≥VDD – 0.2V
typ.(2)
40
40
20
f = 0
ZZ>VIH
ISB2
Sleep Mode
Com.
Ind.
30
35
30
35
30
35
30
35
mA
typ.(2)
20
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
9
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
InputCapacitance
Input/OutputCapacitance
6
8
COUT
Notes:
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
Input Rise and Fall Times
0V to 2.5V
1.5 ns
Input and Output Timing
andReferenceLevel
1.25V
OutputLoad
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
11
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-250
Min.
-200
Min. Max.
Symbol
fmax
tKC
Parameter
Max.
250
—
—
—
2.6
—
—
2.6
2.8
—
2.6
—
—
—
—
—
—
—
—
—
—
—
—
2
Unit
ClockFrequency
—
4.0
1.7
1.7
—
—
5
200
—
—
—
3.1
—
—
3.0
3.1
—
3.0
—
—
—
—
—
—
—
—
—
—
—
—
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Cycle Time
tKH
Clock High Time
2
tKL
Clock Low Time
2
tKQ
Clock Access Time
—
1.5
1
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/WriteSetupTime
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
0.8
0.8
—
(2,3)
tKQLZ
(2,3)
tKQHZ
—
—
0
tOEQ
—
(2,3)
tOELZ
0
(2,3)
tOEHZ
—
—
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
—
—
tAS
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
—
tWS
tCES
tSE
tADVS
tDS
tAH
Address Hold Time
tHE
Clock Enable Hold Time
Write Hold Time
tWH
tCEH
tADVH
tDH
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
tPDS
tPUS
ZZ High to Power Down
ZZ Low to Power Down
—
2
2
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
SLEEPMODEELECTRICALCHARACTERISTICS
Symbol
ISB2
Parameter
Conditions
Min.
Max.
Unit
mA
CurrentduringSLEEPMODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
ZZ ≥ VIH
35
tPDS
2
2
2
0
cycle
cycle
cycle
ns
tPUS
tZZI
tRZZI
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
All Inputs
I
SB2
t
RZZI
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
13
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
READ CYCLE TIMING
t
KH
tKL
CLK
tKC
tADVS tADVH
ADV
tAS tAH
Address
A1
A2
A3
tWS
tWH
WRITE
CKE
tSE tHE
tCES
t
CEH
CE
OE
tKQ
tOEQ
tOEHZ
tDS
tKQHZ
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
WRITE CYCLE TIMING
tKH
tKL
CLK
tKC
ADV
Address
WRITE
CKE
A1
A2
A3
tSE
tHE
CE
OE
tDS
tDH
Data In
Data Out
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
D3-2
D3-3
D3-4
tOEHZ
Q0-3
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
15
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
SINGLE READ/WRITE CYCLE TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
t
OEQ
t
OELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
t
DS
tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
CKE OPERATION TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
ADV
OE
t
KQ
t
KQHZ
t
KQLZ
Data Out
Data In
Q1
Q3
Q4
t
DS
t
DH
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
17
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
CE OPERATION TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CE
ADV
OE
t
OEQ
t
KQHZ
t
KQ
t
OELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D3
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Access Time
Order Part Number
64Kx32
Package
250
200
IS61NLP6432A-250TQ
IS61NLP6432A-200TQ
100 TQFP
100 TQFP
64Kx36
250
200
IS61NLP6436A-250TQ
IS61NLP6436A-200TQ
100 TQFP
100 TQFP
128Kx18
250
200
IS61NLP12818A-250TQ
IS61NLP12818A-200TQ
100 TQFP
100 TQFP
Industrial Range: -40°C to +85°C
AccessTime
OrderPartNumber
64Kx32
Package
250
IS61NLP6432A-250TQI
100 TQFP
100 TQFP
100TQFP,Lead-free
200
200
IS61NLP6432A-200TQI
IS61NLP6432A-200TQLI
64Kx36
250
200
IS61NLP6436A-250TQI
IS61NLP6436A-200TQI
100 TQFP
100 TQFP
128Kx18
250
IS61NLP12818A-250TQI
100 TQFP
200
200
IS61NLP12818A-200TQI
IS61NLP12818A-200TQLI
100 TQFP
100TQFP,Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
19
08/31/05
IS61NLP6432A
IS61NLP6436A/IS61NVP6436A
IS61NLP12818A/IS61NVP12818A
®
ISSI
ORDERING INFORMATION (VDD = 2.5V/VDDQ = 2.5V)
Commercial Range: 0°C to +70°C
Access Time
Order Part Number
64Kx36
Package
250
200
IS61NVP6436A-250TQ
IS61NVP6436A-200TQ
100 TQFP
100 TQFP
128Kx18
250
200
IS61NVP12818A-250TQ
IS61NVP12818A-200TQ
100 TQFP
100 TQFP
Industrial Range: -40°C to +85°C
Access Time
Order Part Number
64Kx36
Package
250
200
IS61NVP6436A-250TQI
IS61NVP6436A-200TQI
100 TQFP
100 TQFP
128Kx18
250
200
IS61NVP12818A-250TQI
IS61NVP12818A-200TQI
100 TQFP
100 TQFP
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/31/05
®
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
Inches Millimeters
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
Millimeters
Min Max
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
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