IS61NVF25636A-7.5B2I [ISSI]
256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM; 256K ×36和512K ×18 9MB ，流过（不等待）态总线SRAM
| 型号： | IS61NVF25636A-7.5B2I |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM |
| 文件： | 总37页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
ISSI
256K x 36 and 512K x 18
9Mb, FLOW THROUGH 'NO WAIT'
STATE BUS SRAM
AUGUST 2005
FEATURES
DESCRIPTION
The 9 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with ISSI's advanced CMOS technology.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
• Power supply:
NVF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
NLF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
is selected. When tied LOW, the linear burst sequence is
selected.
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol
tKQ
Parameter
6.5
6.5
7.5
133
7.5
7.5
8.5
117
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
1
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
BLOCK DIAGRAM
A2-A17 or A2-A18
256Kx36;
512Kx18
MEMORY ARRAY
ADDRESS
REGISTER
x 36: A [0:17] or
x 18: A [0:18]
MODE
BURST
ADDRESS
COUNTER
K
K
DATA-IN
REGISTER
A0-A1
A'0-A'1
DATA-IN
REGISTER
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CONTROL
LOGIC
K
CKE
CE
CE2
CE2
CONTROL
REGISTER
ADV
WE
K
CONTROL
LOGIC
}
BW
X
(X= a-d, or a,b)
BUFFER
OE
ZZ
36 or 18
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
Bottom View
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
3
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
PIN CONFIGURATION — 256K X 36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
A
10
11
NC
A
B
C
D
E
F
NC
A
CE
BWc
BWd
VSS
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CKE
WE
ADV
OE
A
NC
A
CE2
NC
A
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
DQc
DQc
DQc
DQc
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
G
H
J
NC
NC
DQd
DQd
DQd
DQd
DQPd
NC
DQd
DQd
DQd
DQd
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
A
V
DDQ
DDQ
DDQ
DDQ
DDQ
A
DQa
DQa
DQa
DQa
DQPa
NC
K
L
V
V
V
V
V
V
V
V
M
N
P
R
VSS
A
VSS
A
NC
TDI
A1*
A0*
TDO
TCK
MODE
NC
A
A
TMS
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
MODE
Burst Sequence Selection
JTAG Pins
Symbol
A
Pin Name
TCK, TDI
Address Inputs
TDO, TMS
A0, A1
ADV
Synchronous Burst Address Inputs
VDD
NC
3.3V/2.5V Power Supply
NoConnect
Synchronous Burst Address Advance/
Load
DQx
DQPx
VDDQ
DataInputs/Outputs
Parity Data I/O
WE
SynchronousRead/WriteControlInput
SynchronousClock
CLK
CKE
Isolated output Power Supply
3.3V/2.5V
Clock Enable
CE, CE2, CE2 SynchronousChipEnable
VSS
Ground
BWx(x=a-d)
Synchronous Byte Write Inputs
OutputEnable
OE
ZZ
PowerSleepMode
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
119-PIN PBGA PACKAGE CONFIGURATION
256K x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
V
DDQ
A
A
A
A
NC
A
A
A
V
DDQ
NC
NC
CE2
A
ADV
CE2
A
NC
NC
V
DD
A
DQc
DQc
DQPc
DQc
DQc
DQc
V
SS
SS
SS
NC
CE
OE
A
Vss
Vss
Vss
BWb
DQPb
DQb
DQb
DQb
DQb
DQb
V
V
E
F
V
DDQ
DQc
DQc
V
DDQ
BWc
DQb
DQb
G
VSS
DQc
WE
Vss
NC
DQb
H
J
NC
V
DDQ
DQd
DQd
V
DD
VDD
V
DD
V
DDQ
K
L
V
SS
DQd
DQd
DQd
DQd
DQPd
CLK
NC
Vss
BWa
Vss
Vss
Vss
DQa
DQa
DQa
DQa
DQPa
DQa
DQa
BWd
VDDQ
VSS
CKE
V
DDQ
M
N
P
R
T
DQd
DQd
A
A
1
*
*
DQa
DQa
VSS
0
VSS
NC
NC
A
MODE
A
VDD
NC
A
A
NC
ZZ
NC
A
NC
NC
U
V
DDQ
TMS
TDI
TCK
TDO
V
DDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
OE
OutputEnable
Symbol
A
Pin Name
ZZ
PowerSleepMode
Burst Sequence Selection
JTAG Pins
Address Inputs
MODE
TCK, TDO
TMS, TDI
VDD
A0, A1
ADV
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
PowerSupply
Ground
WE
SynchronousRead/WriteControlInput
SynchronousClock
VSS
CLK
NC
NoConnect
CKE
Clock Enable
DQa-DQd
DQPa-Pd
VDDQ
DataInputs/Outputs
Parity Data I/O
Output Power Supply
CE
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
CE2
CE2
BWx(x=a-d)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
5
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
165-PIN PBGA PACKAGE CONFIGURATION
512K x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
CKE
NC
ADV
A
A
A
A
A
BWb
NC
A
CE2
CLK
Vss
Vss
CE
NC
CE2
NC
DDQ
OE
WE
NC
NC
BWa
V
NC
Vss
Vss
DQPa
NC
V
DDQ
DDQ
DDQ
Vss
Vss
NC
NC
NC
VDD
Vss
V
V
V
DD
DQa
DQa
DQa
DQa
ZZ
NC
Vss
Vss
Vss
Vss
V
DDQ
DDQ
DQb
DQb
VDD
V
V
DD
DD
E
F
NC
Vss
Vss
Vss
Vss
V
DDQ
DDQ
V
DDQ
V
DD
DD
NC
DQb
NC
NC
V
V
Vss
Vss
Vss
Vss
V
G
NC
V
DDQ
DQb
NC
NC
NC
NC
VDD
V
DD
DD
DD
DD
DD
V
DD
NC
H
J
NC
NC
Vss
Vss
NC
V
DDQ
V
Vss
Vss
Vss
V
DDQ
DDQ
V
DD
DD
DQb
DQb
DQb
DQb
DQPb
NC
DQa
NC
NC
NC
K
L
V
V
DDQ
DDQ
V
V
Vss
Vss
Vss
Vss
DQa
DQa
DQa
NC
A
V
V
Vss
Vss
VDD
V
DDQ
V
NC
NC
V
DDQ
VDD
M
N
P
NC
NC
NC
NC
Vss
Vss
NC
V
DDQ
Vss
A
NC
VDDQ
Vss
A
NC
TDI
V
DDQ
A
A
NC
A
A
1
*
*
TDO
TCK
TMS
A
A
0
A
A
A
A
R
MODE
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
MODE
Burst Sequence Selection
JTAG Pins
Symbol
A
Pin Name
TCK, TDI
Address Inputs
TDO, TMS
A0, A1
ADV
Synchronous Burst Address Inputs
VDD
NC
3.3V/2.5V Power Supply
NoConnect
Synchronous Burst Address Advance/
Load
DQx
DQPx
VDDQ
DataInputs/Outputs
Parity Data I/O
WE
SynchronousRead/WriteControlInput
SynchronousClock
CLK
CKE
Isolated output Power Supply
3.3V/2.5V
Clock Enable
CE, CE2, CE2 SynchronousChipEnable
VSS
Ground
BWx (x=a,b)
Synchronous Byte Write Inputs
OutputEnable
OE
ZZ
PowerSleepMode
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
119-PIN PBGA PACKAGE CONFIGURATION
512K x 18 (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
V
DDQ
A
CE2
A
A
A
A
NC
A
A
A
CE2
A
V
DDQ
NC
NC
ADV
NC
NC
V
DD
A
NC
NC
DQb
V
SS
SS
SS
NC
CE
OE
A
Vss
Vss
Vss
NC
DQPa
NC
DQa
DQb
NC
V
V
E
F
NC
DQa
NC
V
DDQ
VDDQ
NC
DQa
NC
DQb
NC
BWb
G
DQa
VSS
DQb
WE
Vss
NC
H
J
NC
VDDQ
V
DD
VDD
V
DD
V
DDQ
K
L
V
SS
DQb
NC
CLK
NC
Vss
BWa
Vss
Vss
Vss
DQa
NC
NC
NC
DQa
NC
DQa
NC
A
DQb
NC
VDDQ
DQb
NC
V
SS
SS
CKE
V
DDQ
M
N
P
R
T
NC
DQa
NC
DQb
NC
V
A
A
1
*
*
0
V
SS
DQPb
A
NC
MODE
A
VDD
NC
A
A
NC
ZZ
A
NC
U
V
DDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
OE
OutputEnable
Symbol
A
Pin Name
ZZ
PowerSleepMode
Burst Sequence Selection
JTAG Pins
Address Inputs
MODE
TCK, TDO
TMS, TDI
VDD
A0, A1
ADV
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
PowerSupply
Ground
WE
SynchronousRead/WriteControlInput
SynchronousClock
VSS
CLK
NC
NoConnect
CKE
Clock Enable
DQa-DQb
DQPa-Pb
VDDQ
DataInputs/Outputs
Parity Data I/O
Output Power Supply
CE
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
CE2
CE2
BWx (x=a,b)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
7
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
DQPc
DQc
DQc
VDDQ
Vss
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
Vss
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
V
DDQ
V
DDQ
Vss
Vss
DQc
DQc
DQb
DQb
NC
NC
NC
DQPa
DQc
DQc
Vss
DQb
DQb
Vss
DQb
DQb
Vss
DQa
DQa
Vss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQc
VDDQ
DQb
V
DDQ
V
DDQ
DQb
DQa
DQc
NC
DQb
Vss
NC
DQb
NC
DQa
Vss
NC
VDD
V
DD
NC
Vss
VDD
ZZ
NC
VDD
Vss
ZZ
DQa
DQa
VDDQ
Vss
DQd
DQd
VDDQ
DQb
DQb
DQa
DQa
V
DDQ
VDDQ
Vss
Vss
Vss
DQd
DQa
DQa
DQb
DQa
DQa
DQb
DQd
DQPb
NC
DQd
DQd
Vss
DQa
DQa
Vss
NC
NC
Vss
Vss
VDDQ
VDDQ
V
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
DQd
DQd
DQa
DQa
DQPd
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 18
256K x 36
PIN DESCRIPTIONS
CE, CE2, CE2 SynchronousChipEnable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
OE
OutputEnable
DQa-DQd
DQPa-DQPd
MODE
VDD
SynchronousDataInput/Output
Parity Data I/O
A
Synchronous Address Inputs
SynchronousClock
CLK
ADV
BWa-BWd
WE
Burst Sequence Selection
+3.3V/2.5V Power Supply
Ground for output Buffer
Synchronous Burst Address Advance
Synchronous Byte Write Enable
WriteEnable
VSS
VDDQ
Isolated Output Buffer Supply: +3.3V/2.5V
SnoozeEnable
CKE
Vss
Clock Enable
ZZ
GroundforCore
NC
NotConnected
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
STATE DIAGRAM
READ
WRITE
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
BURST
WRITE
BURST
DS
DS
DS
WRITE
BURST
READ
BURST
BURST
BURST
WRITE
READ
SYNCHRONOUSTRUTHTABLE(1)
Address
Operation
Used
CE
CE2 CE2 ADV
WE
BWx
OE
CKE CLK
Not Selected
N/A
N/A
H
X
X
X
L
X
L
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Not Selected
Not Selected
N/A
X
X
H
X
H
X
H
X
H
X
X
L
NotSelectedContinue
Begin Burst Read
ContinueBurstRead
NOP/DummyRead
DummyRead
N/A
H
L
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write
ContinueBurstWrite
NOP/WriteAbort
WriteAbort
X
L
X
L
H
L
X
L
L
H
H
X
Next Address
CurrentAddress
X
X
X
X
H
X
X
X
IgnoreClock
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
9
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
ASYNCHRONOUSTRUTHTABLE(1)
Operation
ZZ
OE
I/O STATUS
SleepMode
H
X
High-Z
L
L
L
H
DQ
High-Z
Read
Write
L
L
X
X
Din,High-Z
High-Z
Deselected
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BWa
BWb
READ
H
L
L
L
L
X
L
X
H
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITEABORT/NOP
H
L
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
10
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Rev. B
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
WRITE TRUTH TABLE (x36)
Operation
WE
BWa
BWb
BWc
BWd
READ
H
L
L
L
L
L
L
X
L
X
H
L
X
H
H
L
X
H
H
H
L
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITEABORT/NOP
H
H
H
L
H
H
L
H
L
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
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Rev. B
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
Parameter
Value
–65 to +150
1.6
Unit
°C
W
StorageTemperature
PowerDissipation
OutputCurrent(perI/O)
PD
IOUT
100
mA
V
VIN, VOUT
VIN
Voltage Relative to VSS for I/O Pins
–0.5 to VDDQ + 0.3
–0.3 to 4.6
Voltage Relative to VSS for
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,
precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLFx)
Range
AmbientTemperature
0°C to +70°C
VDD
VDDQ
Commercial
Industrial
3.3V ± 5%
3.3V ± 5%
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
-40°Cto+85°C
12
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Rev. B
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
OPERATING RANGE (IS61NVFx)
Range
AmbientTemperature
0°C to +70°C
VDD
VDDQ
Commercial
Industrial
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
-40°Cto+85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
2.0
–0.3
–5
VDD + 0.3
1.7
–0.3
–5
VDD + 0.3
V
V
0.8
5
0.7
5
(1)
Input Leakage Current
Output Leakage Current
VSS ≤ VIN ≤ VDD
µA
µA
ILO
VSS ≤ VOUT ≤ VDDQ, OE = VIH
–5
5
–5
5
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
6.5
7.5
MAX
MAX
Symbol Parameter
Test Conditions
Temp.range
x18
x36
x18
x36
Unit
ICC
ISB
ISBI
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Com.
Ind.
280
300
280
300
270
280
270
280
mA
mA
mA
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
100
100
100
100
100
100
100
100
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
70
80
70
80
70
80
70
80
VIN
≤ VSS + 0.2V or ≥ VDD – 0.2V
f = 0
ISB2
Sleep Mode
ZZ > VIH
Com.
Ind.
45
50
45
50
45
50
45
50
mA
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100 µA maximum leakage current when tied to
≤ VSS + 0.2V or ≥ VDD – 0.2V.
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
InputCapacitance
Input/OutputCapacitance
6
8
COUT
Notes:
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
14
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Rev. B
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.25V
OutputLoad
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
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Rev. B
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
6.5
Min.
7.5
Min. Max.
Symbol
fmax
tKC
Parameter
Max.
133
—
—
—
6.5
—
—
3.8
3.2
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
2
Unit
ClockFrequency
—
7.5
2.2
2.2
—
—
8.5
2.5
2.5
—
117
—
—
—
7.5
—
—
4.0
3.4
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Cycle Time
tKH
Clock High Time
tKL
Clock Low Time
tKQ
Clock Access Time
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/WriteSetupTime
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
2.5
2.5
—
2.5
2.5
—
(2,3)
tKQLZ
(2,3)
tKQHZ
tOEQ
—
—
(2,3)
tOELZ
0
0
(2,3)
tOEHZ
—
—
tAS
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
—
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
—
tWS
tCES
tSE
tADVS
tDS
tAH
Address Hold Time
tHE
Clock Enable Hold Time
Write Hold Time
tWH
tCEH
tADVH
tDH
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
tPDS
tPUS
ZZ High to Power Down
ZZ Low to Power Down
—
2
—
2
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
16
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
SLEEPMODEELECTRICALCHARACTERISTICS
Symbol
ISB2
Parameter
Conditions
Min.
Max.
60
Unit
mA
CurrentduringSLEEPMODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
ZZ ≥ VIH
tPDS
2
cycle
cycle
cycle
ns
tPUS
2
2
0
tZZI
tRZZI
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
All Inputs
I
SB2
t
RZZI
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
READ CYCLE TIMING
tKH
tKL
CLK
tKC
tADVS tADVH
ADV
tAS tAH
Address
A1
A2
A3
tWS
tWH
WRITE
CKE
tSE tHE
tCES
t
CEH
CE
OE
t
DS
KQ
t
OEQ
t
OEHZ
t
t
KQHZ
Q3-4
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
18
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
WRITE CYCLE TIMING
tKH
tKL
CLK
tKC
ADV
Address
WRITE
CKE
A1
A2
A3
tSE
tHE
CE
OE
t
DS
tDH
Data In
Data Out
D1-1
D2-1
D2-2
D2-4
D3-1
D3-2
D3-3
D3-4
D2-3
tOEHZ
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
SINGLE READ/WRITE CYCLE TIMING
tKH
tKL
CLK
t
SE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
tOEQ
t
OELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
tDS tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
20
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
CKE OPERATION TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
ADV
OE
t
KQ
t
KQHZ
t
KQLZ
Q4
Data Out
Data In
Q1
Q3
t
DS
t
DH
D5
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
CE OPERATION TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CE
ADV
OE
t
OEQ
t
KQHZ
t
KQ
t
OELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D3
D5
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
22
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
IEEE1149.1SERIALBOUNDARYSCAN(JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
TheIS61NLFXand IS61NVFXhaveaserialboundaryscan
Test Access Port (TAP) in the PBGA package only. (Not
available in TQFP package.) This port operates in accor-
dance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
oftheSRAM.TheTAPcontrolleroperatesinamannerthat
does not conflict with the performance of other devices
using1149.1fullycompliantTAPs.TheTAPoperatesusing
JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
DISABLING THE JTAG FEATURE
TheSRAMcanoperatewithoutusingtheJTAGfeature.To
disable the TAP controller, TCK must be tied LOW (VSS) to
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
beconnectedtoVDD throughapull-upresistor.TDOshould
beleftdisconnected. Onpower-up, thedevicewillstartina
resetstatewhichwillnotinterferewiththedeviceoperation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
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®
ISSI
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
theregisters.Theoutputisactivedependingonthecurrent
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
is set LOW (VSS) when the BYPASS instruction is ex-
ecuted.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect(NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
andallowdatatobescannedintoandoutoftheSRAMtest
circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
intotheTDIpinontherisingedgeofTCKandoutputonthe
TDO pin on the falling edge of TCK.
TheBoundaryScanOrdertablesshowtheorderinwhichthe
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Instruction Register
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI andTDO pins. (See TAP Controller
Block Diagram) At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with
the IDCODE instruction if the controller is placed in a reset
state as previously described.
Register
Name
Bit Size
(x18)
Bit Size
(x36)
Instruction
Bypass
3
1
3
1
ID
32
75
32
75
BoundaryScan
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
Identification (ID) Register
Bypass Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
commandisloadedtotheinstructionregister.TheIDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
IDENTIFICATION REGISTER DEFINITIONS
InstructionField
Description
256K x 36
xxxx
512K x 18
xxxx
RevisionNumber (31:28)
DeviceDepth (27:23)
DeviceWidth (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
IDRegisterPresence (0)
Reservedforversionnumber.
Defines depth of SRAM. 256K or 512K
Defines Width of the SRAM. x36 or x18
Reserved for future use.
00111
01000
00100
00011
xxxxx
xxxxx
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
00011010101
1
00011010101
1
24
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IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output
buffers. The SRAM does not implement the 1149.1 com-
mands EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; instead it performs a capture of the
Inputs and Output ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compli-
ant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster.
Because of the clock frequency differences, it is possible
that during the Capture-DR state, an input or output will
under-go a transition. The TAP may attempt a signal
capture while in transition (metastable state). The device
will not be harmed, but there is no guarantee of the value
that will be captured or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be
stabilized long enough to meet the TAP controller’s
capture set-up plus hold times (tCS and tCH). To insure that
the SRAM clock input is captured correctly, designs need
a way to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is not an issue, it is possible
to capture all other signals and simply ignore the value of
the CLK captured in the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented,puttingtheTAPintotheUpdatetotheUpdate-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
IDCODE
BYPASS
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
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08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
INSTRUCTION CODES
Code
Instruction
Description
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register between
the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not implement
1149.1 preload function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
VOH1
VOH2
VOL1
VOL2
VIH
Parameter
Test Conditions
IOH = –2.0 mA
IOH = –100 µA
IOL = 2.0 mA
Min.
1.7
2.1
—
Max.
—
Units
V
OutputHIGHVoltage
OutputHIGHVoltage
OutputLOWVoltage
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakageCurrent
—
V
0.7
V
IOL = 100 µA
—
0.2
V
1.7
–0.3
–10
VDD +0.3
0.7
V
VIL
V
IX
VSS ≤ V I ≤ VDDQ
10
µA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot: VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
100
—
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
tTCYC
fTF
TCK Clock cycle time
TCK Clock frequency
MHz
ns
tTH
TCK Clock HIGH
40
40
10
10
10
10
10
10
—
tTL
TCK Clock LOW
ns
tTMSS
tTDIS
tCS
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
ns
ns
ns
tTMSH
tTDIH
tCH
ns
ns
ns
tTDOV
ns
tTDOX
0
ns
Notes:
1. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
27
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
TAP AC TEST CONDITIONS (2.5V/3.3V)
TAP Output Load Equivalent
Input pulse levels
0 to 2.5V/0 to 3.0V
1ns
Input rise and fall times
Input timing reference levels
Output reference levels
1.25V/1.5V
1.25V/1.5V
50Ω
Vtrig
Test load termination supply voltage
Vtrig
1.25V/1.5V
1.25V/1.5V
TDO
20 pF
GND
Z0 = 50Ω
TAP TIMING
1
2
3
4
5
6
t
THTH
t
TLTH
TCK
TMS
t
THTL
t
t
MVTH THMX
t
DVTH
t
THDX
TDI
t
TLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
165 PBGA BOUNDARY SCAN ORDER (x 36)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
ID
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
ID
1
2
MODE
NC
NC
A
1R
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10A
10B
9A
NC
CE2
BWa
BWb
BWc
BWd
CE2
CE
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
6N
1K
1L
3
11P
8P
4
1M
2J
5
A
8R
6
A
9R
2K
2L
7
A
9P
8
A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
2M
1N
3P
3R
4R
4P
6P
6R
9
A
A
10
11
12
13
14
15
16
17
18
19
20
A
A
ZZ
A
NC
A
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
A
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
A
A
A
NC
9B
A1
ADV
OE
8A
A0
8B
CKE
WE
CLK
NC
7A
7B
6B
11B
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
29
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
165 PBGA BOUNDARY SCAN ORDER (x 18)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
DQa
DQa
DQa
DQa
DQa
NC
ID
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
A
ID
1
2
MODE
NC
NC
A
1R
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10A
10B
9A
NC
CE2
BWa
NC
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
6N
1K
1L
3
11P
8P
4
1M
1N
2K
2L
5
A
8R
BWb
NC
6
A
9R
7
A
9P
NC
CE2
CE
8
A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
NC
2M
2J
9
A
NC
A
10
11
12
13
14
15
16
17
18
19
20
A
A
A
3P
3R
4R
4P
6P
6R
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
A
NC
A
A
NC
A
A
NC
A
NC
9B
NC
A1
ADV
OE
CKE
WE
CLK
NC
8A
NC
A0
8B
NC
7A
DQb
DQb
DQb
DQb
7B
6B
11B
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
119 BOUNDARY SCAN ORDER (256K X 36)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
31
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
119 BOUNDARY SCAN ORDER (512K X 18)
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
AccessTime
OrderPartNumber
256Kx36
Package
6.5
IS61NLF25636A-6.5TQ
IS61NLF25636A-6.5B2
100 TQFP
119 PBGA
IS61NLF25636A-6.5B3
165 PBGA
7.5
IS61NLF25636A-7.5TQ
IS61NLF25636A-7.5B2
100 TQFP
119 PBGA
IS61NLF25636A-7.5B3
165 PBGA
512Kx18
6.5
7.5
IS61NLF51218A-6.5TQ
IS61NLF51218A-6.5B2
100 TQFP
119 PBGA
IS61NLF51218A-6.5B3
165 PBGA
IS61NLF51218A-7.5TQ
IS61NLF51218A-7.5B2
100 TQFP
119 PBGA
IS61NLF51218A-7.5B3
165 PBGA
Industrial Range: -40°C to +85°C
AccessTime
OrderPartNumber
256Kx36
Package
6.5
7.5
IS61NLF25636A-6.5TQI
IS61NLF25636A-6.5B2I
100 TQFP
119 PBGA
IS61NLF25636A-6.5B3I
165 PBGA
IS61NLF25636A-7.5TQI
IS61NLF25636A-7.5TQLI
IS61NLF25636A-7.5B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61NLF25636A-7.5B3I
165 PBGA
512Kx18
6.5
7.5
IS61NLF51218A-6.5TQI
IS61NLF51218A-6.5B2I
100 TQFP
119 PBGA
IS61NLF51218A-6.5B3I
165 PBGA
IS61NLF51218A-7.5TQI
IS61NLF51218A-7.5TQLI
IS61NLF51218A-7.5B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61NLF51218A-7.5B3I
165 PBGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
33
08/26/05
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
®
ISSI
ORDERING INFORMATION (VDD = 2.5V/VDDQ = 2.5V)
Commercial Range: 0°C to +70°C
AccessTime
OrderPartNumber
256Kx36
Package
6.5
IS61NVF25636A-6.5TQ
IS61NVF25636A-6.5B2
100 TQFP
119 PBGA
IS61NVF25636A-6.5B3
165 PBGA
7.5
IS61NVF25636A-7.5TQ
IS61NVF25636A-7.5B2
100 TQFP
119 PBGA
IS61NVF25636A-7.5B3
165 PBGA
512Kx18
6.5
7.5
IS61NVF51218A-6.5TQ
IS61NVF51218A-6.5B2
100 TQFP
119 PBGA
IS61NVF51218A-6.5B3
165 PBGA
IS61NVF51218A-7.5TQ
IS61NVF51218A-7.5B2
100 TQFP
119 PBGA
IS61NVF51218A-7.5B3
165 PBGA
Industrial Range: -40°C to +85°C
AccessTime
OrderPartNumber
256Kx36
Package
6.5
7.5
IS61NVF25636A-6.5TQI
IS61NVF25636A-6.5B2I
100 TQFP
119 PBGA
IS61NVF25636A-6.5B3I
165 PBGA
IS61NVF25636A-7.5TQI
IS61NVF25636A-7.5B2I
100 TQFP
119 PBGA
IS61NVF25636A-7.5B3I
165 PBGA
512Kx18
6.5
7.5
IS61NVF51218A-6.5TQI
IS61NVF51218A-6.5B2I
100 TQFP
119 PBGA
IS61NVF51218A-6.5B3I
165 PBGA
IS61NVF51218A-7.5TQI
IS61NVF51218A-7.5B2I
100 TQFP
119 PBGA
IS61NVF51218A-7.5B3I
165 PBGA
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
®
PACKAGING INFORMATION
ISSI
Plastic Ball Grid Array
Package Code: B (119-pin)
φ
b (119X)
E
A
7
6
5
4
3
2
1
A
B
C
D
E
F
30ϒ
G
H
J
D
D2
D1
K
L
M
N
P
R
T
e
U
A2
E1
A1
A3
E2
SEATING PLANE
A4
MILLIMETERS
INCHES
Min.
Sym. Min.
Max.
Max.
N0.
Leads
Notes:
119
1.Controllingdimension:millimeters,unlessotherwisespecified.
2.BSC=Basicleadspacingbetweencenters.
3.DimensionsD1andEdonotincludemoldflashprotrusionand
shouldbemeasuredfromthebottomofthepackage.
4.Formedleadsshallbeplanarwithrespecttooneanotherwithin
0.004inchesattheseatingplane.
A
—
2.41
0.70
1.00
1.70
—
0.095
0.028
0.039
0.067
A1
A2
A3
A4
b
0.50
0.80
1.30
0.020
0.032
0.051
0.56 BSC
0.022 BSC
0.60
0.90
0.024
0.858
0.035
0.874
D
21.80
22.20
D1
D2
E
20.32 BSC
0.800 BSC
19.40
13.80
19.60
14.20
0.764
0.543
0.772
0.559
E1
E2
e
7.62 BSC
0.300 BSC
11.90
12.10
0.469
0.476
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
02/12/03
®
PACKAGING INFORMATION
Ball Grid Array
ISSI
Package Code: B (165-pin)
BOTTOM VIEW
A1 CORNER
TOP VIEW
A1 CORNER
φ b (165X)
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D
D1
K
L
K
L
M
N
P
R
M
N
P
R
e
E1
E
A2
A
A1
BGA - 13mm x 15mm
Notes:
MILLIMETERS
INCHES
1. Controlling dimensions are in millimeters.
Sym. Min. Nom. Max.
Min. Nom. Max.
165
N0.
Leads
165
A
—
0.25
—
—
1.20
0.40
—
—
—
0.047
0.010 0.013 0.016
0.031
A1
A2
D
0.33
0.79
—
—
14.90 15.00 15.10
13.90 14.00 14.10
12.90 13.00 13.10
9.90 10.00 10.10
0.587 0.591 0.594
0.547 0.551 0.555
0.508 0.512 0.516
0.390 0.394 0.398
D1
E
E1
e
—
1.00
0.45
—
—
0.039
—
b
0.40
0.50
0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03
®
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
Inches Millimeters
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
Millimeters
Min Max
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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