IS61NVF25672-6.5B1I-TR [ISSI]
IC SRAM 18M PARALLEL 209LFBGA;
| 型号： | IS61NVF25672-6.5B1I-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC SRAM 18M PARALLEL 209LFBGA 静态存储器 |
| 文件： | 总35页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
NOVEMBER 2013
256K x 72, 512K x 36 and 1M x 18
18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
FEATURES
DESCRIPTION
Theꢀ18ꢀMegꢀ'NLF/NVF'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ
aꢀ burstable,ꢀ high-performance,ꢀ 'noꢀ wait'ꢀ state,ꢀ deviceꢀ
forꢀ networkingꢀ andꢀ communicationsꢀ applications.ꢀ Theyꢀ
areꢀ organizedꢀ asꢀ 256Kꢀ wordsꢀ byꢀ 72ꢀ bits,ꢀ 512Kꢀ wordsꢀ
byꢀ36ꢀbitsꢀandꢀ1Mꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ
advanced CMOS technology.
•ꢀ 100ꢀpercentꢀbusꢀutilization
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite
•ꢀ Internalꢀself-timedꢀwriteꢀcycle
•ꢀ IndividualꢀByteꢀWriteꢀControl
•ꢀ SingleꢀRead/Writeꢀcontrolꢀpin
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ
ꢀ
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ
eliminated when the bus switches from read to write, or
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ
into a single monolithic circuit.
data and control
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-
ing MODE input
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ
device will hold their previous values.
and address pipelining
•ꢀ PowerꢀDownꢀmode
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
•ꢀ CKE pin to enable clock and suspend operation
AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ
whenꢀADVꢀisꢀLOW.
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ209-
ballꢀ(x72)ꢀPBGAꢀpackages
•ꢀ Powerꢀsupply:
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ
the rising edge of the clock inputs and when WEꢀisꢀLOW.ꢀ
Separate byte enables allow individual bytes to be written.
NVF:ꢀVdd 2.5Vꢀ(±ꢀ5%),ꢀVddqꢀ2.5Vꢀ(±ꢀ5%)
NLF:ꢀVddꢀ3.3Vꢀ(±ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ(±ꢀ5%)
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages
•ꢀ Industrialꢀtemperatureꢀavailable
•ꢀ Lead-freeꢀavailable
A burst mode pin (MODE) defines the order of the burst
sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ
selected.
FAST ACCESS TIME
Symbol
Parameter
6.5
7.5
Units
ns
tkqꢀ
tkcꢀ
ꢀ
ClockꢀAccessꢀTimeꢀ
CycleꢀTimeꢀ
6.5ꢀ
7.5ꢀ
133ꢀ
7.5ꢀ
8.5ꢀ
117ꢀ
ns
ꢀ
Frequencyꢀ
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-
ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
BLOCK DIAGRAM
x 72: A [0:17] or
x 36: A [0:18] or
x 18: A [0:19]
A2-A17 or A2-A18 or A2-A19
256Kx72; 512Kx36;
1024Kx18
MEMORY ARRAY
ADDRESS
REGISTER
MODE
BURST
ADDRESS
COUNTER
K
DATA-IN
REGISTER
A0-A1
A'0-A'1
K
DATA-IN
REGISTER
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CONTROL
LOGIC
K
CKE
CE
CE2
CE2
CONTROL
REGISTER
ADV
WE
K
CONTROL
LOGIC
}
BW
X
(X=a-h, a-d, or a,b)
BUFFER
OE
ZZ
72, 36 or 18
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
BottomꢀView
165-Ball,ꢀ13ꢀmmꢀxꢀ15mmꢀBGA
BottomꢀView
209-Ball,ꢀ14ꢀmmꢀxꢀ22ꢀmmꢀBGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
PIN CONFIGURATION — 256K ꢀ 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
ADV
WE
CE
7
A
8
9
A
10
DQb
DQb
DQb
DQb
DQPf
DQf
11
DQb
DQb
DQb
DQb
DQPb
DQf
A
B
C
D
E
F
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
A
CE2
BWg
BWd
NC
A
CE2
BWb
BWe
NC
BWc
BWh
NC
NC
NC
Vdd
A
BWf
BWa
NC
NC
Vdd
V
SS
OE
Vdd
NC
NC
NC
NC
CKE
NC
NC
NC
ZZ
V
SS
Vddq
SS
Vddq
SS
DQPg DQPc
Vddq
Vddq
Vddq
DQc
DQc
DQc
DQc
NC
DQc
DQc
DQc
DQc
NC
VSS
V
SS
Vddq
SS
V
SS
Vdd
SS
Vdd
SS
Vdd
SS
Vdd
SS
V
SS
Vdd
SS
Vdd
SS
Vdd
SS
Vdd
SS
V
SS
Vddq
SS
V
G
H
J
Vddq
DQf
DQf
V
SS
V
V
V
V
V
DQf
DQf
Vddq
CLK
Vddq
Vddq
NC
Vddq
NC
Vddq
NC
DQf
DQf
K
L
V
V
NC
NC
DQh
DQh
DQh
DQh
DQh
DQh
DQh
DQh
Vddq
Vddq
Vddq
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
M
N
P
R
T
VSS
V
SS
Vddq
SS
V
V
V
SS
Vddq
SS
V
SS
Vddq
SS
Vddq
SS
Vddq
VSS
V
V
V
V
V
DQPd DQPh
Vddq
Vddq
NC
A
Vdd
NC
NC
A
Vdd
MODE
A
Vdd
NC
NC
A
Vddq
NC
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
VSS
V
U
V
W
NC
A
NC
A
A
A1
A
TMS
TDI
A
A0
A
TDO
TCK
11ꢀxꢀ19ꢀBallꢀBGA—14ꢀxꢀ22ꢀmm2ꢀBody—1ꢀmmꢀBallꢀPitch
PIN DESCRIPTIONS
VSSꢀ
ꢀ
Ground
Symbolꢀ
A
PinꢀName
MODEꢀꢀ ꢀ
OE
BurstꢀSequenceꢀꢀSelection
Output Enable
Synchronous Address Inputs
A0,ꢀA1ꢀ
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
TCK,ꢀTDIꢀ
TDO,ꢀTMSꢀ
JTAGꢀPins
ADVꢀꢀ
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
Vddꢀ
ꢀ
ꢀ
3.3V/2.5VꢀPowerꢀSupply
BWa-BWhꢀ
Vddq
IsolatedꢀOutputꢀBufferꢀSupply:ꢀꢀꢀ ꢀ
3.3V/2.5V
CE, CE2, CE2 Synchronous Chip Enable
WEꢀ
WriteꢀEnable
Snooze Enable
CLKꢀꢀ
CKE
SynchronousꢀClock
Clock Enable
ZZ
DQxꢀ
DQPxꢀ
ꢀ
ꢀ
SynchronousꢀDataꢀInput/Output
ParityꢀDataꢀI/O
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
PIN CONFIGURATION — 512K x 36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
A
11
NC
A
B
C
D
E
F
NC
A
CE
BWc
BWd
VSS
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CKE
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADV
OE
A
NC
A
CE2
A
A
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
V
V
V
V
V
ddq
ddq
ddq
ddq
ddq
VSS
V
V
V
V
V
ddq
ddq
ddq
ddq
ddq
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
G
H
J
NC
NC
DQd
DQd
DQd
DQd
DQPd
NC
V
ddq
ddq
ddq
ddq
ddq
A
V
ddq
ddq
ddq
ddq
ddq
A
DQa
DQa
DQa
DQa
DQPa
NC
K
L
V
V
V
V
V
V
V
V
M
N
P
R
VSS
A
VSS
A
NC
TdI
TMS
A1*
A0*
TDO
TCK
MODE
NC
A
A
A
A
A
A
Note:ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.
PIN DESCRIPTIONS
Symbolꢀ
A
PinꢀName
Symbolꢀ
OE
PinꢀName
Address Inputs
Output Enable
A0,ꢀA1ꢀ
ADVꢀꢀ
SynchronousꢀBurstꢀAddressꢀInputs
ZZ
Power Sleep Mode
BurstꢀSequenceꢀSelection
JTAGꢀPins
SynchronousꢀBurstꢀAddressꢀAdvance/
Load
MODEꢀ
ꢀ
TCK,ꢀTDIꢀ
TDO,ꢀTMS
WEꢀ
SynchronousꢀRead/WriteꢀControlꢀ
Input
VDDꢀ
ꢀ
ꢀ
3.3V/2.5VꢀPowerꢀSupply
NoꢀConnect
CLKꢀꢀ
CKE
CE
SynchronousꢀClock
NCꢀ
Clock Enable
DQxꢀ
DQPxꢀ
VDDQꢀ
DataꢀInputs/Outputs
ParityꢀDataꢀI/O
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
CE2
CE2
Isolated output Power Supply
3.3V/2.5V
BWxꢀ(x=a-d)ꢀ SynchronousꢀByteꢀWriteꢀInputs
VSS
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
165-PIN PBGA PACKAGE CONFIGURATION
1024K x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
CKE
NC
ADV
A
A
A
A
A
BWb
NC
A
CE2
CLK
Vss
Vss
CE
NC
CE2
A
OE
WE
NC
Vss
NC
BWa
V
DDQ
NC
Vss
DQPa
NC
V
DDQ
DDQ
DDQ
Vss
Vss
NC
NC
NC
V
DD
Vss
V
V
V
DD
DQa
DQa
DQa
DQa
ZZ
NC
Vss
Vss
Vss
Vss
V
DDQ
DDQ
DQb
DQb
VDD
V
V
DD
DD
E
F
NC
Vss
Vss
V
DDQ
DDQ
V
DDQ
Vss
V
DD
DD
NC
DQb
DQb
Vss
NC
NC
V
V
Vss
Vss
Vss
Vss
V
G
NC
V
DDQ
VDD
V
DD
DD
DD
DD
DD
V
DD
NC
VDD
H
J
NC
NC
Vss
Vss
NC
V
DDQ
V
Vss
Vss
Vss
V
DDQ
DDQ
NC
NC
NC
V
DD
DD
DQb
DQb
DQb
DQb
DQPb
NC
DQa
NC
NC
NC
K
L
V
V
DDQ
DDQ
V
V
Vss
Vss
Vss
DQa
DQa
DQa
NC
A
V
V
Vss
Vss
VDD
V
DDQ
Vss
V
NC
NC
V
DDQ
VDD
M
N
P
NC
NC
NC
NC
Vss
Vss
V
DDQ
NC
Vss
A
NC
VDDQ
Vss
NC
TDI
V
DDQ
A
A
A
NC
A1*
TDO
TCK
TMS
A
A
0*
A
A
A
A
A
R
MODE
Note:ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.
PIN DESCRIPTIONS
MODEꢀ
ꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
Symbolꢀ
PinꢀName
TCK,ꢀTDIꢀ
TDO,ꢀTMS
A
Address Inputs
A0,ꢀA1ꢀ
ADVꢀꢀ
SynchronousꢀBurstꢀAddressꢀInputs
VDDꢀ
ꢀ
ꢀ
3.3V/2.5VꢀPowerꢀSupply
NoꢀConnect
SynchronousꢀBurstꢀAddressꢀAdvance/
Load
NCꢀ
DQxꢀ
DQPxꢀ
VDDQꢀ
DataꢀInputs/Outputs
ParityꢀDataꢀI/O
WEꢀ
SynchronousꢀRead/WriteꢀControlꢀ
Input
CLKꢀꢀ
CKE
CE
SynchronousꢀClock
Isolated output Power Supply
3.3V/2.5V
Clock Enable
VSS
Ground
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
CE2
CE2
BWxꢀ(x=a,b)ꢀ SynchronousꢀByteꢀWriteꢀInputs
OE
Output Enable
ZZ
Power Sleep Mode
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
DQPc
DQc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQPb
DQb
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
DQc
NC
DQb
V
DDQ
Vss
V
DDQ
Vss
VDDQ
VDDQ
Vss
Vss
DQc
DQc
NC
NC
DQb
DQb
NC
DQPa
DQc
DQc
Vss
DQb
DQb
Vss
DQb
DQb
Vss
DQa
DQa
Vss
V
DDQ
V
DDQ
VDDQ
VDDQ
DQc
DQb
DQb
DQa
DQc
NC
DQb
NC
DQb
Vss
NC
DQa
Vss
NC
VDD
VDD
NC
Vss
VDD
NC
Vss
VDD
ZZ
ZZ
DQa
DQa
DQb
DQb
DQa
DQa
DQd
DQd
VDDQ
V
DDQ
VDDQ
V
DDQ
Vss
Vss
DQb
Vss
Vss
DQd
DQa
DQa
DQa
DQa
DQb
DQd
DQPb
NC
NC
NC
DQd
DQd
Vss
DQa
DQa
Vss
Vss
Vss
V
DDQ
V
DDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
DQd
DQd
DQPd
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 36
1M x 18
PIN DESCRIPTIONS
CE, CE2, CE2 Synchronous Chip Enable
A0, A1
Synchronous AddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
OE
Output Enable
SynchronousꢀDataꢀInput/Output
DQa-DQdꢀ
A
Synchronous Address Inputs
SynchronousꢀClock
DQPa-DQPdꢀ ParityꢀDataꢀI/O
MODEꢀꢀ ꢀ BurstꢀSequenceꢀSelection
CLKꢀꢀ
ADVꢀꢀ
BWa-BWdꢀ
WEꢀ
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
WriteꢀEnable
Vddꢀ
VSSꢀ
Vddq
ZZ
ꢀ
ꢀ
+3.3V/2.5VꢀPowerꢀSupply
GroundꢀforꢀoutputꢀBuffer
IsolatedꢀOutputꢀBufferꢀSupply:ꢀ+3.3V/2.5V
CKE
Clock Enable
Snooze Enable
Vssꢀ
NCꢀ
ꢀ
ꢀ
GroundꢀforꢀCore
NotꢀConnected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
STATE DIAGRAM
READ
WRITE
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
WRITE
BURST
BURST
DS
DS
DS
WRITE
BURST
READ
BURST
WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE(1)
Address
Operation
Used
N/Aꢀ
N/Aꢀ
N/Aꢀ
N/Aꢀ
CE
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
CE2 CE2 ADV
WE
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
BWx
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
OE
CKE CLK
NotꢀSelectedꢀꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
NotꢀSelectedꢀ
NotꢀSelectedꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
NotꢀSelectedꢀContinueꢀ
BeginꢀBurstꢀReadꢀ
ContinueꢀBurstꢀReadꢀ
NOP/DummyꢀReadꢀ
DummyꢀReadꢀ
ExternalꢀAddressꢀ
NextꢀAddressꢀ
ExternalꢀAddressꢀ
NextꢀAddressꢀ
ExternalꢀAddressꢀ
NextꢀAddressꢀ
N/Aꢀ
Xꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
BeginꢀBurstꢀWriteꢀ
ContinueꢀBurstꢀWriteꢀ
NOP/WriteꢀAbortꢀ
WriteꢀAbortꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Xꢀ
NextꢀAddressꢀ
CurrentꢀAddressꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
IgnoreꢀClockꢀ
Notes:
1.ꢀ "X"ꢀmeansꢀdon'tꢀcare.
2.ꢀ Theꢀrisingꢀedgeꢀofꢀclockꢀisꢀsymbolizedꢀbyꢀ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.ꢀ WEꢀ=ꢀLꢀmeansꢀWriteꢀoperationꢀinꢀWriteꢀTruthꢀTable.
WEꢀ=ꢀHꢀmeansꢀReadꢀoperationꢀinꢀWriteꢀTruthꢀTable.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ASYNCHRONOUS TRUTH TABLE(1)
Operation
ZZ
OE
I/O STATUS
SleepꢀModeꢀ
Hꢀ
Xꢀ
High-Z
Readꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
DQ
High-Z
Writeꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Din,ꢀHigh-Z
High-Z
Deselectedꢀ
Notes:
1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ
2.ꢀ Forꢀwriteꢀcyclesꢀfollowingꢀreadꢀcycles,ꢀtheꢀoutputꢀbuffersꢀmustꢀbeꢀdisabledꢀwithꢀOE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4.ꢀ DeselectedꢀmeansꢀpowerꢀSleepꢀModeꢀwhereꢀstand-byꢀcurrentꢀdependsꢀonꢀcycleꢀtime.
WRITE TRUTH TABLE (x18)
Operation
WE
Hꢀ
Lꢀ
BWa
Xꢀ
BWb
READꢀ
X
H
L
WRITEꢀBYTEꢀaꢀ
WRITEꢀBYTEꢀbꢀ
WRITEꢀALLꢀBYTEsꢀ
WRITEꢀABORT/NOPꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
H
Notes:
1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ
2.ꢀ AllꢀinputsꢀinꢀthisꢀtableꢀmustꢀbeetꢀsetupꢀandꢀholdꢀtimeꢀaroundꢀtheꢀrisingꢀedgeꢀofꢀCLK.
WRITE TRUTH TABLE (x36)
Operation
WE
Hꢀ
Lꢀ
BWa
Xꢀ
BWb
Xꢀ
BWc
Xꢀ
BWd
X
READꢀ
WRITEꢀBYTEꢀaꢀ
WRITEꢀBYTEꢀbꢀ
WRITEꢀBYTEꢀcꢀ
WRITEꢀBYTEꢀdꢀ
WRITEꢀALLꢀBYTEsꢀ
WRITEꢀABORT/NOPꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
H
Lꢀ
Hꢀ
H
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
Hꢀ
Hꢀ
H
Notes:
1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ
2.ꢀ AllꢀinputsꢀinꢀthisꢀtableꢀmustꢀbeetꢀsetupꢀandꢀholdꢀtimeꢀaroundꢀtheꢀrisingꢀedgeꢀofꢀCLK.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ
9
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
WRITE TRUTH TABLE (x72)
Operation
WE
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
BWa
Xꢀ
BWb
Xꢀ
BWc
Xꢀ
BWd
Xꢀ
BWe
Xꢀ
BWf
Xꢀ
BWg
Xꢀ
BWh
X
READꢀ
WRITEꢀBYTEꢀaꢀ
WRITEꢀBYTEꢀbꢀ
WRITEꢀBYTEꢀcꢀ
WRITEꢀBYTEꢀdꢀ
WRITEꢀBYTEꢀeꢀ
WRITEꢀBYTEꢀfꢀ
WRITEꢀBYTEꢀgꢀ
WRITEꢀBYTEꢀhꢀ
WRITEꢀALLꢀBYTEsꢀ
WRITEꢀABORT/NOPꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Hꢀ
Lꢀ
H
Hꢀ
Lꢀ
L
L
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
H
Notes:
1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ
2.ꢀ AllꢀinputsꢀinꢀthisꢀtableꢀmustꢀbeetꢀsetupꢀandꢀholdꢀtimeꢀaroundꢀtheꢀrisingꢀedgeꢀofꢀCLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd orꢀNC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAꢀIMUM RATINGS(1)
Symbol
TSTG
Parameter
Value
–65ꢀtoꢀ+150ꢀ
1.6ꢀ
Unit
°C
W
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
Output Current (per I/O)
ꢀ
ꢀ
Pd
IouT
100
mA
V
VIn, VouTꢀ
VInꢀ
VoltageꢀRelativeꢀtoꢀVSSꢀforꢀI/OꢀPinsꢀ
ꢀ
ꢀ
–0.5ꢀtoꢀVddq + 0.5
–0.5ꢀtoꢀ4.6
VoltageꢀRelativeꢀtoꢀVSSꢀforꢀꢀ
V
for Address and Control Inputs
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2.ꢀThisꢀdeviceꢀcontainsꢀcircuityꢀtoꢀprotectꢀtheꢀinputsꢀagainstꢀdamageꢀdueꢀtoꢀhighꢀstaticꢀvoltagesꢀorꢀelectricꢀfields;ꢀhowever,ꢀprecau-
tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3.ꢀThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputꢀdevicesꢀareꢀinꢀHigh-Zꢀatꢀpowerꢀup.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
OPERATING RANGE (IS61NLFx)
Range
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
VDD
VDDq
ꢀ
ꢀ
Commercialꢀ
Industrialꢀ
3.3Vꢀ±ꢀ5%ꢀ
3.3Vꢀ±ꢀ5%ꢀ
3.3Vꢀ/ꢀ2.5Vꢀ±ꢀ5%
3.3Vꢀ/ꢀ2.5Vꢀ±ꢀ5%
-40°Cꢀtoꢀ+85°Cꢀ
OPERATING RANGE (IS61NVFx)
Range
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
VDD
VDDq
ꢀ
ꢀ
Commercialꢀ
Industrialꢀ
2.5Vꢀ±ꢀ5%ꢀ
2.5Vꢀ±ꢀ5%ꢀ
ꢀ2.5Vꢀ±ꢀ5%
2.5Vꢀ±ꢀ5%
-40°Cꢀtoꢀ+85°Cꢀ
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
Voh
OutputꢀHIGHꢀVoltageꢀ
Ioh = –4.0ꢀmAꢀ (3.3V)ꢀ
Ioh = –1.0ꢀmA (2.5V)
2.4ꢀ
—ꢀ
2.0ꢀ
—ꢀ
V
Vol
OutputꢀLOWꢀVoltageꢀ
Iol = 8.0ꢀmA (3.3V)ꢀ
Iol = 1.0 mA (2.5V)
—ꢀ
0.4ꢀ
—ꢀ
0.4ꢀ
V
(1)
VIh
InputꢀHIGHꢀVoltageꢀꢀ
InputꢀLOWꢀVoltage
ꢀ
2.0ꢀ
–0.3ꢀ
–5ꢀ
Vdd + 0.3
1.7
–0.3ꢀ
–5ꢀ
Vdd + 0.3
V
V
(1)
VIl
ꢀ
0.8ꢀ
5ꢀ
0.7ꢀ
5ꢀ
IlI
InputꢀLeakageꢀCurrentꢀ
OutputꢀLeakageꢀCurrent
VSS ≤ VIn ≤ Vdd(2)ꢀ
µA
µA
Ilo
VSS ≤ VouT ≤ Vddq, OE = VIhꢀ
–5ꢀ
5ꢀ
–5ꢀ
5ꢀ
Note:
1.ꢀOvershoot:ꢀVIhꢀ(AC)ꢀ<ꢀVddꢀ+ꢀ2.0Vꢀ(Pulseꢀwidthꢀlessꢀthanꢀtkc/2).ꢀUndershoot:ꢀVIlꢀ(AC)ꢀ>ꢀ-2Vꢀ(Pulseꢀwidthꢀlessꢀthanꢀtkc/2).
2.ꢀ MODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀVddꢀorꢀVSS.ꢀItꢀexhibitsꢀ±100ꢀµAꢀmaximumꢀleakageꢀcurrentꢀwhenꢀtiedꢀtoꢀ≤
VSSꢀ+ꢀ0.2Vꢀorꢀ≥ꢀVddꢀ–ꢀ0.2V.
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
6.5
7.5
MAꢀ
MAꢀ
Symbol Parameter
Test Conditions
Temp. range x18
x36
x72
x18
x36
x72
Unit
Icc
ACꢀOperatingꢀ
Supply Current
DeviceꢀSelected,ꢀꢀ
OE = VIh, ZZ ≤ VIl,
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
CycleꢀTimeꢀ≥ tkc min.
Device Deselected,
Vdd = Max.,
All Inputs ≤ VIl or ≥ VIh,
ZZ ≤ VIl, f = Max.
Device Deselected,
Vdd = Max.,
Com.ꢀ
Ind.
450ꢀ
500ꢀ
450ꢀ
500ꢀ
600ꢀ
650ꢀ
425ꢀ
475ꢀ
425ꢀ
475ꢀ
550ꢀ
600
mA
mA
mA
ꢀ ꢀ
ꢀ
ISb
ꢀ ꢀ
Standby Current
TTLꢀInputꢀ
com.
Ind.
150
150
150
150
150
150
150
150
150
150
150
150
ISbI
Standby Current
cmoS Input
Com.
Ind.
110
125
110
125
110
125
110
125
110
125
110
125
ꢀ ꢀ
ꢀ
VIn ≤ꢀꢀVSS +ꢀ0.2Vꢀorꢀ≥ꢀVdd –ꢀ0.2V
f = 0
ISb2
SleepꢀModeꢀ
ZZꢀ>ꢀVIhꢀꢀ
Com.ꢀ
60ꢀ
60ꢀ
60ꢀ
60ꢀ
60ꢀ
60ꢀ
mAꢀ
Ind.
75
75
75
75
75
75
Note:
1.ꢀ MODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀVddꢀorꢀVSS.ꢀItꢀexhibitsꢀ±100ꢀµAꢀmaximumꢀleakageꢀcurrentꢀwhenꢀtiedꢀtoꢀ≤
VSSꢀ+ꢀ0.2Vꢀorꢀ≥ꢀVddꢀ–ꢀ0.2V.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIn = 0V
Max.
6ꢀ
Unit
pF
cIn
Input Capacitance
Input/Output Capacitance
couT
VouT = 0V
8ꢀ
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTA = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ3.0V
1.5ꢀns
ꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevel
1.5V
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
2.5V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ2.5V
1.5ꢀns
ꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevel
1.25V
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ3ꢀandꢀ4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
6.5
Min.
7.5
Min. Max.
Symbol
ꢀ fmaxꢀ
Parameter
Max.
133ꢀ
—ꢀ
—ꢀ
—ꢀ
6.5ꢀ
—ꢀ
—ꢀ
3.8ꢀ
3.2ꢀ
—ꢀꢀ
3.5ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
Unit
MHz
ns
ClockꢀFrequencyꢀ
—ꢀ
7.5ꢀ
2.2ꢀ
2.2ꢀ
—ꢀ
—ꢀ 117ꢀ
8.5ꢀ —ꢀ
2.5ꢀ —ꢀ
2.5ꢀ —ꢀ
—ꢀ 7.5ꢀ
2.5ꢀ —ꢀ
2.5ꢀ —ꢀ
—ꢀ 4.0ꢀ
—ꢀ 3.4ꢀ
tkcꢀ
tkhꢀ
tklꢀ
tkqꢀ
CycleꢀTimeꢀ
ClockꢀHighꢀTimeꢀ
ns
ClockꢀLowꢀTimeꢀ
ns
ClockꢀAccessꢀTimeꢀꢀ
ns
(2)
tkqx ꢀ
tkqlZ(2,3)ꢀ
tkqhZ(2,3)ꢀ
toeqꢀ
toelZ(2,3)ꢀ
toehZ(2,3)ꢀ
tASꢀ
ClockꢀHighꢀtoꢀOutputꢀInvalidꢀ
ClockꢀHighꢀtoꢀOutputꢀLow-Zꢀ
ClockꢀHighꢀtoꢀOutputꢀHigh-Zꢀꢀ
OutputꢀEnableꢀtoꢀOutputꢀValidꢀꢀ
OutputꢀEnableꢀtoꢀOutputꢀLow-Zꢀ
OutputꢀDisableꢀtoꢀOutputꢀHigh-Zꢀꢀ
AddressꢀSetupꢀTimeꢀꢀ
Read/WriteꢀSetupꢀTimeꢀꢀ
ChipꢀEnableꢀSetupꢀTimeꢀꢀ
ClockꢀEnableꢀSetupꢀTimeꢀ
AddressꢀAdvanceꢀSetupꢀTimeꢀꢀ
DataꢀSetupꢀTimeꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
ns
ns
ns
—ꢀ
ns
0ꢀ
0ꢀꢀ
—ꢀ
ns
—ꢀ
—ꢀ 3.5ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
0.5ꢀ —ꢀ
0.5ꢀ —ꢀ
0.5ꢀꢀ —ꢀ
0.5ꢀꢀ —ꢀ
0.5ꢀꢀ —ꢀ
0.5ꢀ —ꢀ
ns
1.5ꢀ
1.5ꢀ
1.5ꢀ
1.5ꢀ
1.5ꢀ
1.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
—ꢀ
ns
twSꢀ
ns
tceSꢀ
ns
tSeꢀ
ns
tAdVSꢀ
tdSꢀ
ns
ns
tAhꢀ
AddressꢀHoldꢀTimeꢀ
ns
the
ClockꢀEnableꢀHoldꢀTimeꢀ
WriteꢀHoldꢀTimeꢀꢀ
ns
twhꢀ
ns
tcehꢀ
tAdVhꢀ
tdhꢀ
ChipꢀEnableꢀHoldꢀTimeꢀꢀ
AddressꢀAdvanceꢀHoldꢀTimeꢀꢀ
DataꢀHoldꢀTimeꢀ
ns
ns
ns
tPdSꢀ
ZZꢀHighꢀtoꢀPowerꢀDownꢀꢀ
ZZꢀLowꢀtoꢀPowerꢀDownꢀꢀ
—ꢀꢀ
—ꢀꢀ
2ꢀ
2ꢀ
cyc
cyc
tPuSꢀ
—ꢀ
2ꢀ
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2.ꢀ Guaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled.
3.ꢀ TestedꢀwithꢀloadꢀinꢀFigureꢀ2.
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IS61NLF102418/IS61NVF102418
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
Min.
Max.
60ꢀ
2
Unit
mA
ISb2ꢀ
tPdS
tPuS
tZZIꢀ
CurrentꢀduringꢀSLEEPꢀMODEꢀ
ZZꢀ≥ꢀVIhꢀ
ꢀ
ZZ active to input ignored
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZꢀactiveꢀtoꢀSLEEPꢀcurrentꢀ
ZZꢀinactiveꢀtoꢀexitꢀSLEEPꢀcurrentꢀ
2
ꢀ
ꢀ
2ꢀ
0ꢀ
ꢀ
ꢀ
trZZIꢀ
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
tZZI
Isupply
All Inputs
I
SB2
t
RZZI
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
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READ CYCLE TIMING
t
KH
tKL
CLK
t
KC
tADVS tADVH
ADV
tAS tAH
Address
A1
A2
A3
tWS
tWH
WRITE
CKE
t
SE tHE
t
CES
t
CEH
CE
OE
KQX tKQ
t
OEQ
t
OEHZ
t
t
KQHZ
Q3-4
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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WRITE CYCLE TIMING
t
KH
tKL
CLK
tKC
ADV
Address
WRITE
CKE
A1
A2
A3
tSE
tHE
CE
OE
tDS
t
DH
Data In
Data Out
D1-1
D2-1
D2-2
D2-4
D3-1
D3-2
D3-3
D3-4
D2-3
tOEHZ
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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IS61NLF102418/IS61NVF102418
SINGLE READ/WRITE CYCLE TIMING
t
KH
tKL
CLK
t
SE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
t
OEQ
tOELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
t
DS
tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
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IS61NLF102418/IS61NVF102418
CKE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
ADV
OE
tKQ
tKQHZ
tKQLZ
Q4
Data Out
Data In
Q1
Q3
t
DS
t
DH
D5
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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CE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CE
ADV
OE
tOEQ
t
KQHZ
tKQ
t
OELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D3
D5
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
TheꢀIS61NLFXꢀandꢀꢀIS61NVFXꢀhaveꢀaꢀserialꢀboundaryꢀ
scanꢀTestꢀAccessꢀPortꢀ(TAP)ꢀinꢀtheꢀPBGAꢀpackageꢀonly.ꢀ
(NotꢀavailableꢀinꢀTQFPꢀpackage.)ꢀThisꢀportꢀoperatesꢀinꢀ
accordancewithIEEEꢀStandardꢀ1149.1-1900,ꢀbutꢀdoesꢀnotꢀ
includeꢀallꢀfunctionsꢀrequiredꢀforꢀfullꢀ1149.1ꢀcompliance.ꢀ
TheseꢀfunctionsꢀfromꢀtheꢀIEEE specification are excluded
because they place added delay in the critical speed path
ofꢀtheꢀSRAM.ꢀTheꢀTAPꢀcontrollerꢀoperatesꢀinꢀaꢀmannerꢀthatꢀ
does not conflict with the performance of other devices us-
ingꢀ1149.1ꢀfullyꢀcompliantꢀTAPs.ꢀTheꢀTAPꢀoperatesꢀusingꢀ
JEDECꢀstandardꢀ2.5VꢀI/Oꢀlogicꢀlevels.
TheꢀtestꢀclockꢀisꢀonlyꢀusedꢀwithꢀtheꢀTAPꢀcontroller.ꢀAllꢀinputsꢀ
areꢀcapturedꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputsꢀareꢀ
drivenꢀfromꢀtheꢀfallingꢀedgeꢀofꢀTCK.
TEST MODE SELECT (TMS)
TheꢀTMSꢀinputꢀisꢀusedꢀtoꢀsendꢀcommandsꢀtoꢀtheꢀTAPꢀ
controllerꢀandꢀisꢀsampledꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCK.ꢀThisꢀ
pinꢀmayꢀbeꢀleftꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀnotꢀused.ꢀTheꢀ
pinꢀisꢀinternallyꢀpulledꢀup,ꢀresultingꢀinꢀaꢀlogicꢀHIGHꢀlevel.
TEST DATA-IN (TDI)
TheꢀTDIꢀpinꢀisꢀusedꢀtoꢀseriallyꢀinputꢀinformationꢀtoꢀtheꢀ
registers and can be connected to the input of any regis-
ter.ꢀTheꢀregisterꢀbetweenꢀTDIꢀandꢀTDOꢀisꢀchosenꢀbyꢀtheꢀ
instructionꢀ loadedꢀ intoꢀ theꢀTAPꢀ instructionꢀ register.ꢀ Forꢀ
informationꢀonꢀinstructionꢀregisterꢀloading,ꢀseeꢀtheꢀTAPꢀ
ControllerꢀStateꢀDiagram.ꢀTDIꢀisꢀinternallyꢀpulledꢀupꢀandꢀ
canꢀbeꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀunusedꢀinꢀanꢀapplica-
tion.ꢀTDIꢀisꢀconnectedꢀtoꢀtheꢀMostꢀSignificantꢀBitꢀ(MSB)ꢀ
on any register.
DISABLING THE JTAG FEATURE
TheꢀSRAMꢀcanꢀoperateꢀwithoutꢀusingꢀtheꢀJTAGꢀfeature.ꢀ
Toꢀ disableꢀ theꢀTAPꢀ controller,ꢀTCKꢀ mustꢀ beꢀ tiedꢀ LOWꢀ
(VSS)ꢀtoꢀpreventꢀclockingꢀofꢀtheꢀdevice.ꢀTDIꢀandꢀTMSꢀareꢀ
internallyꢀpulledꢀupꢀandꢀmayꢀbeꢀdisconnected.ꢀTheyꢀmayꢀ
alternatelyꢀbeꢀconnectedꢀtoꢀVdd through a pull-up resistor.
TDOꢀshouldꢀbeꢀleftꢀdisconnected.ꢀOnꢀpower-up,ꢀtheꢀdeviceꢀ
will start in a reset state which will not interfere with the
device operation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
22
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TEST DATA OUT (TDO)
Boundary Scan Register
TheꢀTDOꢀoutputꢀpinꢀisꢀusedꢀtoꢀseriallyꢀclockꢀdata-outꢀfromꢀ
theꢀregisters.ꢀTheꢀoutputꢀisꢀactiveꢀdependingꢀonꢀtheꢀcurrentꢀ
state of the TAP state machine (see TAP Controller State
Diagram).ꢀTheꢀoutputꢀchangesꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCKꢀ
andꢀTDOꢀisꢀconnectedꢀtoꢀtheꢀLeastꢀSignificantꢀBitꢀ(LSB)ꢀ
of any register.
Theꢀboundaryꢀscanꢀregisterꢀisꢀconnectedꢀtoꢀallꢀinputꢀandꢀ
output pins on the SRAM.Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
densityꢀdevices.ꢀTheꢀx36ꢀconfigurationꢀhasꢀaꢀ75-bit-longꢀ
registerꢀandꢀtheꢀx18ꢀconfigurationꢀalsoꢀhasꢀaꢀ75-bit-longꢀ
register.ꢀTheꢀboundaryꢀscanꢀregisterꢀisꢀloadedꢀwithꢀtheꢀ
contentsꢀofꢀtheꢀRAMꢀInputꢀandꢀOutputꢀringꢀwhenꢀtheꢀTAPꢀ
controllerꢀisꢀinꢀtheꢀCapture-DRꢀstateꢀandꢀthenꢀplacedꢀbe-
tween the TDI and TDO pins when the controller is moved
to the Shift-DRꢀstate.ꢀTheꢀEXTEST,ꢀSAMPLE/PRELOADꢀ
andꢀSAMPLE-Zꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀcaptureꢀtheꢀ
contents of the Input and Output ring.
PERFORMING A TAP RESET
AꢀResetꢀisꢀperformedꢀbyꢀforcingꢀTMSꢀHIGHꢀ(Vdd) for five
risingꢀedgesꢀofꢀTCK.ꢀRESETꢀmayꢀbeꢀperformedꢀwhileꢀtheꢀ
SRAMꢀisꢀoperatingꢀandꢀdoesꢀnotꢀaffectꢀitsꢀoperation.ꢀAtꢀ
power-up,ꢀtheꢀTAPꢀisꢀinternallyꢀresetꢀtoꢀensureꢀthatꢀTDOꢀ
comes up in a high-Z state.
TheꢀBoundaryꢀScanꢀOrderꢀtablesꢀshowꢀtheꢀorderꢀinꢀwhichꢀ
the bits are connected.Each bit corresponds to one of the
bumpsꢀonꢀtheꢀSRAMꢀpackage.ꢀTheꢀMSBꢀofꢀtheꢀregisterꢀ
isꢀconnectedꢀtoꢀTDI,ꢀandꢀtheꢀLSBꢀisꢀconnectedꢀtoꢀTDO.
TAP REGISTERS
RegistersꢀareꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ
andꢀallowꢀdataꢀtoꢀbeꢀscannedꢀintoꢀandꢀoutꢀofꢀtheꢀSRAMꢀ
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
intoꢀtheꢀTDIꢀpinꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputꢀonꢀ
theꢀTDOꢀpinꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCK.
Scan Register Sizes
Register
Name
Bit Size
(x18)
3
Bit Size
(x36)
3
Bit Size
(x72)
3
Instruction Register
Instruction
Bypassꢀ
ID
Three-bitꢀinstructionsꢀcanꢀbeꢀseriallyꢀloadedꢀintoꢀtheꢀin-
structionꢀregister.ꢀThisꢀregisterꢀisꢀloadedꢀwhenꢀitꢀisꢀplacedꢀ
between the TDI and TDO pins. (See TAPꢀControllerꢀBlockꢀ
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
1ꢀ
1ꢀ
1
32
32
32
BoundaryꢀScanꢀ
75ꢀ
75ꢀ
TBD
Identification (ID) Register
WhenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCaptureIRꢀstate,ꢀtheꢀtwoꢀ
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
TheꢀIDꢀregisterꢀisꢀloadedꢀwithꢀaꢀvendor-specific,ꢀ32-bitꢀ
codeꢀduringꢀtheꢀCapture-DRꢀstateꢀwhenꢀtheꢀIDCODEꢀcom-
mandꢀisꢀloadedꢀtoꢀtheꢀinstructionꢀregister.ꢀTheꢀIDCODEꢀ
isꢀhardwiredꢀintoꢀtheꢀSRAMꢀandꢀcanꢀbeꢀshiftedꢀoutꢀwhenꢀ
theꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀShift-DRꢀstate.ꢀTheꢀIDꢀregisterꢀ
has vendor code and other information described in the
IdentificationꢀRegisterꢀDefinitionsꢀtable.
Bypass Register
Toꢀsaveꢀtimeꢀwhenꢀseriallyꢀshiftingꢀdataꢀthroughꢀregisters,ꢀ
itꢀisꢀsometimesꢀadvantageousꢀtoꢀskipꢀcertainꢀstates.ꢀTheꢀ
bypass register is a single-bit register that can be placed
betweenꢀTDIꢀandꢀTDOꢀpins.ꢀThisꢀallowsꢀdataꢀtoꢀbeꢀshiftedꢀ
through the SRAMꢀwithꢀminimalꢀdelay.ꢀTheꢀbypassꢀregisterꢀ
isꢀsetꢀLOWꢀ(VSS)ꢀwhenꢀtheꢀBYPASSꢀinstructionꢀisꢀexecuted.
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Description
256K x 72
xxxxꢀ
512K x 36
xxxxꢀ
1M x 18
xxxxꢀ
RevisionꢀNumberꢀ (31:28)ꢀꢀ
DeviceꢀDepthꢀ (27:23)ꢀ
DeviceꢀWidthꢀ (22:18)ꢀ
ISSIꢀDeviceꢀIDꢀ (17:12)ꢀ
ISSIꢀJEDECꢀIDꢀ (11:1)ꢀ
IDꢀRegisterꢀPresenceꢀ (0)ꢀ
Reservedꢀforꢀversionꢀnumber.ꢀ
DefinesꢀdepthꢀofꢀSRAM.ꢀ512Kꢀorꢀ1Mꢀ
DefinesꢀWidthꢀofꢀtheꢀSRAM.ꢀx72,ꢀx36ꢀorꢀx18ꢀ
Reservedꢀforꢀfutureꢀuse.ꢀ
00110ꢀ
00101ꢀ
xxxxꢀ
00111ꢀ
00100ꢀ
xxxxxꢀ
01000ꢀ
00011ꢀ
xxxxxꢀ
AllowsꢀuniqueꢀidentificationꢀofꢀSRAMꢀvendor.ꢀ
IndicateꢀtheꢀpresenceꢀofꢀanꢀIDꢀregister.ꢀ
0011010101ꢀ 00011010101ꢀ 00011010101
1ꢀ 1ꢀ 1ꢀ
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TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Codeꢀtable.ꢀThreeꢀinstructionsꢀareꢀlistedꢀasꢀRESERVED
and should not be used and the other five instructions are
describedꢀbelow.ꢀTheꢀTAPꢀcontrollerꢀusedꢀinꢀthisꢀSRAMꢀ
isꢀnotꢀfullyꢀcompliantꢀwithꢀtheꢀ1149.1ꢀconventionꢀbecauseꢀ
some mandatory instructions are not fully implemented.
TheꢀTAPꢀcontrollerꢀcannotꢀbeꢀusedꢀtoꢀloadꢀaddress,ꢀdataꢀorꢀ
control signals and cannot preload the Input or Output buf-
fers.ꢀTheꢀSRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instruc-
tionsꢀareꢀloadedꢀintoꢀtheꢀTAPꢀcontrollerꢀduringꢀtheꢀShift-IRꢀ
stateꢀwhenꢀtheꢀinstructionꢀregisterꢀisꢀplacedꢀbetweenꢀTDIꢀ
andꢀTDO.ꢀDuringꢀthisꢀstate,ꢀinstructionsꢀareꢀshiftedꢀfromꢀ
theꢀinstructionꢀregisterꢀthroughꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀToꢀ
executeꢀanꢀinstructionꢀonceꢀitꢀisꢀshiftedꢀin,ꢀtheꢀTAPꢀcontrol-
lerꢀmustꢀbeꢀmovedꢀintoꢀtheꢀUpdate-IRꢀstate.
SAMPLE/PRELOADꢀisꢀaꢀ1149.1ꢀmandatoryꢀinstruction.ꢀTheꢀ
PRELOADꢀportionꢀofꢀthisꢀinstructionꢀisꢀnotꢀimplemented,ꢀsoꢀ
theꢀTAPꢀcontrollerꢀisꢀnotꢀfullyꢀ1149.1ꢀcompliant.ꢀWhenꢀtheꢀ
SAMPLE/PRELOADꢀinstructionꢀisꢀloadedꢀtoꢀtheꢀinstruc-
tionꢀregisterꢀandꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCapture-DRꢀ
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
ItꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀtheꢀTAPꢀcontrollerꢀclockꢀoper-
atesꢀatꢀaꢀfrequencyꢀupꢀtoꢀ10ꢀMHz,ꢀwhileꢀtheꢀSRAMꢀclockꢀ
runsꢀmoreꢀthanꢀanꢀorderꢀofꢀmagnitudeꢀfaster.ꢀBecauseꢀofꢀ
the clock frequency differences, it is possible that during
theꢀCapture-DRꢀstate,ꢀanꢀinputꢀorꢀoutputꢀwillꢀunder-goꢀaꢀ
transition.ꢀTheꢀTAPꢀmayꢀattemptꢀaꢀsignalꢀcaptureꢀwhileꢀinꢀ
transitionꢀ(metastableꢀstate).ꢀTheꢀdeviceꢀwillꢀnotꢀbeꢀharmed,ꢀ
but there is no guarantee of the value that will be captured
or repeatable results.
Toꢀguaranteeꢀthatꢀtheꢀboundaryꢀscanꢀregisterꢀwillꢀcaptureꢀ
theꢀcorrectꢀsignalꢀvalue,ꢀtheꢀSRAMꢀsignalꢀmustꢀbeꢀstabilizedꢀ
longꢀenoughꢀtoꢀmeetꢀtheꢀTAPꢀcontroller’sꢀcaptureꢀset-upꢀ
plusholdtimes(tcS andtch).ꢀToꢀinsureꢀthatꢀtheꢀSRAMꢀclockꢀ
input is captured correctly, designs need a way to stop (or
slow)ꢀtheꢀclockꢀduringꢀaꢀSAMPLE/PRELOADꢀinstruction.ꢀ
If this is not an issue, it is possible to capture all other
signalsꢀandꢀsimplyꢀignoreꢀtheꢀvalueꢀofꢀtheꢀCLKꢀcapturedꢀ
in the boundary scan register.
EꢀTEST
EXTESTꢀisꢀaꢀmandatoryꢀ1149.1ꢀinstructionꢀwhichꢀisꢀtoꢀbeꢀ
executed whenever the instruction register is loaded with
allꢀ0s.ꢀBecauseꢀEXTESTꢀisꢀnotꢀimplementedꢀinꢀtheꢀTAPꢀ
controller,ꢀthisꢀdeviceꢀisꢀnotꢀ1149.1ꢀstandardꢀcompliant.ꢀ
TheꢀTAPꢀcontrollerꢀrecognizesꢀanꢀall-0ꢀinstruction.ꢀWhenꢀanꢀ
EXTESTꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregister,ꢀ
theꢀSRAMꢀrespondsꢀasꢀifꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ
hasꢀbeenꢀloaded.ꢀThereꢀisꢀaꢀdifferenceꢀbetweenꢀtheꢀinstruc-
tions, unlike the SAMPLE/PRELOADꢀinstruction,ꢀEXTESTꢀ
placesꢀtheꢀSRAMꢀoutputsꢀinꢀaꢀHigh-Zꢀstate.
Once the data is captured, it is possible to shift out the data
byꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀShift-DRꢀstate.ꢀThisꢀplacesꢀtheꢀ
boundaryꢀscanꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpins.
NoteꢀthatꢀsinceꢀtheꢀPRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-
DR state while performing a SAMPLE/PRELOAD instruction
willꢀhaveꢀtheꢀsameꢀeffectꢀasꢀtheꢀPause-DRꢀcommand.
IDCODE
Theꢀ IDCODEꢀ instructionꢀ causesꢀ aꢀ vendor-specific,ꢀ 32-
bit code to be loaded into the instruction register. It also
placesꢀtheꢀinstructionꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ
pins and allows the IDCODE to be shifted out of the device
whenꢀtheꢀTAPꢀcontrollerꢀentersꢀtheꢀShift-DRꢀstate.ꢀTheꢀ
IDCODE instruction is loaded into the instruction register
uponꢀpower-upꢀorꢀwheneverꢀtheꢀTAPꢀcontrollerꢀisꢀgivenꢀaꢀ
test logic reset state.
BYPASS
WhenꢀtheꢀBYPASSꢀinstructionꢀisꢀloadedꢀinꢀtheꢀinstruc-
tionꢀregisterꢀandꢀtheꢀTAPꢀisꢀplacedꢀinꢀaꢀShift-DRꢀstate,ꢀ
theꢀbypassꢀregisterꢀisꢀplacedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ
pins.ꢀTheꢀadvantageꢀofꢀtheꢀBYPASSꢀinstructionꢀisꢀthatꢀitꢀ
shortens the boundary scan path when multiple devices
are connected together on a board.
SAMPLE-Z
RESERVED
Theꢀ SAMPLE-Zꢀ instructionꢀ causesꢀ theꢀ boundaryꢀ scanꢀ
registerꢀtoꢀbeꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ
whenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀaꢀShift-DRꢀstate.ꢀItꢀalsoꢀplacesꢀ
allꢀSRAMꢀoutputsꢀintoꢀaꢀHigh-Zꢀstate.
Theseꢀinstructionsꢀareꢀnotꢀimplementedꢀbutꢀareꢀreservedꢀ
for future use. Do not use these instructions.
24
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
INSTRUCTION CODES
Code
Instruction
Description
000ꢀ
EXTESTꢀ
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbe-
tweenꢀtheꢀTDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputsꢀtoꢀHigh-Zꢀstate.ꢀThisꢀ
instructionꢀisꢀnotꢀ1149.1ꢀcompliant.
001ꢀ
010ꢀ
IDCODEꢀ
LoadsꢀtheꢀIDꢀregisterꢀwithꢀtheꢀvendorꢀIDꢀcodeꢀandꢀplacesꢀtheꢀregisterꢀbetweenꢀTDIꢀ
andꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀaffectꢀSRAMꢀoperation.
SAMPLE-Zꢀ
CapturesꢀtheꢀInput/Outputꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbetweenꢀ
TDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputꢀdriversꢀtoꢀaꢀHigh-Zꢀstate.
011ꢀ
RESERVEDꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDIꢀandꢀTDO.ꢀDoesꢀnotꢀaffectꢀtheꢀSRAMꢀoperation.ꢀThisꢀinstructionꢀdoesꢀnotꢀ
implementꢀ1149.1ꢀpreloadꢀfunctionꢀandꢀisꢀthereforeꢀnotꢀ1149.1ꢀcompliant.
101ꢀ
110ꢀꢀ
111ꢀ
RESERVEDꢀ
RESERVEDꢀ
BYPASSꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.ꢀꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.
PlacesꢀtheꢀbypassꢀregisterꢀbetweenꢀTDIꢀandꢀTDO.ꢀThisꢀoperationꢀdoesꢀnot
affectꢀSRAMꢀoperation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
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25
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
TAP Electrical Characteristics OverꢀtheꢀOperatingꢀRange(1,2)
Symbol
Voh1
Voh2
Vol1
Vol2
VIh
Parameter
Test Conditions
Iohꢀ=ꢀ–2.0ꢀmAꢀ
Iohꢀ=ꢀ–100ꢀµA
Iol = 2.0 mAꢀ
Iol = 100 µAꢀ
Min.
1.7ꢀ
2.1ꢀ
—ꢀ
Max.
—ꢀ
Units
V
OutputꢀHIGHꢀVoltage
OutputꢀHIGHꢀVoltage
OutputꢀLOWꢀVoltage
OutputꢀLOWꢀVoltage
InputꢀHIGHꢀVoltage
InputꢀLOWꢀVoltage
InputꢀLeakageꢀCurrent
—ꢀ
V
0.7ꢀ
V
—ꢀ
0.2ꢀ
V
1.7
Vdd +0.3ꢀ
0.7ꢀ
V
VIl
–0.3ꢀ
–10ꢀ
V
Ix
VSS ≤ꢀVꢀIꢀ≤ꢀVddq
10ꢀ
µA
Notes:
1.ꢀ AllꢀVoltageꢀreferencedꢀtoꢀGround.
2.ꢀ Overshoot:ꢀVIh (AC) ≤ꢀꢀVddꢀ+1.5Vꢀforꢀtꢀ≤ tTcyc/2,
ꢀ
ꢀ
Undershoot:ꢀVIl (AC) ≤ ꢀ0.5Vꢀforꢀtꢀ≤ tTcyc/2,
Power-up:ꢀVIhꢀ<ꢀ2.6VꢀandꢀVddꢀ<ꢀ2.4VꢀandꢀVddqꢀ<ꢀ1.4Vꢀforꢀtꢀ<ꢀ200ꢀms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
100ꢀ
—ꢀ
Max.
—ꢀ
10
Unit
ns
tTcyc
fTf
TCKꢀClockꢀcycleꢀtime
TCKꢀClockꢀfrequencyꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MHz
ns
tTh
TCKꢀClockꢀHIGH
40ꢀ
40ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
—ꢀ
—
tTl
TCKꢀClockꢀLOWꢀ
—
ns
tTmSS
tTdIS
tcS
TMSꢀsetupꢀtoꢀTCKꢀClockꢀRise
TDIꢀsetupꢀtoꢀTCKꢀClockꢀRise
CaptureꢀsetupꢀtoꢀTCKꢀRise
TMSꢀholdꢀafterꢀTCKꢀClockꢀRise
TDIꢀHoldꢀafterꢀClockꢀRise
CaptureꢀholdꢀafterꢀClockꢀRise
TCKꢀLOWꢀtoꢀTDOꢀvalidꢀ
TCKꢀLOWꢀtoꢀTDOꢀinvalid
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20
ns
ns
ns
tTmSh
tTdIh
tch
ns
ns
ns
tTdoV
ꢀ
ꢀ
ns
tTdox
0ꢀ
—ꢀ
ns
Notes:
1. tcS and tch refer to the set-up and hold time requirements of latching data from the boundary scan register.
2.ꢀTestꢀconditionsꢀareꢀspecifiedꢀusingꢀtheꢀloadꢀinꢀTAPꢀACꢀtestꢀconditions.ꢀtr/tf = 1 ns.
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
TAP AC TEST CONDITIONS (2.5V/3.3V)
TAP Output Load Equivalent
Inputꢀpulseꢀlevelsꢀ
0ꢀtoꢀ2.5V/0ꢀtoꢀ3.0V
1ns
Input rise and fall times
Inputꢀtimingꢀreferenceꢀlevelsꢀ
Outputꢀreferenceꢀlevelsꢀ
1.25V/1.5V
1.25V/1.5V
50Ω
Vtrig
Testꢀloadꢀterminationꢀsupplyꢀvoltageꢀ
Vtrigꢀ
1.25V/1.5V
1.25V/1.5V
TDO
20 pF
GND
Z0
= 50Ω
TAP TIMING
1
2
3
4
5
6
tTHTH
tTLTH
TCK
TMS
tTHTL
t
t
MVTH THMX
t
DVTH
tTHDX
TDI
tTLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
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Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
209 BOUNDARY SCAN ORDER (256K ꢀ 72)
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IS61NLF102418/IS61NVF102418
165 PBGA BOUNDARY SCAN ORDER (x 36)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit # Name
ID
Bit #
41ꢀ
42ꢀ
43ꢀ
44ꢀ
45ꢀ
46ꢀ
47ꢀ
48ꢀ
49ꢀ
50ꢀ
51ꢀ
52ꢀ
53ꢀ
54ꢀ
55ꢀ
56ꢀ
57ꢀ
58ꢀ
59ꢀ
60ꢀ
Bit #
61ꢀ
62ꢀ
63ꢀ
64ꢀ
65ꢀ
66ꢀ
67ꢀ
68ꢀ
69ꢀ
70ꢀ
71ꢀ
72ꢀ
73ꢀ
74ꢀ
75ꢀ
ꢀ
Name
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
Aꢀ
ID
ꢀ 1ꢀ
ꢀ 2ꢀ
ꢀ 3ꢀ
ꢀ 4ꢀ
ꢀ 5ꢀ
ꢀ 6ꢀ
ꢀ 7ꢀ
ꢀ 8ꢀ
ꢀ 9ꢀ
ꢀ10ꢀ
ꢀ11ꢀ
ꢀ12ꢀ
ꢀ13ꢀ
ꢀ14ꢀ
ꢀ15ꢀ
ꢀ16ꢀ
ꢀ17ꢀ
ꢀ18ꢀ
ꢀ19ꢀ
ꢀ20ꢀ
MODEꢀ 1Rꢀ
21ꢀ
22ꢀ
23ꢀ
24ꢀ
25ꢀ
26ꢀ
27ꢀ
28ꢀ
29ꢀ
30ꢀ
31ꢀ
32ꢀ
33ꢀ
34ꢀ
35ꢀ
36ꢀ
37ꢀ
38ꢀ
39ꢀ
40ꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
NCꢀ
11Gꢀ
11Fꢀ
11Eꢀ
11Dꢀ
10Gꢀ
10Fꢀ
10Eꢀ
10Dꢀ
11Cꢀ
11Aꢀ
10Aꢀ
10Bꢀ
9Aꢀ
NCꢀ
CE2ꢀ
BWaꢀ
BWbꢀ
BWcꢀ
BWdꢀ
CE2ꢀ
CEꢀ
1Aꢀ
6Aꢀ
5Bꢀ
5Aꢀ
4Aꢀ
4Bꢀ
3Bꢀ
3Aꢀ
2Aꢀ
2Bꢀ
1Bꢀ
1Cꢀ
1Dꢀ
1Eꢀ
1Fꢀ
1Gꢀ
2D
1J
NCꢀ
NCꢀ
Aꢀ
6Nꢀ
11Pꢀ
8Pꢀ
1K
1L
1M
2J
Aꢀ
8Rꢀ
Aꢀ
9Rꢀ
2K
2L
2M
1N
3P
3R
4R
4P
6P
6R
Aꢀ
9Pꢀ
Aꢀ
10Pꢀ
10Rꢀ
11Rꢀ
11Hꢀ
Aꢀ
Aꢀ
Aꢀ
Aꢀ
ZZꢀ
Aꢀ
NCꢀ
Aꢀ
DQaꢀ 11Nꢀ
DQaꢀ 11Mꢀ
DQaꢀ 11Lꢀ
DQaꢀ 11Kꢀ
DQaꢀ 11Jꢀ
DQaꢀ 10Mꢀ
DQaꢀ 10Lꢀ
DQaꢀ 10Kꢀ
DQaꢀ 10Jꢀ
Aꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
Aꢀ
Aꢀ
Aꢀ
Aꢀ
9Bꢀ
A1ꢀ
ADVꢀ
OEꢀ
8Aꢀ
A0ꢀ
8Bꢀ
CKEꢀ
WEꢀ
CLKꢀ
NCꢀ
7Aꢀ
7Bꢀ
2E
6Bꢀ
2F
11Bꢀ
2G
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29
Rev. E
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
165 PBGA BOUNDARY SCAN ORDER (x 18)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit # Name
ID
Bit #
41ꢀ
42ꢀ
43ꢀ
44ꢀ
45ꢀ
46ꢀ
47ꢀ
48ꢀ
49ꢀ
50ꢀ
51ꢀ
52ꢀ
53ꢀ
54ꢀ
55ꢀ
56ꢀ
57ꢀ
58ꢀ
59ꢀ
60ꢀ
Bit #
61ꢀ
62ꢀ
63ꢀ
64ꢀ
65ꢀ
66ꢀ
67ꢀ
68ꢀ
69ꢀ
70ꢀ
71ꢀ
72ꢀ
73ꢀ
74ꢀ
75ꢀ
ꢀ
Name
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
Aꢀ
ID
ꢀ 1ꢀ
ꢀ 2ꢀ
ꢀ 3ꢀ
ꢀ 4ꢀ
ꢀ 5ꢀ
ꢀ 6ꢀ
ꢀ 7ꢀ
ꢀ 8ꢀ
ꢀ 9ꢀ
ꢀ10ꢀ
ꢀ11ꢀ
ꢀ12ꢀ
ꢀ13ꢀ
ꢀ14ꢀ
ꢀ15ꢀ
ꢀ16ꢀ
ꢀ17ꢀ
ꢀ18ꢀ
ꢀ19ꢀ
ꢀ20ꢀ
MODEꢀ 1Rꢀ
21ꢀ
22ꢀ
23ꢀ
24ꢀ
25ꢀ
26ꢀ
27ꢀ
28ꢀ
29ꢀ
30ꢀ
31ꢀ
32ꢀ
33ꢀ
34ꢀ
35ꢀ
36ꢀ
37ꢀ
38ꢀ
39ꢀ
40ꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
Aꢀ
11Gꢀ
11Fꢀ
11Eꢀ
11Dꢀ
11Cꢀ
10Fꢀ
10Eꢀ
10Dꢀ
10Gꢀ
11Aꢀ
10Aꢀ
10Bꢀ
9Aꢀ
NCꢀ
CE2ꢀ
BWaꢀ
NCꢀ
1Aꢀ
6Aꢀ
5Bꢀ
5Aꢀ
4Aꢀ
4Bꢀ
3Bꢀ
3Aꢀ
2Aꢀ
2Bꢀ
1Bꢀ
1Cꢀ
1Dꢀ
1Eꢀ
1Fꢀ
1Gꢀ
2D
1J
NCꢀ
NCꢀ
Aꢀ
6Nꢀ
11Pꢀ
8Pꢀ
1K
1L
1M
1N
2K
2L
2M
2J
Aꢀ
8Rꢀ
BWbꢀ
NCꢀ
Aꢀ
9Rꢀ
Aꢀ
9Pꢀ
CE2ꢀ
CEꢀ
Aꢀ
10Pꢀ
10Rꢀ
11Rꢀ
11Hꢀ
11Nꢀ
11Mꢀ
11Lꢀ
11Kꢀ
11Jꢀ
Aꢀ
Aꢀ
Aꢀ
Aꢀ
3P
3R
4R
4P
6P
6R
ZZꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
Aꢀ
NCꢀ
Aꢀ
Aꢀ
NCꢀ
Aꢀ
Aꢀ
NCꢀ
Aꢀ
Aꢀ
9Bꢀ
NCꢀ
A1ꢀ
ADVꢀ
OEꢀ
CKEꢀ
WEꢀ
CLKꢀ
NCꢀ
8Aꢀ
NCꢀ
A0ꢀ
8Bꢀ
NCꢀ
DQaꢀ 10Mꢀ
DQaꢀ 10Lꢀ
DQaꢀ 10Kꢀ
DQaꢀ 10Jꢀ
7Aꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
7Bꢀ
2E
6Bꢀ
2F
11Bꢀ
2G
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ORDERING INFORMATION (VDD = 3.3V/VDDq = 2.5V- 3.3V)
Commercial Range: 0°C to +70°C
Access Time
Order Part Number
512Kx36
Package
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
IS61NLF51236-6.5TQꢀ
IS61NLF51236-6.5TQLꢀ
IS61NLF51236-6.5B3ꢀ
IS61NLF51236-7.5TQꢀ
IS61NLF51236-7.5B3ꢀ
1Mx18
100ꢀTQFP
100ꢀTQFPꢀ
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
ꢀ
ꢀ
ꢀ
ꢀ
7.5ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
ꢀ
IS61NLF102418-6.5TQꢀ
IS61NLF102418-6.5TQLꢀ
100ꢀTQFPꢀ
100ꢀTQFP,ꢀLead-free
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7.5ꢀ
ꢀ
IS61NLF102418-6.5B3ꢀ
IS61NLF102418-7.5TQꢀ
IS61NLF102418-7.5B3ꢀ
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
Industrial Range: -40°C to +85°C
Access Time
Order Part Number
256Kx72
Package
ꢀ
ꢀ
6.5ꢀ
7.5ꢀ
IS61NLF25672-6.5B1Iꢀ
IS61NLF25672-7.5B1Iꢀ
512Kx36
209ꢀPBGA
209ꢀPBGA
ꢀ
ꢀ
6.5ꢀ
ꢀ
IS61NLF51236-6.5TQIꢀ
IS61NLF51236-6.5B3Iꢀ
100ꢀTQFP
165ꢀPBGA
ꢀ
ꢀ
7.5ꢀ
ꢀ
IS61NLF51236-7.5TQIꢀ
IS61NLF51236-7.5TQLIꢀ
100ꢀTQFPꢀ
100ꢀTQFP,ꢀLead-free
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS61NLF51236-7.5B3Iꢀ
1Mx18
165ꢀPBGA
ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
IS61NLF102418-6.5TQIꢀ
IS61NLF102418-6.5B3Iꢀ
IS61NLF102418-7.5TQIꢀ
IS61NLF102418-7.5B3Iꢀ
100ꢀTQFP
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
ꢀ
7.5ꢀ
ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
31
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ORDERING INFORMATION (VDD = 2.5V /VDDq = 2.5V)
Commercial Range: 0°C to +70°C
Access Time
Order Part Number
512Kx36
Package
ꢀ
ꢀ
6.5ꢀ
ꢀ
IS61NVF51236-6.5TQꢀ
IS61NVF51236-6.5TQLꢀ
100ꢀTQFPꢀ
100ꢀTQFP,ꢀLead-free
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7.5ꢀ
ꢀ
IS61NVF51236-6.5B3ꢀ
IS61NVF51236-7.5TQꢀ
IS61NVF51236-7.5B3ꢀ
1Mx18
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
IS61NVF102418-6.5TQꢀ
IS61NVF102418-6.5B3ꢀ
IS61NVF102418-7.5TQꢀ
IS61NVF102418-7.5B3ꢀ
100ꢀTQFP
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
ꢀ
7.5ꢀ
ꢀ
Industrial Range: -40°C to +85°C
Access Time
Order Part Number
256Kx72
Package
ꢀ
ꢀ
6.5ꢀ
7.5ꢀ
IS61NVF25672-6.5B1Iꢀ
IS61NVF25672-7.5B1Iꢀ
512Kx36
209ꢀPBGA
209ꢀPBGA
ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
IS61NVF51236-6.5TQIꢀ
IS61NVF51236-6.5B3Iꢀ
IS61NVF51236-7.5TQIꢀ
IS61NVF51236-7.5B3Iꢀ
1Mx18
100ꢀTQFP
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
ꢀ
7.5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
IS61NVF102418-6.5TQIꢀ
IS61NVF102418-6.5B3Iꢀ
IS61NVF102418-7.5TQIꢀ
IS61NVF102418-7.5B3Iꢀ
100ꢀTQFP
165ꢀPBGA
100ꢀTQFP
165ꢀPBGA
ꢀ
7.5ꢀ
ꢀ
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
33
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
35
Rev. E
10/25/2013
相关型号：
IS61NVF25672-7.5B1
ZBT SRAM, 256KX72, 7.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
ISSI
IS61NVF25672-7.5B1I
256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
ISSI
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