IS61NVP51218A-200B2I-TR

AllꢀRead,WriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ

ꢀ

256Kꢀxꢀ36ꢀandꢀ512Kꢀxꢀ18

9Mb,ꢀPIPELINEꢀ'NOꢀWAIT'ꢀSTATEꢀBUSꢀSRAM

AUGUSTꢀ2011

FEATURES

DESCRIPTION

Theꢀ9ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ

low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ

aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ

networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ

organizedꢀasꢀ256Kꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ512Kꢀꢀwordsꢀbyꢀ18ꢀ

bits,ꢀfabricatedꢀwithꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

intoꢀaꢀsingleꢀmonolithicꢀcircuit.

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

dataꢀandꢀcontrol

ꢀ

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ingꢀMODEꢀinputꢀ

Allꢀsynchronousꢀinputsꢀpassꢀthroughꢀregistersꢀareꢀcontrolledꢀ

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

mayꢀbeꢀsuspendedꢀandꢀallꢀsynchronousꢀinputsꢀignoredꢀ

whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

andꢀaddressꢀpipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ

119-ballꢀPBGAꢀpackages

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

byꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinputsꢀandꢀwhenꢀWEꢀisꢀ

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

•ꢀ Powerꢀsupply:ꢀ

NVP:ꢀV^dd2.5Vꢀ( ꢀ5%),ꢀVddqꢀ2.5Vꢀ( ꢀ5%)

NLP:ꢀV^ddꢀ3.3Vꢀ( ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ( ꢀ5%)

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages

•ꢀ Industrialꢀtemperatureꢀavailable

•ꢀ Lead-freeꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.WhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

FASTꢀACCESSꢀTIME

ꢀ

Symbolꢀ

Parameterꢀ

-250ꢀ

2.6ꢀ

4ꢀ

-200ꢀ

3.1ꢀ

5ꢀ

Units

ns

tkqꢀ

tkcꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

ns

Frequencyꢀ

250ꢀ

200ꢀ

MHz

Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspeciﬁcationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀ

liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspeciﬁcationꢀbeforeꢀrelyingꢀonꢀ

anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ

IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀ

failureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsigniﬁcantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀ

assuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:

a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;

b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand

c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

1

Rev.ꢀ Hꢀ

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

BLOCKꢀDIAGRAM

A2-A17 or A2-A18

256Kx36;

512Kx18

MEMORY ARRAY

x 36: A [0:17] or

x 18: A [0:18]

ADDRESS

REGISTER

MODE

BURST

ADDRESS

COUNTER

K

DATA-IN

REGISTER

A0-A1

A'0-A'1

DATA-IN

REGISTER

WRITE

ADDRESS

REGISTER

WRITE

ADDRESS

REGISTER

CLK

CONTROL

LOGIC

K

CKE

CE

CE2

CONTROL

REGISTER

ADV

WE

K

CONTROL

LOGIC

OUTPUT

REGISTER

}

BW

X

(X=a,b,c,d or a,b)

BUFFER

OE

ZZ

36 or 18

DQx/DQPx

2ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

BottomꢀView

165-Ball,ꢀ13ꢀmmꢀxꢀ15mmꢀBGA

1ꢀmmꢀBallꢀPitch,ꢀ11ꢀxꢀ15ꢀBallꢀArray

BottomꢀView

119-Ball,ꢀ14ꢀmmꢀxꢀ22ꢀmmꢀBGA

1ꢀmmꢀBallꢀPitch,ꢀ7ꢀxꢀ17ꢀBallꢀArray

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

3

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

PINꢀCONFIGURATIONꢀ—ꢀ256Kꢀxꢀ36,ꢀ165-BallꢀPBGAꢀ(TOPꢀVIEW)

1

NC

2

A

NC

3

CE

4

5

6

7

8

ADV

OE

9

A

NC

10

A

11

NC

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

BWc

BWd

VSS

BWb

BWa

VSS

NC

CE2

CLK

VSS

NC

CKE

WE

VSS

NC

CE2

DQPc

DQc

NC

DQd

DQPd

NC

V

ddq

VSS

V

ddq

NC

DQb

NC

DQa

NC

A

DQPb

DQb

ZZ

DQa

DQPa

NC

DQc

NC

DQd

NC

Vdd

V

NC

V

ddq

A

V

ddq

A

V

VSS

A

VSS

A

NC

TdI

TMS

A1*

A0*

TDO

TCK

MODE

A

Note:ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsigniﬁcantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀﬁeldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.

PINꢀDESCRIPTIONS

MODEꢀ

ꢀ

BurstꢀSequenceꢀSelection

JTAGꢀPins

Symbolꢀ

Aꢀ

PinꢀName

TCK,ꢀTDIꢀ

TDO,ꢀTMS

AddressꢀInputs

A0,ꢀA1ꢀ

ADVꢀꢀ

SynchronousꢀBurstꢀAddressꢀInputs

VDDꢀ

ꢀ

3.3V/2.5VꢀPowerꢀSupply

NoꢀConnect

SynchronousꢀBurstꢀAddressꢀAdvance/

Load

NCꢀ

DQxꢀ

DQPxꢀ

VDDQꢀ

DataꢀInputs/Outputs

ParityꢀDataꢀI/O

WEꢀ

SynchronousꢀRead/WriteꢀControlꢀ

Input

CLKꢀꢀ

SynchronousꢀClock

ClockꢀEnable

IsolatedꢀoutputꢀPowerꢀSupplyꢀꢀ ꢀ

3.3V/2.5V

CKEꢀ

ꢀ

VSS

Ground

CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable

BWxꢀ(x=a-d)ꢀ SynchronousꢀByteꢀWriteꢀInputs

OEꢀ

ꢀ

OutputꢀEnable

ZZꢀ

PowerꢀSleepꢀModeꢀꢀ

4ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

119-PINꢀPBGAꢀPACKAGEꢀCONFIGURATIONꢀꢀꢀꢀꢀꢀꢀ256Kꢀxꢀ36ꢀ(TOPꢀVIEW)ꢀ

1

2

3

4

5

6

7

A

B

C

D

V

DDQ

A

NC

A

V

DDQ

NC

CE2

A

ADV

CE2

A

NC

VDD

A

DQc

DQPc

DQc

V

SS

NC

CE

OE

A

Vss

BWb

DQPb

DQb

V

E

F

V

DDQ

DQc

VDDQ

BWc

DQb

G

VSS

DQc

WE

Vss

NC

DQb

H

J

NC

V

DDQ

DQd

VDD

V

DD

VDDQ

K

L

V

SS

DQd

DQPd

CLK

NC

Vss

BWa

Vss

DQa

DQPa

DQa

BWd

V

DDQ

V

SS

CKE

VDDQ

M

N

P

R

T

DQd

A

1

*

DQa

VSS

DQd

A0

*

VSS

NC

A

MODE

A

VDD

NC

A

NC

ZZ

NC

A

NC

U

V

DDQ

TMS

TDI

TCK

TDO

V

DDQ

Note:ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsigniﬁcantꢀbits(LSB)ꢀofꢀtheꢀaddressꢀﬁeldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.

PINꢀDESCRIPTIONS

OEꢀ

ꢀ

OutputꢀEnable

PowerꢀSleepꢀModeꢀꢀ

BurstꢀSequenceꢀSelection

JTAGꢀPins

Symbolꢀ

Aꢀ

PinꢀName

ZZꢀ

AddressꢀInputs

MODEꢀ

A0,ꢀA1ꢀ

ADVꢀꢀ

SynchronousꢀBurstꢀAddressꢀInputs

TCK,ꢀTDOꢀ

TMS,ꢀTDIꢀ

Vdd

SynchronousꢀBurstꢀAddressꢀAdvance/

Load

ꢀ

WEꢀ

SynchronousꢀRead/WriteꢀControlꢀInput

SynchronousꢀClock

PowerꢀSupply

Ground

CLKꢀꢀ

CKEꢀ

CEꢀ

VSSꢀ

ꢀ

ClockꢀEnable

NCꢀ

NoꢀConnect

SynchronousꢀChipꢀSelect

DQa-DQdꢀ

DQPa-Pdꢀ

DataꢀInputs/Outputs

ParityꢀDataꢀI/O

OutputꢀPowerꢀSupply

CE2ꢀ

Vddqꢀ

ꢀ

BWxꢀ(x=a-d)ꢀ SynchronousꢀByteꢀWriteꢀInputs

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

5

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

165-PINꢀPBGAꢀPACKAGEꢀCONFIGURATIONꢀꢀꢀꢀꢀꢀꢀ512Kꢀxꢀ18ꢀ(TOPꢀVIEW)ꢀ

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

CKE

NC

ADV

A

BWb

NC

A

CE2

CLK

Vss

CE

NC

CE2

NC

DDQ

OE

WE

NC

Vss

NC

BWa

V

NC

Vss

DQPa

NC

V

DDQ

Vss

NC

V

DD

Vss

V

DD

DQa

ZZ

NC

Vss

V

DDQ

DQb

VDD

V

DD

E

F

NC

Vss

V

DDQ

V

DDQ

Vss

V

DD

NC

DQb

Vss

NC

V

Vss

V

G

NC

V

DDQ

DQb

NC

VDD

V

DD

V

DD

NC

H

J

NC

Vss

NC

V

DDQ

V

Vss

V

DDQ

NC

V

DD

DQb

DQPb

NC

DQa

NC

K

L

V

DDQ

V

Vss

DQa

NC

A

V

Vss

VDD

V

DDQ

Vss

V

NC

V

DDQ

VDD

M

N

P

NC

Vss

V

DDQ

NC

Vss

A

NC

VDDQ

Vss

NC

TDI

V

DDQ

A

NC

A

1*

TDO

TCK

TMS

A

0*

A

R

MODE

Note:ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsigniﬁcantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀﬁeldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.

PINꢀDESCRIPTIONS

MODEꢀ

ꢀ

BurstꢀSequenceꢀSelection

JTAGꢀPins

Symbolꢀ

Aꢀ

PinꢀName

TCK,ꢀTDIꢀ

TDO,ꢀTMS

AddressꢀInputs

A0,ꢀA1ꢀ

ADVꢀꢀ

SynchronousꢀBurstꢀAddressꢀInputs

VDDꢀ

ꢀ

3.3V/2.5VꢀPowerꢀSupply

NoꢀConnect

SynchronousꢀBurstꢀAddressꢀAdvance/

Load

NCꢀ

DQxꢀ

DQPxꢀ

VDDQꢀ

DataꢀInputs/Outputs

ParityꢀDataꢀI/O

WEꢀ

SynchronousꢀRead/WriteꢀControlꢀ

Input

CLKꢀꢀ

SynchronousꢀClock

ClockꢀEnable

IsolatedꢀoutputꢀPowerꢀSupplyꢀꢀ ꢀ

3.3V/2.5V

CKEꢀ

ꢀ

VSS

Ground

CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable

BWxꢀ(x=a,b)ꢀ SynchronousꢀByteꢀWriteꢀInputs

OEꢀ

ꢀ

OutputꢀEnable

ZZꢀ

PowerꢀSleepꢀModeꢀꢀ

6ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

119-PINꢀPBGAꢀPACKAGEꢀCONFIGURATIONꢀꢀꢀꢀꢀꢀꢀ512Kꢀxꢀ18ꢀ(TOPꢀVIEW)ꢀ

1

2

3

4

5

6

7

A

B

C

D

V

DDQ

A

CE2

A

NC

A

CE2

A

V

DDQ

NC

ADV

NC

VDD

A

NC

DQb

V

SS

NC

CE

OE

A

Vss

NC

DQPa

NC

DQa

DQb

NC

V

E

F

NC

DQa

NC

V

DDQ

VDDQ

NC

DQa

NC

DQb

NC

BWb

G

DQa

VSS

DQb

WE

Vss

NC

H

J

NC

VDDQ

VDD

V

DD

VDDQ

K

L

V

SS

DQb

NC

CLK

NC

Vss

BWa

Vss

DQa

NC

DQa

NC

DQa

NC

A

DQb

NC

VDDQ

DQb

NC

V

SS

CKE

VDDQ

M

N

P

R

T

NC

DQa

NC

DQb

NC

V

A

1

*

A0

*

V

SS

DQPb

A

NC

MODE

A

VDD

NC

A

NC

ZZ

A

NC

U

V

DDQ

TMS

TDI

TCK

TDO

NC

V

DDQ

Note:ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsigniﬁcantꢀbits(LSB)ꢀofꢀtheꢀaddressꢀﬁeldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.

PINꢀDESCRIPTIONS

Symbolꢀ

Aꢀ

PinꢀName

OEꢀ

ꢀ

OutputꢀEnable

PowerꢀSleepꢀModeꢀꢀ

BurstꢀSequenceꢀSelection

JTAGꢀPins

AddressꢀInputs

ZZꢀ

A0,ꢀA1ꢀ

ADVꢀꢀ

SynchronousꢀBurstꢀAddressꢀInputs

MODEꢀ

SynchronousꢀBurstꢀAddressꢀAdvance/

Load

TCK,ꢀTDOꢀ

TMS,ꢀTDIꢀ

Vdd

ꢀ

WEꢀ

SynchronousꢀRead/WriteꢀControlꢀ

Input

PowerꢀSupply

Ground

VSSꢀ

ꢀ

CLKꢀꢀ

CKEꢀ

CEꢀ

SynchronousꢀClock

NCꢀ

NoꢀConnect

ꢀ

ClockꢀEnable

DQa-DQbꢀ

DQPa-Pbꢀ

DataꢀInputs/Outputs

ParityꢀDataꢀI/O

OutputꢀPowerꢀSupply

SynchronousꢀChipꢀSelect

CE2ꢀ

Vddqꢀ

ꢀ

BWxꢀ(x=a,b)ꢀ SynchronousꢀByteꢀWriteꢀInputs

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

7

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

PINꢀCONFIGURATION

100-PinꢀTQFP

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

100

DQPc

DQc

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb

NC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A

NC

DQc

DQb

NC

V

DDQ

Vss

V

DDQ

V

DDQ

Vss

VDDQ

Vss

DQc

DQb

NC

DQPa

DQc

Vss

DQb

Vss

DQb

Vss

DQa

Vss

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

DDQ

V

DDQ

V

DDQ

VDDQ

DQc

DQb

DQa

DQc

NC

DQb

Vss

NC

DQb

NC

DQa

Vss

NC

VDD

NC

Vss

VDD

NC

Vss

VDD

ZZ

DQa

DQd

DQb

DQa

V

DDQ

V

DDQ

V

DDQ

VDDQ

Vss

DQd

Vss

DQb

Vss

DQa

DQb

DQd

DQPb

NC

DQd

Vss

DQa

Vss

NC

Vss

V

DDQ

V

DDQ

V

DDQ

VDDQ

NC

DQd

DQPd

DQa

DQPa

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

512Kꢀxꢀ18

256Kꢀxꢀ36

PINꢀDESCRIPTIONS

A0,ꢀA1ꢀ

SynchronousꢀAddressꢀInputs.ꢀTheseꢀ

pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ

addressꢀbus.

CE,ꢀCE2,ꢀCE2ꢀ ꢀ SynchronousꢀChipꢀEnable

OEꢀ

ꢀ

OutputꢀEnable

DQa-DQdꢀ

DQPa-DQPdꢀ

MODEꢀꢀ ꢀ

SynchronousꢀDataꢀInput/Output

ParityꢀDataꢀI/O

Aꢀ

SynchronousꢀAddressꢀInputs

SynchronousꢀClock

CLKꢀꢀ

ADVꢀꢀ

BWa-BWdꢀ

WEꢀ

BurstꢀSequenceꢀSelection

+3.3V/2.5VꢀPowerꢀSupply

GroundꢀforꢀoutputꢀBuffer

SynchronousꢀBurstꢀAddressꢀAdvance

SynchronousꢀByteꢀWriteꢀEnable

WriteꢀEnable

Vddꢀ

VSSꢀ

ꢀ

Vddqꢀ

ꢀ

IsolatedꢀOutputꢀBufferꢀSupply:ꢀꢀꢀ

+3.3V/2.5V

CKEꢀ

Vssꢀ

NCꢀ

ꢀ

ClockꢀEnable

GroundꢀforꢀCore

ZZꢀ

ꢀ

SnoozeꢀEnable

NotꢀConnected

8ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

STATEꢀDIAGRAM

READ

WRITE

BEGIN

READ

BEGIN

WRITE

READ

DS

READ

WRITE

DESELECT

READ

BURST

WRITE

BURST

DS

WRITE

BURST

READ

BURST

WRITE

BURST

READ

SYNCHRONOUSꢀTRUTHꢀTABLE⁽¹⁾

ꢀ

Addressꢀ

Operationꢀ

Usedꢀ

CEꢀ CE2ꢀ CE2ꢀ ADVꢀ WEꢀ BWxꢀ OEꢀ CKEꢀ CLK

NotꢀSelectedꢀꢀ

N/Aꢀ

Hꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Hꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Hꢀ

Lꢀ

Hꢀ

Lꢀ

Hꢀ

Lꢀ

Hꢀ

Lꢀ

Hꢀ

Xꢀ

Hꢀ

Xꢀ

Hꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Xꢀ

Lꢀ

Hꢀ

↑

NotꢀSelectedꢀ

N/Aꢀ

NotꢀSelectedꢀ

N/Aꢀ

Xꢀ

Hꢀ

Xꢀ

Hꢀ

Xꢀ

Hꢀ

Xꢀ

Hꢀ

Xꢀ

NotꢀSelectedꢀContinueꢀ

BeginꢀBurstꢀReadꢀ

ContinueꢀBurstꢀReadꢀ

NOP/DummyꢀReadꢀ

DummyꢀReadꢀ

N/Aꢀ

ExternalꢀAddressꢀ

NextꢀAddressꢀ

ExternalꢀAddressꢀ

NextꢀAddressꢀ

ExternalꢀAddressꢀ

NextꢀAddressꢀ

N/Aꢀ

Lꢀ

Hꢀ

Xꢀ

BeginꢀBurstꢀWriteꢀ

ContinueꢀBurstꢀWriteꢀ

NOP/WriteꢀAbortꢀ

WriteꢀAbortꢀ

Xꢀ

Lꢀ

Hꢀ

Xꢀ

NextꢀAddressꢀ

CurrentꢀAddressꢀ

Xꢀ

IgnoreꢀClockꢀ

Notes:

1.ꢀ "X"ꢀmeansꢀdon'tꢀcare.

2.ꢀ Theꢀrisingꢀedgeꢀofꢀclockꢀisꢀsymbolizedꢀbyꢀ↑ꢀ

3.ꢀ Aꢀcontinueꢀdeselectꢀcycleꢀcanꢀonlyꢀbeꢀenteredꢀifꢀaꢀdeselectꢀcycleꢀisꢀexecutedꢀﬁrst.

4.ꢀ WEꢀ=ꢀLꢀmeansꢀWriteꢀoperationꢀinꢀWriteꢀTruthꢀTable.

ꢀ

WEꢀ=ꢀHꢀmeansꢀReadꢀoperationꢀinꢀWriteꢀTruthꢀTable.

5.ꢀ Operationꢀﬁnallyꢀdependsꢀonꢀstatusꢀofꢀasynchronousꢀpinsꢀ(ZZꢀandꢀOE).

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

9

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

ASYNCHRONOUSꢀTRUTHꢀTABLE⁽¹⁾

Operationꢀ

ZZꢀ

OEꢀ

I/OꢀSTATUS

SleepꢀModeꢀ

Hꢀ

Xꢀ

High-Z

Readꢀ

ꢀ

Lꢀ

Hꢀ

DQꢀ

High-Z

Writeꢀ

Lꢀ

Xꢀ

Din,ꢀHigh-Z

High-Z

Deselectedꢀ

Notes:

1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ

2.ꢀ Forꢀwriteꢀcyclesꢀfollowingꢀreadꢀcycles,ꢀtheꢀoutputꢀbuffersꢀmustꢀbeꢀdisabledꢀwithꢀOE,ꢀotherwiseꢀdataꢀ

busꢀcontentionꢀwillꢀoccur.

3.ꢀ SleepꢀModeꢀmeansꢀpowerꢀSleepꢀModeꢀwhereꢀstand-byꢀcurrentꢀdoesꢀnotꢀdependꢀonꢀcycleꢀtime.

4.ꢀ DeselectedꢀmeansꢀpowerꢀSleepꢀModeꢀwhereꢀstand-byꢀcurrentꢀdependsꢀonꢀcycleꢀtime.

WRITEꢀTRUTHꢀTABLEꢀ(x18)

Operationꢀ

WEꢀ

Hꢀ

Lꢀ

BWaꢀ

Xꢀ

BWb

READꢀ

X

H

L

WRITEꢀBYTEꢀaꢀ

WRITEꢀBYTEꢀbꢀ

WRITEꢀALLꢀBYTEsꢀ

WRITEꢀABORT/NOPꢀ

Lꢀ

Hꢀ

Lꢀ

L

Lꢀ

Hꢀ

H

Notes:

1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ

2.ꢀ AllꢀinputsꢀinꢀthisꢀtableꢀmustꢀmeetꢀsetupꢀandꢀholdꢀtimeꢀaroundꢀtheꢀrisingꢀedgeꢀofꢀCLK.

10ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

WRITEꢀTRUTHꢀTABLEꢀ(x36)

Operationꢀ

WEꢀ

Hꢀ

Lꢀ

BWaꢀ

Xꢀ

BWbꢀ

Xꢀ

BWcꢀ

Xꢀ

BWd

X

READꢀ

WRITEꢀBYTEꢀaꢀ

WRITEꢀBYTEꢀbꢀ

WRITEꢀBYTEꢀcꢀ

WRITEꢀBYTEꢀdꢀ

WRITEꢀALLꢀBYTEsꢀ

WRITEꢀABORT/NOPꢀ

Lꢀ

Hꢀ

H

Lꢀ

Hꢀ

Lꢀ

Hꢀ

H

Lꢀ

Hꢀ

Lꢀ

H

Lꢀ

Hꢀ

L

Lꢀ

L

Lꢀ

Hꢀ

H

Notes:

1.ꢀ Xꢀmeansꢀ"Don'tꢀCare".ꢀ

2.ꢀ AllꢀinputsꢀinꢀthisꢀtableꢀmustꢀmeetꢀsetupꢀandꢀholdꢀtimeꢀaroundꢀtheꢀrisingꢀedgeꢀofꢀCLK.

INTERLEAVEDꢀBURSTꢀADDRESSꢀTABLEꢀ(MODEꢀ=ꢀVdd orꢀNC)

ꢀ ExternalꢀAddressꢀ

1stꢀBurstꢀAddressꢀ

A1ꢀ A0ꢀ

2ndꢀBurstꢀAddressꢀ

A1ꢀ A0ꢀ

3rdꢀBurstꢀAddressꢀ

A1ꢀ A0

ꢀ

A1ꢀ A0ꢀ

00ꢀ

01ꢀ

10ꢀ

11ꢀ

01ꢀ

00ꢀ

11ꢀ

10ꢀ

11ꢀ

00ꢀ

01ꢀ

11

10

01

00

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11

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

LINEARꢀBURSTꢀADDRESSꢀTABLEꢀ(MODEꢀ=ꢀVSS)ꢀ ꢀ

0,0

A1', A0' = 1,1

0,1

1,0

ABSOLUTEꢀMAXIMUMꢀRATINGS⁽¹⁾

ꢀ

Symbolꢀ

TSTG

Parameterꢀ

ꢀ

Valueꢀ

–65ꢀtoꢀ+150ꢀ

1.6ꢀ

Unit

°C

W

StorageꢀTemperatureꢀ

PowerꢀDissipationꢀ

OutputꢀCurrentꢀ(perꢀI/O)ꢀ

Pd

IouTꢀ

100ꢀ

mA

V

VIn, VouTꢀ

VInꢀ

VoltageꢀRelativeꢀtoꢀVSSꢀforꢀI/OꢀPinsꢀ

–0.5ꢀtoꢀVddq + 0.3

–0.3ꢀtoꢀ4.6

VoltageꢀRelativeꢀtoꢀVSSꢀforꢀꢀ

V

forꢀAddressꢀandꢀControlꢀInputs

Notes:

1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ

stressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀ

sectionsꢀofꢀthisꢀspeciﬁcationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreli-

ability.ꢀ

2.ꢀThisꢀdeviceꢀcontainsꢀcircuityꢀtoꢀprotectꢀtheꢀinputsꢀagainstꢀdamageꢀdueꢀtoꢀhighꢀstaticꢀvoltagesꢀorꢀelectricꢀﬁelds;ꢀhowever,ꢀprecau-

tionsꢀmayꢀbeꢀtakenꢀtoꢀavoidꢀapplicationꢀofꢀanyꢀvoltageꢀhigherꢀthanꢀmaximumꢀratedꢀvoltagesꢀtoꢀthisꢀhigh-impedanceꢀcircuit.

3.ꢀThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputꢀdevicesꢀareꢀinꢀHigh-Zꢀatꢀpowerꢀup.

OPERATINGꢀRANGEꢀ(IS61NLPx)

ꢀ

Rangeꢀ

AmbientꢀTemperatureꢀ

0°Cꢀtoꢀ+70°Cꢀ

VDDꢀ

VDDq

Commercialꢀ

Industrialꢀ

3.3Vꢀ ꢀ5%ꢀ

3.3Vꢀ/ꢀ2.5Vꢀ ꢀ5%

-40°Cꢀtoꢀ+85°Cꢀ

OPERATINGꢀRANGEꢀ(IS61NVPx)

ꢀ

Rangeꢀ

AmbientꢀTemperatureꢀ

0°Cꢀtoꢀ+70°Cꢀ

VDDꢀ

VDDq

Commercialꢀ

Industrialꢀ

2.5Vꢀ ꢀ5%ꢀ

ꢀ2.5Vꢀ ꢀ5%

-40°Cꢀtoꢀ+85°Cꢀ

12ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

DCꢀELECTRICALꢀCHARACTERISTICSꢀ(OverꢀOperatingꢀRange)

ꢀ

3.3Vꢀ

2.5V

ꢀ

Symbolꢀ Parameterꢀ

TestꢀConditionsꢀ

Min.ꢀ

Max.ꢀ

Min.ꢀ

Max.ꢀ

Unit

ꢀ

Voh

ꢀ

OutputꢀHIGHꢀVoltageꢀ

ꢀ

Ioh = –4.0ꢀmAꢀ (3.3V)ꢀ

Ioh = –1.0ꢀmA (2.5V)ꢀ

2.4ꢀ

ꢀ

—ꢀ

2.0ꢀ

—ꢀ

V

ꢀ

Vol

ꢀ

OutputꢀLOWꢀVoltageꢀ

ꢀ

Iol = 8.0ꢀmA (3.3V)ꢀ

Iol = 1.0ꢀmAꢀ (2.5V)ꢀ

—ꢀ

ꢀ

0.4ꢀ

—ꢀ

0.4ꢀ

V

ꢀ

VIh

VIl

IlI

InputꢀHIGHꢀVoltageꢀꢀ

InputꢀLOWꢀVoltage^ꢀ

ꢀ

2.0ꢀ

–0.3ꢀ

–5ꢀ

Vdd + 0.3ꢀ

1.7ꢀ

–0.3ꢀ

–5ꢀ

Vdd + 0.3

V

ꢀ

0.8ꢀ

5ꢀ

0.7ꢀ

5ꢀ

InputꢀLeakageꢀCurrentꢀ

OutputꢀLeakageꢀCurrent^ꢀ

VSSꢀ≤ꢀVIn ≤ Vdd⁽¹⁾ꢀ

ꢁA

Ilo

VSSꢀ≤ꢀVouT ≤ Vddq, OE = VIhꢀ

–5ꢀ

5ꢀ

–5ꢀ

5ꢀ

POWERꢀSUPPLYꢀCHARACTERISTICS⁽¹⁾ꢀ(OverꢀOperatingꢀRange)

ꢀ

-250ꢀ

-200

ꢀ

MAXꢀ

MAX

ꢀ Symbolꢀ Parameterꢀ

TestꢀConditionsꢀ

Temp.ꢀrangeꢀꢀ

x18ꢀ

x36ꢀ

ꢀ

x18ꢀ

x36ꢀ

ꢀ

Uni

t

ꢀ Icc

ꢀ ꢀ

ACꢀOperatingꢀ

SupplyꢀCurrentꢀ

DeviceꢀSelected,ꢀꢀ

OE = VIh, ZZ ≤ VIl,

Com.ꢀ

Ind.

280ꢀ

300ꢀ

280ꢀ

300ꢀ

ꢀ

270ꢀ 270ꢀ

280ꢀ 280ꢀ

ꢀ

mA

ꢀ ꢀ

ꢀ

AllꢀInputsꢀ≤ 0.2V orꢀ≥ Vddꢀ–ꢀ0.2V,

CycleꢀTimeꢀ≥ꢀtkc min.

ꢀ ISb

ꢀ ꢀ

StandbyꢀCurrentꢀ

TTLꢀInputꢀ

ꢀ

DeviceꢀDeselected,ꢀꢀ

Vdd = Max.,ꢀ

AllꢀInputs ≤ VIl or ≥ VIh,

ZZ ≤ VIl, fꢀ=ꢀMax.

Com.

Ind.ꢀ

100

100ꢀ

100

100ꢀ

100

100ꢀ 100ꢀ

100

ꢀ

mA

ꢀ

ISbIꢀ

StandbyꢀCurrentꢀ

cMoS Input

DeviceꢀDeselected,ꢀ

Vdd = Max.,ꢀ

Com.ꢀ

Ind.ꢀ

70

80ꢀ

70

80ꢀ

70

80ꢀ

70

80ꢀ

mA

ꢀ ꢀ

ꢀ

VInꢀ≤ꢀVSS +ꢀ0.2Vꢀorꢀ≥Vddꢀ–ꢀ0.2V

ꢀ

ꢀfꢀ=ꢀ0

ꢀ ISb2

ꢀ ꢀ

SleepꢀModeꢀ

ꢀ

ZZ>VIhꢀꢀ

ꢀ

Com.ꢀ

Ind.ꢀ

45ꢀ

50ꢀ

45ꢀ

50ꢀ

ꢀ

45ꢀ

50ꢀ

45ꢀ

50ꢀ

ꢀ

mAꢀ

Note:

1.ꢀ MODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀV^ddꢀorꢀVSS.ꢀItꢀexhibitsꢀ 100ꢁAꢀmaximumꢀleakageꢀcurrentꢀwhenꢀtiedꢀtoꢀ≤ꢀ

V^SSꢀ+ꢀ0.2Vꢀorꢀ≥ꢀVddꢀ–ꢀ0.2V.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

13

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

CAPACITANCE^(1,2)

ꢀ

Symbolꢀ

Parameterꢀ

Conditionsꢀ

VIn = 0V

Max.ꢀ

6ꢀ

Unit

pF

ꢀ cIn

InputꢀCapacitanceꢀ

Input/OutputꢀCapacitanceꢀ

ꢀ couTꢀ

VouT = 0V

8ꢀ

pF

Notes:

1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.

2.ꢀ Testꢀconditions:ꢀT^A= 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.

3.3VꢀI/OꢀACꢀTESTꢀCONDITIONS

ꢀ

Parameterꢀ

InputꢀPulseꢀLevelꢀ

InputꢀRiseꢀandꢀFallꢀTimesꢀ

Unit

0Vꢀtoꢀ3.0V

1.5ꢀns

ꢀ

InputꢀandꢀOutputꢀTimingꢀ

andꢀReferenceꢀLevel

1.5Vꢀ

ꢀ

OutputꢀLoadꢀ

SeeꢀFiguresꢀ1ꢀandꢀ2

3.3VꢀI/OꢀOUTPUTꢀLOADꢀEQUIVALENT

317 Ω

+3.3V

Zo= 50Ω

OUTPUT

5 pF

50Ω

Including

jig and

scope

351 Ω

1.5V

Figureꢀ1

Figureꢀ2

14ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

2.5VꢀI/OꢀACꢀTESTꢀCONDITIONS

ꢀ

Parameterꢀ

InputꢀPulseꢀLevelꢀ

InputꢀRiseꢀandꢀFallꢀTimesꢀ

Unit

0Vꢀtoꢀ2.5V

1.5ꢀns

ꢀ

InputꢀandꢀOutputꢀTimingꢀ

andꢀReferenceꢀLevel

1.25Vꢀ

ꢀ

OutputꢀLoadꢀ

SeeꢀFiguresꢀ3ꢀandꢀ4

2.5VꢀI/OꢀOUTPUTꢀLOADꢀEQUIVALENT

1,667 Ω

+2.5V

ZO = 50Ω

OUTPUT

50Ω

5 pF

Including

jig and

scope

1,538 Ω

1.25V

Figureꢀ3

Figureꢀ4

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

15

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

READ/WRITEꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS⁽¹⁾ꢀ(OverꢀOperatingꢀRange)

ꢀ ꢀ

ꢀ

-250ꢀ

-200

ꢀ Symbolꢀ

Parameterꢀ

Min.ꢀ Max.ꢀ

Unit

MHz

ns

ꢀ fmaxꢀ

ꢀ tkcꢀ

ꢀ tkhꢀ

ꢀ tklꢀ

ClockꢀFrequencyꢀ

—ꢀ

4.0ꢀ

1.7ꢀ

—ꢀ

250ꢀ

—ꢀ

2.6ꢀ

—ꢀ

2.6ꢀ

—ꢀꢀ

2.6ꢀ

—ꢀ

2ꢀ

—ꢀ 200ꢀ

CycleꢀTimeꢀ

5ꢀ

2ꢀ

—ꢀ

ClockꢀHighꢀTimeꢀ

ns

ClockꢀLowꢀTimeꢀ

ns

ꢀ tkqꢀ

ClockꢀAccessꢀTimeꢀꢀ

—ꢀ 3.1ꢀ

1.5ꢀ —ꢀ

ns

(2)

ꢀ tkqx ꢀ

ClockꢀHighꢀtoꢀOutputꢀInvalidꢀ

ClockꢀHighꢀtoꢀOutputꢀLow-Zꢀ

ClockꢀHighꢀtoꢀOutputꢀHigh-Zꢀꢀ

OutputꢀEnableꢀtoꢀOutputꢀValidꢀꢀ

OutputꢀEnableꢀtoꢀOutputꢀLow-Zꢀ

OutputꢀDisableꢀtoꢀOutputꢀHigh-Zꢀꢀ

AddressꢀSetupꢀTimeꢀꢀ

Read/WriteꢀSetupꢀTimeꢀꢀ

ChipꢀEnableꢀSetupꢀTimeꢀꢀ

ClockꢀEnableꢀSetupꢀTimeꢀ

AddressꢀAdvanceꢀSetupꢀTimeꢀꢀ

DataꢀSetupꢀTimeꢀ

0.8ꢀ

—ꢀ

ns

ꢀ tkqlZ^(2,3)ꢀ

ꢀ tkqhZ^(2,3)ꢀ

ꢀ toeqꢀ

ꢀ toelZ^(2,3)ꢀ

ꢀ t^oehZ^(2,3)ꢀ

ꢀ tASꢀ

1ꢀ

—ꢀ

ns

—ꢀ 3.1ꢀ

ns

—ꢀ

ns

0ꢀ

0ꢀꢀ

—ꢀ

ns

—ꢀ

—ꢀ 3.0ꢀ

1.4ꢀ —ꢀ

0.4ꢀ —ꢀ

0.4ꢀꢀ —ꢀ

0.4ꢀ —ꢀ

ns

1.2ꢀ

0.3ꢀ

—ꢀ

ns

ꢀ twSꢀ

ns

ꢀ tceSꢀ

ꢀ tSeꢀ

ns

ꢀ tAdVSꢀ

ꢀ tdSꢀ

ns

ꢀ tAhꢀ

AddressꢀHoldꢀTimeꢀꢀ

ns

ꢀ the

ClockꢀEnableꢀHoldꢀTimeꢀ

WriteꢀHoldꢀTimeꢀꢀ

ns

ꢀ twhꢀ

ns

ꢀ tcehꢀ

ꢀ tAdVhꢀ

ꢀ tdhꢀ

ChipꢀEnableꢀHoldꢀTimeꢀꢀ

AddressꢀAdvanceꢀHoldꢀTimeꢀꢀ

DataꢀHoldꢀTimeꢀ

ns

ꢀ tPdSꢀ

ZZꢀHighꢀtoꢀPowerꢀDownꢀꢀ

ZZꢀLowꢀtoꢀPowerꢀDownꢀꢀ

—ꢀꢀ

2ꢀ

cyc

ꢀ tPuSꢀ

—ꢀ

2ꢀ

Notes:

1.ꢀ ConﬁgurationꢀsignalꢀMODEꢀisꢀstaticꢀandꢀmustꢀnotꢀchangeꢀduringꢀnormalꢀoperation.

2.ꢀ Guaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled.

3.ꢀ TestedꢀwithꢀloadꢀinꢀFigureꢀ2.

16ꢀ

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IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

SLEEPꢀMODEꢀELECTRICALꢀCHARACTERISTICS

ꢀ

Symbolꢀ Parameterꢀ

Conditionsꢀ

Min.ꢀ

ꢀ

Max.ꢀ

Unit

mA

ISb2ꢀ

tPdSꢀ

tPuSꢀ

tZZIꢀ

CurrentꢀduringꢀSLEEPꢀMODEꢀ

ZZꢀ≥ꢀVIhꢀ

60ꢀ

ZZꢀactiveꢀtoꢀinputꢀignoredꢀ

ꢀ

2ꢀ

ꢀ

cycle

ns

ZZꢀinactiveꢀtoꢀinputꢀsampledꢀ

ZZꢀactiveꢀtoꢀSLEEPꢀcurrentꢀ

ZZꢀinactiveꢀtoꢀexitꢀSLEEPꢀcurrentꢀ

2ꢀ

trZZIꢀ

0ꢀ

SLEEPꢀMODEꢀTIMING

CLK

t

PDS

t

ZZ setup cycle

ZZ recov^Pe^Ury^Scycle

ZZ

t

ZZI

Isupply

All Inputs

I

SB2

t

RZZI

Deselect or Read Only

(except ZZ)

Normal

operation

cycle

Outputs

(Q)

High-Z

Don't Care

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ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

READꢀCYCLEꢀTIMING

tKH

tKL

CLK

tKC

tADVS tADVH

ADV

tAS tAH

Address

A1

A2

A3

tWS

tWH

WRITE

CKE

t

SE tHE

t

CES

t

CEH

CE

OE

tKQ

tOEQ

tOEHZ

tKQX

t

KQHZ

t

OEHZ

Data Out

Q1-1

Q2-1

Q2-2

Q2-3

Q2-4

Q3-1

Q3-2

Q3-3

Q3-4

NOTES: WRITE = L means WE = L and BWx = L

WE = L and BWX = L

Don't Care

Undefined

CE = L means CE1 = L, CE2 = H and CE2 = L

CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L

18ꢀ

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IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

WRITEꢀCYCLEꢀTIMING

tKH

tKL

CLK

tKC

ADV

Address

WRITE

CKE

A1

A2

A3

tSE

tHE

CE

OE

tDS

t

DH

Data In

Data Out

D1-1

D2-1

D2-2

D2-3

D2-4

D3-1

D3-2

D3-3

D3-4

t

OEHZ

Q0-3

Q0-4

NOTES: WRITE = L means WE = L and BWx = L

WE = L and BWX = L

Don't Care

Undefined

CE = L means CE1 = L, CE2 = H and CE2 = L

CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L

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IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

SINGLEꢀREAD/WRITEꢀCYCLEꢀTIMING

t

KH

tKL

CLK

t

SE tHE

t

KC

CKE

Address

WRITE

CE

A1

A2

A3

A4

A5

A6

A7

A8

A9

ADV

OE

t

OEQ

t

OELZ

Data Out

Data In

Q1

Q3

Q4

Q6

Q7

t

DS

tDH

D2

D5

NOTES: WRITE = L means WE = L and BWx = L

CE = L means CE1 = L, CE2 = H and CE2 = L

CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L

Don't Care

Undefined

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IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

CKEꢀꢀOPERATIONꢀTIMING

t

KH

tKL

CLK

t

SE tHE

t

KC

CKE

Address

WRITE

CE

A1

A2

A3

A4

A5

A6

ADV

OE

tKQ

tKQHZ

t

KQLZ

Data Out

Data In

Q1

Q3

Q4

t

DS

t

DH

D2

NOTES: WRITE = L means WE = L and BWx = L

CE = L means CE1 = L, CE2 = H and CE2 = L

Don't Care

Undefined

CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L

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IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

CEꢀOPERATIONꢀTIMING

t

KH

tKL

CLK

t

SE tHE

t

KC

CKE

A1

A2

A3

A4

A5

Address

WRITE

CE

ADV

OE

t

OEQ

t

KQHZ

t

KQ

t

OELZ

tKQLZ

Q1

Q2

Q4

Data Out

Data In

t

DS

tDH

D3

D5

NOTES: WRITE = L means WE = L and BWx = L

CE = L means CE1 = L, CE2 = H and CE2 = L

CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L

Don't Care

Undefined

22ꢀ

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IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

IEEEꢀ1149.1ꢀSERIALꢀBOUNDARYꢀSCANꢀ(JTAG)

TESTꢀACCESSꢀPORTꢀ(TAP)ꢀ-ꢀTESTꢀCLOCK

TheꢀIS61NLPꢀandꢀꢀIS61NVPꢀhaveꢀaꢀserialꢀboundaryꢀscanꢀ

TestꢀAccessꢀPortꢀ(TAP)ꢀinꢀtheꢀPBGAꢀpackageꢀonly.ꢀ(Notꢀ

availableꢀ inꢀTQFPꢀ package.)ꢀThisꢀ portꢀ operatesꢀ inꢀ ac-

cordanceꢀwithꢀIEEEꢀStandardꢀ1149.1-1900,ꢀbutꢀdoesꢀnotꢀ

includeꢀallꢀfunctionsꢀrequiredꢀforꢀfullꢀ1149.1ꢀcompliance.ꢀ

TheseꢀfunctionsꢀfromꢀtheꢀIEEEꢀspeciﬁcationꢀareꢀexcludedꢀ

becauseꢀtheyꢀplaceꢀaddedꢀdelayꢀinꢀtheꢀcriticalꢀspeedꢀpathꢀ

ofꢀtheꢀSRAM.ꢀTheꢀTAPꢀcontrollerꢀoperatesꢀinꢀaꢀmannerꢀthatꢀ

doesꢀnotꢀconﬂictꢀwithꢀtheꢀperformanceꢀofꢀotherꢀdevicesꢀus-

ingꢀ1149.1ꢀfullyꢀcompliantꢀTAPs.ꢀTheꢀTAPꢀoperatesꢀusingꢀ

JEDECꢀstandardꢀ2.5VꢀI/Oꢀlogicꢀlevels.

TheꢀtestꢀclockꢀisꢀonlyꢀusedꢀwithꢀtheTAPꢀcontroller.ꢀAllꢀinputsꢀ

areꢀcapturedꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputsꢀareꢀ

drivenꢀfromꢀtheꢀfallingꢀedgeꢀofꢀTCK.

TESTꢀMODEꢀSELECTꢀ(TMS)

TheꢀTMSꢀinputꢀisꢀusedꢀtoꢀsendꢀcommandsꢀtoꢀtheꢀTAPꢀ

controllerꢀandꢀisꢀsampledꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCK.ꢀThisꢀ

pinꢀmayꢀbeꢀleftꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀnotꢀused.ꢀTheꢀpinꢀ

isꢀinternallyꢀpulledꢀup,ꢀresultingꢀinꢀaꢀlogicꢀHIGHꢀlevel.

TESTꢀDATA-INꢀ(TDI)

TheꢀTDIꢀpinꢀisꢀusedꢀtoꢀseriallyꢀinputꢀinformationꢀtoꢀtheꢀ

registersꢀandꢀcanꢀbeꢀconnectedꢀtoꢀtheꢀinputꢀofꢀanyꢀregis-

ter.ꢀTheꢀregisterꢀbetweenꢀTDIꢀandꢀTDOꢀisꢀchosenꢀbyꢀtheꢀ

instructionꢀ loadedꢀ intoꢀ theꢀTAPꢀ instructionꢀ register.ꢀ Forꢀ

informationꢀonꢀinstructionꢀregisterꢀloading,ꢀseeꢀtheꢀTAPꢀ

ControllerꢀStateꢀDiagram.ꢀTDIꢀisꢀinternallyꢀpulledꢀupꢀandꢀ

canꢀbeꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀunusedꢀinꢀanꢀapplica-

tion.ꢀTDIꢀisꢀconnectedꢀtoꢀtheꢀMostꢀSigniﬁcantꢀBitꢀ(MSB)ꢀ

onꢀanyꢀregister.

DISABLINGꢀTHEꢀJTAGꢀFEATURE

TheꢀSRAMꢀcanꢀoperateꢀwithoutꢀusingꢀtheꢀJTAGꢀfeature.ꢀ

Toꢀ disableꢀ theꢀTAPꢀ controller,ꢀTCKꢀ mustꢀ beꢀ tiedꢀ LOWꢀ

(V^SS)ꢀtoꢀpreventꢀclockingꢀofꢀtheꢀdevice.ꢀTDIꢀandꢀTMSꢀareꢀ

internallyꢀpulledꢀupꢀandꢀmayꢀbeꢀdisconnected.ꢀTheyꢀmayꢀ

alternatelyꢀbeꢀconnectedꢀtoꢀVddꢀthroughꢀaꢀpull-upꢀresistor.ꢀ

TDOꢀshouldꢀbeꢀleftꢀdisconnected.ꢀOnꢀpower-up,ꢀtheꢀdeviceꢀ

willꢀstartꢀinꢀaꢀresetꢀstateꢀwhichꢀwillꢀnotꢀinterfereꢀwithꢀtheꢀ

deviceꢀoperation.

TAPꢀCONTROLLERꢀBLOCKꢀDIAGRAM

0

Bypass Register

2

1

0

Instruction Register

TDI

Selection Circuitry

TDO

31 30 29 . . .

2

1

0

Identification Register

x

. . . . .

Boundary Scan Register*

TCK

TMS

TAP CONTROLLER

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IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

TESTꢀDATAꢀOUTꢀ(TDO)

TheꢀTDOꢀoutputꢀpinꢀisꢀusedꢀtoꢀseriallyꢀclockꢀdata-outꢀfromꢀ

theꢀregisters.ꢀTheꢀoutputꢀisꢀactiveꢀdependingꢀonꢀtheꢀcurrentꢀ

stateꢀofꢀtheꢀTAPꢀstateꢀmachineꢀ(seeꢀTAPꢀControllerꢀStateꢀ

Diagram).ꢀTheꢀoutputꢀchangesꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCKꢀ

andꢀTDOꢀisꢀconnectedꢀtoꢀtheꢀLeastꢀSigniﬁcantꢀBitꢀ(LSB)ꢀ

ofꢀanyꢀregister.

BoundaryꢀScanꢀRegister

Theꢀboundaryꢀscanꢀregisterꢀisꢀconnectedꢀtoꢀallꢀinputꢀandꢀ

outputꢀpinsꢀonꢀtheꢀSRAM.ꢀSeveralꢀnoꢀconnectꢀ(NC)ꢀpinsꢀareꢀ

alsoꢀincludedꢀinꢀtheꢀscanꢀregisterꢀtoꢀreserveꢀpinsꢀforꢀhigherꢀ

densityꢀdevices.ꢀTheꢀx36ꢀconﬁgurationꢀhasꢀaꢀ75-bit-longꢀ

registerꢀandꢀtheꢀx18ꢀconﬁgurationꢀalsoꢀhasꢀaꢀ75-bit-longꢀ

register.ꢀTheꢀboundaryꢀscanꢀregisterꢀisꢀloadedꢀwithꢀtheꢀ

contentsꢀofꢀtheꢀRAMꢀInputꢀandꢀOutputꢀringꢀwhenꢀtheꢀTAPꢀ

controllerꢀisꢀinꢀtheꢀCapture-DRꢀstateꢀandꢀthenꢀplacedꢀbe-

tweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀwhenꢀtheꢀcontrollerꢀisꢀmovedꢀ

toꢀtheꢀShift-DRꢀstate.ꢀTheꢀEXTEST,ꢀSAMPLE/PRELOADꢀ

andꢀSAMPLE-Zꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀcaptureꢀtheꢀ

contentsꢀofꢀtheꢀInputꢀandꢀOutputꢀring.

PERFORMINGꢀAꢀTAPꢀRESET

AꢀResetꢀisꢀperformedꢀbyꢀforcingꢀTMSꢀHIGHꢀ(Vdd)ꢀforꢀﬁveꢀ

risingꢀedgesꢀofꢀTCK.ꢀRESETꢀmayꢀbeꢀperformedꢀwhileꢀtheꢀ

SRAMꢀisꢀoperatingꢀandꢀdoesꢀnotꢀaffectꢀitsꢀoperation.ꢀAtꢀ

power-up,ꢀtheꢀTAPꢀisꢀinternallyꢀresetꢀtoꢀensureꢀthatꢀTDOꢀ

comesꢀupꢀinꢀaꢀhigh-Zꢀstate.

TAPꢀREGISTERS

TheꢀBoundaryꢀScanꢀOrderꢀtablesꢀshowꢀtheꢀorderꢀinꢀwhichꢀ

theꢀbitsꢀareꢀconnected.ꢀEachꢀbitꢀcorrespondsꢀtoꢀoneꢀofꢀtheꢀ

bumpsꢀonꢀtheꢀSRAMꢀpackage.ꢀTheꢀMSBꢀofꢀtheꢀregisterꢀisꢀ

connectedꢀtoꢀTDI,ꢀandꢀtheꢀLSBꢀisꢀconnectedꢀtoꢀTDO.

RegistersꢀareꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ

andꢀallowꢀdataꢀtoꢀbeꢀscannedꢀintoꢀandꢀoutꢀofꢀtheꢀSRAMꢀ

testꢀcircuitry.ꢀOnlyꢀoneꢀregisterꢀcanꢀbeꢀselectedꢀatꢀaꢀtimeꢀ

throughꢀtheꢀinstructionꢀregisters.ꢀDataꢀisꢀseriallyꢀloadedꢀ

intoꢀtheꢀTDIꢀpinꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputꢀonꢀ

theꢀTDOꢀpinꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCK.

ScanꢀRegisterꢀSizes

Registerꢀꢀ

Nameꢀ

BitꢀSizeꢀ

(x18)ꢀ

3ꢀ

BitꢀSizeꢀꢀ

(x36)ꢀ

3ꢀ

InstructionꢀRegister

Three-bitꢀinstructionsꢀcanꢀbeꢀseriallyꢀloadedꢀintoꢀtheꢀin-

structionꢀregister.ꢀThisꢀregisterꢀisꢀloadedꢀwhenꢀitꢀisꢀplacedꢀ

betweenꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀ(SeeꢀTAPꢀControllerꢀBlockꢀ

Diagram)ꢀ Atꢀpower-up,ꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀ

withꢀtheꢀIDCODEꢀinstruction.ꢀItꢀisꢀalsoꢀloadedꢀwithꢀtheꢀ

IDCODEꢀinstructionꢀifꢀtheꢀcontrollerꢀisꢀplacedꢀinꢀaꢀresetꢀ

stateꢀasꢀpreviouslyꢀdescribed.

Instructionꢀ

Bypassꢀ

1ꢀ

IDꢀ

32ꢀ

BoundaryꢀScanꢀ

75ꢀ

WhenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCaptureIRꢀstate,ꢀtheꢀtwoꢀ

leastꢀsigniﬁcantꢀbitsꢀareꢀloadedꢀwithꢀaꢀbinaryꢀ“01”ꢀpatternꢀtoꢀ

allowꢀforꢀfaultꢀisolationꢀofꢀtheꢀboardꢀlevelꢀserialꢀtestꢀpath.

Identiﬁcationꢀ(ID)ꢀRegister

TheꢀIDꢀregisterꢀisꢀloadedꢀwithꢀaꢀvendor-speciﬁc,ꢀ32-bitꢀ

codeꢀduringꢀtheꢀCapture-DRꢀstateꢀwhenꢀtheꢀIDCODEꢀcom-

mandꢀisꢀloadedꢀtoꢀtheꢀinstructionꢀregister.ꢀTheꢀIDCODEꢀ

isꢀhardwiredꢀintoꢀtheꢀSRAMꢀandꢀcanꢀbeꢀshiftedꢀoutꢀwhenꢀ

theꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀShift-DRꢀstate.ꢀTheꢀIDꢀregisterꢀ

hasꢀvendorꢀcodeꢀandꢀotherꢀinformationꢀdescribedꢀinꢀtheꢀ

IdentiﬁcationꢀRegisterꢀDeﬁnitionsꢀtable.

BypassꢀRegister

Toꢀsaveꢀtimeꢀwhenꢀseriallyꢀshiftingꢀdataꢀthroughꢀregisters,ꢀ

itꢀisꢀsometimesꢀadvantageousꢀtoꢀskipꢀcertainꢀstates.ꢀTheꢀ

bypassꢀregisterꢀisꢀaꢀsingle-bitꢀregisterꢀthatꢀcanꢀbeꢀplacedꢀ

betweenꢀTDIꢀandꢀTDOꢀpins.ꢀThisꢀallowsꢀdataꢀtoꢀbeꢀshiftedꢀ

throughꢀtheꢀSRAMꢀwithꢀminimalꢀdelay.ꢀTheꢀbypassꢀreg-

isterꢀisꢀsetꢀLOWꢀ(VSS)ꢀwhenꢀtheꢀBYPASSꢀinstructionꢀisꢀ

executed.

IDENTIFICATIONꢀREGISTERꢀDEFINITIONS

InstructionꢀFieldꢀ

Descriptionꢀ

ꢀ

256Kꢀxꢀ36ꢀ

xxxxꢀ

512Kꢀxꢀ18

xxxxꢀ

RevisionꢀNumberꢀ (31:28)ꢀꢀ Reservedꢀforꢀversionꢀnumber.ꢀ

DeviceꢀDepthꢀ (27:23)ꢀ

DeviceꢀWidthꢀ (22:18)ꢀ

ISSIꢀDeviceꢀIDꢀ (17:12)ꢀ

ISSIꢀJEDECꢀIDꢀ (11:1)ꢀ

DeﬁnesꢀdepthꢀofꢀSRAM.ꢀ256Kꢀorꢀ512Kꢀ

DeﬁnesꢀwidthꢀofꢀtheꢀSRAM.ꢀx36ꢀorꢀx18ꢀ

Reservedꢀforꢀfutureꢀuse.ꢀ

00111ꢀ

00100ꢀ

xxxxxꢀ

01000ꢀ

00011ꢀ

xxxxxꢀ

AllowsꢀuniqueꢀidentiﬁcationꢀofꢀSRAMꢀvendor.ꢀ

00011010101ꢀ 00011010101

1ꢀ 1ꢀ

IDꢀRegisterꢀPresenceꢀ (0)ꢀ IndicateꢀtheꢀpresenceꢀofꢀanꢀIDꢀregister.ꢀ

24ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

The

TAPꢀcontrollerꢀrecognizesꢀanꢀall-0ꢀinstruction.Whenꢀanꢀ

Eightꢀinstructionsꢀareꢀpossibleꢀwithꢀtheꢀthree-bitꢀinstructionꢀ

registerꢀandꢀallꢀcombinationsꢀareꢀlistedꢀinꢀtheꢀInstructionꢀ

SAMPLE/PRELOADꢀisꢀaꢀ1149.1ꢀmandatoryꢀinstruction.Theꢀ

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

TAPꢀINSTRUCTIONꢀSET

SAMPLE/PRELOAD

PRELOADꢀportionꢀofꢀthisꢀinstructionꢀisꢀnotꢀimplemented,ꢀsoꢀ

theꢀTAPꢀcontrollerꢀisꢀnotꢀfullyꢀ1149.1ꢀcompliant.ꢀWhenꢀtheꢀ

SAMPLE/PRELOADꢀinstructionꢀisꢀloadedꢀtoꢀtheꢀinstruc-

tionꢀregisterꢀandꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCapture-DRꢀ

state,ꢀaꢀsnapshotꢀofꢀdataꢀonꢀtheꢀinputsꢀandꢀoutputꢀpinsꢀisꢀ

capturedꢀinꢀtheꢀboundaryꢀscanꢀregister.

Codeꢀtable.ꢀThreeꢀinstructionsꢀareꢀlistedꢀasꢀRESERVED

ꢀ

andꢀshouldꢀnotꢀbeꢀusedꢀandꢀtheꢀotherꢀﬁveꢀinstructionsꢀareꢀ

describedꢀbelow.ꢀTheꢀTAPꢀcontrollerꢀusedꢀinꢀthisꢀSRAMꢀ

isꢀnotꢀfullyꢀcompliantꢀwithꢀtheꢀ1149.1ꢀconventionꢀbecauseꢀ

someꢀmandatoryꢀinstructionsꢀareꢀnotꢀfullyꢀimplemented.ꢀ

TheꢀTAPꢀcontrollerꢀcannotꢀbeꢀusedꢀtoꢀloadꢀaddress,ꢀdataꢀorꢀ

controlꢀsignalsꢀandꢀcannotꢀpreloadꢀtheꢀInputꢀorꢀOutputꢀbuf-

fers.ꢀTheꢀSRAMꢀdoesꢀnotꢀimplementꢀtheꢀ1149.1ꢀcommandsꢀ

EXTESTꢀorꢀINTESTꢀorꢀtheꢀPRELOADꢀportionꢀofꢀSAMPLE/

PRELOAD;ꢀinsteadꢀitꢀperformsꢀaꢀcaptureꢀofꢀtheꢀInputsꢀandꢀ

Outputꢀringꢀwhenꢀtheseꢀinstructionsꢀareꢀexecuted.ꢀInstruc-

tionsꢀareꢀloadedꢀintoꢀtheꢀTAPꢀcontrollerꢀduringꢀtheꢀShift-IRꢀ

stateꢀwhenꢀtheꢀinstructionꢀregisterꢀisꢀplacedꢀbetweenꢀTDIꢀ

andꢀTDO.ꢀDuringꢀthisꢀstate,ꢀinstructionsꢀareꢀshiftedꢀfromꢀ

theꢀinstructionꢀregisterꢀthroughꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀToꢀ

executeꢀanꢀinstructionꢀonceꢀitꢀisꢀshiftedꢀin,ꢀtheꢀTAPꢀcontrol-

lerꢀmustꢀbeꢀmovedꢀintoꢀtheꢀUpdate-IRꢀstate.

ItꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀtheꢀTAPꢀcontrollerꢀclockꢀoper-

atesꢀatꢀaꢀfrequencyꢀupꢀtoꢀ10ꢀMHz,ꢀwhileꢀtheꢀSRAMꢀclockꢀ

runsꢀmoreꢀthanꢀanꢀorderꢀofꢀmagnitudeꢀfaster.ꢀBecauseꢀofꢀ

theꢀclockꢀfrequencyꢀdifferences,ꢀitꢀisꢀpossibleꢀthatꢀduringꢀ

theꢀCapture-DRꢀstate,ꢀanꢀinputꢀorꢀoutputꢀwillꢀunder-goꢀaꢀ

transition.ꢀTheꢀTAPꢀmayꢀattemptꢀaꢀsignalꢀcaptureꢀwhileꢀinꢀ

transitionꢀ(metastableꢀstate).Theꢀdeviceꢀwillꢀnotꢀbeꢀharmed,ꢀ

butꢀthereꢀisꢀnoꢀguaranteeꢀofꢀtheꢀvalueꢀthatꢀwillꢀbeꢀcapturedꢀ

orꢀrepeatableꢀresults.

Toꢀguaranteeꢀthatꢀtheꢀboundaryꢀscanꢀregisterꢀwillꢀcaptureꢀ

theꢀcorrectꢀsignalꢀvalue,ꢀtheꢀSRAMꢀsignalꢀmustꢀbeꢀstabilizedꢀ

longꢀenoughꢀtoꢀmeetꢀtheꢀTAPꢀcontroller’sꢀcaptureꢀset-upꢀ

plusꢀholdꢀtimesꢀ(t^cSꢀandꢀtch).ꢀToꢀinsureꢀthatꢀtheꢀSRAMꢀclockꢀ

inputꢀisꢀcapturedꢀcorrectly,ꢀdesignsꢀneedꢀaꢀwayꢀtoꢀstopꢀ(orꢀ

slow)ꢀtheꢀclockꢀduringꢀaꢀSAMPLE/PRELOADꢀinstruction.ꢀ

Ifꢀthisꢀisꢀnotꢀanꢀissue,ꢀitꢀisꢀpossibleꢀtoꢀcaptureꢀallꢀotherꢀ

signalsꢀandꢀsimplyꢀignoreꢀtheꢀvalueꢀofꢀtheꢀCLKꢀcapturedꢀ

inꢀtheꢀboundaryꢀscanꢀregister.

EXTEST

EXTESTꢀisꢀaꢀmandatoryꢀ1149.1ꢀinstructionꢀwhichꢀisꢀtoꢀbeꢀ

executedꢀwheneverꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀwithꢀ

allꢀ0s.ꢀBecauseꢀEXTESTꢀisꢀnotꢀimplementedꢀinꢀtheꢀTAPꢀ

controller,ꢀthisꢀdeviceꢀisꢀnotꢀ1149.1ꢀstandardꢀcompliant.ꢀ

Onceꢀtheꢀdataꢀisꢀcaptured,ꢀitꢀisꢀpossibleꢀtoꢀshiftꢀoutꢀtheꢀdataꢀ

byꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀShift-DRꢀstate.ꢀThisꢀplacesꢀtheꢀ

boundaryꢀscanꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpins.

EXTESTꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregister,ꢀ

theꢀSRAMꢀrespondsꢀasꢀifꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ

hasꢀbeenꢀloaded.ꢀThereꢀisꢀaꢀdifferenceꢀbetweenꢀtheꢀinstruc-

tions,ꢀunlikeꢀtheꢀSAMPLE/PRELOADꢀinstruction,ꢀEXTESTꢀ

placesꢀtheꢀSRAMꢀoutputsꢀinꢀaꢀHigh-Zꢀstate.

NoteꢀthatꢀsinceꢀtheꢀPRELOADꢀpartꢀofꢀtheꢀcommandꢀisꢀnotꢀ

implemented,ꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀUpdateꢀtoꢀtheꢀUpdate-

DRꢀstateꢀwhileꢀperformingꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ

willꢀhaveꢀtheꢀsameꢀeffectꢀasꢀtheꢀPause-DRꢀcommand.

IDCODE

TheꢀIDCODEꢀinstructionꢀcausesꢀaꢀvendor-speciﬁc,ꢀ32-bitꢀ

codeꢀtoꢀbeꢀloadedꢀintoꢀtheꢀinstructionꢀregister.ꢀItꢀalsoꢀplacesꢀ

theꢀinstructionꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ

andꢀallowsꢀtheꢀIDCODEꢀtoꢀbeꢀshiftedꢀoutꢀofꢀtheꢀdeviceꢀ

whenꢀtheꢀTAPꢀcontrollerꢀentersꢀtheꢀShift-DRꢀstate.ꢀTheꢀ

IDCODEꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregisterꢀ

uponꢀpower-upꢀorꢀwheneverꢀtheꢀTAPꢀcontrollerꢀisꢀgivenꢀaꢀ

testꢀlogicꢀresetꢀstate.

BYPASS

WhenꢀtheꢀBYPASSꢀinstructionꢀisꢀloadedꢀinꢀtheꢀinstruc-

tionꢀregisterꢀandꢀtheꢀTAPꢀisꢀplacedꢀinꢀaꢀShift-DRꢀstate,ꢀ

theꢀbypassꢀregisterꢀisꢀplacedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ

pins.ꢀTheꢀadvantageꢀofꢀtheꢀBYPASSꢀinstructionꢀisꢀthatꢀitꢀ

shortensꢀtheꢀboundaryꢀscanꢀpathꢀwhenꢀmultipleꢀdevicesꢀ

areꢀconnectedꢀtogetherꢀonꢀaꢀboard.

SAMPLE-Z

RESERVED

Theꢀ SAMPLE-Zꢀ instructionꢀ causesꢀ theꢀ boundaryꢀ scanꢀ

registerꢀtoꢀbeꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ

whenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀaꢀShift-DRꢀstate.ꢀItꢀalsoꢀplacesꢀ

allꢀSRAMꢀoutputsꢀintoꢀaꢀHigh-Zꢀstate.

Theseꢀinstructionsꢀareꢀnotꢀimplementedꢀbutꢀareꢀreservedꢀ

forꢀfutureꢀuse.ꢀDoꢀnotꢀuseꢀtheseꢀinstructions.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

25

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

INSTRUCTIONꢀCODESꢀ

Codeꢀ

Instructionꢀ

Description

000ꢀ

EXTESTꢀ

CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbe-

tweenꢀtheꢀTDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputsꢀtoꢀHigh-Zꢀstate.ꢀThisꢀꢀ

instructionꢀisꢀnotꢀ1149.1ꢀcompliant.

001ꢀ

010ꢀ

IDCODEꢀ

LoadsꢀtheꢀIDꢀregisterꢀwithꢀtheꢀvendorꢀIDꢀcodeꢀandꢀplacesꢀtheꢀregisterꢀbetweenꢀTDIꢀ

andꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀaffectꢀSRAMꢀoperation.

SAMPLE-Zꢀ

CapturesꢀtheꢀInput/Outputꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbetweenꢀ

TDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputꢀdriversꢀtoꢀaꢀHigh-Zꢀstate.

011ꢀ

100ꢀ

RESERVEDꢀ

DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.

SAMPLE/PRELOAD

ꢀ

CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀ

betweenꢀTDIꢀandꢀTDO.ꢀDoesꢀnotꢀaffectꢀtheꢀSRAMꢀoperation.ꢀThisꢀinstructionꢀdoesꢀnotꢀ

implementꢀ1149.1ꢀpreloadꢀfunctionꢀandꢀisꢀthereforeꢀnotꢀ1149.1ꢀcompliant.

101ꢀ

110ꢀꢀ

111ꢀ

RESERVEDꢀ

BYPASSꢀ

DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.ꢀꢀ

DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.

PlacesꢀtheꢀbypassꢀregisterꢀbetweenꢀTDIꢀandꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀ

affectꢀSRAMꢀoperation.

TAPꢀCONTROLLERꢀSTATEꢀDIAGRAM

Test Logic Reset

1

0

1

Run Test/Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

0

1

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

0

Exit2 DR

1

Exit2 IR

1

0

1

0

1

Update DR

0

Update IR

0

26ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

TAPꢀElectricalꢀCharacteristicsꢀOverꢀtheꢀOperatingꢀRange^(1,2)

Symbolꢀ

Voh1ꢀ

Voh2ꢀ

Vol1ꢀ

Vol2ꢀ

VIhꢀ

Parameterꢀ

TestꢀConditionsꢀ

Min.ꢀ

1.7ꢀ

2.1ꢀ

—ꢀ

Max.ꢀ

—ꢀ

Units

OutputꢀHIGHꢀVoltageꢀ

OutputꢀLOWꢀVoltageꢀ

InputꢀHIGHꢀVoltageꢀ

InputꢀLOWꢀVoltageꢀ

InputꢀLeakageꢀCurrentꢀ

Iohꢀ=ꢀ–2.0ꢀmAꢀ

V

Iohꢀ=ꢀ–100ꢀ

ꢁ

Aꢀ

—ꢀ

Iolꢀ=ꢀ2.0ꢀmAꢀ

0.7ꢀ

Iolꢀ=ꢀ100ꢀ

ꢁ

Aꢀ

—ꢀ

0.2ꢀ

ꢀ

1.7ꢀ

–0.3ꢀ

–10ꢀ

Vddꢀ+0.3ꢀ

0.7ꢀ

VIlꢀ

Ixꢀ

VSSꢀ≤ꢀVꢀIꢀ≤ꢀVddqꢀ

10ꢀ

ꢁA

Notes:

1.ꢀ AllꢀVoltageꢀreferencedꢀtoꢀGround.

2.ꢀ Overshoot:ꢀV^Ihꢀ(AC)ꢀ≤ꢀꢀVddꢀ+1.5Vꢀforꢀtꢀ≤ ꢀtTcyc/2,ꢀ

ꢀ

Undershoot:ꢀV^Ilꢀ(AC)ꢀ≤ ꢀ0.5Vꢀforꢀtꢀ≤ ꢀtTcyc/2,ꢀ

Power-up:ꢀV^Ihꢀ<ꢀ2.6VꢀandꢀVddꢀ<ꢀ2.4VꢀandꢀVddqꢀ<ꢀ1.4Vꢀforꢀtꢀ<ꢀ200ꢀms.

TAPꢀACꢀELECTRICALꢀCHARACTERISTICS^(1,2)ꢀ(OVERꢀOPERATINGꢀRANGE)

ꢀ

Symbolꢀ Parameterꢀ

ꢀ

ꢀ Min.ꢀ

Max.ꢀ

—ꢀ

10ꢀ

—

Unit

ns

tTcyc

fTf

TCKꢀClockꢀcycleꢀtimeꢀ

ꢀ

100ꢀ

—ꢀ

40ꢀ

10ꢀ

—ꢀ

0ꢀ

TCKꢀClockꢀfrequencyꢀ

TCKꢀClockꢀHIGHꢀ

TCKꢀClockꢀLOWꢀ

MHz

ns

tTh

tTlꢀ

—ꢀ

20ꢀ

—ꢀ

ns

tTMSS

tTdIS

tcS

TMSꢀsetupꢀtoꢀTCKꢀClockꢀRiseꢀꢀ

TDIꢀsetupꢀtoꢀTCKꢀClockꢀRiseꢀ ꢀ

ns

CaptureꢀsetupꢀtoꢀTCKꢀRiseꢀ

TMSꢀholdꢀafterꢀTCKꢀClockꢀRiseꢀ ꢀ

TDIꢀHoldꢀafterꢀClockꢀRiseꢀ

CaptureꢀholdꢀafterꢀClockꢀRiseꢀ ꢀ

ꢀ

ns

tTMSh

tTdIh

tch

ns

ꢀ

ns

tTdoV

TCKꢀLOWꢀtoꢀTDOꢀvalidꢀ

TCKꢀLOWꢀtoꢀTDOꢀinvalidꢀ

ꢀ

ns

tTdox

ns

Notes:

1.ꢀBothꢀtcSꢀandꢀtch referꢀtoꢀtheꢀset-upꢀandꢀholdꢀtimeꢀrequirementsꢀofꢀlatchingꢀdataꢀfromꢀtheꢀboundaryꢀscanꢀregister.

2.ꢀTestꢀconditionsꢀareꢀspeciﬁedꢀusingꢀtheꢀloadꢀinꢀTAPꢀACꢀtestꢀconditions.ꢀt^r/tfꢀ=ꢀ1ꢀns.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

27

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

TAPꢀACꢀTESTꢀCONDITIONSꢀ(2.5V/3.3V)

TAPꢀOutputꢀLoadꢀEquivalent

Inputꢀpulseꢀlevelsꢀ

0ꢀtoꢀ2.5V/0ꢀtoꢀ3.0V

1ns

Inputꢀriseꢀandꢀfallꢀtimesꢀ

Inputꢀtimingꢀreferenceꢀlevelsꢀ

Outputꢀreferenceꢀlevelsꢀ

1.25V/1.5V

50Ω

Vtrig

Testꢀloadꢀterminationꢀsupplyꢀvoltageꢀ

Vtrigꢀ

1.25V/1.5V

TDO

20 pF

GND

Z0

= 50Ω

TAPꢀTIMING

1

2

3

4

5

6

tTHTH

tTLTH

TCK

TMS

t

THTL

t

MVTH THMX

t

tDVTH

tTHDX

TDI

tTLOV

TDO

t

TLOX

DON'T CARE

UNDEFINED

28ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

Bitꢀ#ꢀ Nameꢀ

IDꢀ

11Gꢀ

11Fꢀ

11Eꢀ

11Dꢀ

10Gꢀ

10Fꢀ

10Eꢀ

10Dꢀ

11Cꢀ

11Aꢀ

10Aꢀ

10Bꢀ

9Aꢀ

Bitꢀ#ꢀ Nameꢀ

IDꢀ

1Aꢀ

6Aꢀ

5Bꢀ

5Aꢀ

4Aꢀ

4Bꢀ

3Bꢀ

3Aꢀ

2Aꢀ

2Bꢀ

1Bꢀ

1Cꢀ

1Dꢀ

1Eꢀ

1Fꢀ

1Gꢀ

2D

Bitꢀ#ꢀ Nameꢀ

ID

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

165ꢀPBGAꢀBOUNDARYꢀSCANꢀORDERꢀ(xꢀ36)

ꢀ ꢀ

Bitꢀ#ꢀ Nameꢀ IDꢀ

MODEꢀ 1Rꢀ

Signalꢀ Bumpꢀ

ꢀ

Signalꢀ Bumpꢀ

ꢀ

Signalꢀ Bumpꢀ

ꢀ

Signalꢀ Bump

ꢀ 1ꢀ

ꢀ 2ꢀ

ꢀ 3ꢀ

ꢀ 4ꢀ

ꢀ 5ꢀ

ꢀ 6ꢀ

ꢀ 7ꢀ

ꢀ 8ꢀ

ꢀ 9ꢀ

ꢀ10ꢀ

ꢀ11ꢀ

ꢀ12ꢀ

ꢀ13ꢀ

ꢀ14ꢀ

ꢀ15ꢀ

ꢀ16ꢀ

ꢀ17ꢀ

ꢀ18ꢀ

ꢀ19ꢀ

ꢀ20ꢀ

21ꢀ

22ꢀ

23ꢀ

24ꢀ

25ꢀ

26ꢀ

27ꢀ

28ꢀ

29ꢀ

30ꢀ

31ꢀ

32ꢀ

33ꢀ

34ꢀ

35ꢀ

36ꢀ

37ꢀ

38ꢀ

39ꢀ

40ꢀ

DQbꢀ

NCꢀ

41ꢀ

42ꢀ

43ꢀ

44ꢀ

45ꢀ

46ꢀ

47ꢀ

48ꢀ

49ꢀ

50ꢀ

51ꢀ

52ꢀ

53ꢀ

54ꢀ

55ꢀ

56ꢀ

57ꢀ

58ꢀ

59ꢀ

60ꢀ

NCꢀ

CE2ꢀ

BWaꢀ

BWbꢀ

BWcꢀ

BWdꢀ

CE2ꢀ

CEꢀ

61ꢀ

62ꢀ

63ꢀ

64ꢀ

65ꢀ

66ꢀ

67ꢀ

68ꢀ

69ꢀ

70ꢀ

71ꢀ

72ꢀ

73ꢀ

74ꢀ

75ꢀ

ꢀ

DQdꢀ

Aꢀ

1J

NCꢀ

Aꢀ

6Nꢀ

11Pꢀ

8Pꢀ

1K

1L

1M

2J

Aꢀ

8Rꢀ

Aꢀ

9Rꢀ

2K

2L

2M

1N

3P

3R

4R

4P

6P

6R

Aꢀ

9Pꢀ

Aꢀ

10Pꢀ

10Rꢀ

11Rꢀ

11Hꢀ

Aꢀ

ZZꢀ

Aꢀ

NCꢀ

Aꢀ

DQaꢀ 11Nꢀ

DQaꢀ 11Mꢀ

DQaꢀ 11Lꢀ

DQaꢀ 11Kꢀ

DQaꢀ 11Jꢀ

DQaꢀ 10Mꢀ

DQaꢀ 10Lꢀ

DQaꢀ 10Kꢀ

DQaꢀ 10Jꢀ

Aꢀ

DQcꢀ

Aꢀ

NCꢀ

9Bꢀ

A1ꢀ

ADVꢀ

OEꢀ

8Aꢀ

A0ꢀ

8Bꢀ

CKEꢀ

WEꢀ

CLKꢀ

NCꢀ

7Aꢀ

7Bꢀ

2E

6Bꢀ

2F

11Bꢀ

2G

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

29

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

119ꢀBGAꢀBOUNDARYꢀSCANꢀORDERꢀ(xꢀ36)

30ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

Bitꢀ#ꢀ Nameꢀ

IDꢀ

11Gꢀ

11Fꢀ

11Eꢀ

11Dꢀ

11Cꢀ

10Fꢀ

10Eꢀ

10Dꢀ

10Gꢀ

11Aꢀ

10Aꢀ

10Bꢀ

9Aꢀ

Bitꢀ#ꢀ Nameꢀ

IDꢀ

1Aꢀ

6Aꢀ

5Bꢀ

5Aꢀ

4Aꢀ

4Bꢀ

3Bꢀ

3Aꢀ

2Aꢀ

2Bꢀ

1Bꢀ

1Cꢀ

1Dꢀ

1Eꢀ

1Fꢀ

1Gꢀ

2D

Bitꢀ#ꢀ Nameꢀ

ID

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

165ꢀPBGAꢀBOUNDARYꢀSCANꢀORDERꢀ(xꢀ18)

ꢀ ꢀ

Bitꢀ#ꢀ Nameꢀ IDꢀ

MODEꢀ 1Rꢀ

Signalꢀ Bumpꢀ

ꢀ

Signalꢀ Bumpꢀ

ꢀ

Signalꢀ Bumpꢀ

ꢀ

Signalꢀ Bump

ꢀ 1ꢀ

ꢀ 2ꢀ

ꢀ 3ꢀ

ꢀ 4ꢀ

ꢀ 5ꢀ

ꢀ 6ꢀ

ꢀ 7ꢀ

ꢀ 8ꢀ

ꢀ 9ꢀ

ꢀ10ꢀ

ꢀ11ꢀ

ꢀ12ꢀ

ꢀ13ꢀ

ꢀ14ꢀ

ꢀ15ꢀ

ꢀ16ꢀ

ꢀ17ꢀ

ꢀ18ꢀ

ꢀ19ꢀ

ꢀ20ꢀ

21ꢀ

22ꢀ

23ꢀ

24ꢀ

25ꢀ

26ꢀ

27ꢀ

28ꢀ

29ꢀ

30ꢀ

31ꢀ

32ꢀ

33ꢀ

34ꢀ

35ꢀ

36ꢀ

37ꢀ

38ꢀ

39ꢀ

40ꢀ

DQaꢀ

NCꢀ

Aꢀ

41ꢀ

42ꢀ

43ꢀ

44ꢀ

45ꢀ

46ꢀ

47ꢀ

48ꢀ

49ꢀ

50ꢀ

51ꢀ

52ꢀ

53ꢀ

54ꢀ

55ꢀ

56ꢀ

57ꢀ

58ꢀ

59ꢀ

60ꢀ

NCꢀ

CE2ꢀ

BWaꢀ

NCꢀ

61ꢀ

62ꢀ

63ꢀ

64ꢀ

65ꢀ

66ꢀ

67ꢀ

68ꢀ

69ꢀ

70ꢀ

71ꢀ

72ꢀ

73ꢀ

74ꢀ

75ꢀ

ꢀ

DQbꢀ

NCꢀ

Aꢀ

1J

NCꢀ

Aꢀ

6Nꢀ

11Pꢀ

8Pꢀ

1K

1L

1M

1N

2K

2L

2M

2J

Aꢀ

8Rꢀ

BWbꢀ

NCꢀ

Aꢀ

9Rꢀ

Aꢀ

9Pꢀ

CE2ꢀ

CEꢀ

Aꢀ

10Pꢀ

10Rꢀ

11Rꢀ

11Hꢀ

11Nꢀ

11Mꢀ

11Lꢀ

11Kꢀ

11Jꢀ

Aꢀ

3P

3R

4R

4P

6P

6R

ZZꢀ

NCꢀ

Aꢀ

NCꢀ

Aꢀ

NCꢀ

Aꢀ

NCꢀ

Aꢀ

NCꢀ

ADVꢀ

OEꢀ

CKEꢀ

WEꢀ

CLKꢀ

NCꢀ

9Bꢀ

NCꢀ

A1ꢀ

8Aꢀ

NCꢀ

A0ꢀ

8Bꢀ

NCꢀ

DQaꢀ 10Mꢀ

DQaꢀ 10Lꢀ

DQaꢀ 10Kꢀ

DQaꢀ 10Jꢀ

7Aꢀ

DQbꢀ

7Bꢀ

2E

6Bꢀ

2F

11Bꢀ

2G

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

31

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

119ꢀBGAꢀBOUNDARYꢀSCANꢀORDERꢀ(xꢀ18)

32ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

119ꢀPBGA,ꢀLead-free

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

ORDERINGꢀINFORMATIONꢀ(VDDꢀ=ꢀ3.3V/VDDqꢀ=ꢀ2.5V/3.3V)

CommercialꢀRange:ꢀ0°Cꢀtoꢀ+70°C

ꢀ

AccessꢀTimeꢀ

OrderꢀPartꢀNumberꢀ

256Kx36

Package

ꢀ

250ꢀ

IS61NLP25636A-250TQꢀ

100ꢀTQFP

ꢀ

IS61NLP25636A-250B3ꢀ

IS61NLP25636A-250B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

IS61NLP25636A-200TQꢀ

100ꢀTQFP

ꢀ

IS61NLP25636A-200B3ꢀ

IS61NLP25636A-200B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

512Kx18

ꢀ

250ꢀ

IS61NLP51218A-250TQꢀ

100ꢀTQFP

ꢀ

IS61NLP51218A-250B3ꢀ

IS61NLP51218A-250B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

IS61NLP51218A-200TQꢀ

100ꢀTQFP

ꢀ

IS61NLP51218A-200B3ꢀ

IS61NLP51218A-200B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°C

ꢀ

AccessꢀTimeꢀ

OrderꢀPartꢀNumberꢀ

Package

ꢀ

256Kx36

250ꢀ

IS61NLP25636A-250TQIꢀ

100ꢀTQFPꢀ

ꢀ

IS61NLP25636A-250B3Iꢀ

IS61NLP25636A-250B2Iꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

ꢀ

IS61NLP25636A-200TQIꢀ

IS61NLP25636A-200TQLIꢀ

100ꢀTQFPꢀ

ꢀ

100ꢀTQFP,ꢀLead-free

165ꢀPBGAꢀ

165ꢀPBGA,ꢀLead-freeꢀ

119ꢀPBGAꢀ

ꢀ

IS61NLP25636A-200B3Iꢀ

IS61NLP25636A-200B3LIꢀ

IS61NLP25636A-200B2Iꢀ

IS61NLP25636A-200B2LIꢀ

ꢀ

512Kx18

ꢀ

250ꢀ

IS61NLP51218A-250TQIꢀ

100ꢀTQFP

ꢀ

IS61NLP51218A-250B3Iꢀ

IS61NLP51218A-250B2Iꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

ꢀ

IS61NLP51218A-200TQIꢀ

IS61NLP51218A-200TQLIꢀ

100ꢀTQFPꢀ

100ꢀTQFP,ꢀLead-free

ꢀ

IS61NLP51218A-200B3Iꢀ

IS61NLP51218A-200B2Iꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

33

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

ORDERINGꢀINFORMATIONꢀ(VDDꢀ=ꢀ2.5V/VDDqꢀ=ꢀ2.5V)

CommercialꢀRange:ꢀ0°Cꢀtoꢀ+70°C

ꢀ

AccessꢀTimeꢀ

OrderꢀPartꢀNumberꢀ

256Kx36

Package

ꢀ

250ꢀ

IS61NVP25636A-250TQꢀ

100ꢀTQFP

ꢀ

IS61NVP25636A-250B3ꢀ

IS61NVP25636A-250B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

IS61NVP25636A-200TQꢀ

100ꢀTQFP

ꢀ

IS61NVP25636A-200B3ꢀ

IS61NVP25636A-200B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

512Kx18

ꢀ

250ꢀ

IS61NVP51218A-250TQꢀ

100ꢀTQFP

ꢀ

IS61NVP51218A-250B3ꢀ

IS61NVP51218A-250B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

IS61NVP51218A-200TQꢀ

100ꢀTQFP

ꢀ

IS61NVP51218A-200B3ꢀ

IS61NVP51218A-200B2ꢀ

165ꢀPBGAꢀ

119ꢀPBGA

IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°C

ꢀ

AccessꢀTimeꢀ

OrderꢀPartꢀNumberꢀ

Package

ꢀ

256Kx36

250ꢀ

IS61NVP25636A-250TQIꢀ

100ꢀTQFP

ꢀ

IS61NVP25636A-250B3Iꢀ

IS61NVP25636A-250B2Iꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

ꢀ

IS61NVP25636A-200TQIꢀ

IS61NVP25636A-200TQLIꢀ

100ꢀTQFPꢀ

100ꢀTQFP,ꢀLeadfree

ꢀ

IS61NVP25636A-200B3Iꢀ

IS61NVP25636A-200B3LIꢀ

IS61NVP25636A-200B2Iꢀ

165ꢀPBGAꢀ

165ꢀPBGA,ꢀLeadfreeꢀꢀ

119ꢀPBGA

ꢀ

512Kx18

ꢀ

250ꢀ

IS61NVP51218A-250TQIꢀ

100ꢀTQFP

ꢀ

IS61NVP51218A-250B3Iꢀ

IS61NVP51218A-250B2Iꢀ

165ꢀPBGAꢀ

119ꢀPBGA

ꢀ

200ꢀ

IS61NVP51218A-200TQIꢀ

100ꢀTQFP

ꢀ

IS61NVP51218A-200B3Iꢀ

IS61NVP51218A-200B2Iꢀ

165ꢀPBGAꢀ

119ꢀPBGA

34ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

35

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

36ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.ꢀ H

08/09/2011

ꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ ꢀ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

37

Rev.ꢀ H

08/09/2011


型号：	IS61NVP51218A-200B2I-TR
厂家：	INTEGRATED SILICON SOLUTION, INC
描述：	ZBT SRAM, 512KX18, 3.1ns, CMOS, PBGA119 时钟静态存储器内存集成电路
文件：	总37页 (文件大小：533K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IS61NVP51218A-200B2I-TR [ISSI]

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