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IS61QDB41M36C-300M3I [ISSI]

QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165;
IS61QDB41M36C-300M3I
型号： IS61QDB41M36C-300M3I
厂家： INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述：

QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165

静态存储器
文件： 总32页 (文件大小：804K)
中文：  中文翻译
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IS61QDB42M18C  
IS61QDB41M36C  
2Mx18, 1Mx36  
36Mb QUAD (Burst 4) SYNCHRONOUS SRAM  
APRIL 2016  
FEATURES  
DESCRIPTION  
The 36Mb IS61QDB41M36C and IS61QDB42M18C are  
synchronous, high-performance CMOS static random access  
memory (SRAM) devices. These SRAMs have separate I/Os,  
eliminating the need for high-speed bus turnaround. The  
rising edge of K clock initiates the read/write operation, and  
all internal operations are self-timed. Refer to the Timing  
Reference Diagram for Truth Table for a description of the  
basic operations of these QUAD (Burst of 4) SRAMs.  
1Mx36 and 2Mx18 configuration available.  
On-chip Delay-Locked Loop (DLL) for wide data  
valid window.  
Separate independent read and write ports with  
concurrent read and write operations.  
Synchronous pipeline read with late write operation.  
Double Data Rate (DDR) interface for read and  
write input ports.  
Read and write addresses are registered on alternating rising  
edges of the K clock. Reads and writes are performed in  
double data rate. The following are registered internally on  
the rising edge of the K clock:  
1.5 cycle read latency.  
Fixed 4-bit burst for read and write operations.  
Clock stop support.  
Read/write address  
Two input clocks (K and K#) for address and control  
registering at rising edges only.  
Read enable  
Two output clocks (C and C#) for data output control.  
Write enable  
Two echo clocks (CQ and CQ#) that are delivered  
simultaneously with data.  
Byte writes for burst addresses 1 and 3  
Data-in for burst addresses 1 and 3  
+1.8V core power supply and 1.5, 1.8V VDDQ, used  
with 0.75, 0.9V VREF.  
The following are registered on the rising edge of the K#  
clock:  
HSTL input and output levels.  
Byte writes for burst addresses 2 and 4  
Registered addresses, write and read controls, byte  
writes, data in, and data outputs.  
Data-in for burst addresses 2 and 4  
Full data coherency.  
Byte writes can change with the corresponding data-in to  
enable or disable writes on a per-byte basis. An internal write  
buffer enables the data-ins to be registered one cycle after  
the write address. The first data-in burst is clocked one cycle  
later than the write command signal, and the second burst is  
timed to the following rising edge of the K# clock. Two full  
clock cycles are required to complete a write operation.  
Boundary scan using limited set of JTAG 1149.1  
functions.  
Byte write capability.  
Fine ball grid array (FBGA) package:  
13mmx15mm and 15mmx17mm body size  
165-ball (11 x 15) array  
Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
During the burst read operation, the data-outs from the first  
and third bursts are updated from output registers of the  
second and third rising edges of the C# clock (starting 1.5  
cycles later after read command). The data-outs from the  
second and fourth bursts are updated with the third and  
fourth rising edges of the C clock. The K and K# clocks are  
used to time the data-outs whenever the C and C# clocks are  
tied high. Two full clock cycles are required to complete a  
read operation.  
The device is operated with a single +1.8V power supply and  
is compatible with HSTL I/O interfaces.  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
1
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Package ballout and description  
x36 FBGA Ball Configuration (Top View)  
1
2
3
4
5
BW2#  
BW3#  
SA  
6
7
BW1#  
BW0#  
SA  
8
9
10  
NC/SA1  
Q17  
Q7  
11  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
A
B
C
D
E
F
CQ#  
Q27  
D27  
D28  
Q29  
Q30  
D30  
Doff#  
D31  
Q32  
Q33  
D33  
D34  
Q35  
TDO  
NC/SA1 NC/SA1  
W#  
K#  
R#  
SA  
Q18  
Q28  
D20  
D29  
Q21  
D22  
VREF  
Q31  
D32  
Q24  
Q34  
D26  
D35  
TCK  
D18  
D19  
Q19  
Q20  
D21  
Q22  
VDDQ  
D23  
Q23  
D24  
D25  
Q25  
Q26  
SA  
SA  
K
SA  
D17  
D16  
Q16  
Q15  
D14  
Q13  
VDDQ  
D12  
Q12  
D11  
D10  
Q10  
Q9  
VSS  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SA  
C
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
D15  
D6  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
Q14  
D13  
VREF  
Q4  
G
H
J
K
L
D3  
Q11  
Q1  
M
N
P
VSS  
VSS  
D9  
SA  
SA  
SA  
SA  
D0  
R
Notes:  
SA  
SA  
C#  
SA  
SA  
SA  
TMS  
The following balls are reserved for higher densities: 3A for 72Mb, 10A for 144Mb, and 2A for 288Mb.  
x18 FBGA Ball Configuration (Top View)  
1
CQ#  
NC  
NC  
NC  
NC  
NC  
NC  
Doff#  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/SA1  
Q9  
3
4
5
BW1#  
NC  
SA  
6
7
NC/SA1  
BW0#  
SA  
8
9
SA  
10  
NC/SA1  
NC  
11  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
A
B
C
D
E
F
SA  
W#  
K#  
R#  
D9  
SA  
K
SA  
NC  
NC  
NC  
NC  
NC  
NC  
VDDQ  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
NC  
D10  
Q10  
Q11  
D12  
Q13  
VDDQ  
D14  
Q14  
D15  
D16  
Q16  
Q17  
SA  
VSS  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SA  
C
VSS  
Q7  
D11  
NC  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
VSS  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
D6  
Q12  
D13  
VREF  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
NC  
G
H
J
NC  
VREF  
Q4  
K
L
NC  
D3  
Q15  
NC  
NC  
M
N
P
R
VSS  
Q1  
D17  
NC  
VSS  
SA  
VSS  
NC  
SA  
SA  
SA  
SA  
D0  
TCK  
SA  
SA  
C#  
SA  
SA  
TMS  
Notes:  
1.  
The following balls are reserved for higher densities: 10A for 72Mb, 2A for 144Mb, and 7A for 288Mb.  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
2
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Ball Descriptions  
Symbol  
Type  
Description  
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and  
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of  
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.  
These balls cannot remain VREF level.  
K, K#  
Input  
Input clock for output data. C and C# are used to clock out the READ data. They can be used  
together to deskew the flight times of various devices on the board back to the controller. See  
application example for further details.  
C, C#  
Input  
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the  
synchronous data outputs and can be used as a data valid indication. These signals are free running  
clocks and do not stop when Q tri-states.  
CQ, CQ#  
Output  
DLL disable and reset input: when low, this input causes the DLL to be bypassed and reset the  
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock  
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the  
device can be operated at a frequency of up to 167 MHz.  
Synchronous address inputs: These inputs are registered and must meet the setup and hold times  
around the rising edge of K. These inputs are ignored when device is deselected.  
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K  
and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of  
individual signals.  
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.  
The x36 device uses D0~D35.  
Synchronous data outputs: Output data is synchronized to the respective C and C#, or to the  
respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.  
See BALL CONFIGURATION figures for ball site location of individual signals.  
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.  
Doff#  
SA  
Input  
Input  
D0 - Dn  
Q0 - Qn  
Input  
Output  
The x36 device uses Q0~Q35.  
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE  
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.  
Synchronous read: When low, this input causes the address inputs to be registered and a READ  
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.  
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and  
written during WRITE cycles. These signals are sampled on the same edge as the corresponding  
data and must meet setup and hold times around the rising edges of K and #K for each of the two  
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.  
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise  
W#  
R#  
Input  
Input  
BWx#  
Input  
Input  
VREF  
VDD  
reference margin. Provides a reference voltage for the HSTL input buffers.  
Power  
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.  
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating  
Conditions for range.  
VDDQ  
Power  
VSS  
ZQ  
Ground  
Input  
Ground of the device  
Output impedance matching input: This input is used to tune the device outputs to the system data  
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this  
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance  
mode. This ball cannot be connected directly to VSS or left unconnected.  
TMS, TDI,  
TCK  
Input  
Output  
N/A  
IEEE1149.1 input pins for JTAG.  
TDO  
IEEE1149.1 output pins for JTAG.  
No connect: These signals should be left floating or connected to ground to improve package heat  
dissipation.  
NC  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
3
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
SRAM Features description  
Block Diagram  
36 (18)  
Data  
D (Data-In)  
Register  
72 (36)  
72 (36)  
Write  
Driver  
36 (18)  
18 (19)  
Address  
72 (36)  
72 (36)  
Address  
Q (Data-out)  
Register  
18 (19)  
144 (72)  
1M x 36  
(2M x 18)  
Memory Array  
Output  
Register  
2
R#  
CQ, CQ#  
(Echo Clocks)  
Control  
Logic  
W#  
4 (2)  
BWx#  
K
K#  
C
C#  
Clock  
Generator  
Select Output Control  
Doff#  
Note: Numerical values in parentheses refer to the x18 device configuration.  
Read Operations  
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R# in active low state  
at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to  
complete the burst of four in DDR mode. A second set of clocks, C and C#, are used to control the timing to the  
outputs. A set of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs.  
The echo clocks can be used as data capture clocks by the receiver device.  
When the C and C# clocks are connected high, then the K and K# clocks assume the function of those clocks. In this  
case, the data corresponding to the first address is clocked one and half cycles later by the rising edge of the K# clock.  
The data corresponding to the second burst is clocked two cycles later by the following rising edge of the K clock. The  
third data-out is clocked by the subsequent rising edge of the K# clock, and the fourth data-out is clocked by the  
subsequent rising edge of the K clock.  
A NOP operation (R# is high) does not terminate the previous read.  
Write Operations  
Write operations can also be initiated at every other rising edge of the K clock whenever W# is low. The write address  
is provided simultaneously. Again, the write always occurs in bursts of four.  
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is  
presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write  
burst address follows next, registered by the rising edge of K#. The third data-in is clocked by the subsequent rising  
edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the K# clock.  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
4
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array  
on the third write cycle. A read cycle to the last two write addresses produces data from the write buffers. The SRAM  
maintains data coherency.  
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see  
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).  
Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.  
RQ Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust  
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the  
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee  
impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches  
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.  
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be  
connected to VSS.  
Programmable Impedance and Power-Up Requirements  
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in  
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances  
values. The final impedance value is achieved within 1024 clock cycles.  
Clock Consideration  
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to  
minimize power and requires only 1024 cycles to restart.  
No clocks can be issued until VDD reaches its allowable operating range.  
Single Clock Mode  
This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up  
and must never change. Under this condition, K and K# will control the output timings.  
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differential  
clocks.  
Depth Expansion  
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected  
independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending  
read and write transactions are always completed prior to deselecting the corresponding port.  
Delay Locked Loop (DLL)  
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to  
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match  
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.  
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the  
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL  
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy  
QUAD mode.  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
5
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#  
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is  
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being  
reset, it gets locked after 2048 cycles of stable clock.  
Power-Up and Power-Down Sequences  
The recommendation of voltage apply sequence is: VDD → VDDQ 1) →VREF2) → VIN  
Notes:  
VDDQ can be applied concurrently with VDD  
.
VREF can be applied concurrently with VDDQ  
.
After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKC-  
lock cycle period, device initializes internal logics and locks DLL. Depending on Doff# status, locking DLL will be  
skipped. The following timing pictures are possible examples of power up sequence.  
Sequence1. Doff# is fixed low  
After tKC-lock cycle of stable clock, device is ready for normal operation.  
Power On stage  
Unstable Clock Period  
Stable Clock period  
Read to use  
K
K#  
VDD  
>tKC-lock for device initialization  
VDDQ  
VREF  
VIN  
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.  
Sequence2. Doff# is controlled and goes high after clock being stable.  
Power On stage  
Unstable Clock Period  
Stable Clock period  
Read to use  
K
K#  
Doff#  
>tKC-lock for device initialization  
VDD  
VDDQ  
VREF  
VIN  
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
6
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
7
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Sequence3. Doff# is controlled but goes high before clock being stable.  
Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input.  
a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKC-  
Lock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that.  
Power On stage  
Unstable Clock Period  
K-Stop  
Stable Clock period  
Read to use  
K
K#  
Doff#  
>30nS  
>tKC-lock for device initialization  
VDD  
VDDQ  
VREF  
VIN  
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.  
a) Doff# Low to reset. If Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will  
be locked with a new stable value. Device can be ready for normal operation after that.  
Power On stage  
Unstable Clock Period Doff reset DLL  
Stable Clock period  
Read to use  
K
K#  
Doff#  
>tKC-lock for device  
initialization  
>tDoffLowToReset  
VDD  
VDDQ  
VREF  
VIN  
Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off.  
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
8
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Application Example  
In the following application example, the second pair of C and C# clocks is delayed such that the return data meets the  
data setup and hold times at the memory controller.  
Vt Vt  
R
R
Data-Out  
Address  
D
SA  
R#  
W#  
BWx#  
K
Read Control  
Write Control  
Byte Write Control  
Source CLK  
Return CLK  
C
Source CLK#  
Return CLK#  
K#  
SRAM #1  
C#  
Vt  
R
R
Memory  
Controller  
R
Vt Vt  
Data-In  
SRAM #1 CQ Input  
SRAM #1 CQ# Input  
SRAM #4 CQ Input  
SRAM #4 CQ# Input  
Q
CQ  
CQ#  
ZQ  
RQ = 250Ω  
R = 50Ω  
Vt = V REF  
D
SA  
R#  
W#  
BWx#  
K
C
K#  
SRAM #4  
C#  
Q
CQ  
CQ#  
ZQ  
RQ = 250Ω  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
9
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
State Diagram  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
10  
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Power-Up  
Read#  
Read NOP  
Read  
Write#  
Write NOP  
Write  
Load New Read  
Address  
D count = 0  
Load New Write  
Address  
D count = 0  
Read#  
D count = 2  
Write#  
D count = 2  
Read  
D count = 2  
Write  
D count = 2  
Always  
Always  
DDR-II Read  
D count =  
DDR-II Write  
D count =  
D count +1  
D count +1  
Read  
D count = 1  
Write  
D count = 1  
Always  
Always  
Increment Read  
Address  
Increment Write  
Address  
Notes:  
1.  
2.  
3.  
4.  
5.  
Internal burst counter is fixed as four-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1, A0+2, and A0+3.  
Read refers to read active status with R# = LOW. Read# refers to read inactive status with R# = HIGH.  
Write refers to write active status with W# = LOW. Write# refers to write inactive status with W# = HIGH.  
The read and write state machines can be active simultaneously.  
State machine control timing sequence is controlled by K.  
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Timing Reference Diagram for Truth Table  
The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it  
shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued  
at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”.  
Cycle  
t
t + 1  
t + 2  
t + 3  
t + 4  
t + 5  
K Clock  
K# Clock  
R#  
W#  
BWx#  
Address  
Data-In  
Data-Out  
C Clock  
C# Clock  
CQ Clock  
CQ# Clock  
A
B
DB  
DB+1  
QA+1  
DB+2  
DB+3  
QA+3  
QA  
QA+2  
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Clock Truth Table  
(Use the following table with the Timing Reference Diagram for Truth Table.)  
Clock  
Controls  
Data In  
Data Out  
QA+1  
Mode  
K
R# W#  
DB  
DB+1  
DB+2  
DB+3  
QA  
QA+2  
QA+3  
Previous  
State  
Previous  
State  
Previous  
State  
Previous  
State  
Previous  
State  
Previous  
State  
Previous  
State  
Previous  
State  
Stop Clock  
Stop  
X
H
X
H
No  
Operation  
(NOP)  
L → H  
X
X
X
X
X
X
X
X
High-Z  
High-Z  
High-Z  
High-Z  
DOUT at C#  
(t+1.5)  
DOUT at C  
(t+2.0)  
DOUT at C#  
(t+2.5)  
DOUT at C  
(t+3.0)  
Read A  
Write B  
L → H  
L → H  
L
X
L
DIN at K  
(t+2.0)  
DIN at K#  
(t+2.5)  
DIN at K  
(t+3.0)  
DIN at K#  
(t+3.5)  
X
X
X
X
X
Notes:  
1. Internal burst counter is always fixed as four-bit.  
2. X = “don’t care”; H = logic “1”; L = logic “0”.  
3. A read operation is started when control signal R# is active low  
4. A write operation is started when control signal W# is active low.  
5. Before entering into stop clock, all pending read and write commands must be completed.  
6. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are issued in  
consecutive K clock rising edges, the second one will be ignored.  
7. If both R# and W# are active low after a NOP operation, the write operation will be ignored.  
8.  
For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with  
respect to switching clocks K, K#, C and C#.  
x18 Write Truth Table  
(Use the following table with the Timing Reference Diagram for Truth Table.)  
Operation  
Write Byte 0  
Write Byte 1  
Write All Bytes  
Abort Write  
K (t+1.0) K# (t+1.5) K (t+2.0) K# (t+2.5) BW0# BW1#  
DB  
DB+1  
DB+2  
DB+3  
L → H  
L → H  
L → H  
L → H  
L
H
L
H
L
D0-8 (t+2.0)  
D9-17 (t+2.0)  
D0-17 (t+2.0)  
Don't Care  
L
H
L
H
H
L
Write Byte 0  
Write Byte 1  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
D0-8 (t+2.5)  
D9-17 (t+2.5)  
D0-17 (t+2.5)  
Don't Care  
H
L
L
H
L
H
H
L
Write Byte 0  
Write Byte 1  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
D0-8 (t+3.0)  
D9-17 (t+3.0)  
D0-17 (t+3.0)  
Don't Care  
H
L
L
H
L
H
H
L
Write Byte 0  
Write Byte 1  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
D0-8 (t+3.5)  
D9-17 (t+3.5)  
D0-17 (t+3.5)  
Don't Care  
H
L
L
H
H
Notes:  
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.  
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and  
K#.  
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x36 WRITE TRUTH TABLE  
(Use the following table with the Timing Reference Diagram for Truth Table.)  
Operation  
K (t+1.0)  
K# (t+1.5)  
K (t+2.0)  
K# (t+2.5)  
BW0#  
BW1#  
BW2#  
BW3#  
DB  
DB+1  
DB+2  
DB+3  
D0-8  
(t+2.0)  
Write Byte 0  
L → H  
L
H
H
H
D9-17  
(t+2.0)  
Write Byte 1  
Write Byte 2  
Write Byte 3  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
L → H  
H
H
H
L
L
H
H
L
H
L
H
H
L
D18-26  
(t+2.0)  
D27-35  
(t+2.0)  
H
L
D0-35  
(t+2.0)  
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
Don't Care  
D0-8  
(t+2.5)  
Write Byte 0  
Write Byte 1  
Write Byte 2  
Write Byte 3  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
L → H  
L → H  
D9-17  
(t+2.5)  
H
H
H
L
D18-26  
(t+2.5)  
H
H
L
D27-35  
(t+2.5)  
H
L
D0-35  
(t+2.5)  
L
Don't  
Care  
H
L
H
H
L
H
H
H
L
H
H
H
H
L
D0-8  
(t+3.0)  
Write Byte 0  
Write Byte 1  
Write Byte 2  
Write Byte 3  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
L → H  
L → H  
D9-17  
(t+3.0)  
H
H
H
L
D18-26  
(t+3.0)  
H
H
L
D27-35  
(t+3.0)  
H
L
D0-35  
(t+3.0)  
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
Don't Care  
D0-8  
(t+3.5)  
Write Byte 0  
Write Byte 1  
Write Byte 2  
Write Byte 3  
Write All Bytes  
Abort Write  
L → H  
L → H  
L → H  
L → H  
L → H  
L → H  
D9-17  
(t+3.5)  
H
H
H
L
D18-26  
(t+3.5)  
H
H
L
D27-35  
(t+3.5)  
H
L
D0-35  
(t+3.5)  
L
H
H
H
H
Don't Care  
Notes:  
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.  
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and  
K#.  
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IS61QDB41M36C  
Electrical Specifications  
Absolute Maximum Ratings  
Parameter  
Symbol  
Min  
0.5  
0.5  
0.5  
0.5  
-
Max  
2.9  
Units  
V
Power Supply Voltage  
I/O Power Supply Voltage  
Input Voltage  
VDD  
VDDQ  
VIN  
VDD  
V
VDD+0.3  
VDDQ+0.3  
110  
V
Input/output Voltage  
Junction Temperature  
Storage Temperature  
VI/O  
TJ  
V
°C  
°C  
TSTG  
+125  
55  
Note:  
Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability.  
Operating Temperature Range  
Temperature Range  
Commercial  
Symbol  
TA  
Min  
0
Max  
+70  
+85  
Units  
°C  
Industrial  
TA  
°C  
40  
DC Electrical Characteristics  
(Over the Operating Temperature Range, VDD=1.8V±5%)  
Parameter  
Symbol  
Min  
Max  
Units  
Notes  
400MHz  
750  
650  
600  
550  
x36 Average Power Supply Operating Current  
(f=fMAX, IOUT=0, VIN=VIH or VIL)  
333MHz  
300MHz  
250MHz  
1
IDD  
mA  
400MHz  
333MHz  
300MHz  
250MHz  
400MHz  
333MHz  
300MHz  
250MHz  
700  
600  
550  
500  
270  
250  
240  
230  
x18 Average Power Supply Operating Current  
(f= fMAX, IOUT=0, VIN=VIH or VIL)  
1
IDD  
mA  
mA  
Power Supply Standby Current  
(Device deselected, f= fMAX, IOUT=0, VIN=VIH or VIL)  
1
ISB1  
Input leakage current  
( 0 ≤VIN≤VDDQ for all input balls except VREF, ZQ, TCK,  
TMS, TDI ball)  
Output leakage current  
(0 ≤VOUT ≤VDDQ for all output balls except TDO ball;  
Output must be disabled.)  
ILI  
+2  
+2  
µA  
µA  
2
2  
2  
ILO  
VOH  
VOL  
VDDQ  
VSS+0.2  
V
V
Output “high” level voltage (IOH=100uA, Nominal ZQ)  
Output “low” level voltage (IOL= 100uA, Nominal ZQ)  
VDDQ0.2  
VSS  
Notes:  
1.  
IOUT = chip output current.  
2.  
DOFF# Ball does not follow this spec, ILI = ±100uA  
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Recommended DC Operating Conditions  
(Over the Operating Temperature Range)  
Parameter  
Symbol  
Min  
1.8–5%  
1.4  
Typical  
Max  
1.8+5%  
VDD  
Units  
Notes  
1
Supply Voltage  
VDD  
1.8  
V
V
V
V
V
V
Output Driver Supply Voltage  
Input High Voltage  
Input Low Voltage  
Input Reference Voltage  
Clock Signal Voltage  
VDDQ  
VIH  
1.5  
1
VREF+0.1  
–0.2  
-
VDDQ+0.2  
VREF –0.1  
0.95  
1, 2  
1, 3  
1, 5  
1, 4  
VIL  
-
0.75  
-
VREF  
VIN-CLK  
0.68  
–0.2  
VDDQ+0.2  
Notes:  
1.  
2.  
3.  
4.  
5.  
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.  
VIH(max) AC = See 0vershoot and Undershoot Timings.  
VIL(min) AC = See 0vershoot and Undershoot Timings.  
VIN-CLK specifies the maximum allowable DC excursions of each clock (K, K#, C, and C#).  
Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF  
.
Overshoot and Undershoot Timings  
20% Min Cycle Time  
20% Min Cycle Time  
VDDQ + 0.6V  
GND  
VDDQ  
GND - 0.6V  
VIH(max) AC Overshoot Timing  
VIL(min) AC Undershoot Timing  
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Typical AC Input Characteristics  
Parameter  
Symbol  
VIH (AC)  
Min  
Max  
Units  
Notes  
1, 2, 3, 4  
1, 2, 3, 4  
1, 2, 3  
AC Input Logic HIGH  
AC Input Logic LOW  
Clock Input Logic HIGH  
Clock Input Logic LOW  
VREF+0.2  
V
V
V
V
VIL (AC)  
VREF–0.2  
VREF–0.2  
VIH-CLK (AC)  
VIL-CLK (AC)  
VREF+0.2  
1, 2, 3  
Notes:  
1.  
2.  
3.  
4.  
The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.  
Performance is a function of VIH and VIL levels to clock inputs.  
See the AC Input Definition diagram.  
See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past  
VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.  
AC Input Definition  
K#  
VREF  
K
VRAIL  
VIH(AC)  
VREF  
Setup Time  
Hold Time  
VIL(AC)  
V-RAIL  
PBGA Thermal Characteristics  
Parameter  
Symbol  
13x15 BGA 15x17 BGA  
Units  
°C/W  
°C/W  
°C/W  
Thermal resistance (junction to ambient at airflow = 1m/s)  
Thermal resistance (junction to pins)  
RθJA  
RθJB  
RθJC  
23.5  
7.1  
6
23.3  
7.1  
Thermal resistance (junction to case)  
5.9  
Note: these parameters are guaranteed by design and tested by a sample basis only.  
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Pin Capacitance  
Parameter  
Symbol  
CIN  
Test Condition  
Max  
Units  
pF  
Input capacitance  
5
6
4
°
D and Q capacitance (D0–Dx, Q0-Qx)  
CDQ  
pF  
Clocks Capacitance (K, K, C, C)  
CCLK  
pF  
Note: these parameters are guaranteed by design and tested by a sample basis only.  
Programmable Impedance Output Driver DC Electrical Characteristics  
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)  
Parameter  
Symbol  
Min  
Max  
Units  
Notes  
Output Logic HIGH Voltage  
Output Logic LOW Voltage  
VOH  
VDDQ /2 -0.12  
VDDQ /2 -0.12  
VDDQ /2 + 0.12  
VDDQ /2 + 0.12  
V
V
1, 3  
2, 3  
VOL  
1.  
Notes:  
2.  
4.  
6.  
V
DDQ  
3.  
2
|IOH |  
RQ  
5
V
DDQ  
5.  
2
|IOL |  
RQ  
5
Parameter Tested with RQ=250Ω and VDDQ=1.5V  
AC Test Conditions  
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)  
Parameter  
Symbol  
VDDQ  
VIH  
Conditions  
1.5/1.8  
VREF+0.5  
VREF–0.5  
0.75/0.9  
2.0  
Units  
V
Notes  
Output Drive Power Supply Voltage  
Input Logic HIGH Voltage  
Input Logic LOW Voltage  
Input Reference Voltage  
Input Rise Time  
V
VIL  
V
VREF  
TR  
V
V/ns  
V/ns  
V
Input Fall Time  
TF  
2.0  
Output Timing Reference Level  
Clock Reference Level  
Output Load Conditions  
VREF  
VREF  
V
1, 2  
Notes:  
1.  
See AC Test Loading.  
2.  
Parameter Tested with RQ=250Ω and VDDQ=1.5V  
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AC Test Loading  
(a) Unless otherwise noted, AC test loading assume this condition.  
VREF  
50Ω  
50Ω  
Output  
Test Comparator  
VREF  
(b) tCHQZ and tCHQX1 are specified with 5pF load capacitance and measured when transition occurs ±100mV from  
the steady state voltage.  
VREF  
50Ω  
Output  
5pF  
Test Comparator  
VREF ± 100mV  
(c)TDO  
VREF  
50Ω  
50Ω  
Output  
20pF  
Test Comparator  
VREF  
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AC Timing Characteristics  
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)  
400MHz  
333MHz  
300MHz  
250MHz  
Parameter  
Symbol  
unit  
notes  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Clock  
Clock Cycle Time (K, K#,C,C#)  
Clock Phase Jitter (K, K#,C,C#)  
Clock High Time (K, K#,C,C#)  
Clock Low Time (K, K#,C,C#)  
Clock to Clock (KH→ K#H, CH→ C#H)  
Clock to Data Clock (K > C, K# > C#)  
DLL Lock Time (K,C)  
tKHKH  
tKC var  
ns  
ns  
2.50  
8.4  
0.3  
3.00  
8.4  
0.3  
3.33  
8.4  
0.3  
4.00  
8.4  
0.3  
3
tKHKL  
cycle  
cycle  
ns  
0.4  
0.4  
1.10  
0
0.4  
0.4  
1.35  
0
0.4  
0.4  
1.50  
0
0.4  
0.4  
1.80  
0
tKLKH  
tKHK#H  
tKHCH  
ns  
1.10  
1.35  
1.48  
1.8  
tKC lock  
tDoffLowToReset  
cycle  
ns  
4
1024  
5
1024  
5
1024  
5
1024  
5
Doff# Low period to DLL reset  
ns  
K static to DLL reset  
tKCreset  
30  
30  
30  
30  
Output Times  
C,C# High to Output Valid  
C,C# High to Output Hold  
C,C# High to Echo Clock Valid  
C,C# High to Echo Clock Hold  
CQ, CQ# High to Output Valid  
CQ, CQ# High to Output Hold  
C,C# High to Output High-Z  
C,C# High to Output Low-Z  
Setup Times  
tCHQV  
tCHQX  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
2
2
2
5
5
2
2
0.45  
0.45  
0.20  
0.45  
0.45  
0.45  
0.25  
0.45  
0.45  
0.45  
0.27  
0.45  
0.45  
0.45  
0.30  
0.45  
-0.45  
-0.45  
-0.20  
-0.45  
-0.45  
-0.45  
-0.25  
-0.45  
-0.45  
-0.45  
-0.27  
-0.45  
-0.45  
-0.45  
-0.30  
-0.45  
tCHCQV  
tCHCQX  
tCQHQV  
tCQHQX  
tCHQZ  
tCHQX1  
Address valid to K rising edge  
tAVKH  
tIVKH  
0.40  
0.40  
0.40  
0.40  
0.40  
0.40  
0.40  
0.40  
ns  
ns  
R#,W# control inputs valid to K rising  
edge  
BWx# control inputs valid to K rising  
edge  
tIVKH2  
tDVKH  
0.28  
0.28  
0.30  
0.30  
0.30  
0.30  
0.30  
0.30  
ns  
ns  
Data-in valid to K, K# rising edge  
Hold Times  
K rising edge to address hold  
tKHAX  
tKHIX  
0.40  
0.40  
0.40  
0.40  
0.40  
0.40  
0.40  
0.40  
ns  
ns  
K rising edge to R#,W# control inputs  
hold  
K rising edge to BWx# control inputs  
hold  
tKHIX2  
tKHDX  
0.28  
0.28  
0.30  
0.30  
0.30  
0.30  
0.30  
0.30  
ns  
ns  
K, K# rising edge to data-in hold  
Notes:  
1.  
2.  
3.  
4.  
5.  
All address inputs must meet the specified setup and hold times for all latching clock edges.  
If C, C are tied high, then K, K become the references for C, C timing parameters.  
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.  
VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.  
These parameters are only guaranteed by design and not tested in production.  
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IS61QDB41M36C  
READ, WRITE, AND NOP TIMING DIAGRAM  
1
2
3
4
5
6
7
READ  
WRITE  
NOP  
READ  
WRITE  
tKHKH  
tKHKL  
tKLKH  
K Clock  
tKHK#H  
K# Clock  
tAVKH tKHAX  
Address  
(SA)  
A1  
A2  
A3  
A4  
tIVKH tKHIX  
R#  
W#  
tIVKH tKHIX  
tIVKH2  
B2-1  
tKHDX2  
B2-2  
B2-3  
B2-4  
D2-4  
B4-1  
D4-1  
B4-2  
D4-2  
B4-3  
D4-3  
B4-4  
D4-4  
BWx#  
tDVKH  
D2-1  
tKHDX  
D2-2  
Data-In  
(D)  
D2-3  
Q1-3  
tKHCH  
tCHQX1  
Data-Out  
(Q)  
Q1-1  
Q1-2  
Q1-4  
Q3-1  
Q3-2  
Q3-3  
Q3-4  
tKHKH  
tCHQZ  
tCHQV  
tKHKL  
tKLKH  
C Clock  
tKHK#H  
tCHQX  
C# Clock  
tCHCQX  
CQ Clock  
tCQHQV  
tCQHQX  
CQ# Clock  
tCHCQV  
Undefined  
Don’t Care  
Notes:  
1. If address A3 = A2, data Q3-1 = D2-1, data Q3-2 = D2-2, data Q3-3 = D2-3, data Q3-4 = D2-4. Write data is forwarded immediately as read  
results.  
2. B2-1 refers to all BWx# byte controls for D2-1. B2-2, B2-3, and B2-4 refer to all BWx# byte controls for D2-2, D2-3, and D2-4 respectively.  
3. B4-1 refers to all BWx# byte controls for D4-1. B4-2, B4-3, and B4-4 refer to all BWx# byte controls for D4-2, D4-3, and D4-4 respectively.  
4. Outputs are disabled one cycle after a NOP.  
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IS61QDB41M36C  
IEEE 1149.1 Serial Boundary Scan of JTAG  
These SRAMs incorporate a serial boundary scan Test Access Port (TAP) controller in 165 FBGA package. That is  
fully compliant with IEEE Standard 1149.1-2001. The TAP controller operates using standard 1.8 V interface logic  
levels.  
Disabling the JTAG feature  
These SRAMs operate without using the JTAG feature. To disable the TAP controller, TCK must be tied Low (VSS) to  
prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively  
be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up  
in a reset state, which does not interfere with the operation of the device.  
Test Access Port Signal List:  
Test Clock (TCK)  
The test clock is to operate only TAP controller. All inputs are captured on the rising edge of TCK. All outputs are  
driven from the falling edge of TCK.  
Test Mode Select (TMS)  
The TMS input is to set commands of the TAP controller and is sampled on the rising edge of TCK. This pin can be left  
unconnected at SRAM operation. The pin is pulled up internally to keep logic high level.  
Test Data-In (TDI)  
The TDI pin is to receive serially input information into the instruction and data registers. It can be connected to the  
input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the  
TAP instruction register. For information on loading the instruction register (Refer to the TAP Controller State  
Diagram). TDI is internally pulled up and can be unconnected at SRAM. TDI is connected to the most significant bit  
(MSB) on any register.  
Test Data-Out (TDO)  
The TDO pin is to drive serially clock data out from the JTAG registers. The output is active, depending upon the  
current state of the TAP state machine (Refer to instruction codes). The output changes on the falling edge of TCK.  
TDO is connected to the least significant bit (LSB) of any register.  
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TAP Controller State and Block Diagram  
...  
Boundary Scan Register (109 bits)  
TDI  
Bypass Register (1 bit)  
Identification Register (32 bits)  
Instruction Register (3 bits)  
Control Signals  
TDO  
TMS  
TCK  
TAP Controller  
TAP Controller State Machine  
1
Test Logic  
Reset  
0
1
1
1
Run Test  
Idle  
Select DR  
0
Select IR  
0
0
1
1
Capture  
Capture  
DR  
IR  
0
0
0
0
Shift DR  
1
Shift IR  
1
1
1
Exit1 DR  
0
Exit1 IR  
0
0
0
Pause DR  
1
Pause IR  
1
0
0
Exit2 DR  
1
Exit2 IR  
1
Update  
DR  
Update IR  
1
0
1
0
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Performing a TAP Reset  
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the  
operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to  
ensure that TDO comes up in a High Z state.  
TAP Registers  
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the  
TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.  
Instruction Register  
This register is loaded during the update-IR state of the TAP controller. Three-bit instructions can be serially loaded  
into the instruction register. At power-up, the instruction register is loaded with the IDCODE instruction. It is also  
loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.  
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault  
isolation of the board-level serial test data path.  
Bypass Register  
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. It is to skip certain chips  
without serial boundary scan. This allows data to be shifted through the SRAM with minimal delay. The bypass register  
is set LOW (VSS) when the BYPASS instruction is executed.  
Boundary Scan Register  
The boundary scan register is connected to all the input and output balls on the SRAM. Several No Connected(NC)  
balls are also included in the scan register to reserve other product options. The boundary scan register is loaded with  
the contents of the SRAM input and output ring when the TAP controller is in the capture-DR state and is then placed  
between the TDI and TDO balls when the controller is moved to the shift-DR state. The EXTEST, SAMPLE/PRELOAD,  
and SAMPLE Z instructions can be used to capture the contents of the input and output ring. Each bit corresponds to  
one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command  
is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP  
controller is in the shift-DR state. The ID register has a vendor ID code and other information  
TAP Instruction Set  
TAP Instruction Set is available to set eight instructions with the three bit instruction register and all combinations are  
listed in the TAP Instruction Code Table. Three of listed instructions on this table are reserved and must not be used.  
Instructions are loaded serially into the TAP controller during the Shift-IR state when the instruction register is placed  
between TDI and TDO. To execute an instruction once it is shifted in, the TAP controller must be moved into the  
Update-IR state.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places  
the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when  
the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-  
up or whenever the TAP controller is given a test logic reset state.  
SAMPLE Z  
The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next  
command is supplied during the Update IR state.  
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SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a IEEE 1149.1 basic instruction which connects the boundary scan register between the TDI  
and TDO pins when the TAP controller is in a Shift-DR state.. A snapshot of data on the inputs and output balls is  
captured in the boundary scan register when the TAP controller is in a Shift-DR state. The user must be aware that the  
TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates significantly faster.  
Because there is a large difference between the clock frequencies, it is possible that during the capture-DR state, an  
input or output will undergo a transition. The TAP may then try to capture a signal while in transition. This will not harm  
the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To  
ensure that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller’s capture setup plus hold time. The SRAM clock input might not be captured  
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an  
issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the  
boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the shift-  
DR state. This places the boundary scan register between the TDI and TDO balls.  
PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the  
selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can  
occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in.  
BYPASS  
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass  
register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary  
scan path when multiple devices are connected together on a board.  
PRIVATE  
Do not use these instructions. They are reserved for future use and engineering mode.  
EXTEST  
The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects  
the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. IEEE Standard  
1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan  
register has a special bit located at bit #109. When this scan cell, called the “EXTEST output bus tri-state,” is latched  
into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-  
bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive  
the output bus. When LOW, this bit places the output bus into a High Z condition. This bit can be set by entering the  
SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell during the Shift-DR state.  
During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST  
instruction is entered, this bit directly controls the output Q-bus pins. By default, it places Q in high-Z. The actual  
transfer occurs during the update IR state after EXTEST is loaded. The value of the internal register can be changed  
during SAMPLE and EXTEST only.  
JTAG DC Operating Characteristics  
(Over the Operating Temperature Range, VDD=1.8V±5%)  
Parameter  
Symbol  
VIH1  
Min  
1.3  
–0.3  
1.4  
-
Max  
VDD+0.3  
0.5  
Units  
V
Notes  
JTAG Input High Voltage  
JTAG Input Low Voltage  
JTAG Output High Voltage  
JTAG Output Low Voltage  
JTAG Output High Voltage  
JTAG Output Low Voltage  
JTAG Input Leakage Current  
VIL1  
V
VOH1  
-
V
|IOH1|=2mA  
IOL1=2mA  
VOL1  
0.4  
V
VOH2  
1.6  
-
-
V
|IOH2|=100uA  
IOL2=100uA  
VOL2  
0.2  
V
ILIJTAG  
ILOJTAG  
-100  
-5  
+100  
+5  
uA  
uA  
0 ≤ Vin ≤ VDD  
0 ≤ Vout ≤ VDD  
JTAG Output Leakage Current  
Notes:  
1.  
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.  
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JTAG AC Test Conditions  
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)  
Parameter  
Symbol  
VIH1  
Conditions  
Units  
V
Input Pulse High Level  
Input Pulse Low Level  
Input Rise Time  
1.3  
0.5  
1.0  
1.0  
0.9  
VIL1  
V
TR1  
ns  
ns  
V
Input Fall Time  
TF1  
Input and Output Timing Reference Level  
JTAG AC Characteristics  
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)  
Parameter  
Symbol  
tTHTH  
tTHTL  
Min  
50  
20  
20  
5
Max  
–
Units  
ns  
TCK cycle time  
TCK high pulse width  
TCK low pulse width  
TMS Setup  
–
ns  
tTLTH  
–
ns  
tMVTH  
tTHMX  
tDVTH  
tTHDX  
tCVTH  
tTHCX  
tTLOV  
tTLQX  
–
ns  
TMS Hold  
5
–
ns  
TDI Setup  
5
–
ns  
TDI Hold  
5
–
ns  
Capture Setup  
Capture Hold  
5
–
ns  
5
–
ns  
TCK Low to Valid Data*  
TCK Low to Invalid Data*  
–
10  
–
ns  
0
ns  
Note: See AC Test Loading(c)  
JTAG Timing Diagram  
tTHTL  
tTLTH  
tTHTH  
TCK  
tMVTH  
tTHMX  
TMS  
TDI  
tDVTH  
tTHDX  
tTLOX  
tTLOV  
TDO  
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Instruction Set  
Code  
Instruction  
TDO Output  
000  
001  
010  
EXTEST  
IDCODE  
Boundary Scan Register  
32-bit Identification Register  
Boundary Scan Register  
SAMPLE-Z  
011  
100  
101  
110  
111  
PRIVATE  
SAMPLE(/PRELOAD)  
PRIVATE  
Do Not Use  
Boundary Scan Register  
Do Not Use  
PRIVATE  
Do Not Use  
BYPASS  
Bypass Register  
ID Register Definition  
Revision Number (31:29)  
Part Configuration (28:12)  
Vendor ID Code (11:1)  
Start Bit (0)  
000  
0TDEF0WX01PQLBTS0  
00001010101  
1
Part Configuration Definition:  
1. DEF = 001 for 18Mb, 010 for 36Mb, 011 for 72Mb  
2. WX = 11 for x36, 10 for x18  
3. P = 1 for II+(QUAD-P/DDR-IIP), 0 for II(QUAD/DDR-II)  
4. Q = 1 for QUAD, 0 for DDR-II  
5. L = 1 for RL=2.5, 0 for RL≠2.5  
6. B = 1 for burst of 4, 0 for burst of 2  
7. S = 1 for Separate I/O, 0 for Common I/O  
8. T = 1 for ODT option, 0 for No ODT option  
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Boundary Scan Exit Order  
ORDER  
1
Pin ID  
6R  
6P  
6N  
7P  
7N  
7R  
8R  
8P  
ORDER  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
Pin ID  
10D  
9E  
10C  
11D  
9C  
9D  
11B  
11C  
9B  
ORDER  
73  
Pin ID  
2C  
3E  
2D  
2E  
1E  
2F  
3F  
1G  
1F  
3G  
2G  
1H  
1J  
2J  
3K  
3J  
2
3
4
5
6
7
8
9
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
9R  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
11P  
10P  
10N  
9P  
10M  
11N  
9M  
10B  
11A  
10A  
9A  
8B  
7C  
6C  
8A  
7A  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
2A  
1A  
2B  
3B  
1C  
1B  
9N  
2K  
1K  
2L  
3L  
1M  
1L  
11L  
11M  
9L  
10L  
11K  
10K  
9J  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
Internal  
9K  
10J  
11J  
11H  
10G  
9G  
11F  
11G  
9F  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
10F  
11E  
10E  
3D  
3C  
1D  
Notes:  
1. NC pins as defined on the FBGA Ball Assignments are read as ”Don’t Cares”.  
2. State of internal pin (#109) is loaded via JTAG  
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IS61QDB41M36C  
Ordering Information  
Commercial Range: 0 °C to + 70 °C  
Speed  
Order Part No.  
Organization  
Package  
400MHz  
IS61QDB41M36C-400M3  
IS61QDB41M36C-400M3L  
IS61QDB42M18C-400M3  
IS61QDB42M18C-400M3L  
IS61QDB41M36C-333M3  
IS61QDB41M36C-333M3L  
IS61QDB42M18C-333M3  
IS61QDB42M18C-333M3L  
IS61QDB41M36C-300M3  
IS61QDB41M36C-300M3L  
IS61QDB42M18C-300M3  
IS61QDB42M18C-300M3L  
IS61QDB41M36C-250M3  
IS61QDB41M36C-250M3L  
IS61QDB42M18C-250M3  
IS61QDB42M18C-250M3L  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
333MHz  
300MHz  
250MHz  
165 FBGA (15x17 mm), lead free  
Commercial Range: 0 °C to + 70 °C  
Speed  
Order Part No.  
Organization  
Package  
400MHz  
IS61QDB41M36C-400B4  
IS61QDB41M36C-400B4L  
IS61QDB42M18C-400B4  
IS61QDB42M18C-400B4L  
IS61QDB41M36C-333B4  
IS61QDB41M36C-333B4L  
IS61QDB42M18C-333B4  
IS61QDB42M18C-333B4L  
IS61QDB41M36C-300B4  
IS61QDB41M36C-300B4L  
IS61QDB42M18C-300B4  
IS61QDB42M18C-300B4L  
IS61QDB41M36C-250B4  
IS61QDB41M36C-250B4L  
IS61QDB42M18C-250B4  
IS61QDB42M18C-250B4L  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
333MHz  
300MHz  
250MHz  
165 FBGA (13x15 mm), lead free  
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IS61QDB41M36C  
Industrial Range: -40 °C to + 85 °C  
Speed  
Order Part No.  
Organization  
Package  
400MHz  
IS61QDB41M36C-400M3I  
IS61QDB41M36C-400M3LI  
IS61QDB42M18C-400M3I  
IS61QDB42M18C-400M3LI  
IS61QDB41M36C-333M3I  
IS61QDB41M36C-333M3LI  
IS61QDB42M18C-333M3I  
IS61QDB42M18C-333M3LI  
IS61QDB41M36C-300M3I  
IS61QDB41M36C-300M3LI  
IS61QDB42M18C-300M3I  
IS61QDB42M18C-300M3LI  
IS61QDB41M36C-250M3I  
IS61QDB41M36C-250M3LI  
IS61QDB42M18C-250M3I  
IS61QDB42M18C-250M3LI  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
165 FBGA (15x17 mm), lead free  
165 FBGA (15x17 mm)  
333MHz  
300MHz  
250MHz  
165 FBGA (15x17 mm), lead free  
Industrial Range: -40 °C to + 85 °C  
Speed  
Order Part No.  
Organization  
Package  
400MHz  
IS61QDB41M36C-400B4I  
IS61QDB41M36C-400B4LI  
IS61QDB42M18C-400B4I  
IS61QDB42M18C-400B4LI  
IS61QDB41M36C-333B4I  
IS61QDB41M36C-333B4LI  
IS61QDB42M18C-333B4I  
IS61QDB42M18C-333B4LI  
IS61QDB41M36C-300B4I  
IS61QDB41M36C-300B4LI  
IS61QDB42M18C-300B4I  
IS61QDB42M18C-300B4LI  
IS61QDB41M36C-250B4I  
IS61QDB41M36C-250B4LI  
IS61QDB42M18C-250B4I  
IS61QDB42M18C-250B4LI  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
1Mx36  
1Mx36  
2Mx18  
2Mx18  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
165 FBGA (13x15 mm), lead free  
165 FBGA (13x15 mm)  
333MHz  
300MHz  
250MHz  
165 FBGA (13x15 mm), lead free  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
30  
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Package drawing – 15x17x1.4 BGA  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
31  
04/06/2016  
IS61QDB42M18C  
IS61QDB41M36C  
Package drawing – 13x15x1.4 BGA  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. A1  
32  
04/06/2016  

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