IS61QDB44M18-300M3I [ISSI]
72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs; 72 MB（ 2M ×36和4M ×18 ） QUAD （突发的4 ）同步SRAM
| 型号： | IS61QDB44M18-300M3I |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs |
| 文件： | 总28页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
72 Mb (2M x 36 & 4M x 18)
.
QUAD (Burst of 4) Synchronous SRAMs
November 2009
• Two echo clocks (CQ and CQ) that are delivered
Features
simultaneously with data.
• 2M x 36 or 4M x 18.
• +1.8V core power supply and 1.5, 1.8V VDDQ
used with 0.75, 0.9V VREF
,
• On-chip delay-locked loop (DLL) for wide data
valid window.
.
• HSTL input and output levels.
• Separate read and write ports with concurrent
read and write operations.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Synchronous pipeline read with late write opera-
tion.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Double data rate (DDR) interface for read and
write input ports.
• Byte write capability.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
- 165-ball (11 x 15) array
• Two input clocks (C and C) for data output con-
trol.
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
• Industrial temperature available
Description
The 72Mb IS61QDB42M36 and
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
IS61QDB44M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these QUAD (Burst of 4) SRAMs.
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle after the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
During the burst read operation, the data-outs from
the first and third bursts are updated from output
registers off the second and fourth rising edges of
the C clock (starting 1.5 cycles later). The data-outs
from the second and fourth bursts are updated with
the third and fifth rising edges of the C clock. The K
and K clocks are used to time the data-outs when-
ever the C and C clocks are tied high. Two full clock
cycles are required to complete a read operation
• Read/write address
• Read enable
• Write enable
• Byte writes for burst addresses 1 and 3
• Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc.
1
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
x36 FBGA Pinout (Top View)
1
2
NC/SA*
Q18
3
4
5
6
K
7
8
R
9
10
NC/SA*
Q17
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ
SA
W
BW
BW
BW
SA
2
1
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
D18
D19
Q19
Q20
D21
Q22
SA
K
BW
SA
D17
D16
Q16
Q15
D14
Q13
3
0
Q28
V
SA
NC
SA
V
SS
SS
SS
SS
D20
V
V
V
V
V
V
V
V
V
V
V
V
V
D15
D6
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
D29
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Q21
V
V
V
V
V
V
V
V
V
V
Q14
D13
G
H
J
D22
V
V
V
V
REF
REF
DDQ
DDQ
Q31
D32
Q24
Q34
D26
D35
TCK
D23
D12
Q4
D3
K
L
Q23
D24
D25
Q25
Q26
SA
Q12
D11
D10
Q10
Q9
V
V
V
V
Q11
Q1
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
C
SA
SA
SA
V
D9
SA
SA
SA
SA
D0
C
SA
TMS
Note: *The following pins are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Pinout (Top View)
1
2
NC/SA*
Q9
3
4
5
6
K
7
8
R
9
10
SA
NC
Q7
NC
D6
NC
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
SA
W
BW
NC
SA
NC
NC
NC
NC
NC
NC
1
D9
SA
NC
SA
K
BW
SA
0
NC
D10
Q10
Q11
D12
Q13
V
NC
SA
V
SS
SS
SS
SS
D11
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Q12
D13
V
V
V
V
V
V
V
V
V
V
G
H
J
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
D14
NC
Q4
D3
K
L
Q14
D15
D16
Q16
Q17
SA
NC
NC
NC
NC
NC
SA
Q15
NC
V
V
V
V
NC
Q1
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
D17
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
D0
SA
SA
SA
SA
TCK
C
TMS
Note: *The following pins are reserved for higher densities: 2A for 144Mb.
2
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Pin Description
Symbol
Pin Number
Description
K, K
C, C
6B, 6A
6P, 6R
Input clock.
Input clock for output data control.
CQ, CQ
Doff
11A, 1A
1H
Output echo clock.
DLL disable when low.
3A, 9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R, 8R, 9R
SA
SA
2M x 36 address inputs.
4M x 18 address inputs.
10A, 3A, 9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R,
5R, 7R, 8R, 9R
D0–D8
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
D9–D17
D18–D26
D27–D35
2M x 36 data inputs.
2M x 36 data outputs.
1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P
Q0–Q8
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
Q9–Q17
Q18–Q26
Q27–Q35
1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P
D0–D8
D9–D17
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
4M x 18 data inputs.
4M x 18 data outputs.
Q0–Q8
Q9–Q17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
W
R
4A
8A
Write control, active low.
Read control, active low.
2M x 36 byte write control, active low.
4M x 18 byte write control, active low.
Input reference level.
BW BW BW BW 7B, 7A, 5A,5B
0,
1,
2,
3
BW BW
7B, 5A
0,
1
V
V
V
2H, 10H
REF
DD
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Power supply.
Output power supply.
DDQ
4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N
V
Ground.
SS
ZQ
11H
Output driver impedance control.
IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).
TMS, TDI, TCK
TDO
10R, 11R, 2R
1R
IEEE 1149.1 test output (1.8V LVTTL level).
NC for x36
NC for x18
2A, 10A, 6C
2A, 7A, 1B, 5B, 9B, 10B, 1C, 2C, 6C, 9C, 1D, 9D, 10D, 1E, 2E,
9E, 1F, 9F, 10F, 1G, 9G, 10G, 1J, 2J, 9J, 1K, 2K, 9K, 1L, 9L,
10L, 1M, 2M, 9M, 1N, 9N, 10N, 1P, 2P, 9P
Integrated Silicon Solution, Inc.
3
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Block Diagram
36 (o r 18)
Data
D (Data-In)
Reg
72 (or 36 )
72 (or 36)
Write Driver
36 ( or 18)
19 (or 20 )
19 (o r 20)
Add
Reg
72
Address
144
Q (Data-Out)
(or 36)
(or 72)
2M x 36
(4M x 18)
Memory
Array
CQ, CQ
R
Control
Logic
72
W
(Ech o Cloc k Out)
(or 36)
4 (or 2)
BW
x
K
K
C
C
Cloc k
Gen
Select OutputControl
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. R can be activated every other cycle because two full cycles are
required to complete the burst of four in DDR mode. A second set of clocks, C and C, are used to control the
timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings
identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is
clocked by the subsequent rising edge of the K clock.
A NOP operation (R is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever W is low. The write
address is provided simultaneously. Again, the write always occurs in bursts of four.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K. The third data-in is clocked by the
subsequent rising edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the
K clock.
4
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into
the array on the third write cycle. A read cycle to the last two write addresses produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see X18/X36 Write Truth Tables on page 10 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ωresults in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 16. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never
be connected to VSS
.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differ-
ential clocks
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.
In the following application example, the second pair of C and C clocks is delayed such that the return data
meets the data setup and hold times at the memory controller.
Integrated Silicon Solution, Inc.
5
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Application Example
R=250Ω
SRAM #1
SRAM #4
ZQ
CQ
CQ
Q
R=250Ω
ZQ
CQ
CQ
Q
D
D
Vt
SA
R
W
BW BW
C
C
K
K
SA
R
W
BW BW C
1
C
K
K
0
1
0
R
Data In
Data Out
Address
R
Vt
Vt
R
W
BW
Memory
Controller
Return CLK
Vt
Vt
Source CLK
Return CLK
Source CLK
R=50Ω Vt=V
REF
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.
6
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
State Diagram
Power-Up
Read NOP
Read
Write NOP
Read
Write
Write
Load New
Read Address
D count = 0
Load New
Write Address
D count = 0
Read
D count = 2
Write
D count = 2
Write
D count = 2
Read
D count = 2
Always
Always
DDR-II Read
DDR-II Write
D count =
D count =
D count + 1
D count + 1
Read
D count = 1
Write
D count = 1
Always
Always
Increment
Read Address
Increment
Write Address
Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst addresses are
A0+1, A0+2, and A0+3
.
2. Read refers to read active status with R = low. Read refers to read inactive status with R = high.
3. Write refers to write active status with W = low. Write refers to write inactive status with W = high.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle “t”.
Integrated Silicon Solution, Inc.
7
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Timing Reference Diagram for Truth Table
Cycle
t
t+1
Write B
t+2
t+3
Read A
K Clock
K Clock
R
W
BW
X
Address
Data-In
A
B
DB
QA
DB+1
QA+1
DB+2
QA+2
DB+3
QA+3
Data-Out
C Clock
C Clock
CQ Clock
CQ Clock
8
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Clock
K
Controls
Data In
Data Out
Mode
D
D
D
D
Q
Q
Q
Q
A+3
R
X
H
L
W
X
B
B+1
B+2
B+3
A
A+1
A+2
Previous Previous Previous Previous Previous Previous Previous Previous
Stop Clock
Stop
State
State
State
State
State
State
State
State
No Operation (NOP) L→H
H
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Dout at C Dout at C Dout at C Dout at C
Read B
Write A
L →H
L →H
X
X
X
X
(t + 1.5)
(t + 2)
(t + 2.5)
(t + 3)
Din at K Din at K Din at K Din at K
(t + 1) (t + 1.5) (t + 2) (t + 2.5)
X
L
X
X
X
X
Notes:
1. Internal burst counter is always fixed as four-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R is active low
4. A write operation is started when control signal W is active low. Before entering into stop clock, all pending read and write com-
mands must be completed.
5. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are
issued in consecutive K clock rising edges, the second one will be ignored.
6. If both R and W are active low after a NOP operation, the write operation will be ignored.
7. For timing definitions, refer to the AC Characteristics on page 17. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K, K, C, and C.
Integrated Silicon Solution, Inc.
9
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
BW
L
BW
H
L
BW BW
D
D
D
D
B+3
Operation
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
K
(t+1)
K
(t+1.5)
K(t+2) K(t+2.5)
0
1
2
3
B
B+1
B+2
L→H
L→H
L→H
L→H
H
H
L
H
H
H
L
D0-8 (t+1)
D9-17 (t+1)
D18-26 (t+1)
D27-35 (t+1)
H
H
H
L
H
H
L
H
L
Write All Bytes L→H
L
D0-35 (t+1
)
Abort Write
Write Byte 0
Write Byte 1
L→H
H
L
H
H
L
H
H
H
H
H
H
Don’t care
L→H
L→H
D0-8 (t+1.5)
H
D9-17 (t+1.5)
D18-26
(t+1.5)
Write Byte 2
Write Byte 3
L→H
L→H
H
H
H
H
L
H
L
D27-35
(t+1.5)
H
Write All Bytes
Abort Write
L→H
L→H
L
H
L
L
H
H
L
L
L
H
H
H
D0-35 (t+1.5)
H
H
H
Don’t care
Write Byte 0
Write Byte 1
L→H
L→H
D0-8 (t+2)
H
D9-17 (t+2)
D18-26
(t+2)
Write Byte 2
Write Byte 3
L→H
L→H
H
H
H
H
L
H
L
D27-35
(t+2)
H
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
Abort Write
Notes;
L→H
L→H
L
H
L
L
H
H
L
L
H
H
H
L
L
H
H
H
H
L
D0-35 (t+2
)
Don’t care
L→H
L→H
L→H
L→H
L→H
L→H
D0-8 (t+2.5)
D9-17 (t+2.5)
D18-26 (t+2.5)
D27-35 (t+2.5)
H
H
H
L
H
H
L
H
L
L
D0-35 (t+2.5)
H
H
H
H
Don’t care
1. For all cases, W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching
clocks K and K.
10
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
BW
L
BW
H
L
D
D
D
D
B+3
Operation
Write Byte 0
Write Byte 1
K
(t+1)
K
(t+1.5)
K(t+2) K(t+2.5)
0
1
B
B+1
B+2
L→H
L→H
D0-8 (t+1)
H
L
D9-17 (t+1)
Write All Bytes L→H
L→H
L
D0-17 (t+1
)
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Notes;
H
L
H
H
L
Don’t care
L→H
L→H
L→H
L→H
D0-8 (t+1.5)
H
L
D9-17 (t+1.5)
L
D0-17 (t+1.5
)
H
L
H
H
L
Don’t care
L→H
L→H
L→H
L→H
D0-8 (t+2)
H
L
D9-17 (t+2)
L
D0-17 (t+2
)
H
L
H
H
L
Don’t care
L→H
L→H
L→H
L→H
D0-8 (t+2.5)
H
L
D9-17 (t+2.5)
L
D0-17 (t+2.5)
H
H
Don’t care
1. For all cases. W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching
clocks K and K.
Integrated Silicon Solution, Inc.
11
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Absolute Maximum Ratings
Item
Power supply voltage
Output power supply voltage
Input voltage
Symbol
Rating
Units
V
V
-0.5 to 2.9V
-0.5 to 2.9V
-0.5 to VDD+0.3V
-0.5 to 2.6
0 to 70
DD
V
V
DDQ
V
V
IN
Data out voltage
V
V
DOUT
Operating temperature
Junction temperature
Storage temperature
T
°C
°C
°C
A
T
110
J
T
-55 to +125
STG
Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
12
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Recommended DC Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
Minimum
1.8 - 5%
1.4
Typical
Maximum
1.8 + 5%
1.9
Units
V
Notes
1
Supply voltage
V
DD
Output driver supply voltage
Input high voltage
V
V
1
DDQ
V
V
+0.1
V + 0.3
DDQ
V
1, 2
1, 3
1, 5
1, 4
IH
REF
Input low voltage
V
-0.3
V
- 0.1
V
IL
REF
Input reference voltage
Clocks signal voltage
V
0.68
0.95
V
REF
V
-0.3
V
+ 0.3
V
IN - CLK
DDQ
1. All voltages are referenced to V . All V , V
, and V pins must be connected.
SS
SS
DD
DDQ
2. V (Max) AC = See 0vershoot and Undershoot Timings.
IH
3. V (Min) AC = See 0vershoot and Undershoot Timings.
IL
4. V
specifies the maximum allowable DC excursions of each clock (K, K, C, and C).
IN-CLK
5. Peak-to-peak AC component superimposed on V
may not exceed 5% of V
REF
REF.
0vershoot and Undershoot Timings
20% Min Cycle Time
VIL(Min) AC
V
+0.6V
DDQ
Undershoot Timing
VDDQ
GND
V (Max) AC
IH
GND-0.6V
Overshoot Timing
20% Min Cycle Time
PBGA Thermal Characteristics
Item
Thermal resistance junction to ambient (airflow = 1m/s)
Thermal resistance junction to case
Symbol
Rating
18.6
4.3
Units
° C/W
° C/W
° C/W
RΘJA
RΘJC
RΘJB
Thermal resistance junction to pins
1.77
Integrated Silicon Solution, Inc.
13
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Capacitance (TA = 0 to + 70 C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter
Symbol
Test Condition
Maximum
Units
pF
Input capacitance
C
V
= 0V
= 0V
4
4
4
4
IN
IN
Data-in capacitance (D0–D35)
Data-out capacitance (Q0–Q35)
C
V
pF
DIN
OUT
CLK
DIN
C
C
V
= 0V
= 0V
pF
OUT
Clocks Capacitance (K, K, C, C
)
V
pF
CLK
DC Electrical Characteristics (TA = 0 to + 70 C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum Maximum
Units
Notes
1
I
I
I
DD33
DD40
950
x36 average power supply operating current
850
mA
(I
= 0, V = V or V )
—
OUT
IN
IH
IL
750
DD50
I
I
I
DD33
DD40
900
x18 average power supply operating current
(I = 0, V = V or V )
—
800
mA
1
1
OUT
IN
IH
IL
700
DD50
Power supply standby current
(R = V , W = V . All other inputs = V or V , I = 0)
I
—
-2
400
+2
mA
µA
µA
SB
IH
IH
IH
IH IH
Input leakage current, any input (except JTAG)
(V = V or V
I
LI
)
DD
IN
SS
Output leakage current
(V = V or V , Q in High-Z)
I
-2
+2
LO
OUT
SS
DDQ
Output “high” level voltage (I = -6mA)
V
V
-.4
V
DDQ
V
V
2, 3
OH
OH
DDQ
Output “low” level voltage (I = +6mA)
V
V
V +.4
SS
2, 3
OL
OL
SS
JTAG leakage current
I
-100
+100
A
4
LIJTAG
(V = V or V
)
IN
SS
DD
1. I
= chip output current.
OUT
2. Minimum impedance output driver.
3. JEDEC Standard JESD8-6 Class 1 compatible.
4. For JTAG inputs only.
14
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Typical AC Input Characteristics
Item
Symbol
Minimum
Maximum
Notes
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
AC input logic high
V
(ac)
(ac)
V
+ 0.2
IH
REF
AC input logic low
V
V
- 0.2
- 0.2
IL
REF
Clock input logic high (K, K, C, C)
Clock input logic low (K, K, C, C)
V
(ac)
(ac)
V
+ 0.2
IH-CLK
REF
V
V
1, 2, 3
IL-CLK
REF
1. The peak-to-peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. Performance is a function of V and V levels to clock inputs.
IH
IL
3. See the AC Input Definition diagram.
4. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ring-
ing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing pur-
poses only.
AC Input Definition
K
V
REF
K
V
RAIL
V
(AC)
IH
V
REF
Setup
Time
Hold
Time
V
(AC)
IL
V
-RAIL
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Output “high” level voltage
Output “low” level voltage
Symbol
Minimum
/ 2
Maximum
Units
V
Notes
1, 3
V
V
V
DDQ
OH
DDQ
V
V
V / 2
DDQ
V
2, 3
OL
SS
VDDQ
------------------
RQ
--------
⁄
1. I
=
=
15% @ V = V
/ 2 For: 175Ω ≤RQ ≤350Ω.
/ 2 For: 175Ω ≤RQ ≤350Ω.
= 1.5V.
OH
OL
OH
DDQ
2
5
VDDQ
------------------
RQ
--------
⁄
2. I
15% @ V = V
OL
DDQ
2
5
3. Parameter tested with RQ = 250Ω and V
DDQ
Integrated Silicon Solution, Inc.
15
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Conditions
1.5, 1.8
Units
V
Notes
Output driver supply voltage
Input high level
V
DDQ
V
V
+0.5
REF
V
IH
Input Low Level
V
V
-0.5
REF
V
IL
Input reference voltage
Input rise time
V
0.75, 0.9
0.35
V
REF
T
ns
ns
V
R
Input fall time
T
0.35
F
Output timing reference level
Clocks reference level
V
V
REF
REF
V
Output load conditions
1, 2
1. See AC Test Loading.
2. Parameter tested with RQ = 250Ω and V
= 1.5V.
DDQ
AC Test Loading
Ω
50
0.75, 0.9V
Q
Ω
50
Test
Comparator
5pF
0.75, 0.9V
16
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
AC CHARACTERISTICS(VDD=1.8V 0.1V, TA=0 C to +70 C)
33 (300 MHz)
40 (250 MHz)
50 (200 MHz)
PARAMETER
SYMBOL
UNIT NOTE
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K, C, C)
Clock Low Time (K, K, C, C)
tKHKH
tKC var
3.30
7.5
4.00
7.5
5.00
7.5
ns
0.20
0.20
0.20
ns
ns
5
6
tKHKL
1.32
1.32
1.49
0.00
1024
5
1.60
1.60
1.80
0.00
1024
5
2.00
2.00
2.20
0.00
1024
5
tKLKH
ns
Clock to Clock (K
K
, C
C
C )
tKHKH
ns
Clock to data clock (K
, K
C )
tKHCH
0.8
0.8
0.8
ns
DLL Lock Time (K, C)
tKC lock
tDoꢀLowToReset
cycle
ns
Doff Low period to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
tCHQV
tCHQX
0.45
0.40
0.27
0.45
0.45
0.40
0.30
0.45
0.45
0.40
0.35
0.45
ns
ns
ns
ns
ns
ns
ns
ns
3
3
-0.45
-0.40
-0.27
-0.45
-0.45
-0.40
-0.30
-0.45
-0.45
-0.40
-0.35
-0.45
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
C, High to Output High-Z
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
7
7
3
3
C, High to Output Low-Z
tCHQX1
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
tAVKH
tIVKH
tDVKH
0.35
0.35
0.35
0.35
0.35
0.35
0.4
0.4
0.4
ns
ns
ns
2
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
tKHAX
tKHIX
0.35
0.35
0.35
0.35
0.35
0.35
0.4
0.4
0.4
ns
ns
ns
tKHDX
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0 C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70 C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a
The data sheet parameters reflect tester guard bands and test setup variations.
ns variation from echo clock to data.
+ 0.1
Integrated Silicon Solution, Inc.
17
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Read and Deselect Cycles Timing Diagram
Read
Read
NOP
NOP
t
KHKH
t
t
KHKL
KLKH
K
K
t
KHKH
t
AVKH
t
KHAX
A1
A2
SA
t
t
IVKH
KHIX
R
Q1-1
t
Q1-2
Q1-3
Q1-4
Q2-1
Q2-2
Q2-3
Q2-4
Q (Data-Out)
t
CHQX
CHQV
t
KHKH
t
CHQX
t
t
t
KHKL
KLKH
CHQZ
C
C
t
KHCH
t
CHQV
t
CHCQX
t
CQHQX
t
CQHQV
CQ
CQ
t
CHCQV
t
CHCQX
t
CHCQV
Don’t Care
Undefined
Note: 1. Q1-1 refers to the output from address A1+0, Q1-2, Q1-3, Q1-4 refers to the output from address A1+1, A1+2, A1+3,
which is the nex internal burst addresses following A1+0.
2. Outputs are disabled one cycle after a NOP.
18
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Write and NOP Timing Diagram
Write
Write
NOP
NOP
t
KLKH
t
KHKH
t
KHKL
K
K
t
KHKH
t
AVKH
t
t
KHAX
KHIX
SA
A1
A2
t
t
IVKH
KHIX
W
B1-1
D1-1
B1-2
D1-2
B1-3
B1-4
B2-1
B2-2
D2-2
B2-3
B2-4
D2-4
BW
X
t
t
KHDX
DVKH
D (Data-In)
D1-3
D1-4
D2-1
D2-3
Don’t Care
Undefined
NOTE: (B1-1 refers to all BW byte controls for D1-1)
X
Integrated Silicon Solution, Inc.
19
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Read, Write, and NOP Timing Diagram
Read
NOP
Read
Write
Read
Write
NOP
K
K
SA
BW
R
A1
A2
A3
A4
B2-2
B4-1
B4-3
B2-1
B2-3
B4-2
B2-4
X
W
D (Data-In)
D2-1
Q1-1
D2-2
Q1-2
D2-3
Q1-3
D2-4
Q1-4
D4-1
Q3-1
D4-2
Q3-2
D4-3
Q3-3
D (Data-Out)
C
C
CQ
CQ
Don’t Care
Undefined
Note: If address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2, data Q3-3=D2-3, and
data Q3-4=D2-4, then write data is forwarded immediately as read results.
20
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.
Signal List
• TCK: test clock
• TMS: test mode select
• TDI: test data-in
• TDO: test data-out
JTAG DC Operating Characteristics (TA = 0 to +70° C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter
JTAG input high voltage
Symbol
Minimum
1.3
Typical
—
Maximum
Units
Notes
1
V
V
+0.3
DD
V
V
V
V
IH1
JTAG input low voltage
JTAG output high level
JTAG output low level
V
-0.3
—
0.5
1
IL1
V
V
-0.4
—
V
1, 2
1, 3
OH1
DD
DD
V
V
—
0.4
OL1
SS
1. All JTAG inputs and outputs are LVTTL-compatible.
2. I
3. I
= -2mA
= +2mA
OH1
OL1
JTAG AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Conditions
1.3
Units
V
Input pulse high level
V
IH1
Input pulse low level
V
T
0.5
V
IL1
Input rise time
1.0
ns
ns
V
R1
Input fall time
T
1.0
F1
Input and output timing reference level
0.9
Integrated Silicon Solution, Inc.
21
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
JTAG AC Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
Units
ns
Notes
TCK cycle time
TCK high pulse width
TCk low pulse width
TMS setup
t
20
7
—
—
—
—
—
—
—
7
THTH
t
ns
THTL
t
7
ns
TLTH
MVTH
THMX
t
t
4
ns
TMS hold
4
ns
TDI setup
t
4
ns
DVTH
THDX
TDI hold
t
4
ns
TCK low to valid data
t
—
ns
1
TLOV
1. See AC Test Loading on page 16.
JTAG Timing Diagram
t
t
t
THTH
THTL
TLTH
TCK
TMS
t
THMX
t
MVTH
t
THDX
TDI
t
DVTH
TDO
t
TLOV
22
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Scan Register Definition
Register Name
Instruction
Bypass
Bit Size x18 or x36
3
1
ID
32
109
Boundary Scan
ID Register Definition
Field Bit Number and Description
Part
Revision Number
(31:29)
Part Configuration
(28:12)
JEDEC Code
Start Bit
(0)
(11:1)
4M x 18
2M x 36
000
000
00def0wx0t0q0b0s0
00def0wx0t0q0b0s0
000 101 001 00
000 101 001 00
1
1
Part Configuration Definition:
def = 011 for 72Mb
wx = 11 for x36, 10 for x18
t = 1 for DLL, 0 for non-DLL
q = 1 for QUADB4, 0 for DDR-II
b = 1 for burst of 4, 0 for burst of 2
s = 1 for separate I/0, 0 for common I/O
Integrated Silicon Solution, Inc.
23
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Instruction Set
Code
000
001
010
011
100
101
110
111
Instruction
EXTEST
IDCODE
TDO Output
Boundary Scan Register
32-bit Identification Register
Boundary Scan Register
Do not use
Notes
2,6
SAMPLE-Z
PRIVATE
SAMPLE
PRIVATE
PRIVATE
BYPASS
1, 2
5
Boundary Scan Register
Do not use
4
5
Do not use
5
Bypass Register
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to V when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
SS
TDI when exiting the shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,
Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR
state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations
• 7.2.1.b, e
• 7.7.1.a-f
• 10.1.1.b, e
• 10.7.1.a-d
• 6.1.1.d
JTAG Block Diagram
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
Instruction Register (3 bits)
TDO
Control Signals
TAP Controller
TMS
TCK
24
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
TAP Controller State Machine
1
Test Logic Reset
0
0
1
1
1
Select IR
0
Run Test Idle
Select DR
0
1
Capture IR
0
1
Capture DR
0
0
Shift IR
1
0
Shift DR
1
1
Exit1 IR
0
1
Exit1 DR
0
0
0
Pause IR
1
Pause DR
1
0
Exit2 DR
1
Exit2 IR
1
0
1
Update DR
0
Update IR
0
1
Integrated Silicon Solution, Inc.
25
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Boundary Scan Exit Order The same length is used for x18 and x36 I/O configuration.
Order
Pin ID
Order
Pin ID
Order
Pin ID
1
6R
6P
37
37
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10D
9E
73
74
2C
3E
2D
2E
1E
2F
2
3
6N
10C
11D
9C
9D
11B
11C
9B
75
4
7P
76
5
7N
77
6
7R
78
7
8R
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
10A
9A
82
3G
2G
1H
1J
83
84
85
10M
11N
9M
8B
86
2J
7C
6C
8A
87
3K
3J
88
9N
89
2K
1K
2L
11L
11M
9L
7A
90
7B
91
6B
92
3L
10L
11K
10K
9J
6A
93
1M
1L
5B
94
5A
95
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Internal
4A
96
9K
5C
4B
97
10J
11J
11H
10G
9G
98
3A
99
2A
100
101
102
103
104
105
106
107
108
109
1A
2B
11F
11G
9F
3B
1C
1B
10F
11E
10E
3D
3C
1D
Note:
1) NC pins as defined on FBGA pinouts on page 2 are read as “don’t cares”.
2) State of Internal pin (#109) is loaded via JTAG
26
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
Integrated Silicon Solution, Inc.
27
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ORDERING INFORMATION:
Commercial Range: 0°C to +70°C
Speed
Order Part No.
Organization
2Mx36
4Mx18
2Mx36
4Mx18
Package
165 BGA
165 BGA
165 BGA
300 MHz
IS61QDB42M36-300M3
IS61QDB44M18-300M3
IS61QDB42M36-250M3
IS61QDB44M18-250M3L
250 MHz
165 BGA, Lead-free
Industrial Range: -40°C to +85°C
Speed
Order Part No.
Organization
Package
300 MHz
IS61QDB44M18-300M3I
4Mx18
165 BGA
28
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
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