IS61VF102418A-7.5B3-TR [ISSI]
IC SRAM 18M PARALLEL 165TFBGA;
| 型号： | IS61VF102418A-7.5B3-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC SRAM 18M PARALLEL 165TFBGA 静态存储器 |
| 文件： | 总35页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LF25672A IS61VF25672A
IS61LF51236A IS61VF51236A
IS61LF102418A IS61VF102418A
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
JULY 2010
DESCRIPTION
FEATURES
The ISSI IS61LF/VF25672A, IS61LF/VF51236A and
IS61LF/VF102418A are high-speed, low-power synchro-
nous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LF/VF25672A is organized as
262,144 words by 72 bits. The IS61LF/VF51236A is orga-
nizedas524,288wordsby36bits.TheIS61LF/VF102418A
is organized as 1,048,576 words by 18 bits. Fabricated
with ISSI's advanced CMOS technology, the device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic cir-
cuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
•
Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball
PBGA and 165-pin PBGA packages.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
• Lead-free available
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-6.5
6.5
-7.5
7.5
Units
ns
Clock Access Time
Cycle Time
tKC
7.5
8.5
ns
Frequency
133
117
MHz
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
BLOCK DIAGRAM
MODE
A0'
Q0
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
A1'
ADV
A1
256Kx72;
512Kx36;
1024Kx18;
ADSC
ADSP
CLR
MEMORY ARRAY
19/20
17/18
19/20
D
Q
A
ADDRESS
REGISTER
CE
CLK
36,18
or 72
36,18
or 72
D
Q
GW
BWE
DQ(a-d)
BYTE WRITE
REGISTERS
BW(a-h)
x18: a,b
x36: a-d
x72: a-h
CLK
36,18
or 72
CE
CE2
CE2
2/4/8
INPUT
D
Q
DQa - DQd
REGISTERS
ENABLE
OE
REGISTER
CLK
CE
CLK
POWER
DOWN
ZZ
OE
2
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
119-PIN BGA
165-PIN BGA
119-Ball, 14x22 mm BGA
165-Ball, 13x15 mm BGA
BOTTOM VIEW
BOTTOM VIEW
209-BALL BGA
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc.
3
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
A
CE2
BWg
BWd
NC
ADSP
NC
ADSC
BWE
CE
ADV
A
CE2
BWb
BWe
NC
A
DQb
DQb
DQb
DQb
DQPf
DQf
DQb
DQb
DQb
DQb
DQPb
DQf
BWc
BWh
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CLK
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
BWf
BWa
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
NC
NC
GW
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
NC
OE
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
VDD
NC
NC
NC
NC
NC
NC
NC
NC
ZZ
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
G
H
J
DQf
DQf
DQf
DQf
DQf
DQf
K
L
NC
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
M
N
P
R
T
VDD
MODE
A
U
V
W
A
A
A
A
A
A
A1
A
A
A
TMS
TDI
A
A0
A
TDO
TCK
11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
Pin Name
BWE
Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
OE
Output Enable
Synchronous Burst Address
Advance
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
JTAG Pins
ADSP
Address Status Processor
Address Status Controller
Global Write Enable
TCK, TDO
TMS, TDI
ADSC
GW
NC
No Connect
CLK
Synchronous Clock
DQx
DQPx
VDD
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
CE, CE2, CE2
Synchronous Chip Select
BWx (x=a,b,c,d Synchronous Byte Write
e,f,g,h) Controls
VDDQ
Isolated Output Power Supply
3.3V/2.5V
Vss
Ground
4
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CE
OE
G
H
J
ADV
GW
VDD
CLK
NC
K
L
M
N
P
R
T
BWE
A1*
A0*
VDD
A
NC
NC
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
OE
Pin Name
Symbol
A
Pin Name
Address Inputs
Output Enable
A0, A1
ADV
Synchronous Burst Address Inputs
ZZ
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
Synchronous Burst Address
Advance.
MODE
TCK, TDO
TMS, TDI
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
Global Write Enable
NC
No Connect
DQa-DQd
DQPa-Pd
VDD
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
CLK
CE
Synchronous Clock
Synchronous Chip Select
VDDQ
Output Power Supply
BWx (x=a-d) Synchronous Byte Write Controls
BWE Byte Write Enable
Vss
Ground
Integrated Silicon Solution, Inc.
5
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
119 BGA PACKAGE PIN CONFIGURATION
1MX18 (TOP VIEW)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
MODE
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CE
DQa
VDDQ
DQa
NC
VDDQ
NC
OE
G
H
J
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
BWE
A1*
VDDQ
NC
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
OE
Pin Name
Output Enable
A0, A1
ADV
Synchronous Burst Address Inputs
ZZ
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
Synchronous Burst Address
Advance.
MODE
TCK, TDO
TMS, TDI
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
Global Write Enable
NC
No Connect
DQa-DQb
DQPa-Pb
VDD
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
CLK
CE
Synchronous Clock
Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Controls
BWE Byte Write Enable
VDDQ
Output Power Supply
Vss
Ground
6
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
165 PBGA PACKAGE PIN CONFIGURATION
512K X 36 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWc
BWd
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
TDO
TCK
ADSC
OE
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
NC
A
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
DQc
DQc
DQc
DQc
Vss
DQd
DQd
DQd
DQd
NC
G
H
J
DQd
DQd
DQd
DQd
DQPd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
A
K
L
M
N
P
R
NC
TDI
TMS
A1*
A0*
MODE
NC
A
A
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
A
Pin Name
Address Inputs
BWE
Byte Write Enable
A0, A1
Synchronous Burst Address
Inputs
OE
Output Enable
ZZ
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
ADV
Synchronous Burst Address
Advance.
MODE
TCK, TDO
TMS, TDI
ADSP
Address Status Processor
Address Status Controller
Global Write Enable
ADSC
NC
No Connect
GW
DQa-DQd
DQPa-Pd
VDD
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
CLK
Synchronous Clock
CE, CE2, CE2
Synchronous Chip Select
BWx (x=a,b,c,d) Synchronous Byte Write
VDDQ
Output Power Supply
Controls
Vss
Ground
Integrated Silicon Solution, Inc.
7
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
165 PBGA PACKAGE PIN CONFIGURATION
1M X 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWb
NC
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
TDO
TCK
ADSC
OE
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
A
NC
A
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
DQb
DQb
DQb
DQb
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
NC
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
A
K
L
M
N
P
R
TDI
TMS
A1*
A0*
MODE
A
A
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
Pin Name
BWE
Byte Write Enable
A0, A1
Synchronous Burst Address
Inputs
OE
Output Enable
ZZ
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
ADV
Synchronous Burst Address
Advance.
MODE
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
Global Write Enable
TCK, TDO
TMS, TDI
NC
No Connect
DQa-DQd
DQPa-Pd
VDD
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
CLK
Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a,b)
Synchronous Byte Write
Controls
VDDQ
Output Power Supply
Vss
Ground
8
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
DQPa-DQPd Parity Data Input/Output
pins must tied to the two LSBs of the
address bus.
Vss
Ground
GW
Synchronous Global Write Enable
Burst Sequence Mode Selection
Output Enable
A
Synchronous Address Inputs
MODE
OE
ADSC
ADSP
ADV
Synchronous Controller Address Status
Synchronous Processor Address Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
TMS, TDI,
TCK, TDO
JTAG Boundary Scan Pins
BWa-BWd
BWE
VDD
3.3V/2.5V Power Supply
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
CE, CE2, CE2 Synchronous Chip Enable
CLK
Synchronous Clock
ZZ
Snooze Enable
DQa-DQd
Synchronous Data Input/Output
Integrated Silicon Solution, Inc.
9
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VDD
ZZ
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1024K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQPa-DQPb Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
VSS
Ground
A
Synchronous Address Inputs
GW
Synchronous Global Write Enable
Burst Sequence Mode Selection
Output Enable
ADSC
ADSP
ADV
Synchronous Controller Address Status
Synchronous Processor Address Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
MODE
OE
TMS, TDI,
TCK, TDO
JTAG Boundary Scan Pins
BWa-BWb
BWE
VDD
3.3V/2.5V Power Supply
CE, CE2, CE2 Synchronous Chip Enable
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
CLK
Synchronous Clock
ZZ
Snooze Enable
DQa-DQb
Synchronous Data Input/Output
10
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TRUTH TABLE(1-8) (3CE option)
OPERATION
ADDRESS CE
CE2
X
X
H
X
H
X
L
CE2
X
L
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP ADSC ADV WRITE OE
CLK
L-H
L-H
L-H
L-H
L-H
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
None
None
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
High-Z
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
NOTE:
L
D
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available
on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc.
11
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLE
ADDRESS CE
ADSP ADSC
ADV WRITE
OE
X
L
DQ
High-Z
Q
Deselected
None
External
External
External
External
External
Next
H
L
X
L
L
X
X
L
X
X
X
X
X
X
L
X
X
X
L
Read, Begin Burst
Read, Begin Burst
Write, Begin Burst
Read, Begin Burst
Read, Begin Burst
Read, Continue Burst
Read, Continue Burst
Read, Continue Burst
Read, Continue Burst
Write, Continue Burst
Write, Continue Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Write, Suspend Burst
L
L
H
X
L
High-Z
D
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
Write, Suspend Burst
L
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available
on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
X
X
X
X
X
X
12
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–55 to +150
1.6
Unit
°C
W
TSTG
PD
Storage Temperature
Power Dissipation
IOUT
Output Current (per I/O)
100
mA
V
V
VIN, VOUT Voltage Relative to Vss for I/O Pins
–0.5 to VDDQ + 0.5
–0.5 to VDD + 0.5
VIN
Voltage Relative to Vss for
for Address and Control Inputs
VDD
Voltage on VDD Supply Relative to Vss
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
orelectricfields;however,precautionsmaybetakentoavoidapplicationofanyvoltagehigher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc.
13
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
OPERATING RANGE (IS61LFxxxxx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD
3.3V 5%
3.3V 5%
VDDQ
3.3V/2.5V 5%
3.3V/2.5V 5%
-40°C to +85°C
OPERATING RANGE (IS61VFxxxxx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD
2.5V 5%
2.5V 5%
VDDQ
2.5V 5%
2.5V 5%
-40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
Max.
2.5V
Symbol
Parameter
Test Conditions
Min.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
2.0
–0.3
–5
VDD + 0.3
1.7
–0.3
–5
VDD + 0.3
V
V
0.8
5
0.7
5
(1)
Input Leakage Current
Output Leakage Current
VSS ≤ VIN ≤ VDD
ꢀA
ꢀA
ILO
VSS ≤ VOUT ≤ VDDQ, OE = VIH
–5
5
–5
5
Note:
1. VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
6.5
7.5
MAX
x36
MAX
x18
Symbol Parameter
Test Conditions
Temp. range
x18
x72
x36
Unit
ICC
ISB
ISBI
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Com.
Ind.
250
275
250
275
300
350
240
250
240
250
mA
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
140
150
140
150
140
150
140
150
140
150
mA
mA
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
110
125
110
125
110
125
110
125
110
125
VIN
≤ VSS + 0.2V or ≥VDD – 0.2V
f = 0
ZZ>VIH
ISB2
Sleep Mode
Com.
Ind.
60
75
60
75
60
75
60
75
60
75
mA
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits 100 ꢀA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
14
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
1.5 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
351 Ω
5 pF
Including
jig and
1.5V
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc.
15
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 2.5V
1.5 ns
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
16
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
6.5
Min.
7.5
Min. Max.
Symbol
fmax
tKC
Parameter
Max.
133
—
Unit
MHz
ns
Clock Frequency
—
7.5
2.2
2.2
—
—
8.5
2.5
2.5
—
117
—
—
—
7.5
—
—
4.0
3.4
—
3.5
—
—
—
—
—
—
—
—
—
—
2
Cycle Time
tKH
Clock High Time
—
ns
tKL
Clock Low Time
—
ns
tKQ
Clock Access Time
6.5
—
ns
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup Time
2.5
2.5
—
2.5
2.5
—
ns
(2,3)
tKQLZ
—
ns
(2,3)
tKQHZ
3.8
3.2
—
ns
tOEQ
—
—
ns
(2,3)
tOELZ
0
0
ns
(2,3)
tOEHZ
—
3.5
—
—
ns
tAS
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
—
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
—
ns
tWS
tCES
tAVS
tDS
—
ns
—
ns
—
ns
—
ns
tAH
Address Hold Time
—
ns
tWH
tCEH
tAVH
tDH
Write Hold Time
—
ns
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
—
ns
—
ns
—
ns
tPDS
tPUS
ZZ High to Power Down
ZZ Low to Power Down
2
cyc
cyc
—
2
—
2
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
17
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
tKH
tKL
ADSP is blocked by CE inactive
t
SS
tSH
tSS
tSH
ADV
t
AS
tAH
Address
RD1
WR1
RD2
RD3
t
WS
WS
t
t
WH
GW
BWE
t
WH
t
WS
tWH
WR1
BWd-BWa
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
t
OEHZ
OE
tKQX
t
OEQX
High-Z
KQLZ
KQ
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
tKQLZ
tKQHZ
t
KQX
t
tKQ
t
KQHZ
High-Z
1a
DATAIN
tDS
tDH
Single Write
Burst Read
Single Read
Flow-through
Unselected
18
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
tKH
tKL
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
SS
tSH
t
AVH
tAVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
WS
WS
t
t
WH
WH
GW
BWE
t
tWS
tWH
tWS
tWH
BWd-BWa
WR1
WR2
CE1 Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
tDS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Silicon Solution, Inc.
19
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
Min.
—
—
2
Max.
60
2
Unit
mA
ISB2
tPDS
tPUS
tZZI
Current during SNOOZE MODE
ZZ ≥ Vih
ZZ active to input ignored
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
—
2
—
0
tRZZI
—
SNOOZE MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
tZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
20
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
The IS61LF/VF51236A and IS61LF/VF102418A have a
serial boundary scan Test Access Port (TAP) in the PBGA
package only. This port operates in accordance with IEEE
Standard 1149.1-1900, but does not include all functions
required for full 1149.1 compliance. These functions from
the IEEE specification are excluded because they place
added delay in the critical speed path of the SRAM. The
TAP controller operates in a manner that does not conflict
with the performance of other devices using 1149.1 fully
compliant TAPs. The TAP operates using JEDEC stan-
dard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pinmaybeleftdisconnectediftheTAPisnotused. Thepin
is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registersandcanbeconnectedtotheinputofanyregister.
The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
canbedisconnectediftheTAPisunusedinanapplication.
TDI is connected to the Most Significant Bit (MSB) on any
register.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to VDD through a pull-up resistor.
TDO should be left disconnected. On power-up, the de-
vicewillstartinaresetstatewhichwillnotinterferewiththe
device operation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
Integrated Silicon Solution, Inc.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TEST DATA OUT (TDO)
is set LOW (Vss) when the BYPASS instruction is ex-
ecuted.
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the
current state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge of
TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect(NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
andallowdatatobescannedintoandoutoftheSRAMtest
circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
intotheTDIpinontherisingedgeofTCKandoutputonthe
TDO pin on the falling edge of TCK.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Instruction Register
Register Name
Bit Size
(x18)
Bit Size
(x36)
Bit Size
(x72)
Three-bit instructions can be serially loaded into the in-
struction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
Instruction
Bypass
3
1
3
1
3
1
ID
32
75
32
75
32
Boundary Scan
TBD
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
commandisloadedtotheinstructionregister.TheIDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Description
256Kx72
xxxx
512K x 36
xxxx
1M x 18
xxxx
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Reserved for version number.
Defines depth of SRAM. 512K or 1M
Defines with of the SRAM. x36 or x18
Reserved for future use.
00110
00101
xxxxx
00111
00100
xxxxx
01000
00011
xxxxx
Allows unique identification of SRAM vendor. 00011010101 00011010101 00011010101
Indicate the presence of an ID register.
1
1
1
22
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Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output
buffers. The SRAM does not implement the 1149.1 com-
mands EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; instead it performs a capture of the
Inputs and Output ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed be-
tween TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compli-
ant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster. Be-
cause of the clock frequency differences, it is possible that
during the Capture-DR state, an input or output will under-
go a transition. The TAP may attempt a signal capture
while in transition (metastable state). The device will not
be harmed, but there is no guarantee of the value that will
be captured or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabi-
lizedlongenoughtomeettheTAPcontroller’scaptureset-
up plus hold times (tCS and tCH). To insure that the SRAM
clock input is captured correctly, designs need a way to
stop (or slow) the clock during a SAMPLE/PRELOAD
instruction. If this is not an issue, it is possible to capture
allothersignalsandsimplyignorethevalueoftheCLKand
CLK captured in the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction regis-
ter, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented,puttingtheTAPintotheUpdatetotheUpdate-DR
state while performing a SAMPLE/PRELOAD instruction will
have the same effect as the Pause-DR command.
IDCODE
BYPASS
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it short-
ens the boundary scan path when multiple devices are
connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
INSTRUCTION CODES
Code
Instruction
Description
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
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Integrated Silicon Solution, Inc.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
VOH1
VOH2
VOL1
VOL2
VIH
Parameter
Test Conditions
IOH = –2.0 mA
IOH = –100 μA
IOL = 2.0 mA
Min.
1.7
2.1
—
Max.
—
Units
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
—
V
0.7
V
IOL = 100 μA
—
0.2
V
1.7
–0.3
–5
VDD +0.3
0.7
V
VIL
IOLT = 2mA
V
IX
Vss ≤ V I ≤ VDDQ
5
mA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot: Vil (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
100
—
Max.
—
Unit
ns
tTCYC
fTF
TCK Clock cycle time
TCK Clock frequency
10
—
MHz
ns
tTH
TCK Clock HIGH
40
40
10
10
10
10
10
10
—
tTL
TCK Clock LOW
—
ns
tTMSS
tTDIS
tCS
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
—
ns
—
ns
—
ns
tTMSH
tTDIH
tCH
—
ns
—
ns
—
ns
tTDOV
tTDOX
20
—
ns
0
ns
Notes:
1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Integrated Silicon Solution, Inc.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TAP AC TEST CONDITIONS
TAP Output Load Equivalent
Input pulse levels
0 to 2.5V/0 to 3.0V
1ns
Input rise and fall times
Input timing reference levels
Output reference levels
1.25V/1.5V
1.25V/1.5V
50Ω
1.25V/1.5V
TDO
Test load termination supply voltage
1.25V/1.5V
20 pF
GND
Z0
= 50Ω
TAP TIMING
1
2
3
4
5
6
t
THTH
t
TLTH
TCK
TMS
t
THTL
t
t
MVTH
DVTH
t
THMX
t
THDX
TDI
t
TLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
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Integrated Silicon Solution, Inc.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
165 PBGA BOUNDARY SCAN ORDER (512K x 36)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit # Name
ID
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10A
10B
9A
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
ID
1
2
MODE 1R
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
NC
CE2
BWa
BWb
BWc
BWd
CE2
CE
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
A
A
6N
11P
8P
1K
1L
1M
2J
3
4
A
5
A
8R
6
A
9R
2K
2L
2M
1N
3P
3R
4R
4P
6P
6R
7
A
9P
8
A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
9
A
A
10
11
12
13
14
15
16
17
18
19
20
A
A
ZZ
A
NC
A
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
A
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
A
ADV
ADSP
ADSC
OE
A
9B
A1
8A
A0
8B
BWE
GW
7A
7B
CLK
NC
6B
11B
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
165 PBGA BOUNDARY SCAN ORDER (1M x 18)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit # Name
ID
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
A
ID
1
2
MODE 1R
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQa
DQa
DQa
DQa
DQa
NC
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10A
10B
9A
NC
CE2
BWa
NC
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
A
A
6N
11P
8P
1K
1L
1M
1N
2K
2L
2M
2J
3
4
A
5
A
8R
BWb
NC
6
A
9R
7
A
9P
NC
CE2
CE
8
A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
NC
9
A
NC
A
10
11
12
13
14
15
16
17
18
19
20
A
A
A
3P
3R
4R
4P
6P
6R
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
A
NC
A
A
NC
A
ADV
ADSP
ADSC
OE
NC
A
9B
NC
A1
8A
NC
A0
8B
NC
BWE
GW
CLK
NC
7A
DQb
DQb
DQb
DQb
7B
6B
11B
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Integrated Silicon Solution, Inc.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
209 BOUNDARY SCAN ORDER (256K X 72)
Integrated Silicon Solution, Inc.
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Configuration
256Kx72
AccessTime
OrderPartNumber
Package
6.5
6.5
IS61LF25672A-6.5B1
209 PBGA
512Kx36
IS61LF51236A-6.5TQ
IS61LF51236A-6.5B2
100 TQFP
119 PBGA
IS61LF51236A-6.5B3
165 PBGA
512Kx36
1Mx18
7.5
6.5
IS61LF51236A-7.5TQ
IS61LF51236A-7.5B2
100 TQFP
119 PBGA
IS61LF51236A-7.5B3
165 PBGA
IS61LF102418A-6.5TQ
IS61LF102418A-6.5TQL
IS61LF102418A-6.5B2
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61LF102418A-6.5B3
165 PBGA
1Mx18
7.5
IS61LF102418A-7.5TQ
IS61LF102418A-7.5B2
100 TQFP
119 PBGA
IS61LF102418A-7.5B3
165 PBGA
Industrial Range: -40°C to +85°C
Configuration
256Kx72
AccessTime
OrderPartNumber
Package
6.5
6.5
IS61LF25672A-6.5B1I
209 PBGA
512Kx36
IS61LF51236A-6.5TQI
IS61LF51236A-6.5TQLI
IS61LF51236A-6.5B2I
IS61LF51236A-6.5B2LI
100 TQFP
100TQFP,Lead-free
119 PBGA
119PBGA,Lead-free
IS61LF51236A-6.5B3I
165 PBGA
512Kx36
7.5
IS61LF51236A-7.5TQI
IS61LF51236A-7.5TQLI
IS61LF51236A-7.5B2I
100 TQFP
100 TQFP, Lead-free
119 PBGA
IS61LF51236A-7.5B3I
IS61LF51236A-7.5B3LI
165 PBGA
165 PBGA, Lead-free
1Mx18
1Mx18
6.5
7.5
IS61LF102418A-6.5TQI
IS61LF102418A-6.5B2I
100 TQFP
119 PBGA
IS61LF102418A-6.5B3I
165 PBGA
IS61LF102418A-7.5TQI
IS61LF102418A-7.5TQLI
IS61LF102418A-7.5B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61LF102418A-7.5B3I
IS61LF102418A-7.5B3LI
165 PBGA
165PBGA,Lead-free
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IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
ORDERING INFORMATION (VDD = 2.5V /VDDQ = 2.5V)
Commercial Range: 0°C to +70°C
Configuration
256Kx72
Access Time
Order Part Number
Package
6.5
6.5
IS61VF25672A-6.5B1
209 PBGA
512Kx36
IS61VF51236A-6.5TQ
IS61VF51236A-6.5B2
100 TQFP
119 PBGA
IS61VF51236A-6.5B3
165 PBGA
512Kx36
1Mx18
7.5
6.5
7.5
IS61VF51236A-7.5TQ
IS61VF51236A-7.5B2
100 TQFP
119 PBGA
IS61VF51236A-7.5B3
165 PBGA
IS61VF102418A-6.5TQ
IS61VF102418A-6.5B2
100 TQFP
119 PBGA
IS61VF102418A-6.5B3
165 PBGA
1Mx18
IS61VF102418A-7.5TQ
IS61VF102418A-7.5B2
100 TQFP
119 PBGA
IS61VF102418A-7.5B3
165 PBGA
Industrial Range: -40°C to +85°C
Configuration
256Kx72
Access Time
Order Part Number
Package
6.5
6.5
IS61VF25672A-6.5B1I
209 PBGA
512Kx36
IS61VF51236A-6.5TQI
IS61VF51236A-6.5B2I
100 TQFP
119 PBGA
IS61VF51236A-6.5B3I
165 PBGA
512Kx36
7.5
IS61VF51236A-7.5TQI
IS61VF51236A-7.5TQLI
IS61VF51236A-7.5B2I
100 TQFP
100 TQFP, Lead-free
119 PBGA
IS61VF51236A-7.5B3I
165 PBGA
1Mx18
1Mx18
6.5
7.5
IS61VF102418A-6.5TQI
IS61VF102418A-6.5B2I
100 TQFP
119 PBGA
IS61VF102418A-6.5B3I
165 PBGA
IS61VF102418A-7.5TQI
IS61VF102418A-7.5B2I
100 TQFP
119 PBGA
IS61VF102418A-7.5B3I
165 PBGA
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Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
32
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
Integrated Silicon Solution, Inc.
33
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
34
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
Integrated Silicon Solution, Inc.
35
Rev. K
07/29/2010
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