IS61VF102436A-6.5B3 [ISSI]
36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM; 36MB流同步，通过静态RAM
| 型号： | IS61VF102436A-6.5B3 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| 文件： | 总20页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LF102436A IS61VF102436A
IS61LF204818A IS61VF204818A
1M x 36, 2M x 18
36Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
APRIL 2008
FEATURES
DESCRIPTION
The ISSI IS61LF/VF102436A and IS61LF/VF204818A
are high-speed, low-power synchronous static RAMs de-
signed to provide burstable, high-performance memory for
communication and networking applications.The IS61LF/
VF102436Aꢀisꢀorganizedꢀasꢀ1,048,476ꢀwordsꢀbyꢀ36ꢀbits.ꢀ
The IS61LF/VF204818Aꢀisꢀorganizedꢀasꢀ2M-wordsꢀbyꢀ18ꢀ
bits. Fabricated with ISSI'sꢀadvancedꢀCMOSꢀtechnology,ꢀ
the device integrates a 2-bit burst counter, high-speed
SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
•ꢀ Internalꢀself-timedꢀwriteꢀcycle
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ
control
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ
•ꢀ Three chip enable option for simple depth expan-
sion and address pipelining
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
•ꢀ AutoꢀPower-downꢀduringꢀdeselect
•ꢀ Singleꢀcycleꢀdeselect
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀtheꢀ
risingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀoneꢀtoꢀ
four bytes wide as controlled by the write control inputs.
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby
•ꢀ PowerꢀSupply
Separate byte enables allow individual bytes to be written.
Byteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀbyteꢀwriteꢀen-
able (BWE) input combined with one or more individual
byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀWriteꢀ(GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
LF: Vd d 3.3V + 5%, Vd d q 3.3V/2.5V + 5%
VF: Vd d 2.5V + 5%, Vd d q 2.5V + 5%
•ꢀ JEDECꢀ100-PinꢀTQFPꢀandꢀ165-pinꢀPBGAꢀpack-
ages.
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status
Processor)ꢀorꢀADSC (Address Status Cache Controller)
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-
ated internally and controlled by the ADV (burst address
advance) input pin.
•ꢀ Lead-freeꢀavailable
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀorder,ꢀ
LinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀInter-
leaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀorꢀleftꢀ
floating.
FAST ACCESS TIME
Symbol
Parameter
-6.5
6.5ꢀ
7.5ꢀ
133ꢀ
-7.5
7.5ꢀ
8.5ꢀ
117ꢀ
Units
ns
tk q
tk c
ꢀ
ClockꢀAccessꢀTimeꢀ
CycleꢀTimeꢀ
ns
ꢀ
Frequencyꢀ
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
BLOCK DIAGRAM
MODE
A0
A0'
A1'
Q0
CLK
CLK
BINARY
COUNTER
Q1
CE
ADV
A1
1Mx36;
2Mx18;
MEMORY ARRAY
ADSC
ADSP
CLR
20/21
18/19
20/21
D
Q
A
ADDRESS
REGISTER
CE
CLK
36,
or 18
36,
or 18
D
Q
GW
BWE
DQ(a-d)
BYTE WRITE
REGISTERS
BW(a-d)
x18: a,b
x36: a-d
CLK
36,
or 18
CE
CE2
CE2
2/4/8
INPUT
D
Q
DQa - DQd
REGISTERS
ENABLE
OE
REGISTER
CLK
CE
CLK
POWER
DOWN
ZZ
OE
2
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
165-PIN BGA
165-Ball,ꢀ13x15ꢀmmꢀBGA
BOTTOMꢀꢁIEW
Integrated Silicon Solution, Inc.
3
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
165 PBGA PACKAGE PIN CONFIGURATION
1M x 36 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWc
BWd
Vss
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vss
A
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
ADSC
OE
Vss
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vss
A
ADV
ADSP
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
Nc
A
NC
NC
A
CE2
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
NC
A
NC
DQPcꢀ
DQcꢀ
DQc
DQc
DQc
NC
NC
Nc
DQPb
DQb
DQb
DQb
DQb
ZZ
DQcꢀ
DQc
DQc
DQc
NC
DQb
DQb
DQb
DQb
Nc
G
H
J
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQPdꢀ
NC
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
NCꢀ
NC
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
A
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
A
dqa
dqa
dqa
dqa
dqa
dqa
dqa
dqa
K
L
M
N
P
R
NCꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀDQPa
NC
A1*
A0*
NC
A
A
A
A
MODEꢀ Aꢀ
Aꢀ
Aꢀ
NCꢀ
NC
A
A
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.
(UnderꢀEvaluation)ꢀ
PIN DESCRIPTIONS
Symbol
BWE
Pin Name
Symbol
A
Pin Name
Address Inputs
ByteꢀWriteꢀEnable
OutputꢀEnable
A0, A1
SynchronousꢀBurstꢀAddressꢀꢀꢀ
Inputs
OE
ZZꢀ
PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
No Connect
ADVꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance.
MODE
NC
ADSP
AddressꢀStatusꢀProcessor
Address Status Controller
GlobalꢀWriteꢀEnable
DQa-DQd
DQPa-Pdꢀ
Vd d
DataꢀInputs/Outputs
DataꢀInputs/Outputs
PowerꢀSupply
ADSC
GW
CLK
Synchronous Clock
Vd d q
OutputꢀPowerꢀSupplyꢀꢀ
Ground
CE, CE2, CE2
Synchronous Chip Select
ꢁssꢀ
BWxꢀ(x=a,b,c,d)ꢀ SynchronousꢀByteꢀWriteꢀꢀ
ꢀ
Controls
4
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
165 PBGA PACKAGE PIN CONFIGURATION
2M x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWb
NC
Vss
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vss
A
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
ADSC
OE
Vss
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vd d
Vss
A
ADV
ADSP
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
Nc
A
A
NC
A
CE2
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
Nc
NC
NC
NC
NC
Nc
dqa
dqa
dqa
dqa
NC
A
NCꢀ
NCꢀ
NCꢀ
NCꢀ
NC
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
NC
G
H
J
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQPbꢀ
NC
NCꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
NC
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
A
Vd d q
Vd d q
Vd d q
Vd d q
Vd d q
A
Nc
Nc
Nc
Nc
NC
A
K
L
M
N
P
R
NC
A1*
A0*
NC
MODEꢀ Aꢀ
Aꢀ
Aꢀ
NCꢀ
NC
A
A
A
A
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.
(UnderꢀEvaluation)ꢀ
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
BWE
Pin Name
ByteꢀWriteꢀEnable
OutputꢀEnable
A0, A1
SynchronousꢀBurstꢀAddressꢀꢀ ꢀ
Inputs
OE
ZZꢀ
PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
No Connect
ADVꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance.
MODE
NC
ADSP
ADSC
GW
AddressꢀStatusꢀProcessor
Address Status Controller
GlobalꢀWriteꢀEnable
DQa-DQd
DQPa-Pdꢀ
Vd d
DataꢀInputs/Outputs
DataꢀInputs/Outputs
PowerꢀSupply
CLK
Synchronous Clock
Vd d q
OutputꢀPowerꢀSupplyꢀ
Ground
CE, CE2, CE2 Synchronous Chip Select
ꢁssꢀ
BWxꢀ(x=a,b)ꢀ
SynchronousꢀByteꢀWriteꢀꢀ
ꢀ
Controls
Integrated Silicon Solution, Inc.ꢀ
5
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1M x 36
PIN DESCRIPTIONS
DQPa-DQPdꢀ ParityꢀDataꢀInput/Output
A0, A1
Synchronous Address Inputs. These
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
ꢁssꢀ
GWꢀ
ꢀ
ꢀ
Ground
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
OutputꢀEnable
A
Synchronous Address Inputs
MODEꢀꢀ ꢀ
ADSC
ADSP
ADV
Synchronous Controller Address Status
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
OEꢀ
ꢀ
ꢀ
Vd d ꢀ
Vd d q ꢀ
3.3ꢁ/2.5ꢁꢀPowerꢀSupply
ꢀ
ꢀ
IsolatedꢀOutputꢀBufferꢀSupply:
3.3ꢁ/2.5ꢁ
BWa-BWdꢀ
BWEꢀ
ZZꢀ
ꢀ
SnoozeꢀEnable
CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable
CLK
Synchronous Clock
DQa-DQdꢀ
SynchronousꢀDataꢀInput/Output
6
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VDD
ZZ
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2M x 18
PIN DESCRIPTIONS
DQPa-DQPbꢀ ParityꢀDataꢀI/O;ꢀDQPaꢀisꢀparityꢀforꢀꢀ
A0, A1
Synchronous Address Inputs. These
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
ꢀ
ꢀ
ꢀ
DQa1-8;ꢀDQPbꢀisꢀparityꢀforꢀDQb1-8
Vs s ꢀ
Ground
A
Synchronous Address Inputs
GWꢀ
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
OutputꢀEnable
ADSC
ADSP
ADV
Synchronous Controller Address Status
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
MODEꢀꢀ ꢀ
OEꢀ
ꢀ
ꢀ
Vd d ꢀ
Vd d q ꢀ
3.3ꢁ/2.5ꢁꢀPowerꢀSupply
BWa-BWbꢀ
BWEꢀ
ꢀ
ꢀ
IsolatedꢀOutputꢀBufferꢀSupply:
3.3ꢁ/2.5ꢁ
ZZꢀ
ꢀ
SnoozeꢀEnable
CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable
CLK
Synchronous Clock
DQa-DQbꢀ
SynchronousꢀDataꢀInput/Output
Integrated Silicon Solution, Inc.
7
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
TRUTH TABLE(1-8) (3CEꢀoption)
OPERATION
ADDRESS CE
CE2
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
CE2
Xꢀ
Lꢀ
ZZ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
ADSP ADSC ADV WRITE OE
CLK
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
Xꢀ
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
SnoozeꢀꢀMode,ꢀPower-Downꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
WriteꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
WriteꢀCycle,ꢀContinueꢀBurstꢀ
WriteꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
WriteꢀCycle,ꢀSuspendꢀBurstꢀ
Noneꢀ
Noneꢀ
Hꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Noneꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Noneꢀ
Lꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Noneꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Noneꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Nextꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
Lꢀ
High-Z
D
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Q
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
High-Z
Q
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Nextꢀ
Lꢀ
Hꢀ
Lꢀ
High-Z
Q
Nextꢀ
Lꢀ
Nextꢀ
Lꢀ
Hꢀ
Xꢀ
Xꢀ
Lꢀ
High-Z
D
Nextꢀ
Lꢀ
Nextꢀ
Lꢀ
Lꢀ
D
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Q
Hꢀ
Lꢀ
High-Z
Q
Hꢀ
Xꢀ
Xꢀ
High-Z
D
WriteꢀCycle,ꢀSuspendꢀBurstꢀ
Lꢀ
D
NOTE:
1.ꢀ Xꢀmeansꢀ“Don’tꢀCare.”ꢀHꢀmeansꢀlogicꢀHIGH.ꢀLꢀmeansꢀlogicꢀLOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWEꢀareꢀLOWꢀorꢀGWꢀisꢀLOW.ꢀWRITE = H for all
BWx, BWE, GWꢀHIGH.
3. BWaꢀenablesꢀWRITEsꢀtoꢀDQa’sꢀandꢀDQPa.ꢀBWbꢀenablesꢀWRITEsꢀtoꢀDQb’sꢀandꢀDQPb.ꢀBWcꢀenablesꢀWRITEsꢀtoꢀDQc’sꢀ andꢀ
DQPc.ꢀBWdꢀenablesꢀWRITEsꢀtoꢀDQd’sꢀandꢀDQPd.ꢀBWeꢀenablesꢀWRITEsꢀtoꢀDQe’sꢀandꢀDQPe.ꢀBWfꢀenablesꢀWRITEsꢀtoꢀDQf’sꢀ
andꢀDQPf.ꢀBWgꢀenablesꢀWRITEsꢀtoꢀDQg’sꢀandꢀDQPg.ꢀBWhꢀenablesꢀWRITEsꢀtoꢀDQh’sꢀandꢀDQPh.ꢀDQPa-DQPhꢀareꢀꢀavailableꢀ
onꢀtheꢀx72ꢀversion.ꢀDQPaꢀandꢀDQPbꢀareꢀavailableꢀonꢀtheꢀx18ꢀversion.ꢀ DQPa-DQPdꢀareꢀavailableꢀonꢀtheꢀx36ꢀversion.
4. All inputs except OEꢀandꢀZZꢀmustꢀmeetꢀsetupꢀandꢀholdꢀtimesꢀaroundꢀtheꢀrisingꢀedgeꢀ(LOWꢀtoꢀHIGH)ꢀofꢀCLK.
5.ꢀ Waitꢀstatesꢀareꢀinsertedꢀbyꢀsuspendingꢀburst.
6.ꢀ ForꢀaꢀWRITEꢀoperationꢀfollowingꢀaꢀREADꢀoperation,ꢀOEꢀmustꢀbeꢀHIGHꢀbeforeꢀtheꢀinputꢀdataꢀsetupꢀtimeꢀandꢀheldꢀHIGHꢀduringꢀ
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSPꢀLOWꢀalwaysꢀinitiatesꢀanꢀinternalꢀREADꢀatꢀtheꢀL-HꢀedgeꢀofꢀCLK.ꢀAꢀWRITEꢀisꢀperformedꢀbyꢀsettingꢀoneꢀorꢀmoreꢀbyteꢀwriteꢀ
enable signals and BWEꢀLOWꢀorꢀGWꢀLOWꢀforꢀtheꢀsubsequentꢀL-HꢀedgeꢀofꢀCLK.ꢀSeeꢀWRITEꢀtimingꢀdiagramꢀforꢀclarification.
8
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
INTERLEAVED BURST ADDRESS TABLE (MODE = VD D or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–55ꢀtoꢀ+150ꢀ
1.6ꢀ
Unit
°C
W
Ts T g
Pd
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
IO u T ꢀ
OutputꢀCurrentꢀ(perꢀI/O)ꢀ
100ꢀ
mA
V
V
VIN, VO u T ꢀ ꢁoltageꢀRelativeꢀtoꢀꢁssꢀforꢀI/OꢀPinsꢀ
–0.5ꢀtoꢀꢁd d q + 0.5
–0.5ꢀtoꢀꢁd d + 0.5
VINꢀ
ꢁoltageꢀRelativeꢀtoꢀꢁssꢀforꢀꢀ
for Address and Control Inputs
Vd d
Voltage on Vd d ꢀSupplyꢀRelativeꢀtoꢀꢁssꢀ
–0.5ꢀtoꢀ4.6
V
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀperma-
nent damage to the device.This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀ
periods may affect reliability.
2.This device contains circuity to protect the inputs against damage due to high static voltages
orꢀelectricꢀfields;ꢀhowever,ꢀprecautionsꢀmayꢀbeꢀtakenꢀtoꢀavoidꢀapplicationꢀofꢀanyꢀvoltageꢀ
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc.
9
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
OPERATING RANGE (IS61LFxxxxx)
Range
Commercialꢀ
Industrialꢀ
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
VD D
3.3ꢁꢀ±ꢀ5%ꢀ
3.3ꢁꢀ±ꢀ5%ꢀ
VD D q
ꢀ3.3ꢁ/2.5ꢁꢀ±ꢀ5%
3.3ꢁ/2.5ꢁꢀ±ꢀ5%
ꢀ
ꢀ
-40°Cꢀtoꢀ+85°Cꢀ
OPERATING RANGE (IS61VFxxxxx)
Range
Commercialꢀ
Industrialꢀ
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
VD D
2.5ꢁꢀ±ꢀ5%ꢀ
2.5ꢁꢀ±ꢀ5%ꢀ
VD D q
ꢀ2.5ꢁꢀ±ꢀ5%
2.5ꢁꢀ±ꢀ5%
ꢀ
ꢀ
-40°Cꢀtoꢀ+85°Cꢀ
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VO h
OutputꢀHIGHꢀꢁoltageꢀ
IO h = –4.0 mA (3.3V)
IO h = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VO l
OutputꢀLOWꢀꢁoltageꢀ
IO l = 8.0 mA (3.3V)
IO l = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIh
VIl
Il I
InputꢀHIGHꢀꢁoltageꢀꢀ
InputꢀLOWꢀꢁoltage
ꢀ
2.0ꢀ
–0.3
–5ꢀ
Vd d + 0.3
1.7
–0.3
–5ꢀ
Vd d + 0.3
V
V
0.8
5ꢀ
0.7
5ꢀ
Input Leakage Current
OutputꢀLeakageꢀCurrent
Vs s ≤ VIN ≤ Vd d (1)ꢀ
µA
µA
Il O
Vs s ≤ VO u T ≤ Vd d q , OE = VIhꢀ
–5ꢀ
5ꢀ
–5ꢀ
5ꢀ
Note:
1. VIl (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
VIh (max.) = Vd d +ꢀ2.0V Ac (pulse width 2.0 ns). Not 100% tested.
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
6.5
7.5
MAX
MAX
Symbol Parameter
Test Conditions
Temp. range
x18
x36
x18
x36
Unit
Ic c
Is b
ACꢀOperatingꢀ
Supply Current
DeviceꢀSelected,ꢀꢀ
Com.ꢀ
Ind.
360ꢀ
375ꢀ
360ꢀ
375ꢀ
ꢀ
ꢀ
340ꢀ 340ꢀ
350ꢀ 350ꢀ
295
mA
OE = VIh, ZZ ≤ VIl,
All Inputs ≤ 0.2V or ≥ Vd d – 0.2V, typ.(2)
Cycle Time ≥ tk c min.
295
StandbyꢀCurrentꢀ
TTL Input
DeviceꢀDeselected,ꢀꢀ
Vd d = Max.,ꢀ
All Inputs ≤ VIl or ≥ VIh,
ZZ ≤ VIl, fꢀ=ꢀMax.
Com.
Ind.ꢀ
155
160ꢀ
155
160ꢀ
155
155
mA
ꢀ
ꢀ
160ꢀ 160ꢀ
Is b Iꢀ
StandbyꢀCurrentꢀ
cMOs Input
DeviceꢀDeselected,ꢀ
Vd d = Max.,ꢀ
Com.ꢀ
Ind.ꢀ
140
145ꢀ
140
145ꢀ
140
140
mA
145ꢀ 145ꢀ
VIN
≤
Vs s +ꢀ0.2ꢁꢀorꢀ≥Vd d – 0.2V
typ.(2)
80
80
f = 0
Note:
1.ꢀ MODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀꢁd d or Vs s . It exhibits 100 ꢀA maximum leakage current when tied to ≤
Vs s ꢀ+ꢀ0.2ꢁꢀorꢀ≥ Vd d – 0.2V.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀꢁccꢀ=ꢀ3.3ꢁ,ꢀTAꢀ=ꢀ25oC and not 100% tested.
10
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
cIN
Input Capacitance
Input/OutputꢀCapacitanceꢀ
6
8
cO u T ꢀ
VO u T = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀꢁd d = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0ꢁꢀtoꢀ3.0ꢁ
1.5ꢀns
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
1.5ꢁ
and Reference Level
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
351 Ω
5 pF
Including
jig and
1.5V
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc.
11
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
2.5V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0ꢁꢀtoꢀ2.5ꢁ
1.5ꢀns
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
1.25ꢁ
and Reference Level
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ3ꢀandꢀ4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
12
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
6.5
Min.
7.5
Min. Max.
Symbol
ꢀ fmaxꢀ
Parameter
Max.
133ꢀ
—ꢀ
—ꢀ
—ꢀ
6.5ꢀ
—ꢀ
—ꢀ
3.8ꢀ
3.2ꢀ
—ꢀꢀ
3.5ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
Unit
MHz
ns
ClockꢀFrequencyꢀ
—ꢀ
7.5ꢀ
2.2ꢀ
2.2ꢀ
—ꢀ
—ꢀ 117ꢀ
8.5ꢀ —ꢀ
2.5ꢀ —ꢀ
2.5ꢀ —ꢀ
—ꢀ 7.5ꢀ
2.5ꢀ —ꢀ
2.5ꢀ —ꢀ
—ꢀ 4.0ꢀ
—ꢀ 3.4ꢀ
tk c ꢀ
tk h ꢀ
tk l ꢀ
tk q ꢀ
CycleꢀTimeꢀ
ClockꢀHighꢀTimeꢀ
ns
ClockꢀLowꢀTimeꢀ
ns
ClockꢀAccessꢀTimeꢀꢀ
ns
(2)
tk q x ꢀ
tk q l Z (2,3)ꢀ
tk q h Z (2,3)ꢀ
tO E q ꢀ
tO E l Z (2,3)ꢀ
tO E h Z (2,3)ꢀ
tA s ꢀ
ClockꢀHighꢀtoꢀOutputꢀInvalidꢀ
ClockꢀHighꢀtoꢀOutputꢀLow-Zꢀ
ClockꢀHighꢀtoꢀOutputꢀHigh-Zꢀꢀ
OutputꢀEnableꢀtoꢀOutputꢀꢁalidꢀꢀ
OutputꢀEnableꢀtoꢀOutputꢀLow-Zꢀ
OutputꢀDisableꢀtoꢀOutputꢀHigh-Zꢀꢀ
AddressꢀSetupꢀTimeꢀꢀ
Read/WriteꢀSetupꢀTimeꢀꢀ
ChipꢀEnableꢀSetupꢀTimeꢀꢀ
AddressꢀAdvanceꢀSetupꢀTimeꢀꢀ
DataꢀSetupꢀTimeꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
ns
ns
ns
—ꢀ
ns
0ꢀ
0ꢀꢀ
—ꢀ
ns
—ꢀ
—ꢀ 3.5ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
1.5ꢀ —ꢀ
0.5ꢀ —ꢀ
0.5ꢀꢀ —ꢀ
0.5ꢀꢀ —ꢀ
0.5ꢀꢀ —ꢀ
0.5ꢀ —ꢀ
ns
1.5ꢀ
1.5ꢀ
1.5ꢀ
1.5ꢀ
1.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
0.5ꢀ
—ꢀ
ns
tW s ꢀ
ns
tc E s ꢀ
ns
tA V s ꢀ
ns
td s ꢀ
ns
tA h
Address Hold Time
ns
tW h ꢀ
WriteꢀHoldꢀTimeꢀꢀ
ns
tc E h ꢀ
ChipꢀEnableꢀHoldꢀTimeꢀꢀ
AddressꢀAdvanceꢀHoldꢀTimeꢀꢀ
DataꢀHoldꢀTimeꢀ
ns
tA V h ꢀ
ns
td h ꢀ
ns
tP d s ꢀ
ZZꢀHighꢀtoꢀPowerꢀDownꢀꢀ
ZZꢀLowꢀtoꢀPowerꢀDownꢀꢀ
—ꢀꢀ
—ꢀꢀ
2ꢀ
2ꢀ
cyc
cyc
tP u s ꢀ
—ꢀ
2ꢀ
Notes:
1.ꢀ ConfigurationꢀsignalꢀMODEꢀisꢀstaticꢀandꢀmustꢀnotꢀchangeꢀduringꢀnormalꢀoperation.
2.ꢀ Guaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
13
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
READ/WRITE CYCLE TIMING
tKC
CLK
ADSP
ADSC
tKH
tKL
ADSP is blocked by CE inactive
t
SS
tSH
tSS
tSH
ADV
t
AS
tAH
Address
RD1
WR1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
tWS
tWH
WR1
BWd-BWa
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
tOEHZ
OE
t
KQX
t
OEQX
High-Z
KQLZ
KQ
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
tKQLZ
t
KQHZ
t
KQX
KQHZ
t
tKQ
t
High-Z
1a
DATAIN
t
DS
tDH
Single Write
Burst Read
Single Read
Flow-through
Unselected
14
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
WRITE CYCLE TIMING
tKC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE1 inactive
ADSC initiate Write
tSS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
tAS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
tWS
tWH
tWS
tWH
BWd-BWa
WR1
WR2
CE1 Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
t
t
OE
DATAOUT
DATAIN
High-Z
tDS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Silicon Solution, Inc.ꢀ
15
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
Min. typ. (1) Max.
Unit
mA
Is b 2
tP d s
tP u s
tZ Z I
CurrentꢀduringꢀSNOOZEꢀMODE
ZZ ≥ Vih
—
—
2
27
90
2
ZZ active to input ignored
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZꢀactiveꢀtoꢀSNOOZEꢀcurrent
ZZꢀinactiveꢀtoꢀexitꢀSNOOZEꢀcurrent
—
2
—
0
tr Z Z I
—
1.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀꢁccꢀ=ꢀ3.3ꢁ,ꢀTAꢀ=ꢀ25oC and not 100% tested.
SNOOZE MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
ISB2
tRZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
16
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
ORDERING INFORMATION (VD D = 3.3V/VD D q = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Configuration
Access Time
Order Part Number
Package
1Mx36ꢀ
6.5ꢀ
ꢀ
IS61LF102436A-6.5TQLꢀ
IS61LF102436A-6.5B3ꢀ
100ꢀTQFP,ꢀLead-free
165ꢀPBGA
ꢀ ꢀ
2Mx18ꢀ
ꢀ ꢀ
ꢀ ꢀ
6.5ꢀ
ꢀ
ꢀ
IS61LF204818A-6.5TQꢀ
IS61LF204818A-6.5TQLꢀ
IS61LF204818A-6.5B3ꢀ
100ꢀTQFPꢀ
ꢀ
ꢀ
ꢀ
100ꢀTQFP,ꢀLead-free
165ꢀPBGA
Industrial Range: -40°C to +85°C
Configuration
Access Time
Order Part Number
Package
1Mx36ꢀ
6.5ꢀ
ꢀ
IS61LF102436A-6.5TQLIꢀ
IS61LF102436A-6.5B3Iꢀ
100ꢀTQFP,ꢀLead-free
165ꢀPBGA
ꢀ ꢀ
1Mx36ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
7.5ꢀ
IS61LF102436A-7.5TQIꢀ
IS61LF102436A-7.5TQLIꢀ
IS61LF102436A-7.5B3Iꢀ
IS61LF102436A-7.5B3LIꢀ
100ꢀTQFPꢀ
100ꢀTQFP,ꢀLead-free
165ꢀPBGAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
165ꢀPBGA,ꢀLead-free
2Mx18ꢀ
ꢀ ꢀ
2Mx18ꢀ
ꢀ ꢀ
ꢀ ꢀ
6.5ꢀ
ꢀ
IS61LF204818A-6.5TQIꢀ
IS61LF204818A-6.5B3Iꢀ
100ꢀTQFP
165ꢀPBGA
7.5ꢀ
ꢀ
ꢀ
IS61LF204818A-7.5TQIꢀ
IS61LF204818A-7.5TQLIꢀ
IS61LF204818A-7.5B3Iꢀ
100ꢀTQFPꢀ
100ꢀTQFP,ꢀLead-free
165ꢀPBGA
ꢀ
ꢀ
ꢀ
Integrated Silicon Solution, Inc.
17
Rev. B
04/17/08
IS61LF102436A IS61LF204818A
IS61VF102436A IS61VF204818A
ORDERING INFORMATION (VD D = 2.5V /VD D q = 2.5V)
Commercial Range: 0°C to +70°C
Configuration
Access Time
Order Part Number
Package
1Mx36ꢀ
6.5ꢀ
ꢀ
IS61ꢁF102436A-6.5TQꢀ
IS61ꢁF102436A-6.5B3ꢀ
100ꢀTQFP
165ꢀPBGA
ꢀ ꢀ
1Mx36ꢀ
ꢀ ꢀ
2Mx18ꢀ
ꢀ ꢀ
2Mx18ꢀ
ꢀ ꢀ
7.5ꢀ
ꢀ
IS61ꢁF102436A-7.5TQꢀ
IS61ꢁF102436A-7.5B3ꢀ
100ꢀTQFP
165ꢀPBGA
6.5ꢀ
ꢀ
IS61ꢁF204818A-6.5TQꢀ
IS61ꢁF204818A-6.5B3ꢀ
100ꢀTQFP
165ꢀPBGA
7.5ꢀ
ꢀ
IS61ꢁF204818A-7.5TQꢀ
IS61ꢁF204818A-7.5B3ꢀ
100ꢀTQFP
165ꢀPBGA
Industrial Range: -40°C to +85°C
Configuration
Access Time
Order Part Number
Package
1Mx36ꢀ
6.5ꢀ
ꢀ
IS61ꢁF102436A-6.5TQIꢀ
IS61ꢁF102436A-6.5B3Iꢀ
100ꢀTQFP
165ꢀPBGA
ꢀ ꢀ
1Mx36ꢀ
ꢀ ꢀ
ꢀ ꢀ
2Mx18ꢀ
ꢀ ꢀ
2Mx18ꢀ
7.5ꢀ
ꢀ
ꢀ
IS61ꢁF102436A-7.5TQIꢀ
IS61ꢁF102436A-7.5TQLIꢀ
IS61ꢁF102436A-7.5B3Iꢀ
100ꢀTQFPꢀ
100ꢀTQFP,ꢀLead-free
165ꢀPBGA
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
6.5ꢀ
ꢀ
IS61ꢁF204818A-6.5TQIꢀ
IS61ꢁF204818A-6.5B3Iꢀ
100ꢀTQFPꢀ
165ꢀPBGA
ꢀ
7.5ꢀ
ꢀ
IS61ꢁF204818A-7.5TQIꢀ
IS61ꢁF204818A-7.5B3Iꢀ
100ꢀTQFP
165ꢀPBGA
ꢀ ꢀ
18
Integrated Silicon Solution, Inc.
Rev. B
04/17/08
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
Millimeters
Min Max
Inches
Millimeters
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
PACKAGING INFORMATION
Ball Grid Array
Package Code: B (165-pin)
BOTTOM VIEW
A1 CORNER
TOP VIEW
A1 CORNER
φ b (165X)
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D
D1
K
L
K
L
M
N
P
R
M
N
P
R
e
E1
E
A2
A
A1
BGA - 13mm x 15mm
Notes:
MILLIMETERS
INCHES
1. Controlling dimensions are in millimeters.
Sym. Min. Nom. Max.
Min. Nom. Max.
165
N0.
Leads
165
A
—
0.25
—
—
1.20
0.40
—
—
—
0.047
0.010 0.013 0.016
0.031
A1
A2
D
0.33
0.79
—
—
14.90 15.00 15.10
13.90 14.00 14.10
12.90 13.00 13.10
9.90 10.00 10.10
0.587 0.591 0.594
0.547 0.551 0.555
0.508 0.512 0.516
0.390 0.394 0.398
D1
E
E1
e
—
1.00
0.45
—
—
0.039
—
b
0.40
0.50
0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03
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