IS61WV25616BLL/BLS [ISSI]
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM; 256K ×16高速异步的CMOS静态RAM
| 型号： | IS61WV25616BLL/BLS |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM |
| 文件： | 总21页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61WV25616ALL/ALS
IS61WV25616BLL/BLS
IS64WV25616BLL/BLS
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
JULY2010
DESCRIPTION
FEATURES
The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx
are high-speed, 4,194,304-bit static RAMs organized as
262,144 words by 16 bits. It is fabricated usingISSI's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields high-performance and low power consumption de-
vices.
HIGHSPEED:(IS61/64WV25616ALL/BLL)
• High-speed access time: 8, 10, 20 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
LOWPOWER:(IS61/64WV25616ALS/BLS)
• High-speed access time: 25, 35, 45 ns
• Low Active Power: 35 mW (typical)
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• Low Standby Power: 0.6 mW (typical)
CMOS standby
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Singlepowersupply
— VDD 1.65V to 2.2V (IS61WV25616Axx)
— VDD 2.4V to 3.6V (IS61/64WV25616Bxx)
• Fully static operation: no clock or refresh required
• Three state outputs
The IS61WV25616Axx/Bxx and IS64WV25616Bxx are
packagedintheJEDECstandard44-pinTSOPTypeII and
48-pin Mini BGA (6mm x 8mm).
• Data control for upper and lower bytes
• IndustrialandAutomotivetemperaturesupport
• Lead-freeavailable
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
ISB1, ISB2
ICC
Not Selected
OutputDisabled
X
H
X
X
X
High-Z
High-Z
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
A0
A1
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
OE
A2
3
WE
A3
4
A4
5
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NoConnection
CE
6
UB
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
8
9
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD
Power
GND
Ground
A6
A7
A8
A9
*SOJ package under evaluation.
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
PIN CONFIGURATIONS
44-Pin LQFP
48-Pin mini BGA (6mm x 8mm)
1
1
2
3
4
5
6
2
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
A0
A3
A1
A4
A2
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
3
CE
I/O
0
8
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
TOP VIEW
GND
A7
I/O
I/O
A17
NC
A14
A12
I/O
I/O
I/O
VDD
11
3
4
5
4
GND
V
DD
A16
A15
A13
A10
12
I/O
I/O
I/O
I/O
6
14
13
9
10
11
NC
A8
WE
I/O
7
15
5
G
H
I/O8
NC
NC
A9
A11
NC
12 13 14 15 16 17 18 19 20 21 22
6
7
*LQFP package under evaluation.
PIN DESCRIPTIONS
8
A0-A17
I/O0-I/O15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
9
OE
WE
10
11
12
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NoConnection
UB
NC
VDD
Power
GND
Ground
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3
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VDD + 0.3
V
–0.3
–1
0.8
1
V
ILI
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter
TestConditions
Min.
1.8
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 1.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2.0
–0.3
–1
VDD + 0.3
V
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter
TestConditions
IOH = -0.1 mA
IOL = 0.1 mA
VDD
Min.
1.4
—
Max.
Unit
V
VOH
VOL
VIH
OutputHIGHVoltage
1.65-2.2V
1.65-2.2V
1.65-2.2V
1.65-2.2V
—
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakage
0.2
V
1.4
–0.2
–1
VDD + 0.2
V
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
4
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Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC TEST CONDITIONS
1
Parameter
Unit
(2.4V-3.6V)
Unit
(3.3V+10%)
Unit
(1.65V-2.2V)
InputPulseLevel
0Vto3V
1V/ns
1.5V
0Vto3V
1V/ns
1.5V
0Vto1.8V
1V/ns
InputRiseandFallTimes
2
InputandOutputTiming
andReferenceLevel(VRef
0.9V
)
OutputLoad
SeeFigures1and2
SeeFigures1and2
SeeFigures1and2
3
AC TEST LOADS
319 Ω
4
3.3V
OUTPUT
ZO = 50Ω
50Ω
1.5V
OUTPUT
30 pF
5
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
6
Figure 1.
Figure 2.
7
8
9
10
11
12
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5
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to VDD + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
VTERM
VDD
Terminal Voltage with Respect to GND
VDD Relates to GND
StorageTemperature
PowerDissipation
TSTG
PT
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
tothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
6
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Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
HIGH SPEED (IS61WV25616ALL/BLL)
OPERATING RANGE (VDD) (IS61WV25616ALL)
1
Range
AmbientTemperature
0°C to +70°C
VDD
Speed
20ns
20ns
20ns
Commercial
Industrial
Automotive
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
–40°Cto+85°C
–40°Cto+125°C
2
OPERATING RANGE (VDD) (IS61WV25616BLL)(1)
3
Range
AmbientTemperature
0°C to +70°C
VDD (8 nS)1
3.3V + 5%
3.3V + 5%
VDD (10nS)1
2.4V-3.6V
2.4V-3.6V
Commercial
Industrial
–40°Cto+85°C
Note:
4
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the
range of 3.3V + 5%, the device meets 8ns.
5
OPERATING RANGE (VDD) (IS64WV25616BLL)
Range
AmbientTemperature
VDD (10 nS)
Automotive
–40°Cto+125°C
2.4V-3.6V
6
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
7
-8
-10
-20
Symbol Parameter
Test Conditions
Min.
Max.
Min. Max.
Min. Max.
Unit
ICC
VDD Dynamic Operating VDD = Max.,
Com.
Ind.
—
—
—
50
55
—
—
—
—
40
45
65
—
—
—
35
40
60
mA
8
Supply Current
IOUT = 0 mA, f = fMAX
Auto.
typ.(2)
25
ICC1
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
35
40
—
—
—
—
35
40
60
—
—
—
30
40
60
mA
mA
mA
9
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
10
15
—
—
—
—
10
15
30
—
—
—
10
15
30
10
11
12
ISB2
CMOS Standby
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VDD = Max.,
Com.
Ind.
—
—
—
8
9
—
—
—
—
8
9
20
—
—
—
8
9
20
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Auto.
typ.(2)
2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
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7
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
LOW POWER (IS61WV25616ALS/BLS)
OPERATING RANGE (VDD) (IS61WV25616ALS)
Range
AmbientTemperature
0°C to +70°C
VDD
Speed
45ns
45ns
45ns
Commercial
Industrial
Automotive
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
–40°Cto+85°C
–40°Cto+125°C
OPERATING RANGE (VDD) (IS61WV25616BLS)
Range
Commercial
Industrial
AmbientTemperature
0°C to +70°C
VDD (25 nS)
2.4V-3.6V
2.4V-3.6V
–40°Cto+85°C
OPERATING RANGE (VDD) (IS64WV25616BLS)
Range
AmbientTemperature
VDD (35 nS)
Automotive
–40°Cto+125°C
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
-35
-45
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
—
20
25
50
—
—
—
20
25
50
—
—
—
15
20
40
mA
Auto.
typ.(2)
11
ICC1
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
10
12
20
—
—
—
10
12
20
—
—
—
10
12
20
mA
mA
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
5
7
10
—
—
—
5
7
10
—
—
—
5
7
10
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
—
1
2
10
—
—
—
1
2
10
—
—
—
1
2
10
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Auto.
typ.(2)
0.2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
8
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Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-10
1
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
AA
OHA
ACE
DOE
ReadCycleTime
8
—
2.0
—
—
—
0
—
8
10
—
2.0
—
—
—
0
—
10
—
10
4.5
4
t
AddressAccessTime
OutputHoldTime
CEAccessTime
2
t
—
8
t
t
OEAccessTime
4.5
3
3
(2)
tHZOE
OEtoHigh-ZOutput
OEtoLow-ZOutput
CEtoHigh-ZOutput
CEtoLow-ZOutput
LB,UBAccessTime
LB,UBtoHigh-ZOutput
LB,UBtoLow-ZOutput
PowerUpTime
(2)
tLZOE
—
3
—
4
(2
t
HZCE
0
0
4
(2)
tLZCE
3
—
5.5
3
3
—
6.5
3
tBA
—
0
—
0
(2)
tHZB
(2)
5
t
LZB
PU
PD
0
—
—
8
0
—
—
10
t
0
0
t
PowerDownTime
—
—
6
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.
7
8
9
10
11
12
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Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20ns
Min. Max.
-25ns
Min.
-35ns
Min. Max.
-45ns
Min. Max.
Symbol
Parameter
Max.
—
25
—
25
12
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
AA
OHA
ACE
DOE
ReadCycleTime
20
—
2.5
—
—
0
—
20
—
20
8
25
—
4
35
—
4
—
35
—
35
15
10
—
10
—
35
10
—
45
—
7
—
45
—
45
20
15
—
15
—
45
15
—
t
AddressAccessTime
OutputHoldTime
t
t
CEAccessTime
—
—
0
—
—
0
—
—
0
t
OEAccessTime
(2)
tHZOE
OEtoHigh-ZOutput
OEtoLow-ZOutput
CEtoHigh-ZOutput
CEtoLow-ZOutput
LB,UBAccessTime
LB,UBtoHigh-ZOutput
LB,UBtoLow-ZOutput
8
(2)
tLZOE
0
—
8
0
—
8
0
0
(2
t
HZCE
0
0
0
0
(2)
t
LZCE
BA
HZB
LZB
3
—
8
10
—
0
—
25
8
10
—
0
15
—
0
t
—
0
t
8
t
0
—
0
—
0
0
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
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Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1
t
RC
2
ADDRESS
t
AA
t
OHA
t
OHA
3
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
4
READ CYCLE NO. 2(1,3)
5
t
RC
ADDRESS
OE
6
tAA
tOHA
tHZOE
t
DOE
LZOE
ACE
7
t
CE
t
t
HZCE
tLZCE
8
LB, UB
t
BA
tHZB
t
RC
tLZB
HIGH-Z
D
OUT
DATA VALID
9
I
CC
SB
V
DD
Supply
Current
50%
50%
t
PD
tPU
I
UB_CEDR2.eps
10
11
12
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Symbol
Parameter
Min.
8
Max.
—
Min.
10
8
Max.
—
Unit
ns
t
WC
SCE
AW
WriteCycleTime
CEtoWriteEnd
t
6.5
6.5
—
—
ns
t
AddressSetupTime
toWriteEnd
—
8
—
ns
t
HA
SA
PWB
PWE
PWE
SD
HD
HZWE
AddressHoldfromWriteEnd
AddressSetupTime
0
0
—
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
LB,UBValidtoEndofWrite
WEPulseWidth
6.5
6.5
8.0
5
8
t
1
8
t
2
WEPulseWidth (OE=LOW)
DataSetuptoWriteEnd
DataHoldfromWriteEnd
WELOWtoHigh-ZOutput
WEHIGHtoLow-ZOutput
10
6
t
t
0
0
(2)
(2)
t
—
2
—
2
tLZWE
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write. Shaded area product in development
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20ns
-25ns
-35ns
-45ns
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
1
t
WC
SCE
AW
WriteCycleTime
CEtoWriteEnd
20
12
12
—
—
—
25
18
15
—
—
—
35
25
25
—
—
—
45
35
35
—
—
—
t
ns
t
AddressSetupTime
toWriteEnd
ns
2
t
HA
SA
PWB
PWE
PWE
SD
HD
HZWE
AddressHoldfromWriteEnd
AddressSetupTime
0
0
—
—
—
—
—
—
—
9
0
0
—
—
—
—
—
—
—
12
—
0
0
—
—
—
—
—
—
—
20
—
0
0
—
—
—
—
—
—
—
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
3
t
LB,UBValidtoEndofWrite
WEPulseWidth(OE=HIGH)
WEPulseWidth(OE=LOW)
DataSetuptoWriteEnd
12
12
17
9
18
18
20
12
0
30
30
30
15
0
35
35
35
20
0
t
1
t
2
4
t
t
DataHoldfromWriteEnd
WELOWtoHigh-ZOutput
WEHIGHtoLow-ZOutput
0
(3)
(3)
t
—
3
—
5
—
5
—
5
5
tLZWE
—
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
(1 )
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
(1,2)
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
1
t
WC
ADDRESS
OE
VALID ADDRESS
2
t
HA
LOW
LOW
CE
3
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
4
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
5
UB_CEWR3.eps
6
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
7
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
8
OE
CE
t
SA
LOW
t
HA
SA
t
HA
9
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
10
11
12
HIGH-Z
D
OUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
HIGH SPEED (IS61WV25616ALL/BLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
3.6
8
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 2.0V, CE ≥ VDD – 0.2V
2.0
—
IDR
Com.
—
—
2
mA
Ind.
—
9
Auto.
15
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
Recovery Time
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 3.0V, T
A
= 25 C and not 100% tested.
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.2V, CE ≥ VDD – 0.2V
1.2
—
3.6
IDR
Com.
Ind.
—
—
5
10
15
mA
—
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
Recovery Time
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 1.8V, T
A
= 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE ≥ VDD - 0.2V
CE
GND
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
LOW POWER (IS61WV25616ALS/BLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
1
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
3.6
1
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 2.0V, CE ≥ VDD – 0.2V
2.0
—
IDR
Com.
—
—
0.2
—
mA
2
Ind.
Auto.
2
10
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
3
Recovery Time
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 3.0V, T
A
= 25 C and not 100% tested.
4
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
Unit
V
5
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.2V, CE ≥ VDD – 0.2V
1.2
—
3.6
IDR
Com.
Ind.
—
—
0.2
—
1
2
mA
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
6
Recovery Time
See Data Retention Waveform
tRC
O
: Typical values are measured at VDD = 1.8V, T
A
= 25 C and not 100% tested.
7
8
DATA RETENTION WAVEFORM (CE Controlled)
9
tSDR
Data Retention Mode
tRDR
VDD
10
11
12
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
ORDERING INFORMATION (HIGH SPEED)
Commercial Range: 0°C to +70°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10(81)
IS61WV25616BLL-10TL
TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10(81)
IS61WV25616BLL-10BI
48 mini BGA (6mm x 8mm)
IS61WV25616BLL-10BLI 48 mini BGA (6mm x 8mm), Lead-free
IS61WV25616BLL-10TI
IS61WV25616BLL-10TLI
TSOP (Type II)
TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed(ns)
Order Part No.
Package
20
IS61WV25616ALL-20BI
IS61WV25616ALL-20TI
IS61WV25616ALL-20TLI
48 mini BGA (6mm x 8mm)
TSOP (Type II)
TSOP (Type II), Lead-free
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10
IS64WV25616BLL-10BA3
IS64WV25616BLL-10BLA3
IS64WV25616BLL-10CTA3
48 mini BGA (6mm x 8mm)
48 mini BGA (6mm x 8mm), Lead-free
TSOP (Type II), Copper Leadframe
IS64WV25616BLL-10CTLA3 TSOP(TypeII), Lead-free, CopperLeadframe
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
ORDERING INFORMATION (LOW POWER)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
1
Speed(ns)
Order Part No.
Package
25
IS61WV25616BLS-25TLI TSOP (Type II), Lead-free
2
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
3
Speed(ns)
Order Part No.
Package
45
IS61WV25616ALS-45TLI TSOP (Type II), Lead-free
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
21
Rev. G
07/15/2010
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