IS61WV25616EDBLL-8BLI-TR [ISSI]
Application Specific SRAM, 256KX16, 8ns, CMOS, PBGA48;
| 型号： | IS61WV25616EDBLL-8BLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Application Specific SRAM, 256KX16, 8ns, CMOS, PBGA48 静态存储器 |
| 文件： | 总14页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61WV25616EDBLL
IS64WV25616EDBLL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
OCTOBER 2011
DESCRIPTION
FEATURES
Theꢀ ISSIꢀ IS61/64WV25616EDBLLꢀ isꢀ aꢀ ꢀ high-speed,ꢀ
4,194,304-bitꢀstaticꢀRAMsꢀorganizedꢀasꢀ262,144ꢀwordsꢀ
byꢀ16ꢀbits.ꢀItꢀisꢀfabricatedꢀusingꢀISSI'sꢀhigh-performanceꢀ
CMOSꢀtechnology.ꢀThisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀ
withꢀ innovativeꢀ circuitꢀ designꢀ techniques,ꢀ yieldsꢀ high-
performanceꢀandꢀlowꢀpowerꢀconsumptionꢀdevices.
•ꢀ High-speedꢀaccessꢀtime:ꢀ8,ꢀ10ꢀns
•ꢀ LowꢀActiveꢀPower:ꢀ85ꢀmWꢀ(typical)
•ꢀ LowꢀStandbyꢀPower:ꢀ7ꢀmWꢀ(typical)ꢀ
CMOSꢀstandby
•ꢀ Singleꢀpowerꢀsupply
ꢀ —ꢀꢀVddꢀ2.4Vꢀtoꢀ3.6Vꢀ(10ꢀns)
—ꢀꢀVdd 3.3Vꢀ ꢀ10%ꢀ(8ꢀns)
WhenꢀCEꢀisꢀHIGHꢀ(deselected),ꢀtheꢀdeviceꢀassumesꢀaꢀ
standbyꢀmodeꢀatꢀwhichꢀtheꢀpowerꢀdissipationꢀcanꢀbeꢀre-
ducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀꢀ
required
EasyꢀmemoryꢀexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ
andꢀOutputꢀEnableꢀinputs,ꢀCEꢀandꢀOE.ꢀTheꢀactiveꢀLOWꢀ
WriteꢀEnableꢀ(WE)ꢀcontrolsꢀbothꢀwritingꢀandꢀreadingꢀofꢀtheꢀ
memory.ꢀꢀAꢀdataꢀbyteꢀallowsꢀUpperꢀByteꢀ(UB)ꢀandꢀLowerꢀ
Byteꢀ(LB)ꢀaccess.
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport
•ꢀ Lead-freeꢀavailable
•ꢀ ErrorꢀDetectionꢀandꢀErrorꢀCorrection
TheꢀIS61/64WV25616EDBLLꢀisꢀꢀpackagedꢀinꢀtheꢀJEDECꢀ
standardꢀ44-pinꢀTSOP-IIꢀꢀandꢀ48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ
8mm).
FUNCTIONAL BLOCK DIAGRAM
Memory
Lower IO
Array-
Memory
Upper IO
Array-
A0-A17
ECC
Array-
256K
x4
ECC
Array-
256K
x4
Decoder
256Kx8
256Kx8
8
4
8
4
8
8
8
8
12
12
IO0-7
ECC
ECC
I/O Data
Circuit
Column I/O
IO8-15
/CE
/OE
/WE
/UB
/LB
Control
Circuit
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstancesꢀꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
1
Rev. A
09/29/2011
IS61/64WV25616EDBLL
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LBꢀ
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Isb1, Isb2
Iccꢀ
NotꢀSelectedꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
High-Zꢀ
High-Zꢀ
OutputꢀDisabledꢀ
ꢀ
Hꢀ
Xꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Z
ꢀ
ꢀ
ꢀ
Readꢀ
ꢀ
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
doutꢀ
High-Zꢀ
dout
High-Z
dout
dout
Iccꢀ
Iccꢀ
ꢀ
ꢀ
Writeꢀ
ꢀ
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Xꢀ
Xꢀ
X
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
dInꢀ
High-Zꢀ
dIn
High-Z
dIn
dIn
PIN CONFIGURATIONS
PIN DESCRIPTIONS
A0-A17ꢀ
I/O0-I/O15ꢀ
CEꢀꢀ
AddressꢀInputs
44-Pin TSOP (Type II)
DataꢀInputs/Outputs
ChipꢀEnableꢀInput
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
OEꢀꢀ
A0
A1
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
WEꢀꢀ
A2
3
LBꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
NoꢀConnection
A3
4
UBꢀ
A4
5
CE
6
NCꢀ
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
8
9
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Vddꢀ
Power
GNDꢀ
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
A6
A7
A8
A9
*soJꢀpackageꢀunderꢀevaluation.
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
PIN CONFIGURATIONS
1
44-Pin LQFP*
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
2
44 43 42 41 40 39 38 37 36 35 34
3
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
A0
A3
A1
A4
A2
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
CE
I/O
0
8
I/O
I/O
I/O
A5
A6
I/O
I/O
I/O
2
9
10
1
4
TOP VIEW
GND
A7
A17
NC
A14
A12
VDD
11
3
4
5
I/O
I/O
GND
V
DD
I/O
I/O
A16
A15
A13
A10
12
I/O
I/O
I/O
6
14
13
5
9
NC
A8
WE
I/O
7
15
G
H
10
11
I/O8
NC
NC
A9
A11
NC
12 13 14 15 16 17 18 19 20 21 22
6
7
*LQFPꢀpackageꢀunderꢀevaluation.
8
PIN DESCRIPTIONS
A0-A17ꢀ
I/O0-I/O15ꢀ
CEꢀꢀ
AddressꢀInputs
DataꢀInputs/Outputs
ChipꢀEnableꢀInput
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
9
OEꢀꢀ
WEꢀꢀ
10
11
12
LBꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
NoꢀConnection
UBꢀ
NCꢀ
Vddꢀ
Power
GNDꢀ
Ground
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev. A
09/29/2011
IS61/64WV25616EDBLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–0.3ꢀtoꢀ4.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
V
°C
W
Vterm
ꢀ Vdd
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
VddꢀRelatesꢀtoꢀGNDꢀ
ꢀ tstg
ꢀ Pt
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.ꢀ
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIn = 0V
Max.
6ꢀ
Unit
pF
cIn
InputꢀCapacitanceꢀ
Input/OutputꢀCapacitanceꢀ
ꢀ cI/oꢀ
Vout = 0V
8ꢀ
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTa = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
ERROR DETECTION AND ERROR CORRECTION
•ꢀ IndependentꢀECCꢀforꢀeachꢀbyte
•ꢀ Detectꢀandꢀcorrectꢀoneꢀbitꢀerrorꢀperꢀbyte
•ꢀ Betterꢀreliabilityꢀthanꢀparityꢀcodeꢀschemesꢀwhichꢀcanꢀonlyꢀdetectꢀanꢀerrorꢀbutꢀnotꢀcorrectꢀanꢀerror
•ꢀ BackwardꢀCompatible:ꢀDropꢀinꢀreplacementꢀtoꢀcurrentꢀinꢀindustryꢀstandardꢀdevicesꢀ(withoutꢀECC)
OPERATING RANGE (VDD)1
Range
Ambient Temperature
IS61WV25616EDBLL
IS64WV25616EDBLL
VDD (8, 10nS)
VDD (10nS)
Industrialꢀ
ꢀ ꢀ
–40°Cꢀtoꢀ+85°Cꢀ
ꢀ
2.4V-3.6Vꢀ(10ns)ꢀ
3.3Vꢀ ꢀ10%ꢀ(8ns)
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ Automotiveꢀ(A1)ꢀ
Automotiveꢀ(A3)ꢀ –40°Cꢀtoꢀ+125°Cꢀ
–40°Cꢀtoꢀ+85°Cꢀ
—ꢀ
—ꢀ
2.4V-3.6V
2.4V-3.6V
Note:
1.ꢀꢀContactꢀSRAM@issi.comꢀforꢀ1.8Vꢀoption
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 3.3V + 10%
Symbol Parameter
Test Conditions
Vdd = Min.,ꢀIoH = –4.0ꢀmAꢀ
Min.
2.4ꢀ
—ꢀ
2ꢀ
–0.3ꢀ
–1ꢀ
Max.
—ꢀ
0.4ꢀ
Unit
V
V
V
V
1
VoH
ꢀ VoL
ꢀ VIH
ꢀ VIL
ꢀ ILI
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vdd = Min.,ꢀIoL = 8.0ꢀmAꢀ
ꢀ
ꢀ
Vdd + 0.3
0.8ꢀ
2
ꢀ
GNDꢀ≤ꢀVIn ≤ Vdd
1ꢀ
1ꢀ
µA
µA
ꢀ ILo
OutputꢀLeakageꢀ
GNDꢀ≤ꢀVout ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
Note:
1.ꢀꢀVIL (min.)ꢀ= –0.3VꢀDC;ꢀVILꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
VIH (max.)ꢀ= Vdd +ꢀ0.3V dc;ꢀVIH (max.)ꢀ= Vdd +ꢀ2.0V acꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
3
ꢀ
4
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 2.4V-3.6Vꢀ
ꢀ
ꢀ
ꢀ
Symbol Parameter
Test Conditions
Min.
1.8ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
5
VoH
ꢀ VoL
ꢀ VIH
ꢀ VIL
ꢀ ILI
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vdd = Min.,ꢀIoH = –1.0ꢀmAꢀ
Vdd = Min.,ꢀIoL = 1.0ꢀmAꢀ
0.4ꢀ
V
ꢀ
ꢀ
2.0ꢀ
–0.3ꢀ
–1ꢀ
Vdd + 0.3
0.8ꢀ
V
6
V
ꢀ
GNDꢀ≤ꢀ VIn ≤ Vdd
1ꢀ
µA
µA
ꢀ ILo
OutputꢀLeakageꢀ
GNDꢀ≤ꢀ Vout ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1.ꢀ VIL (min.)ꢀ= –0.3VꢀDC;ꢀVILꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
VIH (max.)ꢀ= Vdd +ꢀ0.3V dc;ꢀVIH (max.)ꢀ= Vdd +ꢀ2.0V acꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
7
ꢀ
8
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-8
-10
Min. Max.
-20
Min. Max.
Symbol Parameter
Test Conditions
Min. Max.
Unit
9
ꢀ Icc
ꢀ ꢀ
VddꢀDynamicꢀOperatingꢀ Vdd = Max.,ꢀꢀ
SupplyꢀCurrentꢀ
Com.ꢀ ꢀ —ꢀ ꢀ 40ꢀ
Ind.ꢀ ꢀ —ꢀ ꢀ 45ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
30ꢀ
35ꢀ
50ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
25ꢀ
30ꢀ
45ꢀ
mA
ꢀ
ꢀ
Iout = 0 mA,ꢀfꢀ=ꢀfmaX
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ
ꢀ
typ.(2)
ꢀ
ꢀ
ꢀ 21ꢀ ꢀ
21
10
11
12
Icc1
ꢀ ꢀ
ꢀ ꢀ
Operatingꢀ
SupplyꢀCurrentꢀ
ꢀ
Vdd = Max.,ꢀꢀ
Iout = 0 mA,ꢀfꢀ=ꢀ0
ꢀ
Com.ꢀ ꢀ —ꢀ ꢀ 20ꢀ
Ind.ꢀ ꢀ —ꢀ ꢀ 25ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
25ꢀ
40ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
25ꢀ
40ꢀ
mA
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ Isb1
ꢀ ꢀ
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
Vdd = Max.,ꢀ
VIn = VIH orꢀVIL
CEꢀ≥ꢀVIH,ꢀfꢀ=ꢀ0ꢀ
Com.
—
10
—
—ꢀ
—ꢀ
10
15ꢀ
30ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
15
30
mA
mA
Ind.ꢀ ꢀ —ꢀ ꢀ 15ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
ꢀ
ꢀ
ꢀ Isb2ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CEꢀ≥ꢀVdd – 0.2V,
VIn ≥ Vdd – 0.2V, orꢀ
Vdd = Max.,ꢀ
Com.
Ind.
—
—
5
6
—
—
—ꢀ
ꢀ
5
6
15ꢀ
—
—
—
5ꢀ
6
15
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
ꢀ
ꢀ ꢀ
ꢀ
VIn ≤ 0.2V, fꢀ=ꢀ0ꢀ
typ.(2)
ꢀ
ꢀ
ꢀ 1.5ꢀ ꢀ
1.5
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmaX,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTaꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
5
Rev. A
09/29/2011
IS61/64WV25616EDBLL
AC TEST CONDITIONS
Parameter
Unit
(2.4V-3.6V)
0.4VꢀtoꢀVdd-0.3V
1V/ꢀns
InputꢀPulseꢀLevelꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ(VRef
Vdd/2
)
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
AC TEST LOADS
319 Ω
3.3V
ZO
= 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-8
-10
-20
Symbol
ꢀ ꢀ trc
ꢀ ꢀ taa
ꢀ ꢀ toHa
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ReadꢀCycleꢀTimeꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
CEꢀAccessꢀTimeꢀ
8ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
2.0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
—ꢀ ꢀ 4.5ꢀ
—ꢀ ꢀ 3ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 3ꢀꢀ
3ꢀ ꢀ —ꢀ
—ꢀ ꢀ 5.5ꢀ
0ꢀ ꢀ 3ꢀꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
2.0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
—ꢀ ꢀ 4.5ꢀ
—ꢀ ꢀ 4ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 4ꢀ
20ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
2.5ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
—ꢀ ꢀ 8ꢀ
0ꢀ ꢀ 8ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 8ꢀ
3ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
0ꢀ ꢀ 8ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ tace
ꢀ
ꢀ ꢀ tdoe
OEꢀAccessꢀTimeꢀ
ꢀ ꢀ tHzoe(2)ꢀ
ꢀ ꢀ tLzoe(2)ꢀ
ꢀ ꢀ tHzce(2ꢀ
ꢀ ꢀ tLzce(2)ꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CEꢀtoꢀHigh-ZꢀOutputꢀ
CEꢀtoꢀLow-ZꢀOutputꢀ
LB,ꢀUBꢀAccessꢀTimeꢀ
LB,ꢀUBꢀtoꢀHigh-ZꢀOutputꢀ
LB,ꢀUBꢀtoꢀLow-ZꢀOutputꢀ
PowerꢀUpꢀTimeꢀ
3ꢀ ꢀ —ꢀ
—ꢀ ꢀ 6.5ꢀ
0ꢀ ꢀ 3ꢀ
ꢀ ꢀ tba
ꢀ
ꢀ ꢀ tHzb(2)ꢀ
ꢀ ꢀ tLzb(2)ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
ꢀ ꢀ tPu
ꢀ ꢀ tPd
ꢀ
ꢀ
PowerꢀDownꢀTimeꢀ
Notes:ꢀ
1.ꢀ TestꢀconditionsꢀandꢀoutputꢀloadingꢀconditionsꢀareꢀspecifiedꢀinꢀtheꢀACꢀTestꢀConditionsꢀandꢀACꢀTestꢀLoadsꢀ(Figureꢀ1).
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2)ꢀ(AddressꢀControlled)ꢀ(CEꢀ=ꢀOEꢀ=ꢀVIL, UB orꢀLB = VIL)
1
2
t
RC
ADDRESS
t
AA
t
OHA
3
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
4
5
READ CYCLE NO. 2(1,3)
t
RC
6
ADDRESS
OE
t
AA
t
OHA
7
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
tHZCE
8
tLZCE
LB, UB
t
BA
t
HZB
tRC
tLZB
HIGH-Z
DOUT
9
DATA VALID
I
CC
V
DD
Supply
Current
50%
50%
t
PD
tPU
I
SB
10
11
12
UB_CEDR2.eps
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCE,ꢀUB,ꢀorꢀLBꢀ=ꢀVIL.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCEꢀLOWꢀtransition.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev. A
09/29/2011
IS61/64WV25616EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (OverꢀOperatingꢀRange)
-8
-10
-20
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ꢀ ꢀ twc
ꢀ
WriteꢀCycleꢀTimeꢀ
CEꢀtoꢀWriteꢀEndꢀ
ꢀ
ꢀ
ꢀ
8ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
ꢀ 10ꢀ ꢀ —ꢀ
20ꢀ
12ꢀ
12ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ ꢀ tsce
ꢀ
ꢀ
8ꢀ ꢀ —ꢀ
8ꢀ ꢀ —ꢀ
ns
ꢀ ꢀ taw
ꢀ
AddressꢀSetupꢀTimeꢀꢀ
toꢀWriteꢀEnd
ns
ꢀ ꢀ ꢀ
ꢀ ꢀ tHa
ꢀ ꢀ tsa
ꢀ ꢀ tPwb
ꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
8ꢀ ꢀ —ꢀ
5ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 3.5ꢀ
2ꢀ ꢀ —ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
8ꢀ ꢀ —ꢀ
8ꢀ ꢀ —ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
9ꢀ
ns
ns
ns
ns
ns
ns
nꢀ s
ns
ns
ꢀ
ꢀ
LB,ꢀUBꢀValidꢀtoꢀEndꢀofꢀWriteꢀ
WEꢀPulseꢀWidthꢀ
12ꢀ
12ꢀ
17ꢀ
9ꢀ
ꢀ ꢀ tPwe1ꢀ
ꢀ ꢀ tPwe2ꢀ
WEꢀPulseꢀWidthꢀꢀ(OEꢀ=ꢀLOW)ꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
ꢀ 10ꢀ ꢀ —ꢀ
ꢀ ꢀ tsd
ꢀ
ꢀ
ꢀ
6ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
ꢀ ꢀ tHd
ꢀ
0ꢀ
ꢀ ꢀ tHzwe(2)ꢀ
ꢀ ꢀ tLzwe(2)ꢀ
Notes:ꢀ
ꢀ —ꢀ ꢀ 5ꢀ
2ꢀ ꢀ —ꢀ
—ꢀ
3ꢀ
ꢀ
—ꢀ
1.ꢀ TestꢀconditionsꢀandꢀoutputꢀloadingꢀconditionsꢀareꢀspecifiedꢀinꢀtheꢀACꢀTestꢀConditionsꢀandꢀACꢀTestꢀLoadsꢀ(Figureꢀ1).
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀUBꢀorꢀLB,ꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀ
toꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀ
theꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.ꢀShadedꢀareaꢀproductꢀinꢀdevelopmentꢀ
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
AC WAVEFORMS
WRITE CYCLE NO. 1ꢀ(CEꢀControlled,ꢀOEꢀisꢀHIGHꢀorꢀLOW)ꢀ(1ꢀ)
1
t
WC
VALID ADDRESS
SCE
2
ADDRESS
CE
t
SA
t
t
HA
3
t
AW
t
tPPWWEE21
WE
t
PWB
4
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
5
DATAIN VALID
DIN
UB_CEWR1.eps
6
Notes:ꢀ
1.ꢀ WRITEꢀisꢀanꢀinternallyꢀgeneratedꢀsignalꢀassertedꢀduringꢀanꢀoverlapꢀofꢀtheꢀLOWꢀstatesꢀonꢀtheꢀCEꢀandꢀWEꢀinputsꢀandꢀatꢀleastꢀ
oneꢀofꢀtheꢀLBꢀandꢀUBꢀinputsꢀbeingꢀinꢀtheꢀLOWꢀstate.
2.ꢀ WRITEꢀ=ꢀ(CE)ꢀ[ꢀ(LB)ꢀ=ꢀ(UB)ꢀ]ꢀ(WE).
7
WRITE CYCLE NO. 2ꢀ(WE Controlled.ꢀ OE isꢀHIGHꢀDuringꢀWriteꢀCycle)ꢀ(1,2)
8
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
9
LOW
CE
t
AW
10
11
12
t
PWE1
WE
UB, LB
DOUT
t
SA
t
PWB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. A
09/29/2011
IS61/64WV25616EDBLL
AC WAVEFORMS
WRITE CYCLE NO. 3ꢀ(WE Controlled.ꢀ OE isꢀLOWꢀDuringꢀWriteꢀCycle)ꢀ(1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PWB
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
WRITE CYCLE NO. 4ꢀ(LB, UB Controlled,ꢀBack-to-BackꢀWrite)ꢀ(1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PWB
t
PWB
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:ꢀ
1.ꢀ TheꢀꢀinternalꢀWriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀ=ꢀLow, UBꢀand/orꢀLBꢀ=ꢀLow,ꢀandꢀWEꢀ=ꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀ
validꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀcanꢀbeꢀdeassertedꢀtoꢀterminateꢀtheꢀWrite.ꢀTheꢀtsa,ꢀtHa, tsd,ꢀandꢀtHdꢀtimingꢀisꢀreferencedꢀ
toꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀWrite.
2.ꢀ TestedꢀwithꢀOEꢀHIGHꢀforꢀaꢀminimumꢀofꢀ4ꢀnsꢀbeforeꢀWEꢀ=ꢀLOWꢀtoꢀplaceꢀtheꢀI/OꢀinꢀaꢀHIGH-Zꢀstate.
3.ꢀ WEꢀmayꢀbeꢀheldꢀLOWꢀacrossꢀmanyꢀaddressꢀcyclesꢀandꢀtheꢀLB,ꢀUBꢀpinsꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀWriteꢀfunction.
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
HIGH SPEED (IS61/64WV25616EDBLL)
1
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
ꢀ ꢀ Vdrꢀ
ꢀ ꢀ Idrꢀ
Parameter
Test Condition
Options
Min.
2.0ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
5ꢀ
Unit
V
VddꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
Vddꢀ=ꢀ2.0V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
ꢀ
ꢀ
ꢀ
2
Com.ꢀ
0.5ꢀ
mA
ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
—ꢀ
ꢀ
6ꢀ
15
ꢀ
ꢀ ꢀ tsdr
ꢀ ꢀ trdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
3
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trcꢀ
o
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀVdr(min),ꢀTa = 25 c andꢀnotꢀ100%ꢀtested.
4
DATA RETENTION WAVEFORM (CEꢀControlled)
5
t
SDR
Data Retention Mode
tRDR
VDD
6
VDR
7
CE ≥ VDD - 0.2V
CE
GND
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
11
Rev. A
09/29/2011
IS61/64WV25616EDBLL
ORDERING INFORMATION (HIGH SPEED)
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
ꢀ
ꢀ
IS61WV25616EDBLL-8BIꢀ
IS61WV25616EDBLL-8BLIꢀ
IS61WV25616EDBLL-8TIꢀ
IS61WV25616EDBLL-8TLIꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-free
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS61WV25616EDBLL-10BIꢀ
IS61WV25616EDBLL-10BLIꢀ
IS61WV25616EDBLL-10TIꢀ
IS61WV25616EDBLL-10TLIꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
Automotive (A1) Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS64WV25616EDBLL-10BA1ꢀ
IS64WV25616EDBLL-10BLA1ꢀ
IS64WV25616EDBLL-10CTA1ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
TSOPꢀ(TypeꢀII),ꢀCopperꢀLeadframeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS64WV25616EDBLL-10CTLA1ꢀ TSOPꢀ(TypeꢀII),ꢀLead-free,ꢀCopperꢀLeadframeꢀ
Automotive (A3) Range: -40°C to +125°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS64WV25616EDBLL-10BA3ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS64WV25616EDBLL-10BLA3ꢀ 48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀꢀ
IS64WV25616EDBLL-10CTA3ꢀ TSOPꢀ(TypeꢀII),ꢀCopperꢀLeadframeꢀ
IS64WV25616EDBLL-10CTLA3ꢀ TSOPꢀ(TypeꢀII),ꢀLead-free,ꢀCopperꢀLeadframe
ꢀ
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. A
09/29/2011
IS61/64WV25616EDBLL
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
相关型号：
IS61WV25632BLL-10BLI
Standard SRAM, 256KX32, 10ns, CMOS, PBGA90, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, MINI, BGA-90
ISSI
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