IS61WV25632BLS [ISSI]
TTL compatible inputs and outputs;
| 型号： | IS61WV25632BLS |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | TTL compatible inputs and outputs |
| 文件： | 总19页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
PRELIMINARY INFORMATION
APRIL 2008
FEATURES
DESCRIPTION
The ISSI IS61WV25632Axx/Bxx and IS64WV25632Bxx
are high-speed, 8M-bit static RAMs organized as 256K
words by 32 bits. It is fabricated using ISSI's high-per-
formance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE op-
tions
• CE power-down
• Fully static operation: no clock or refresh
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
required
Easymemory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of
the memory.
• TTL compatible inputs and outputs
• Single power supply
Vd d 1.65V to 2.2V (IS61WV25632Axx)
speed = 20ns for Vd d 1.65V to 2.2V
Vd d 2.4V to 3.6V (IS61/64WV25632Bxx)
speed = 10ns for Vd d 2.4V to 3.6V
speed = 8ns for Vd d 3.3V + 5%
• Packages available:
The device is packaged in the JEDEC standard 90-ball
BGA (8mm x 13mm).
–
90-ball miniBGA (8mm x 13mm)
• Industrial and Automotive Temperature Support
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
256K x 32
MEMORY ARRAY
A0-A17
DECODER
VDD
VSS
DQa-d
I/O
COLUMN I/O
DATA
CIRCUIT
CE
OE
WE
CONTROL
CIRCUIT
BWa-d
CE2
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
DQ1 DQ0 VSS
DQ2 VDD VSS
VSS DQ3 DQ4
VSS DQ6 DQ5
VDD DQ7 NC
VSS BWa A3
VDD DQ31 DQ30
VDD VSS DQ29
DQ27 DQ28 VDD
DQ26 DQ25 VDD
NC DQ24 VSS
A4 BWd VDD
B
C
D
E
F
G
H
J
A0
A1
A2
A10
A8
A5
A6
A15 A14 A13
CE2 A17 A16
A7 A11
A9
A12
WE
CE
K
L
BWb NC
NC
OE
BWc
VSS
VDD DQ8 VSS
VSS DQ9 DQ10
VSS DQ12 DQ11
DQ13 VDD VSS
DQ14 DQ15 VSS
DQ23
DQ22
DQ19
VSS
VDD
DQ21
DQ20
VDD
VDD
M
N
P
R
VDD
VDD
DQ18
DQ17
DQ16
PIN DESCRIPTIONS
A0-A17
Address Inputs
DQx
Data I/O
CE, CE2
OE
Chip Enable Input
Output Enable Input
Write Enable Input
Byte Write Control
Power
WE
BWx (x=a-d)
Vd d
Vss
Ground
NC
No Connection
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
TRUTH TABLE
CE CE2 OE WE BWa BWb BWc BWd
DQ0-7
High-Z
High-Z
DQ8-15
High-Z
High-Z
DQ16-23
High-Z
High-Z
DQ24-31
High-Z
High-Z
Mode
Power
(Is b )
H
X
L
X
L
X
X
L
L
X
X
H
H
X
X
L
L
X
X
L
X
X
L
X
X
L
Power Down
Power Down
(Is b )
H
H
Data Out Data Out Data Out Data Out Read All Bits
(IC C )
(IC C )
L
H
H
H
Data Out High-Z
High-Z
High-Z
Read Byte a
Bits Only
L
L
L
H
H
H
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
H
L
High-Z Data Out High-Z
High-Z
Read Byte b
Bits Only
(IC C )
(IC C )
(IC C )
High-Z
High-Z
High-Z Data Out High-Z
Read Byte c
Bits Only
H
High-Z
High-Z Data Out Read Byte d
Bits Only
L
L
H
H
X
X
L
L
L
L
L
L
L
Data In Data In
Data In High-Z
Data In
High-Z
Data In
High-Z
Write All Bits
(IC C )
(IC C )
H
H
H
Write Byte a
Bits Only
L
L
L
L
H
H
H
H
X
X
X
H
L
L
H
H
H
X
L
H
H
X
H
L
H
H
L
High-Z Data In
High-Z
Data In
High-Z
High-Z
High-Z
High-Z
Data In
High-Z
Write Byte b
Bits Only
(IC C )
(IC C )
(IC C )
(IC C )
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Write Byte c
Bits Only
L
H
X
Write Byte d
Bits Only
H
X
Selected,
Outputs
Disabled
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
Vt e r m
Vd d
Terminal Voltage with Respect to GND
Vd d Relates to GND
–0.5 to Vd d + 0.5
–0.3 to 4.0
–65 to +150
1.0
V
ts t g
Pt
Storage Temperature
°C
W
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
Vin = 0V
Max.
Unit
pF
Cin
Input Capacitance
Input/Output Capacitance
6
8
Ci/O
VO u t = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vd d = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VD D = 3.3V + 5%
Symbol Parameter
Test Conditions
Min.
2.4
—
Max.
Unit
V
VO h
VO l
Vih
Vil
il i
Output HIGH Voltage
Vd d = Min., iO h = –4.0 mA
Vd d = Min., iO l = 8.0 mA
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2
Vd d + 0.3
V
–0.3
–1
0.8
1
V
GND ≤ Vin ≤ Vd d
GND ≤ VO u t ≤ Vd d , Outputs Disabled
µA
µA
il O
Output Leakage
–1
1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
ih (max.) = Vd d + 0.3V dC; Vih (max.) = Vd d + 2.0V aC (pulse width 2.0 ns). Not 100% tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VD D = 2.4V-3.6V
Symbol Parameter
Test Conditions
Min.
1.8
—
Max.
Unit
V
VO h
VO l
Vih
Vil
il i
Output HIGH Voltage
Vd d = Min., iO h = –1.0 mA
Vd d = Min., iO l = 1.0 mA
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2.0
–0.3
–1
Vd d + 0.3
V
0.8
1
V
GND ≤ Vin ≤ Vd d
µA
µA
il O
Output Leakage
GND ≤ VO u t ≤ Vd d , Outputs Disabled
–1
1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
ih (max.) = Vd d + 0.3V dC; Vih (max.) = Vd d + 2.0V aC (pulse width 2.0 ns). Not 100% tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VD D = 1.65V-2.2V
Symbol Parameter
Test Conditions
iO h = -0.1 mA
iO l = 0.1 mA
VD D
Min.
1.4
—
Max.
Unit
V
VO h
VO l
Vih
Output HIGH Voltage
1.65-2.2V
1.65-2.2V
1.65-2.2V
1.65-2.2V
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
0.2
V
1.4
–0.2
–1
Vd d + 0.2
V
(1)
Vil
il i
0.4
1
V
GND ≤ Vin ≤ Vd d
µA
µA
il O
Output Leakage
GND ≤ VO u t ≤ Vd d , Outputs Disabled
–1
1
Notes:
1. Vil (min.) = –0.3V dC; Vil (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested.
ih (max.) = Vd d + 0.3V dC; Vih (max.) = Vd d + 2.0V AC (pulse width -2.0ns). Not 100% tested.
V
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
HIGH SPEED
OPERATING RANGE (VD D ) (IS61WV25632ALL)
Range
Ambient Temperature
VD D
Speed
20ns
20ns
20ns
Commercial
Industrial
Automotive
0°C to +70°C
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
–40°C to +85°C
–40°C to +125°C
OPERATING RANGE (VD D ) (IS61WV25632BLL)(1)
Range
Ambient Temperature
VD D (8 nS)1
3.3V + 5%
3.3V + 5%
VD D (10 nS)1
2.4V-3.6V
2.4V-3.6V
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (VD D ) (IS64WV25632BLL)
Range
Ambient Temperature
VD D (10 nS)
Automotive
–40°C to +125°C
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
-10
-20
Symbol Parameter
Test Conditions
Min.
Max.
Min. Max.
Min. Max.
Unit
iC C
Vd d Dynamic Operating
Supply Current
Vd d = Max.,
iO u t = 0 mA, f = fm a x
Com.
Ind.
—
—
—
110
115
—
—
—
—
90
95
140
—
—
—
50
60
100
mA
Auto.
typ.(2)
60
iC C 1
is b 1
is b 2
Operating
Supply Current
Vd d = Max.,
iO u t = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
85
90
—
—
—
—
85
90
110
—
—
—
45
55
90
mA
mA
mA
TTL Standby Current
(TTL Inputs)
Vd d = Max.,
Vin = Vih or Vil
CE ≥ Vih, f = 0
Com.
Ind.
Auto.
—
—
—
30
35
—
—
—
—
30
35
70
—
—
—
30
35
70
CMOS Standby
Current (CMOS Inputs)
Vd d = Max.,
Com.
Ind.
—
—
—
20
25
—
—
—
—
20
25
60
—
—
—
20
25
60
CE ≥ Vd d – 0.2V,
Vin ≥ Vd d – 0.2V, or
Vin ≤ 0.2V, f = 0
Auto.
typ.(2)
4
Note:
1. At f = fm a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vd d = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
LOW POWER
OPERATING RANGE (VD D ) (IS61WV25632ALS)
Range
Ambient Temperature
VD D
Speed
35ns
35ns
35ns
Commercial
Industrial
Automotive
0°C to +70°C
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
–40°C to +85°C
–40°C to +125°C
OPERATING RANGE (VD D ) (IS61WV25632BLS)(1)
Range
Ambient Temperature
VD D (25 nS)1
2.4V-3.6V
2.4V-3.6V
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in the
range of 3.3V + 5%, the device meets 20ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
-35
Symbol Parameter
Test Conditions
Min.
Max.
Min. Max.
Unit
iC C
Vd d Dynamic Operating
Supply Current
Vd d = Max.,
iO u t = 0 mA, f = fm a x
Com.
Ind.
—
—
—
30
35
60
—
—
—
25
30
60
mA
Auto.
typ.(2)
25
iC C 1
is b 1
is b 2
Operating
Supply Current
Vd d = Max.,
iO u t = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
20
30
50
—
—
—
20
30
50
mA
mA
mA
TTL Standby Current
(TTL Inputs)
Vd d = Max.,
Vin = Vih or Vil
CE ≥ Vih, f = 0
Com.
Ind.
Auto.
—
—
—
15
20
40
—
—
—
15
20
40
CMOS Standby
Current (CMOS Inputs)
Vd d = Max.,
Com.
Ind.
—
—
—
0.8
1.2
2
—
—
—
0.8
1.2
2
CE ≥ Vd d – 0.2V,
Vin ≥ Vd d – 0.2V, or
Vin ≤ 0.2V, f = 0
Auto.
typ.(2)
0.1
0.1
Note:
1. At f = fm a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vd d = 3.0V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Unit
Unit
Unit
(2.4V-3.6V)
(3.3V + 5%)
(1.65V-2.2V)
Input Pulse Level
0.4V to Vd d -0.3V
1.5ns
0.4V to Vd d -0.3V
1.5ns
0.4V to Vd d -0.2V
1.5ns
Input Rise and Fall Times
Input and Output Timing
Vd d /2
Vd d /2 + 0.05
Vd d /2
and Reference Level (VRef)
Output Load
See Figures 1 and 2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-10
Min. Max.
Symbol
Parameter
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
r C
Read Cycle Time
8
—
2.5
—
—
—
0
—
8
10
—
2.5
—
—
—
0
—
10
—
10
6.5
4
a a
Address Access Time
Output Hold Time
CE Access Time
O h a
a C e
d O e
h z O e
—
8
OE Access Time
5.5
3
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Enable to High-Z
(2)
(2
l z O e
—
3
—
4
h z C e
0
0
(2)
l z C e
b a
3
—
5.5
—
3
3
—
6.5
—
3
—
0
—
0
l z b
h z b
0
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol
tr C
Parameter
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
20
—
2.5
—
—
0
—
20
—
20
8
ta a
Address Access Time
Output Hold Time
CE Access Time
tO h a
ta C e
td O e
OE Access Time
(2)
th z O e
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Enable to High-Z
8
(2)
tl z O e
0
—
8
(2
th z C e
0
(2)
tl z C e
3
—
8
—
3
tb a
tl z b
—
0
th z b
0
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vd d -0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
t
HZOE
HZB
t
DOE
BA
BWa-d
t
t
t
t
t
LZB
CE
LZOE
ACE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Min.
Symbol
Parameter
Min.
8
Max.
—
Max.
—
Unit
ns
tw C
ts C e
t
a w
Write Cycle Time
CE to Write End
10
8
6.5
6.5
—
—
ns
Address Setup Time
to Write End
—
8
—
ns
t
t
t
t
t
t
t
t
t
h a
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
s a
P w b
P w e
P w e
s d
BWa-d Valid to End of Write
WE Pulse Width
6.5
6.5
8.0
5
8
1
2
8
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
10
6
h d
0
0
(2)
h z w e
—
2
—
2
(2)
l z w e
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns
Symbol
tw C
Parameter
Min. Max.
Unit
ns
Write Cycle Time
CE to Write End
20
12
12
—
—
—
ts C e
ns
ta w
Address Setup Time
to Write End
ns
th a
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ts a
tP w b
tP w e 1
tP w e 2
ts d
BWa-d Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
12
12
17
9
th d
0
(3)
th z w e
—
3
(3)
tl z w e
—
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup
and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 2(WE Controlled. OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
BWa-d
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
BWa-d
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 4(Byte Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
BWa-d
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of and WE = LOW. All signals must be in valid states to initiate a Write, but any can be
deasserted to terminate the Write. The ts a , th a , ts d , and th d timing is referenced to the rising or falling edge of the signal that terminates the
Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61WV25632ALL/BLL)
Symbol
Vd r
id r
Parameter
Test Condition
Min.
Max.
Unit
V
Vd d for Data Retention
Data Retention Current
See Data Retention Waveform
Vd d = 1.2V, CE ≥ Vd d – 0.2V
1.2
3.6
Ind.
Auto.
—
—
25
60
mA
ts d r
tr d r
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
ns
tr C
—
ns
DATA RETENTION WAVEFORM (CE Controlled)
t
SDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE ≥ VDD - 0.2V
CE
GND
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61WV25632ALS/BLS)
Symbol
Vd r
id r
Parameter
Test Condition
Min.
Max.
Unit
V
Vd d for Data Retention
Data Retention Current
See Data Retention Waveform
Vd d = 1.2V, CE ≥ Vd d – 0.2V
1.2
3.6
Ind.
Auto.
—
—
1.2
2
mA
ts d r
tr d r
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
ns
tr C
—
ns
DATA RETENTION WAVEFORM (CE Controlled)
t
SDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
10 (81)
IS61WV25632BLL-10BI
90-ball BGA (8mm x 13mm)
IS61WV25632BLL-10BLI 90-ball BGA (8mm x 13mm), Lead-free
Note:
1. Speed = 8ns for Vd d = 3.3V + 5%. Speed = 10ns for Vd d = 2.4V - 3.6V
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
Order Part No.
Package
20
IS61WV25632ALL-20BI
90-ball BGA (8mm x 13mm)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
10
IS64WV25632BLL-10BA3 90-ball BGA (8mm x 13mm)
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
D1
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. 00B
04/23/08
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